xref: /freebsd/sys/contrib/device-tree/src/arm64/qcom/talos.dtsi (revision 69ed3df4f588860308677cda76cbcce1f19a54c9)

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,qcs615-camcc.h>
#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
#include <dt-bindings/clock/qcom,qcs615-videocc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x0>;
			enable-method = "psci";
			power-domains = <&cpu_pd0>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&l2_0>;
			clocks = <&cpufreq_hw 0>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			l2_0: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      cache-unified;
			      next-level-cache = <&l3_0>;
			};
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x100>;
			enable-method = "psci";
			power-domains = <&cpu_pd1>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&l2_100>;
			clocks = <&cpufreq_hw 0>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			l2_100: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      cache-unified;
			      next-level-cache = <&l3_0>;
			};
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x200>;
			enable-method = "psci";
			power-domains = <&cpu_pd2>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&l2_200>;
			clocks = <&cpufreq_hw 0>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			l2_200: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      cache-unified;
			      next-level-cache = <&l3_0>;
			};
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x300>;
			enable-method = "psci";
			power-domains = <&cpu_pd3>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&l2_300>;
			clocks = <&cpufreq_hw 0>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			l2_300: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      cache-unified;
			      next-level-cache = <&l3_0>;
			};
		};

		cpu4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x400>;
			enable-method = "psci";
			power-domains = <&cpu_pd4>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&l2_400>;
			clocks = <&cpufreq_hw 0>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			l2_400: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      cache-unified;
			      next-level-cache = <&l3_0>;
			};
		};

		cpu5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x500>;
			enable-method = "psci";
			power-domains = <&cpu_pd5>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&l2_500>;
			clocks = <&cpufreq_hw 0>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			l2_500: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      cache-unified;
			      next-level-cache = <&l3_0>;
			};
		};

		cpu6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x0 0x600>;
			enable-method = "psci";
			power-domains = <&cpu_pd6>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <404>;
			next-level-cache = <&l2_600>;
			clocks = <&cpufreq_hw 1>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			#cooling-cells = <2>;
			operating-points-v2 = <&cpu6_opp_table>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			l2_600: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      cache-unified;
			      next-level-cache = <&l3_0>;
			};
		};

		cpu7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x0 0x700>;
			enable-method = "psci";
			power-domains = <&cpu_pd7>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <404>;
			next-level-cache = <&l2_700>;
			clocks = <&cpufreq_hw 1>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			operating-points-v2 = <&cpu6_opp_table>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;

			l2_700: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			      cache-unified;
			      next-level-cache = <&l3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};

				core4 {
					cpu = <&cpu4>;
				};

				core5 {
					cpu = <&cpu5>;
				};

				core6 {
					cpu = <&cpu6>;
				};

				core7 {
					cpu = <&cpu7>;
				};
			};
		};

		l3_0: l3-cache {
			compatible = "cache";
			cache-level = <3>;
			cache-unified;
		};
	};

	cpu0_opp_table: opp-table-cpu0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-peak-kBps = <(300000 * 4) (300000 * 16)>;
		};

		opp-576000000 {
			opp-hz = /bits/ 64 <576000000>;
			opp-peak-kBps = <(300000 * 4) (576000 * 16)>;
		};

		opp-748800000 {
			opp-hz = /bits/ 64 <748800000>;
			opp-peak-kBps = <(300000 * 4) (576000 * 16)>;
		};

		opp-998400000 {
			opp-hz = /bits/ 64 <998400000>;
			opp-peak-kBps = <(451000 * 4) (806400 * 16)>;
		};

		opp-1209600000 {
			opp-hz = /bits/ 64 <1209600000>;
			opp-peak-kBps = <(547000 * 4) (1017600 * 16)>;
		};

		opp-1363200000 {
			opp-hz = /bits/ 64 <1363200000>;
			opp-peak-kBps = <(768000 * 4) (1209600 * 16)>;
		};

		opp-1516800000 {
			opp-hz = /bits/ 64 <1516800000>;
			opp-peak-kBps = <(768000 * 4) (1209600 * 16)>;
		};

		opp-1593600000 {
			opp-hz = /bits/ 64 <1593600000>;
			opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>;
		};
	};

	cpu6_opp_table: opp-table-cpu6 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-peak-kBps = <(451000 * 4) (300000 * 16)>;
		};

		opp-652800000 {
			opp-hz = /bits/ 64 <652800000>;
			opp-peak-kBps = <(451000 * 4) (576000 * 16)>;
		};

		opp-768000000 {
			opp-hz = /bits/ 64 <768000000>;
			opp-peak-kBps = <(451000 * 4) (576000 * 16)>;
		};

		opp-979200000 {
			opp-hz = /bits/ 64 <979200000>;
			opp-peak-kBps = <(547000 * 4) (806400 * 16)>;
		};

		opp-1017600000 {
			opp-hz = /bits/ 64 <1017600000>;
			opp-peak-kBps = <(547000 * 4) (806400 * 16)>;
		};

		opp-1094400000 {
			opp-hz = /bits/ 64 <109440000>;
			opp-peak-kBps = <(1017600 * 4) (940800 * 16)>;
		};

		opp-1209600000 {
			opp-hz = /bits/ 64 <1209600000>;
			opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>;
		};

		opp-1363200000 {
			opp-hz = /bits/ 64 <1363200000>;
			opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>;
		};

		opp-1516800000 {
			opp-hz = /bits/ 64 <1516800000>;
			opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>;
		};

		opp-1708800000 {
			opp-hz = /bits/ 64 <1708800000>;
			opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>;
		};

		opp-1900800000 {
			opp-hz = /bits/ 64 <1900800000>;
			opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>;
		};
	};

	dummy_eud: dummy-sink {
		compatible = "arm,coresight-dummy-sink";

		in-ports {
			port {
				eud_in: endpoint {
					remote-endpoint = <&replicator_swao_out1>;
				};
			};
		};
	};

	idle-states {
		entry-method = "psci";

		little_cpu_sleep_0: cpu-sleep-0-0 {
			compatible = "arm,idle-state";
			idle-state-name = "silver-power-collapse";
			arm,psci-suspend-param = <0x40000003>;
			entry-latency-us = <549>;
			exit-latency-us = <901>;
			min-residency-us = <1774>;
			local-timer-stop;
		};

		little_cpu_sleep_1: cpu-sleep-0-1 {
			compatible = "arm,idle-state";
			idle-state-name = "silver-rail-power-collapse";
			arm,psci-suspend-param = <0x40000004>;
			entry-latency-us = <702>;
			exit-latency-us = <915>;
			min-residency-us = <4001>;
			local-timer-stop;
		};

		big_cpu_sleep_0: cpu-sleep-1-0 {
			compatible = "arm,idle-state";
			idle-state-name = "gold-power-collapse";
			arm,psci-suspend-param = <0x40000003>;
			entry-latency-us = <523>;
			exit-latency-us = <1244>;
			min-residency-us = <2207>;
			local-timer-stop;
		};

		big_cpu_sleep_1: cpu-sleep-1-1 {
			compatible = "arm,idle-state";
			idle-state-name = "gold-rail-power-collapse";
			arm,psci-suspend-param = <0x40000004>;
			entry-latency-us = <526>;
			exit-latency-us = <1854>;
			min-residency-us = <5555>;
			local-timer-stop;
		};
	};

	domain-idle-states {
		cluster_sleep_0: cluster-sleep-0 {
			compatible = "domain-idle-state";
			arm,psci-suspend-param = <0x41000044>;
			entry-latency-us = <2752>;
			exit-latency-us = <3048>;
			min-residency-us = <6118>;
		};

		cluster_sleep_1: cluster-sleep-1 {
			compatible = "domain-idle-state";
			arm,psci-suspend-param = <0x41001344>;
			entry-latency-us = <3263>;
			exit-latency-us = <4562>;
			min-residency-us = <8467>;
		};

		cluster_sleep_2: cluster-sleep-2 {
			compatible = "domain-idle-state";
			arm,psci-suspend-param = <0x4100b344>;
			entry-latency-us = <3638>;
			exit-latency-us = <6562>;
			min-residency-us = <9826>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0 0x80000000 0 0>;
	};

	firmware {
		scm {
			compatible = "qcom,scm-qcs615", "qcom,scm";
			qcom,dload-mode = <&tcsr 0x13000>;
		};
	};

	camnoc_virt: interconnect-0 {
		compatible = "qcom,qcs615-camnoc-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect-2 {
		compatible = "qcom,qcs615-mc-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING 0>;
		/* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */
		mboxes = <&apss_shared 26>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING 0>;
		mboxes = <&apss_shared 6>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

	};

	qup_opp_table: opp-table-qup {
		compatible = "operating-points-v2";

		opp-75000000 {
			opp-hz = /bits/ 64 <75000000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};

		opp-128000000 {
			opp-hz = /bits/ 64 <128000000>;
			required-opps = <&rpmhpd_opp_nom>;
		};
	};

	pmu-a55 {
		compatible = "arm,cortex-a55-pmu";
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
	};

	pmu-a76 {
		compatible = "arm,cortex-a76-pmu";
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		cpu_pd0: power-domain-cpu0 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cpu_pd1: power-domain-cpu1 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cpu_pd2: power-domain-cpu2 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cpu_pd3: power-domain-cpu3 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cpu_pd4: power-domain-cpu4 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cpu_pd5: power-domain-cpu5 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd>;
			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
		};

		cpu_pd6: power-domain-cpu6 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd>;
			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
		};

		cpu_pd7: power-domain-cpu7 {
			#power-domain-cells = <0>;
			power-domains = <&cluster_pd>;
			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
		};

		cluster_pd: power-domain-cluster {
			#power-domain-cells = <0>;
			domain-idle-states = <&cluster_sleep_0
					      &cluster_sleep_1
					      &cluster_sleep_2>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		aop_cmd_db_mem: aop-cmd-db@85f20000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x85f20000 0x0 0x20000>;
			no-map;
		};

		smem_region: smem@86000000 {
			compatible = "qcom,smem";
			reg = <0x0 0x86000000 0x0 0x200000>;
			no-map;
			hwlocks = <&tcsr_mutex 3>;
		};

		pil_video_mem: pil-video@93400000 {
			reg = <0x0 0x93400000 0x0 0x500000>;
			no-map;
		};

		rproc_cdsp_mem: rproc-cdsp@93b00000 {
			reg = <0x0 0x93b00000 0x0 0x1e00000>;
			no-map;
		};

		rproc_adsp_mem: rproc-adsp@95900000 {
			reg = <0x0 0x95900000 0x0 0x1e00000>;
			no-map;
		};

		pil_gpu_mem: pil-gpu@97715000 {
			reg = <0x0 0x97715000 0x0 0x2000>;
			no-map;
		};
	};

	soc: soc@0 {
		compatible = "simple-bus";
		ranges = <0 0 0 0 0x10 0>;
		dma-ranges = <0 0 0 0 0x10 0>;
		#address-cells = <2>;
		#size-cells = <2>;

		gcc: clock-controller@100000 {
			compatible = "qcom,qcs615-gcc";
			reg = <0 0x00100000 0 0x1f0000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&rpmhcc RPMH_CXO_CLK_A>,
				 <&sleep_clk>;
			clock-names = "bi_tcxo",
				      "bi_tcxo_ao",
				      "sleep_clk";

			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		qfprom: efuse@780000 {
			compatible = "qcom,qcs615-qfprom", "qcom,qfprom";
			reg = <0x0 0x00780000 0x0 0x7000>;
			#address-cells = <1>;
			#size-cells = <1>;

			qusb2_hstx_trim: hstx-trim@1f8 {
				reg = <0x1fb 0x1>;
				bits = <1 4>;
			};
		};

		rng@793000 {
			compatible = "qcom,qcs615-trng", "qcom,trng";
			reg = <0x0 0x00793000 0x0 0x1000>;
		};

		sdhc_1: mmc@7c4000 {
			compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
			reg = <0x0 0x007c4000 0x0 0x1000>,
			      <0x0 0x007c5000 0x0 0x1000>,
			      <0x0 0x007c8000 0x0 0x8000>;
			reg-names = "hc",
				    "cqhci",
				    "ice";

			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
			interrupt-names = "hc_irq",
					  "pwr_irq";

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
			clock-names = "iface",
				      "core",
				      "xo",
				      "ice";

			resets = <&gcc GCC_SDCC1_BCR>;

			power-domains = <&rpmhpd RPMHPD_CX>;
			operating-points-v2 = <&sdhc1_opp_table>;
			iommus = <&apps_smmu 0x02c0 0x0>;
			interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "sdhc-ddr",
					     "cpu-sdhc";

			qcom,dll-config = <0x000f642c>;
			qcom,ddr-config = <0x80040868>;
			supports-cqe;
			dma-coherent;

			status = "disabled";

			sdhc1_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-50000000 {
					opp-hz = /bits/ 64 <50000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>;
					required-opps = <&rpmhpd_opp_svs>;
				};

				opp-200000000 {
					opp-hz = /bits/ 64 <200000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
				};

				opp-384000000 {
					opp-hz = /bits/ 64 <384000000>;
					required-opps = <&rpmhpd_opp_nom>;
				};
			};
		};

		gpi_dma0: dma-controller@800000  {
			compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
			reg = <0x0 0x800000 0x0 0x60000>;
			#dma-cells = <3>;
			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
			dma-channels = <8>;
			dma-channel-mask = <0xf>;
			iommus = <&apps_smmu 0xd6 0x0>;
			status = "disabled";
		};

		qupv3_id_0: geniqup@8c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x008c0000 0x0 0x6000>;
			ranges;
			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
			clock-names = "m-ahb",
				      "s-ahb";
			iommus = <&apps_smmu 0xc3 0x0>;
			#address-cells = <2>;
			#size-cells = <2>;
			status = "disabled";

			uart0: serial@880000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0x0 0x00880000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>;
				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table>;
				status = "disabled";
			};

			i2c1: i2c@884000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x884000 0x0 0x4000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_i2c1_data_clk>;
				pinctrl-names = "default";
				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
						<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";
				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;
				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};

			i2c2: i2c@888000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x888000 0x0 0x4000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_i2c2_data_clk>;
				pinctrl-names = "default";
				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
						<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";
				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;
				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};

			spi2: spi@888000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00888000 0x0 0x4000>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
				pinctrl-names = "default";
				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table>;
				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart2: serial@888000 {
				compatible = "qcom,geni-uart";
				reg = <0x0 0x00888000 0x0 0x4000>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
					    <&qup_uart2_tx>, <&qup_uart2_rx>;
				pinctrl-names = "default";
				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table>;
				status = "disabled";
			};

			i2c3: i2c@88c000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x88c000 0x0 0x4000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_i2c3_data_clk>;
				pinctrl-names = "default";
				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
						<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";
				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;
				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};
		};

		gpi_dma1: dma-controller@a00000 {
			compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
			reg = <0x0 0xa00000 0x0 0x60000>;
			#dma-cells = <3>;
			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
			dma-channels = <8>;
			dma-channel-mask = <0xf>;
			iommus = <&apps_smmu 0x376 0x0>;
			status = "disabled";
		};

		qupv3_id_1: geniqup@ac0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0xac0000 0x0 0x2000>;
			ranges;
			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			clock-names = "m-ahb",
				      "s-ahb";
			iommus = <&apps_smmu 0x363 0x0>;
			#address-cells = <2>;
			#size-cells = <2>;
			status = "disabled";

			i2c4: i2c@a80000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0xa80000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_i2c4_data_clk>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";
				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;
				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};

			spi4: spi@a80000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0xa80000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table>;
				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};

			uart4: serial@a80000 {
				compatible = "qcom,geni-uart";
				reg = <0x0 0xa80000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
					    <&qup_uart4_tx>, <&qup_uart4_rx>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table>;
				status = "disabled";
			};

			i2c5: i2c@a84000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0xa84000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_i2c5_data_clk>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";
				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;
				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};

			i2c6: i2c@a88000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0xa88000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_i2c6_data_clk>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";
				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;
				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};

			spi6: spi@a88000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0xa88000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table>;
				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};

			uart6: serial@a88000 {
				compatible = "qcom,geni-uart";
				reg = <0x0 0xa88000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
					    <&qup_uart6_tx>, <&qup_uart6_rx>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table>;
				status = "disabled";
			};

			i2c7: i2c@a8c000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0xa8c000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_i2c7_data_clk>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config",
						     "qup-memory";
				power-domains = <&rpmhpd RPMHPD_CX>;
				required-opps = <&rpmhpd_opp_low_svs>;
				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};

			spi7: spi@a8c000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0xa8c000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table>;
				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
				dma-names = "tx",
					    "rx";
				status = "disabled";
			};

			uart7: serial@a8c000 {
				compatible = "qcom,geni-uart";
				reg = <0x0 0xa8c000 0x0 0x4000>;
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				clock-names = "se";
				pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
					    <&qup_uart7_tx>, <&qup_uart7_rx>;
				pinctrl-names = "default";
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table>;
				status = "disabled";
			};
		};

		config_noc: interconnect@1500000 {
			reg = <0x0 0x01500000 0x0 0x5080>;
			compatible = "qcom,qcs615-config-noc";
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		system_noc: interconnect@1620000 {
			reg = <0x0 0x01620000 0x0 0x1f300>;
			compatible = "qcom,qcs615-system-noc";
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		aggre1_noc: interconnect@1700000 {
			reg = <0x0 0x01700000 0x0 0x3f200>;
			compatible = "qcom,qcs615-aggre1-noc";
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
				 <&rpmhcc RPMH_IPA_CLK>;
		};

		mmss_noc: interconnect@1740000 {
			reg = <0x0 0x01740000 0x0 0x1c100>;
			compatible = "qcom,qcs615-mmss-noc";
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		pcie: pcie@1c08000 {
			device_type = "pci";
			compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150";
			reg = <0x0 0x01c08000 0x0 0x3000>,
			      <0x0 0x40000000 0x0 0xf1d>,
			      <0x0 0x40000f20 0x0 0xa8>,
			      <0x0 0x40001000 0x0 0x1000>,
			      <0x0 0x40100000 0x0 0x100000>,
			      <0x0 0x01c0b000 0x0 0x1000>;
			reg-names = "parf",
				    "dbi",
				    "elbi",
				    "atu",
				    "config",
				    "mhi";
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
			bus-range = <0x00 0xff>;

			dma-coherent;

			linux,pci-domain = <0>;
			num-lanes = <1>;

			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>;
			interrupt-names = "msi0",
					  "msi1",
					  "msi2",
					  "msi3",
					  "msi4",
					  "msi5",
					  "msi6",
					  "msi7",
					  "global";

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>,
					<0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
				 <&gcc GCC_PCIE_0_AUX_CLK>,
				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
			clock-names = "pipe",
				      "aux",
				      "cfg",
				      "bus_master",
				      "bus_slave",
				      "slave_q2a";
			assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
			assigned-clock-rates = <19200000>;

			interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "pcie-mem", "cpu-pcie";

			iommu-map = <0x0 &apps_smmu 0x400 0x1>,
				    <0x100 &apps_smmu 0x401 0x1>;

			resets = <&gcc GCC_PCIE_0_BCR>;
			reset-names = "pci";

			power-domains = <&gcc PCIE_0_GDSC>;

			phys = <&pcie_phy>;
			phy-names = "pciephy";

			max-link-speed = <2>;

			operating-points-v2 = <&pcie_opp_table>;

			status = "disabled";

			pcie_opp_table: opp-table {
				compatible = "operating-points-v2";

				/* GEN 1 x1 */
				opp-2500000 {
					opp-hz = /bits/ 64 <2500000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <250000 1>;
				};

				/* GEN 2 x1 */
				opp-5000000 {
					opp-hz = /bits/ 64 <5000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
					opp-peak-kBps = <500000 1>;
				};
			};

			pcie_port0: pcie@0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				#address-cells = <3>;
				#size-cells = <2>;
				ranges;
				bus-range = <0x01 0xff>;
			};
		};

		pcie_phy: phy@1c0e000 {
			compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy";
			reg = <0x0 0x01c0e000 0x0 0x1000>;

			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_0_CLKREF_CLK>,
				 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
				 <&gcc GCC_PCIE_0_PIPE_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "refgen",
				      "pipe";

			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
			reset-names = "phy";

			assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
			assigned-clock-rates = <100000000>;

			#clock-cells = <0>;
			clock-output-names = "pcie_0_pipe_clk";

			#phy-cells = <0>;

			status = "disabled";
		};

		ufs_mem_hc: ufshc@1d84000 {
			compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
			reg = <0x0 0x01d84000 0x0 0x3000>,
			      <0x0 0x01d90000 0x0 0x8000>;
			reg-names = "std",
				    "ice";

			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;

			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_UFS_PHY_AHB_CLK>,
				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
			clock-names = "core_clk",
				      "bus_aggr_clk",
				      "iface_clk",
				      "core_clk_unipro",
				      "ref_clk",
				      "tx_lane0_sync_clk",
				      "rx_lane0_sync_clk",
				      "ice_core_clk";

			resets = <&gcc GCC_UFS_PHY_BCR>;
			reset-names = "rst";

			operating-points-v2 = <&ufs_opp_table>;
			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "ufs-ddr",
					     "cpu-ufs";

			power-domains = <&gcc UFS_PHY_GDSC>;

			iommus = <&apps_smmu 0x300 0x0>;
			dma-coherent;

			lanes-per-direction = <1>;

			phys = <&ufs_mem_phy>;
			phy-names = "ufsphy";

			#reset-cells = <1>;

			status = "disabled";

			ufs_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-50000000 {
					opp-hz = /bits/ 64 <50000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <37500000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <75000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <75000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <150000000>;
					required-opps = <&rpmhpd_opp_svs>;
				};

				opp-200000000 {
					opp-hz = /bits/ 64 <200000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <150000000>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <0>,
						 /bits/ 64 <300000000>;
					required-opps = <&rpmhpd_opp_nom>;
				};
			};
		};

		ufs_mem_phy: phy@1d87000 {
			compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";
			reg = <0x0 0x01d87000 0x0 0xe00>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
				 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
			clock-names = "ref",
				      "ref_aux",
				      "qref";

			power-domains = <&gcc UFS_PHY_GDSC>;

			resets = <&ufs_mem_hc 0>;
			reset-names = "ufsphy";

			#clock-cells = <1>;
			#phy-cells = <0>;

			status = "disabled";
		};

		cryptobam: dma-controller@1dc4000 {
			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
			reg = <0x0 0x01dc4000 0x0 0x24000>;
			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			num-channels = <16>;
			qcom,num-ees = <4>;
			iommus = <&apps_smmu 0x0104 0x0011>;
		};

		crypto: crypto@1dfa000 {
			compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce";
			reg = <0x0 0x01dfa000 0x0 0x6000>;
			dmas = <&cryptobam 4>, <&cryptobam 5>;
			dma-names = "rx", "tx";
			iommus = <&apps_smmu 0x0104 0x0011>;
			interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
			interconnect-names = "memory";
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x0 0x01f40000 0x0 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr: syscon@1fc0000 {
			compatible = "qcom,qcs615-tcsr", "syscon";
			reg = <0x0 0x01fc0000 0x0 0x30000>;
		};

		tlmm: pinctrl@3100000 {
			compatible = "qcom,qcs615-tlmm";
			reg = <0x0 0x03100000 0x0 0x300000>,
			      <0x0 0x03500000 0x0 0x300000>,
			      <0x0 0x03d00000 0x0 0x300000>;
			reg-names = "east",
				    "west",
				    "south";
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;
			gpio-ranges = <&tlmm 0 0 124>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			wakeup-parent = <&pdc>;

			cam_mclk0_default: cam-mclk0-default-state {
				pins = "gpio28";
				function = "cam_mclk";
				drive-strength = <2>;
				bias-disable;
			};

			cam_mclk1_default: cam-mclk1-default-state {
				pins = "gpio29";
				function = "cam_mclk";
				drive-strength = <2>;
				bias-disable;
			};

			cam_mclk2_default: cam-mclk2-default-state {
				pins = "gpio30";
				function = "cam_mclk";
				drive-strength = <2>;
				bias-disable;
			};

			cam_mclk3_default: cam-mclk3-default-state {
				pins = "gpio31";
				function = "cam_mclk";
				drive-strength = <2>;
				bias-disable;
			};

			cci_i2c0_default: cci-i2c0-default-state {
				/* SDA, SCL */
				pins = "gpio32", "gpio33";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-up;
			};

			cci_i2c1_default: cci-i2c1-default-state {
				/* SDA, SCL */
				pins = "gpio34", "gpio35";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
				pins = "gpio4", "gpio5";
				function = "qup0";

			};

			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
				pins = "gpio0", "gpio1";
				function = "qup0";
			};

			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
				pins = "gpio18", "gpio19";
				function = "qup0";
			};

			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
				pins = "gpio20", "gpio21";
				function = "qup1";
			};

			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
				pins = "gpio14", "gpio15";
				function = "qup1";
			};

			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
				pins = "gpio6", "gpio7";
				function = "qup1";
			};

			qup_i2c7_data_clk: qup-i2c7-data-clk-state {
				pins = "gpio10", "gpio11";
				function = "qup1";
			};

			qup_spi2_data_clk: qup-spi2-data-clk-state {
				pins = "gpio0", "gpio1", "gpio2";
				function = "qup0";
			};

			qup_spi2_cs: qup-spi2-cs-state {
				pins = "gpio3";
				function = "qup0";
			};

			qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
				pins = "gpio3";
				function = "gpio";
			};

			qup_spi4_data_clk: qup-spi4-data-clk-state {
				pins = "gpio20", "gpio21", "gpio22";
				function = "qup1";
			};

			qup_spi4_cs: qup-spi4-cs-state {
				pins = "gpio23";
				function = "qup1";
			};

			qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
				pins = "gpio23";
				function = "gpio";
			};

			qup_spi6_data_clk: qup-spi6-data-clk-state {
				pins = "gpio6", "gpio7", "gpio8";
				function = "qup1";
			};

			qup_spi6_cs: qup-spi6-cs-state {
				pins = "gpio9";
				function = "qup1";
			};

			qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
				pins = "gpio9";
				function = "gpio";
			};

			qup_spi7_data_clk: qup-spi7-data-clk-state {
				pins = "gpio10", "gpio11", "gpio12";
				function = "qup1";
			};

			qup_spi7_cs: qup-spi7-cs-state {
				pins = "gpio13";
				function = "qup1";
			};

			qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
				pins = "gpio13";
				function = "gpio";
			};

			qup_uart0_tx: qup-uart0-tx-state {
				pins = "gpio16";
				function = "qup0";
			};

			qup_uart0_rx: qup-uart0-rx-state {
				pins = "gpio17";
				function = "qup0";
			};

			qup_uart2_cts: qup-uart2-cts-state {
				pins = "gpio0";
				function = "qup0";
			};

			qup_uart2_rts: qup-uart2-rts-state {
				pins = "gpio1";
				function = "qup0";
			};

			qup_uart2_tx: qup-uart2-tx-state {
				pins = "gpio2";
				function = "qup0";
			};

			qup_uart2_rx: qup-uart2-rx-state {
				pins = "gpio3";
				function = "qup0";
			};

			qup_uart4_cts: qup-uart4-cts-state {
				pins = "gpio20";
				function = "qup1";
			};

			qup_uart4_rts: qup-uart4-rts-state {
				pins = "gpio21";
				function = "qup1";
			};

			qup_uart4_tx: qup-uart4-tx-state {
				pins = "gpio22";
				function = "qup1";
			};

			qup_uart4_rx: qup-uart4-rx-state {
				pins = "gpio23";
				function = "qup1";
			};

			qup_uart6_cts: qup-uart6-cts-state {
				pins = "gpio6";
				function = "qup1";
			};

			qup_uart6_rts: qup-uart6-rts-state {
				pins = "gpio7";
				function = "qup1";
			};

			qup_uart6_tx: qup-uart6-tx-state {
				pins = "gpio8";
				function = "qup1";
			};

			qup_uart6_rx: qup-uart6-rx-state {
				pins = "gpio9";
				function = "qup1";
			};

			qup_uart7_cts: qup-uart7-cts-state {
				pins = "gpio10";
				function = "qup1";
			};

			qup_uart7_rts: qup-uart7-rts-state {
				pins = "gpio11";
				function = "qup1";
			};

			qup_uart7_tx: qup-uart7-tx-state {
				pins = "gpio12";
				function = "qup1";
			};

			qup_uart7_rx: qup-uart7-rx-state {
				pins = "gpio13";
				function = "qup1";
			};

			sdc1_state_on: sdc1-on-state {
				clk-pins {
					pins = "sdc1_clk";
					bias-disable;
					drive-strength = <16>;
				};

				cmd-pins {
					pins = "sdc1_cmd";
					bias-pull-up;
					drive-strength = <10>;
				};

				data-pins {
					pins = "sdc1_data";
					bias-pull-up;
					drive-strength = <10>;
				};

				rclk-pins {
					pins = "sdc1_rclk";
					bias-pull-down;
				};
			};

			sdc1_state_off: sdc1-off-state {
				clk-pins {
					pins = "sdc1_clk";
					bias-disable;
					drive-strength = <2>;
				};

				cmd-pins {
					pins = "sdc1_cmd";
					bias-pull-up;
					drive-strength = <2>;
				};

				data-pins {
					pins = "sdc1_data";
					bias-pull-up;
					drive-strength = <2>;
				};

				rclk-pins {
					pins = "sdc1_rclk";
					bias-pull-down;
				};
			};

			sdc2_state_on: sdc2-on-state {
				clk-pins {
					pins = "sdc2_clk";
					bias-disable;
					drive-strength = <16>;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					bias-pull-up;
					drive-strength = <10>;
				};

				data-pins {
					pins = "sdc2_data";
					bias-pull-up;
					drive-strength = <10>;
				};
			};

			sdc2_state_off: sdc2-off-state {
				clk-pins {
					pins = "sdc2_clk";
					bias-disable;
					drive-strength = <2>;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					bias-pull-up;
					drive-strength = <2>;
				};

				data-pins {
					pins = "sdc2_data";
					bias-pull-up;
					drive-strength = <2>;
				};
			};
		};

		gpu: gpu@5000000 {
			compatible = "qcom,adreno-612.0", "qcom,adreno";
			reg = <0x0 0x05000000 0x0 0x40000>,
			      <0x0 0x0509e000 0x0 0x1000>,
			      <0x0 0x05061000 0x0 0x800>;
			reg-names = "kgsl_3d0_reg_memory",
				    "cx_mem",
				    "cx_dbgc";

			clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>;
			clock-names = "core";

			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;

			interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
			interconnect-names = "gfx-mem";

			iommus = <&adreno_smmu 0x0 0x401>;

			operating-points-v2 = <&gpu_opp_table>;
			power-domains = <&rpmhpd RPMHPD_CX>;

			qcom,gmu = <&gmu>;

			#cooling-cells = <2>;

			status = "disabled";

			gpu_zap_shader: zap-shader {
				memory-region = <&pil_gpu_mem>;
			};

			gpu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-845000000 {
					opp-hz = /bits/ 64 <845000000>;
					required-opps = <&rpmhpd_opp_turbo>;
					opp-peak-kBps = <7050000>;
				};

				opp-745000000 {
					opp-hz = /bits/ 64 <745000000>;
					required-opps = <&rpmhpd_opp_nom_l1>;
					opp-peak-kBps = <6075000>;
				};

				opp-650000000 {
					opp-hz = /bits/ 64 <650000000>;
					required-opps = <&rpmhpd_opp_nom>;
					opp-peak-kBps = <5287500>;
				};

				opp-500000000 {
					opp-hz = /bits/ 64 <500000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
					opp-peak-kBps = <3975000>;
				};

				opp-435000000 {
					opp-hz = /bits/ 64 <435000000>;
					required-opps = <&rpmhpd_opp_svs>;
					opp-peak-kBps = <3000000>;
				};
			};
		};

		gmu: gmu@506a000 {
			compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
			reg = <0x0 0x0506d000 0x0 0x2c000>;

			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
				 <&gpucc GPU_CC_CXO_CLK>,
				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
			clock-names = "gmu",
				      "cxo",
				      "axi",
				      "memnoc",
				      "smmu_vote";

			power-domains = <&gpucc CX_GDSC>,
					<&gpucc GX_GDSC>;
			power-domain-names = "cx",
					     "gx";

			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
			interrupt-names = "oob",
					  "gmu";

			operating-points-v2 = <&gmu_opp_table>;

			gmu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-200000000 {
					opp-hz = /bits/ 64 <200000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};
			};
		};

		gpucc: clock-controller@5090000 {
			compatible = "qcom,qcs615-gpucc";
			reg = <0 0x05090000 0 0x9000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GPLL0>,
				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		adreno_smmu: iommu@50a0000 {
			compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu",
				     "qcom,smmu-500", "arm,mmu-500";
			reg = <0x0 0x050a0000 0x0 0x40000>;
			#iommu-cells = <2>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
			clock-names = "mem",
				      "hlos",
				      "iface";
			power-domains = <&gpucc CX_GDSC>;
			dma-coherent;
		};

		stm@6002000 {
			compatible = "arm,coresight-stm", "arm,primecell";
			reg = <0x0 0x06002000 0x0 0x1000>,
			      <0x0 0x16280000 0x0 0x180000>;
			reg-names = "stm-base",
				    "stm-stimulus-base";

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					stm_out: endpoint {
						remote-endpoint = <&funnel_in0_in7>;
					};
				};
			};
		};

		tpda@6004000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x06004000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					tpda_qdss_in0: endpoint {
						remote-endpoint = <&tpdm_center_out>;
					};
				};

				port@4 {
					reg = <4>;

					tpda_qdss_in4: endpoint {
						remote-endpoint = <&funnel_monaq_out>;
					};
				};

				port@5 {
					reg = <5>;

					tpda_qdss_in5: endpoint {
						remote-endpoint = <&funnel_ddr_0_out>;
					};
				};

				port@6 {
					reg = <6>;

					tpda_qdss_in6: endpoint {
						remote-endpoint = <&funnel_turing_out>;
					};
				};

				port@7 {
					reg = <7>;

					tpda_qdss_in7: endpoint {
						remote-endpoint = <&tpdm_vsense_out>;
					};
				};

				port@8 {
					reg = <8>;

					tpda_qdss_in8: endpoint {
						remote-endpoint = <&tpdm_dcc_out>;
					};
				};

				port@9 {
					reg = <9>;

					tpda_qdss_in9: endpoint {
						remote-endpoint = <&tpdm_prng_out>;
					};
				};

				port@b {
					reg = <11>;

					tpda_qdss_in11: endpoint {
						remote-endpoint = <&tpdm_qm_out>;
					};
				};

				port@c {
					reg = <12>;

					tpda_qdss_in12: endpoint {
						remote-endpoint = <&tpdm_west_out>;
					};
				};

				port@d {
					reg = <13>;

					tpda_qdss_in13: endpoint {
						remote-endpoint = <&tpdm_pimem_out>;
					};
				};
			};

			out-ports {
				port {
					tpda_qdss_out: endpoint {
						remote-endpoint = <&funnel_qatb_in>;
					};
				};
			};
		};

		funnel@6005000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x06005000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					funnel_qatb_in: endpoint {
						remote-endpoint = <&tpda_qdss_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_qatb_out: endpoint {
						remote-endpoint = <&funnel_in0_in6>;
					};
				};
			};
		};

		cti@6010000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06010000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6011000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06011000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6012000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06012000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6013000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06013000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6014000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06014000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6015000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06015000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6016000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06016000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6017000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06017000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6018000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06018000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6019000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06019000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@601a000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x0601a000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@601b000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x0601b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@601c000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x0601c000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@601d000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x0601d000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@601e000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x0601e000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@601f000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x0601f000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		funnel@6041000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x06041000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@6 {
					reg = <6>;

					funnel_in0_in6: endpoint {
						remote-endpoint = <&funnel_qatb_out>;
					};
				};

				port@7 {
					reg = <7>;

					funnel_in0_in7: endpoint {
						remote-endpoint = <&stm_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_in0_out: endpoint {
						remote-endpoint = <&funnel_merg_in0>;
					};
				};
			};
		};

		funnel@6042000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x06042000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@3 {
					reg = <3>;

					funnel_in1_in3: endpoint {
						remote-endpoint = <&replicator_swao_out0>;
					};
				};

				port@4 {
					reg = <4>;

					funnel_in1_in4: endpoint {
						remote-endpoint = <&tpdm_wcss_out>;
					};
				};

				port@7 {
					reg = <7>;

					funnel_in1_in7: endpoint {
						remote-endpoint = <&funnel_apss_merg_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_in1_out: endpoint {
						remote-endpoint = <&funnel_merg_in1>;
					};
				};
			};
		};

		funnel@6045000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x06045000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					funnel_merg_in0: endpoint {
						remote-endpoint = <&funnel_in0_out>;
					};
				};

				port@1 {
					reg = <1>;

					funnel_merg_in1: endpoint {
						remote-endpoint = <&funnel_in1_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_merg_out: endpoint {
						remote-endpoint = <&tmc_etf_in>;
					};
				};
			};
		};

		replicator@6046000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x0 0x06046000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					replicator0_in: endpoint {
						remote-endpoint = <&tmc_etf_out>;
					};
				};
			};

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					replicator0_out0: endpoint {
						remote-endpoint = <&tmc_etr_in>;
					};
				};

				port@1 {
					reg = <1>;

					replicator0_out1: endpoint {
						remote-endpoint = <&replicator1_in>;
					};
				};
			};
		};

		tmc@6047000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x0 0x06047000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tmc_etf_in: endpoint {
						remote-endpoint = <&funnel_merg_out>;
					};
				};
			};

			out-ports {
				port {
					tmc_etf_out: endpoint {
						remote-endpoint = <&replicator0_in>;
					};
				};
			};
		};

		tmc@6048000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x0 0x06048000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			iommus = <&apps_smmu 0x01e0 0x0>;
			arm,scatter-gather;

			in-ports {
				port {
					tmc_etr_in: endpoint {
						remote-endpoint = <&replicator0_out0>;
					};
				};
			};
		};

		replicator@604a000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x0 0x0604a000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
			status = "disabled";

			in-ports {
				port {
					replicator1_in: endpoint {
						remote-endpoint = <&replicator0_out1>;
					};
				};
			};

			out-ports {
				port {
					replicator1_out: endpoint {
						remote-endpoint = <&funnel_swao_in6>;
					};
				};
			};
		};

		cti@683b000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x0683b000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		tpdm@6840000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06840000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					tpdm_vsense_out: endpoint {
						remote-endpoint = <&tpda_qdss_in7>;
					};
				};
			};
		};

		tpdm@684c000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x0684c000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_prng_out: endpoint {
						remote-endpoint = <&tpda_qdss_in9>;
					};
				};
			};
		};

		tpdm@6850000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06850000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;
			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_pimem_out: endpoint {
						remote-endpoint = <&tpda_qdss_in13>;
					};
				};
			};
		};

		tpdm@6860000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06860000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_turing_out: endpoint {
						remote-endpoint = <&funnel_turing_in>;
					};
				};
			};
		};

		funnel@6861000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x06861000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					funnel_turing_in: endpoint {
						remote-endpoint = <&tpdm_turing_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_turing_out: endpoint {
						remote-endpoint = <&tpda_qdss_in6>;
					};
				};
			};
		};

		cti@6867000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06867000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		tpdm@6870000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06870000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					tpdm_dcc_out: endpoint {
						remote-endpoint = <&tpda_qdss_in8>;
					};
				};
			};
		};

		tpdm@699c000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x0699c000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;
			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					tpdm_wcss_out: endpoint {
						remote-endpoint = <&funnel_in1_in4>;
					};
				};
			};
		};

		tpdm@69c0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x069c0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_monaq_out: endpoint {
						remote-endpoint = <&funnel_monaq_in>;
					};
				};
			};
		};

		funnel@69c3000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x069c3000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					funnel_monaq_in: endpoint {
						remote-endpoint = <&tpdm_monaq_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_monaq_out: endpoint {
						remote-endpoint = <&tpda_qdss_in4>;
					};
				};
			};
		};

		tpdm@69d0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x069d0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					tpdm_qm_out: endpoint {
						remote-endpoint = <&tpda_qdss_in11>;
					};
				};
			};
		};

		tpdm@6a00000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06a00000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					tpdm_ddr_out: endpoint {
						remote-endpoint = <&funnel_ddr_0_in>;
					};
				};
			};
		};

		cti@6a02000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06a02000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6a03000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06a03000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6a10000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06a10000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6a11000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06a11000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		funnel@6a05000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x06a05000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					funnel_ddr_0_in: endpoint {
						remote-endpoint = <&tpdm_ddr_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_ddr_0_out: endpoint {
						remote-endpoint = <&tpda_qdss_in5>;
					};
				};
			};
		};

		tpda@6b01000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x06b01000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					tpda_swao_in0: endpoint {
						remote-endpoint = <&tpdm_swao0_out>;
					};
				};

				port@1 {
					reg = <1>;

					tpda_swao_in1: endpoint {
						remote-endpoint = <&tpdm_swao1_out>;
					};

				};
			};

			out-ports {
				port {
					tpda_swao_out: endpoint {
						remote-endpoint = <&funnel_swao_in7>;
					};
				};
			};
		};

		tpdm@6b02000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06b02000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					tpdm_swao0_out: endpoint {
						remote-endpoint = <&tpda_swao_in0>;
					};
				};
			};
		};

		tpdm@6b03000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06b03000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;
			status = "disabled";

			out-ports {
				port {
					tpdm_swao1_out: endpoint {
						remote-endpoint = <&tpda_swao_in1>;
					};
				};
			};
		};

		cti@6b04000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06b04000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6b05000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06b05000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6b06000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06b06000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6b07000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06b07000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		funnel@6b08000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x06b08000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@6 {
					reg = <6>;

					funnel_swao_in6: endpoint {
						remote-endpoint = <&replicator1_out>;
					};
				};

				port@7 {
					reg = <7>;

					funnel_swao_in7: endpoint {
						remote-endpoint = <&tpda_swao_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_swao_out: endpoint {
						remote-endpoint = <&tmc_etf_swao_in>;
					};
				};
			};
		};

		tmc@6b09000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x0 0x06b09000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tmc_etf_swao_in: endpoint {
						remote-endpoint = <&funnel_swao_out>;
					};
				};
			};

			out-ports {
				port {
					tmc_etf_swao_out: endpoint {
						remote-endpoint = <&replicator_swao_in>;
					};
				};
			};
		};

		replicator@6b0a000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x0 0x06b0a000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					replicator_swao_in: endpoint {
						remote-endpoint = <&tmc_etf_swao_out>;
					};
				};
			};

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					replicator_swao_out0: endpoint {
						remote-endpoint = <&funnel_in1_in3>;
					};
				};

				port@1 {
					reg = <1>;

					replicator_swao_out1: endpoint {
						remote-endpoint = <&eud_in>;
					};
				};
			};
		};

		cti@6b21000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06b21000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		tpdm@6b48000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06b48000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_west_out: endpoint {
						remote-endpoint = <&tpda_qdss_in12>;
					};
				};
			};
		};

		cti@6c13000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06c13000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			/* Not all required clocks can be enabled from the OS */
			status = "fail";
		};

		cti@6c20000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06c20000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		tpdm@6c28000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x06c28000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_center_out: endpoint {
						remote-endpoint = <&tpda_qdss_in0>;
					};
				};
			};
		};

		cti@6c29000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06c29000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@6c2a000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x06c2a000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@7020000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x07020000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		etm@7040000 {
			compatible = "arm,primecell";
			reg = <0x0 0x07040000 0x0 0x1000>;
			cpu = <&cpu0>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint = <&funnel_apss_in0>;
					};
				};
			};
		};

		cti@7120000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x07120000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		etm@7140000 {
			compatible = "arm,primecell";
			reg = <0x0 0x07140000 0x0 0x1000>;
			cpu = <&cpu1>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint = <&funnel_apss_in1>;
					};
				};
			};
		};

		cti@7220000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x07220000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		etm@7240000 {
			compatible = "arm,primecell";
			reg = <0x0 0x07240000 0x0 0x1000>;
			cpu = <&cpu2>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint = <&funnel_apss_in2>;
					};
				};
			};
		};

		cti@7320000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x07320000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		etm@7340000 {
			compatible = "arm,primecell";
			reg = <0x0 0x07340000 0x0 0x1000>;
			cpu = <&cpu3>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint = <&funnel_apss_in3>;
					};
				};
			};
		};

		cti@7420000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x07420000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		etm@7440000 {
			compatible = "arm,primecell";
			reg = <0x0 0x07440000 0x0 0x1000>;
			cpu = <&cpu4>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm4_out: endpoint {
						remote-endpoint = <&funnel_apss_in4>;
					};
				};
			};
		};

		cti@7520000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x07520000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		etm@7540000 {
			compatible = "arm,primecell";
			reg = <0x0 0x07540000 0x0 0x1000>;
			cpu = <&cpu5>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm5_out: endpoint {
						remote-endpoint = <&funnel_apss_in5>;
					};
				};
			};
		};

		cti@7620000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x07620000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		etm@7640000 {
			compatible = "arm,primecell";
			reg = <0x0 0x07640000 0x0 0x1000>;
			cpu = <&cpu6>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm6_out: endpoint {
						remote-endpoint = <&funnel_apss_in6>;
					};
				};
			};
		};

		cti@7720000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x07720000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		etm@7740000 {
			compatible = "arm,primecell";
			reg = <0x0 0x07740000 0x0 0x1000>;
			cpu = <&cpu7>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			arm,coresight-loses-context-with-cpu;
			qcom,skip-power-up;

			out-ports {
				port {
					etm7_out: endpoint {
						remote-endpoint = <&funnel_apss_in7>;
					};
				};
			};
		};

		funnel@7800000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x07800000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					funnel_apss_in0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};

				port@1 {
					reg = <1>;

					funnel_apss_in1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};

				port@2 {
					reg = <2>;

					funnel_apss_in2: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};

				port@3 {
					reg = <3>;

					funnel_apss_in3: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};

				port@4 {
					reg = <4>;

					funnel_apss_in4: endpoint {
						remote-endpoint = <&etm4_out>;
					};
				};

				port@5 {
					reg = <5>;

					funnel_apss_in5: endpoint {
						remote-endpoint = <&etm5_out>;
					};
				};

				port@6 {
					reg = <6>;

					funnel_apss_in6: endpoint {
						remote-endpoint = <&etm6_out>;
					};
				};

				port@7 {
					reg = <7>;

					funnel_apss_in7: endpoint {
						remote-endpoint = <&etm7_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_apss_out: endpoint {
						remote-endpoint = <&funnel_apss_merg_in0>;
					};
				};
			};
		};

		funnel@7810000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x0 0x07810000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					funnel_apss_merg_in0: endpoint {
						remote-endpoint = <&funnel_apss_out>;
					};
				};

				port@2 {
					reg = <2>;

					funnel_apss_merg_in2: endpoint {
						remote-endpoint = <&tpda_olc_out>;
					};
				};

				port@3 {
					reg = <3>;

					funnel_apss_merg_in3: endpoint {
						remote-endpoint = <&tpda_llm_silver_out>;
					};
				};

				port@4 {
					reg = <4>;

					funnel_apss_merg_in4: endpoint {
						remote-endpoint = <&tpda_llm_gold_out>;
					};
				};

				port@5 {
					reg = <5>;

					funnel_apss_merg_in5: endpoint {
						remote-endpoint = <&tpda_apss_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_apss_merg_out: endpoint {
						remote-endpoint = <&funnel_in1_in7>;
					};
				};
			};
		};

		tpdm@7830000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x07830000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <64>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_olc_out: endpoint {
						remote-endpoint = <&tpda_olc_in>;
					};
				};
			};
		};

		tpda@7832000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x07832000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tpda_olc_in: endpoint {
						remote-endpoint = <&tpdm_olc_out>;
					};
				};
			};

			out-ports {
				port {
					tpda_olc_out: endpoint {
						remote-endpoint = <&funnel_apss_merg_in2>;
					};
				};
			};
		};

		tpdm@7860000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x07860000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,dsb-element-bits = <32>;
			qcom,dsb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_apss_out: endpoint {
						remote-endpoint = <&tpda_apss_in>;
					};
				};
			};
		};

		tpda@7862000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x07862000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tpda_apss_in: endpoint {
						remote-endpoint = <&tpdm_apss_out>;
					};
				};
			};

			out-ports {
				port {
					tpda_apss_out: endpoint {
						remote-endpoint = <&funnel_apss_merg_in5>;
					};
				};
			};
		};

		tpdm@78a0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x078a0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_llm_silver_out: endpoint {
						remote-endpoint = <&tpda_llm_silver_in>;
					};
				};
			};
		};

		tpdm@78b0000 {
			compatible = "qcom,coresight-tpdm", "arm,primecell";
			reg = <0x0 0x078b0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			qcom,cmb-element-bits = <32>;
			qcom,cmb-msrs-num = <32>;

			out-ports {
				port {
					tpdm_llm_gold_out: endpoint {
						remote-endpoint = <&tpda_llm_gold_in>;
					};
				};
			};
		};

		tpda@78c0000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x078c0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tpda_llm_silver_in: endpoint {
						remote-endpoint = <&tpdm_llm_silver_out>;
					};
				};
			};

			out-ports {
				port {
					tpda_llm_silver_out: endpoint {
						remote-endpoint = <&funnel_apss_merg_in3>;
					};
				};
			};
		};

		tpda@78d0000 {
			compatible = "qcom,coresight-tpda", "arm,primecell";
			reg = <0x0 0x078d0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tpda_llm_gold_in: endpoint {
						remote-endpoint = <&tpdm_llm_gold_out>;
					};
				};
			};

			out-ports {
				port {
					tpda_llm_gold_out: endpoint {
						remote-endpoint = <&funnel_apss_merg_in4>;
					};
				};
			};
		};

		cti@78e0000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x078e0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@78f0000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x078f0000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		cti@7900000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x0 0x07900000 0x0 0x1000>;

			clocks = <&aoss_qmp>;
			clock-names = "apb_pclk";
		};

		remoteproc_cdsp: remoteproc@8300000 {
			compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas";
			reg = <0x0 0x08300000 0x0 0x4040>;

			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog",
					  "fatal",
					  "ready",
					  "handover",
					  "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_CX>;
			power-domain-names = "cx";

			memory-region = <&rproc_cdsp_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&cdsp_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING 0>;
				mboxes = <&apss_shared 4>;
				label = "cdsp";
				qcom,remote-pid = <5>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "cdsp";
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@1 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <1>;
						iommus = <&apps_smmu 0x1081 0x0>;
						dma-coherent;
					};

					compute-cb@2 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <2>;
						iommus = <&apps_smmu 0x1082 0x0>;
						dma-coherent;
					};

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x1083 0x0>;
						dma-coherent;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x1084 0x0>;
						dma-coherent;
					};

					compute-cb@5 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <5>;
						iommus = <&apps_smmu 0x1085 0x0>;
						dma-coherent;
					};

					compute-cb@6 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <6>;
						iommus = <&apps_smmu 0x1086 0x0>;
						dma-coherent;
					};
				};
			};
		};

		pmu@90b6300 {
			compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
			reg = <0x0 0x090b6300 0x0 0x600>;
			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;

			operating-points-v2 = <&cpu_bwmon_opp_table>;

			cpu_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-0 {
					opp-peak-kBps = <12896000>;
				};

				opp-1 {
					opp-peak-kBps = <14928000>;
				};
			};
		};

		pmu@90cd000 {
			compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
			reg = <0x0 0x090cd000 0x0 0x1000>;
			interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>;
			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;

			operating-points-v2 = <&llcc_bwmon_opp_table>;

			llcc_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-0 {
					opp-peak-kBps = <800000>;
				};

				opp-1 {
					opp-peak-kBps = <1200000>;
				};

				opp-2 {
					opp-peak-kBps = <1804800>;
				};

				opp-3 {
					opp-peak-kBps = <2188800>;
				};

				opp-4 {
					opp-peak-kBps = <2726400>;
				};

				opp-5 {
					opp-peak-kBps = <3072000>;
				};

				opp-6 {
					opp-peak-kBps = <4070400>;
				};

				opp-7 {
					opp-peak-kBps = <5414400>;
				};

				opp-8 {
					opp-peak-kBps = <6220800>;
				};
			};
		};

		sdhc_2: mmc@8804000 {
			compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
			reg = <0x0 0x08804000 0x0 0x1000>;
			reg-names = "hc";

			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
			interrupt-names = "hc_irq",
					  "pwr_irq";

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "iface",
				      "core",
				      "xo";

			power-domains = <&rpmhpd RPMHPD_CX>;
			operating-points-v2 = <&sdhc2_opp_table>;
			iommus = <&apps_smmu 0x02a0 0x0>;
			resets = <&gcc GCC_SDCC2_BCR>;
			interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "sdhc-ddr",
					     "cpu-sdhc";

			qcom,dll-config = <0x0007642c>;
			qcom,ddr-config = <0x80040868>;
			dma-coherent;

			status = "disabled";

			sdhc2_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-50000000 {
					opp-hz = /bits/ 64 <50000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>;
					required-opps = <&rpmhpd_opp_svs>;
				};

				opp-202000000 {
					opp-hz = /bits/ 64 <202000000>;
					required-opps = <&rpmhpd_opp_nom>;
				};
			};
		};

		dc_noc: interconnect@9160000 {
			reg = <0x0 0x09160000 0x0 0x3200>;
			compatible = "qcom,qcs615-dc-noc";
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		llcc: system-cache-controller@9200000 {
			compatible = "qcom,qcs615-llcc";
			reg = <0x0 0x09200000 0x0 0x50000>,
			      <0x0 0x09600000 0x0 0x50000>;
			reg-names = "llcc0_base",
				    "llcc_broadcast_base";
		};

		gem_noc: interconnect@9680000 {
			reg = <0x0 0x09680000 0x0 0x3e200>;
			compatible = "qcom,qcs615-gem-noc";
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		venus: video-codec@aa00000 {
			compatible = "qcom,qcs615-venus", "qcom,sc7180-venus";
			reg = <0x0 0x0aa00000 0x0 0x100000>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;

			clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
				 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
				 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
				 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
				 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
			clock-names = "core",
				      "iface",
				      "bus",
				      "vcodec0_core",
				      "vcodec0_bus";

			power-domains = <&videocc VENUS_GDSC>,
					<&videocc VCODEC0_GDSC>,
					<&rpmhpd RPMHPD_CX>;
			power-domain-names = "venus",
					     "vcodec0",
					     "cx";

			operating-points-v2 = <&venus_opp_table>;

			interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "video-mem",
					     "cpu-cfg";

			iommus = <&apps_smmu 0xe60 0x20>;

			memory-region = <&pil_video_mem>;

			status = "disabled";

			venus_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-133330000 {
					opp-hz = /bits/ 64 <133330000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-240000000 {
					opp-hz = /bits/ 64 <240000000>;
					required-opps = <&rpmhpd_opp_svs>;
				};

				opp-300000000 {
					opp-hz = /bits/ 64 <300000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
				};

				opp-380000000 {
					opp-hz = /bits/ 64 <380000000>;
					required-opps = <&rpmhpd_opp_nom>;
				};

				opp-410000000 {
					opp-hz = /bits/ 64 <410000000>;
					required-opps = <&rpmhpd_opp_nom_l1>;
				};

				opp-460000000 {
					opp-hz = /bits/ 64 <460000000>;
					required-opps = <&rpmhpd_opp_turbo>;
				};
			};
		};

		videocc: clock-controller@ab00000 {
			compatible = "qcom,qcs615-videocc";
			reg = <0 0x0ab00000 0 0x10000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&sleep_clk>;

			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		cci: cci@ac4a000 {
			compatible = "qcom,sm6150-cci", "qcom,msm8996-cci";

			reg = <0x0 0x0ac4a000 0x0 0x4000>;
			interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING 0>;
			power-domains = <&camcc TITAN_TOP_GDSC>;
			clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
				 <&camcc CAM_CC_CPAS_AHB_CLK>,
				 <&camcc CAM_CC_CCI_CLK>;
			clock-names = "camnoc_axi",
				      "cpas_ahb",
				      "cci";
			pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>;
			pinctrl-names = "default";

			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";

			cci_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <1000000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cci_i2c1: i2c-bus@1 {
				reg = <1>;
				clock-frequency = <1000000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		camss: isp@acb3000 {
			compatible = "qcom,sm6150-camss";

			reg = <0x0 0x0acb3000 0x0 0x1000>,
			      <0x0 0x0acba000 0x0 0x1000>,
			      <0x0 0x0acc8000 0x0 0x1000>,
			      <0x0 0x0ac65000 0x0 0x1000>,
			      <0x0 0x0ac66000 0x0 0x1000>,
			      <0x0 0x0ac67000 0x0 0x1000>,
			      <0x0 0x0acaf000 0x0 0x4000>,
			      <0x0 0x0acb6000 0x0 0x4000>,
			      <0x0 0x0acc4000 0x0 0x4000>,
			      <0x0 0x0ac6f000 0x0 0x3000>,
			      <0x0 0x0ac42000 0x0 0x5000>,
			      <0x0 0x0ac48000 0x0 0x1000>,
			      <0x0 0x0ac40000 0x0 0x1000>,
			      <0x0 0x0ac18000 0x0 0x3000>,
			      <0x0 0x0ac00000 0x0 0x6000>,
			      <0x0 0x0ac10000 0x0 0x8000>,
			      <0x0 0x0ac87000 0x0 0x3000>,
			      <0x0 0x0ac52000 0x0 0x4000>,
			      <0x0 0x0ac4e000 0x0 0x4000>,
			      <0x0 0x0ac6b000 0x0 0x0a00>;
			reg-names = "csid0",
				    "csid1",
				    "csid_lite",
				    "csiphy0",
				    "csiphy1",
				    "csiphy2",
				    "vfe0",
				    "vfe1",
				    "vfe_lite",
				    "bps",
				    "camnoc",
				    "cpas_cdm",
				    "cpas_top",
				    "icp_csr",
				    "icp_qgic",
				    "icp_sierra",
				    "ipe0",
				    "jpeg_dma",
				    "jpeg_enc",
				    "lrme";

			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
				 <&gcc GCC_CAMERA_HF_AXI_CLK>,
				 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
				 <&camcc CAM_CC_CPAS_AHB_CLK>,
				 <&camcc CAM_CC_CSIPHY0_CLK>,
				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
				 <&camcc CAM_CC_CSIPHY1_CLK>,
				 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
				 <&camcc CAM_CC_CSIPHY2_CLK>,
				 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
				 <&camcc CAM_CC_SOC_AHB_CLK>,
				 <&camcc CAM_CC_IFE_0_CLK>,
				 <&camcc CAM_CC_IFE_0_AXI_CLK>,
				 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
				 <&camcc CAM_CC_IFE_0_CSID_CLK>,
				 <&camcc CAM_CC_IFE_1_CLK>,
				 <&camcc CAM_CC_IFE_1_AXI_CLK>,
				 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
				 <&camcc CAM_CC_IFE_1_CSID_CLK>,
				 <&camcc CAM_CC_IFE_LITE_CLK>,
				 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
				 <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
				 <&camcc CAM_CC_BPS_CLK>,
				 <&camcc CAM_CC_BPS_AHB_CLK>,
				 <&camcc CAM_CC_BPS_AXI_CLK>,
				 <&camcc CAM_CC_BPS_AREG_CLK>,
				 <&camcc CAM_CC_ICP_CLK>,
				 <&camcc CAM_CC_IPE_0_CLK>,
				 <&camcc CAM_CC_IPE_0_AHB_CLK>,
				 <&camcc CAM_CC_IPE_0_AREG_CLK>,
				 <&camcc CAM_CC_IPE_0_AXI_CLK>,
				 <&camcc CAM_CC_JPEG_CLK>,
				 <&camcc CAM_CC_LRME_CLK>;
			clock-names = "gcc_ahb",
				      "gcc_axi_hf",
				      "camnoc_axi",
				      "cpas_ahb",
				      "csiphy0",
				      "csiphy0_timer",
				      "csiphy1",
				      "csiphy1_timer",
				      "csiphy2",
				      "csiphy2_timer",
				      "soc_ahb",
				      "vfe0",
				      "vfe0_axi",
				      "vfe0_cphy_rx",
				      "vfe0_csid",
				      "vfe1",
				      "vfe1_axi",
				      "vfe1_cphy_rx",
				      "vfe1_csid",
				      "vfe_lite",
				      "vfe_lite_cphy_rx",
				      "vfe_lite_csid",
				      "bps",
				      "bps_ahb",
				      "bps_axi",
				      "bps_areg",
				      "icp",
				      "ipe0",
				      "ipe0_ahb",
				      "ipe0_areg",
				      "ipe0_axi",
				      "jpeg",
				      "lrme";

			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
			interconnect-names = "ahb",
					     "hf_0",
					     "hf_1",
					     "sf_mnoc";

			interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 466 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 468 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 465 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 467 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 469 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 459 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 461 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 463 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 475 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 474 IRQ_TYPE_EDGE_RISING 0>,
				     <GIC_SPI 476 IRQ_TYPE_EDGE_RISING 0>;
			interrupt-names = "csid0",
					  "csid1",
					  "csid_lite",
					  "csiphy0",
					  "csiphy1",
					  "csiphy2",
					  "vfe0",
					  "vfe1",
					  "vfe_lite",
					  "camnoc",
					  "cdm",
					  "icp",
					  "jpeg_dma",
					  "jpeg_enc",
					  "lrme";

			iommus = <&apps_smmu 0x0820 0x40>,
				 <&apps_smmu 0x0840 0x00>,
				 <&apps_smmu 0x0860 0x40>,
				 <&apps_smmu 0x0c00 0x00>,
				 <&apps_smmu 0x0cc0 0x00>,
				 <&apps_smmu 0x0c80 0x00>,
				 <&apps_smmu 0x0ca0 0x00>,
				 <&apps_smmu 0x0d00 0x00>,
				 <&apps_smmu 0x0d20 0x00>,
				 <&apps_smmu 0x0d40 0x00>,
				 <&apps_smmu 0x0d80 0x20>,
				 <&apps_smmu 0x0da0 0x20>,
				 <&apps_smmu 0x0de2 0x00>;

			power-domains = <&camcc IFE_0_GDSC>,
					<&camcc IFE_1_GDSC>,
					<&camcc TITAN_TOP_GDSC>,
					<&camcc BPS_GDSC>,
					<&camcc IPE_0_GDSC>;
			power-domain-names = "ife0",
					     "ife1",
					     "top",
					     "bps",
					     "ipe";

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
				};

				port@1 {
					reg = <1>;
				};

				port@2 {
					reg = <2>;
				};
			};
		};

		camcc: clock-controller@ad00000 {
			compatible = "qcom,qcs615-camcc";
			reg = <0 0x0ad00000 0 0x10000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		mdss: display-subsystem@ae00000 {
			compatible = "qcom,sm6150-mdss";
			reg = <0x0 0x0ae00000 0x0 0x1000>;
			reg-names = "mdss";

			interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "mdp0-mem",
					     "cpu-cfg";

			power-domains = <&dispcc MDSS_CORE_GDSC>;

			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
				 <&gcc GCC_DISP_HF_AXI_CLK>,
				 <&dispcc DISP_CC_MDSS_MDP_CLK>;

			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
			interrupt-controller;
			#interrupt-cells = <1>;

			iommus = <&apps_smmu 0x800 0x0>;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			status = "disabled";

			mdss_mdp: display-controller@ae01000 {
				compatible = "qcom,sm6150-dpu";
				reg = <0x0 0x0ae01000 0x0 0x8f000>,
				      <0x0 0x0aeb0000 0x0 0x2008>;
				reg-names = "mdp",
					    "vbif";

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&gcc GCC_DISP_HF_AXI_CLK>,
					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
				clock-names = "iface",
					      "bus",
					      "core",
					      "vsync";

				operating-points-v2 = <&mdp_opp_table>;
				power-domains = <&rpmhpd RPMHPD_CX>;

				interrupts-extended = <&mdss 0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						dpu_intf0_out: endpoint {
							remote-endpoint = <&mdss_dp0_in>;
						};
					};

					port@1 {
						reg = <1>;

						dpu_intf1_out: endpoint {
							remote-endpoint = <&mdss_dsi0_in>;
						};
					};
				};

				mdp_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-192000000 {
						opp-hz = /bits/ 64 <192000000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-256000000 {
						opp-hz = /bits/ 64 <256000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-307200000 {
						opp-hz = /bits/ 64 <307200000>;
						required-opps = <&rpmhpd_opp_nom>;
					};
				};
			};

			mdss_dp0: displayport-controller@ae90000 {
				compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp";

				reg = <0x0 0x0ae90000 0x0 0x200>,
				      <0x0 0x0ae90200 0x0 0x200>,
				      <0x0 0x0ae90400 0x0 0x600>,
				      <0x0 0x0ae90a00 0x0 0x600>,
				      <0x0 0x0ae91000 0x0 0x600>;

				interrupt-parent = <&mdss>;
				interrupts = <12>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
					 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
					 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
					 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
				clock-names = "core_iface",
					      "core_aux",
					      "ctrl_link",
					      "ctrl_link_iface",
					      "stream_pixel",
					      "stream_1_pixel";

				assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
				assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>,
							 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>,
							 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>;

				phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>;
				phy-names = "dp";

				operating-points-v2 = <&dp_opp_table>;
				power-domains = <&rpmhpd RPMHPD_CX>;

				#sound-dai-cells = <0>;

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mdss_dp0_in: endpoint {
							remote-endpoint = <&dpu_intf0_out>;
						};
					};

					port@1 {
						reg = <1>;

						mdss_dp0_out: endpoint {
							data-lanes = <3 2 0 1>;
						};
					};
				};

				dp_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-162000000 {
						opp-hz = /bits/ 64 <162000000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-270000000 {
						opp-hz = /bits/ 64 <270000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-540000000 {
						opp-hz = /bits/ 64 <540000000>;
						required-opps = <&rpmhpd_opp_svs_l1>;
					};
				};
			};

			mdss_dsi0: dsi@ae94000 {
				compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
				reg = <0x0 0x0ae94000 0x0 0x400>;
				reg-names = "dsi_ctrl";

				interrupts-extended = <&mdss 4>;

				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&gcc GCC_DISP_HF_AXI_CLK>;
				clock-names = "byte",
					      "byte_intf",
					      "pixel",
					      "core",
					      "iface",
					      "bus";

				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
				assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
							 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;

				operating-points-v2 = <&dsi0_opp_table>;
				power-domains = <&rpmhpd RPMHPD_CX>;

				phys = <&mdss_dsi0_phy>;

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";

				dsi0_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-164000000 {
						opp-hz = /bits/ 64 <164000000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};
				};

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mdss_dsi0_in: endpoint {
							remote-endpoint = <&dpu_intf1_out>;
						};
					};

					port@1 {
						reg = <1>;

						mdss_dsi0_out: endpoint {
						};
					};
				};
			};

			mdss_dsi0_phy: phy@ae94400 {
				compatible = "qcom,sm6150-dsi-phy-14nm";
				reg = <0x0 0x0ae94400 0x0 0x100>,
				      <0x0 0x0ae94500 0x0 0x300>,
				      <0x0 0x0ae94800 0x0 0x124>;
				reg-names = "dsi_phy",
					    "dsi_phy_lane",
					    "dsi_pll";

				#clock-cells = <1>;
				#phy-cells = <0>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&rpmhcc RPMH_CXO_CLK>;
				clock-names = "iface",
					      "ref";

				status = "disabled";
			};
		};

		dispcc: clock-controller@af00000 {
			compatible = "qcom,qcs615-dispcc";
			reg = <0 0x0af00000 0 0x20000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
				 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
				 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
				 <0>,
				 <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>,
				 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>;

			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		pdc: interrupt-controller@b220000 {
			compatible = "qcom,qcs615-pdc", "qcom,pdc";
			reg = <0x0 0x0b220000 0x0 0x30000>,
			      <0x0 0x17c000f0 0x0 0x64>;
			qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
			interrupt-parent = <&intc>;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		aoss_qmp: power-management@c300000 {
			compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
			reg = <0x0 0x0c300000 0x0 0x400>;
			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING 0>;
			mboxes = <&apss_shared 0>;

			#clock-cells = <0>;
		};

		sram@c3f0000 {
			compatible = "qcom,rpmh-stats";
			reg = <0x0 0x0c3f0000 0x0 0x400>;
		};

		sram@14680000 {
			compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
			reg = <0x0 0x14680000 0x0 0x2c000>;
			ranges = <0 0 0x14680000 0x2c000>;

			#address-cells = <1>;
			#size-cells = <1>;

			pil-reloc@2a94c {
				compatible = "qcom,pil-reloc-info";
				reg = <0x2a94c 0xc8>;
			};
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
			reg = <0x0 0x15000000 0x0 0x80000>;
			#iommu-cells = <2>;
			#global-interrupts = <1>;
			dma-coherent;

			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
		};

		spmi_bus: spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x0 0x0c440000 0x0 0x1100>,
			      <0x0 0x0c600000 0x0 0x2000000>,
			      <0x0 0x0e600000 0x0 0x100000>,
			      <0x0 0x0e700000 0x0 0xa0000>,
			      <0x0 0x0c40a000 0x0 0x26000>;
			reg-names = "core",
				    "chnls",
				    "obsrvr",
				    "intr",
				    "cnfg";
			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "periph_irq";
			interrupt-controller;
			#interrupt-cells = <4>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,channel = <0>;
			qcom,ee = <0>;
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
			#address-cells = <0>;
			#interrupt-cells = <4>;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x20000>;

			ppi-partitions {
				ppi_cluster0: interrupt-partition-0 {
					affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
				};

				ppi_cluster1: interrupt-partition-1 {
					affinity = <&cpu6 &cpu7>;
				};
			};
		};

		apss_shared: mailbox@17c00000 {
			compatible = "qcom,qcs615-apss-shared",
				     "qcom,sdm845-apss-shared";
			reg = <0x0 0x17c00000 0x0 0x1000>;
			#mbox-cells = <1>;
		};

		watchdog: watchdog@17c10000 {
			compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
			reg = <0x0 0x17c10000 0x0 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&sleep_clk>;
		};

		timer@17c20000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0x0 0x17c20000 0x0 0x1000>;
			ranges = <0 0 0 0x20000000>;
			#address-cells = <1>;
			#size-cells = <1>;

			frame@17c21000 {
				reg = <0x17c21000 0x1000>,
				      <0x17c22000 0x1000>;
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
			};

			frame@17c23000 {
				reg = <0x17c23000 0x1000>;
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
				status = "disabled";
			};

			frame@17c25000 {
				reg = <0x17c25000 0x1000>;
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
				status = "disabled";
			};

			frame@17c27000 {
				reg = <0x17c27000 0x1000>;
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
				status = "disabled";
			};

			frame@17c29000 {
				reg = <0x17c29000 0x1000>;
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
				status = "disabled";
			};

			frame@17c2b000 {
				reg = <0x17c2b000 0x1000>;
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
				status = "disabled";
			};

			frame@17c2d000 {
				reg = <0x17c2d000 0x1000>;
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@18200000 {
			compatible = "qcom,rpmh-rsc";
			reg = <0x0 0x18200000 0x0 0x10000>,
			      <0x0 0x18210000 0x0 0x10000>,
			      <0x0 0x18220000 0x0 0x10000>;
			reg-names = "drv-0",
				    "drv-1",
				    "drv-2";

			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>;

			qcom,drv-id = <2>;
			qcom,tcs-offset = <0xd00>;
			qcom,tcs-config = <ACTIVE_TCS    2>,
					  <SLEEP_TCS     3>,
					  <WAKE_TCS      3>,
					  <CONTROL_TCS   1>;

			label = "apps_rsc";
			power-domains = <&cluster_pd>;

			apps_bcm_voter: bcm-voter {
				compatible = "qcom,bcm-voter";
			};

			rpmhcc: clock-controller {
				compatible = "qcom,qcs615-rpmh-clk";
				clocks = <&xo_board_clk>;
				clock-names = "xo";

				#clock-cells = <1>;
			};

			rpmhpd: power-controller {
				compatible = "qcom,qcs615-rpmhpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmhpd_opp_table>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp-0 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp-1 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs: opp-2 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_svs: opp-3 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l1: opp-4 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_nom: opp-5 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp-6 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp-7 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp-8 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp-9 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};
		};

		osm_l3: interconnect@18321000 {
			compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3";
			reg = <0x0 0x18321000 0x0 0x1400>;

			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
			clock-names = "xo", "alternate";

			#interconnect-cells = <1>;
		};

		usb_1_hsphy: phy@88e2000 {
			compatible = "qcom,qcs615-qusb2-phy";
			reg = <0x0 0x88e2000 0x0 0x180>;

			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "cfg_ahb", "ref";

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
			nvmem-cells = <&qusb2_hstx_trim>;

			#phy-cells = <0>;

			status = "disabled";
		};

		usb_2_hsphy: phy@88e3000 {
			compatible = "qcom,qcs615-qusb2-phy";
			reg = <0x0 0x088e3000 0x0 0x180>;

			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "cfg_ahb",
				      "ref";

			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

			#phy-cells = <0>;

			status = "disabled";
		};

		usb_qmpphy: phy@88e6000 {
			compatible = "qcom,qcs615-qmp-usb3-phy";
			reg = <0x0 0x88e6000 0x0 0x1000>;

			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
				 <&gcc GCC_AHB2PHY_WEST_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
			clock-names = "aux",
				      "ref",
				      "cfg_ahb",
				      "pipe";

			resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
				 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
			reset-names = "phy", "phy_phy";

			qcom,tcsr-reg = <&tcsr 0xb244>;

			clock-output-names = "usb3_phy_pipe_clk_src";
			#clock-cells = <0>;

			#phy-cells = <0>;

			status = "disabled";
		};

		usb_qmpphy_2: phy@88e8000 {
			compatible = "qcom,qcs615-qmp-usb3-dp-phy";
			reg = <0x0 0x088e8000 0x0 0x2000>;

			clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>,
				 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
				 <&gcc GCC_AHB2PHY_WEST_CLK>,
				 <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>;
			clock-names = "aux",
				      "ref",
				      "cfg_ahb",
				      "pipe";

			resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >,
				 <&gcc GCC_USB3_DP_PHY_SEC_BCR>;
			reset-names = "phy_phy",
				      "dp_phy";

			#clock-cells = <1>;
			#phy-cells = <1>;

			qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>;

			status = "disabled";
		};

		usb_1: usb@a600000 {
			compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3";
			reg = <0x0 0x0a600000 0x0 0xfc100>;

			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi",
				      "xo";

			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <200000000>;

			interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
					      <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
					      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
					      <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dwc_usb3",
					  "pwr_event",
					  "hs_phy_irq",
					  "dp_hs_phy_irq",
					  "dm_hs_phy_irq",
					  "ss_phy_irq";

			iommus = <&apps_smmu 0x140 0x0>;

			phys = <&usb_1_hsphy>, <&usb_qmpphy>;
			phy-names = "usb2-phy", "usb3-phy";

			power-domains = <&gcc USB30_PRIM_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			resets = <&gcc GCC_USB30_PRIM_BCR>;

			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis_u3_susphy_quirk;
			snps,dis_enblslpm_quirk;
			snps,has-lpm-erratum;
			snps,hird-threshold = /bits/ 8 <0x10>;
			snps,usb3_lpm_capable;

			wakeup-source;

			status = "disabled";
		};

		usb_2: usb@a800000 {
			compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3";
			reg = <0x0 0x0a800000 0x0 0xfc100>;

			clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>,
				 <&gcc GCC_USB20_SEC_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
				 <&gcc GCC_USB20_SEC_SLEEP_CLK>,
				 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB2_PRIM_CLKREF_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi",
				      "xo";

			assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB20_SEC_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <200000000>;

			interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>,
					      <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>,
					      <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>,
					      <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 10 IRQ_TYPE_EDGE_BOTH>;
			interrupt-names = "dwc_usb3",
					  "pwr_event",
					  "hs_phy_irq",
					  "dp_hs_phy_irq",
					  "dm_hs_phy_irq";

			iommus = <&apps_smmu 0xe0 0x0>;

			phys = <&usb_2_hsphy>;
			phy-names = "usb2-phy";

			power-domains = <&gcc USB20_SEC_GDSC>;
			required-opps = <&rpmhpd_opp_nom>;

			resets = <&gcc GCC_USB20_SEC_BCR>;

			qcom,select-utmi-as-pipe-clk;

			snps,dis_u2_susphy_quirk;
			snps,dis_u3_susphy_quirk;
			snps,dis_enblslpm_quirk;
			snps,has-lpm-erratum;
			snps,hird-threshold = /bits/ 8 <0x10>;

			maximum-speed = "high-speed";
			wakeup-source;

			status = "disabled";
		};

		tsens0: thermal-sensor@c263000 {
			compatible = "qcom,qcs615-tsens", "qcom,tsens-v2";
			reg = <0x0 0x0c263000 0x0 0x1000>,
			      <0x0 0x0c222000 0x0 0x1000>;
			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>,
				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>;
			interrupt-names = "uplow", "critical";
			#qcom,sensors = <16>;
			#thermal-sensor-cells = <1>;
		};

		remoteproc_adsp: remoteproc@62400000 {
			compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas";
			reg = <0x0 0x62400000 0x0 0x4040>;

			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>,
					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog",
					  "fatal",
					  "ready",
					  "handover",
					  "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_CX>;
			power-domain-names = "cx";

			memory-region = <&rproc_adsp_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&adsp_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink_edge: glink-edge {
				interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING 0>;
				mboxes = <&apss_shared 24>;
				label = "lpass";
				qcom,remote-pid = <2>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "adsp";
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x1723 0x0>;
						dma-coherent;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x1724 0x0>;
						dma-coherent;
					};

					compute-cb@5 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <5>;
						iommus = <&apps_smmu 0x1725 0x0>;
						dma-coherent;
					};

					compute-cb@6 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <6>;
						iommus = <&apps_smmu 0x1726 0x0>;
						qcom,nsessions = <5>;
						dma-coherent;
					};
				};
			};
		};

		cpufreq_hw: cpufreq@18323000 {
			compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw";
			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
			reg-names = "freq-domain0", "freq-domain1";

			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
			clock-names = "xo", "alternate";

			#freq-domain-cells = <1>;
			#clock-cells = <1>;
		};
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW 0>;
	};

	thermal-zones {
		aoss-thermal {
			thermal-sensors = <&tsens0 0>;

			trips {
				aoss-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss-0-thermal {
			thermal-sensors = <&tsens0 1>;

			trips {
				cpuss0-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss-1-thermal {
			thermal-sensors = <&tsens0 2>;

			trips {
				cpuss1-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss-2-thermal {
			thermal-sensors = <&tsens0 3>;

			trips {
				cpuss2-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpuss-3-thermal {
			thermal-sensors = <&tsens0 4>;

			trips {
				cpuss3-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu-1-0-thermal {
			thermal-sensors = <&tsens0 5>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu-1-1-thermal {
			thermal-sensors = <&tsens0 6>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu-1-2-thermal {
			thermal-sensors = <&tsens0 7>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu-1-3-thermal {
			thermal-sensors = <&tsens0 8>;

			trips {
				cpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		gpu-thermal {
			thermal-sensors = <&tsens0 9>;

			trips {
				gpu_alert0: trip-point0 {
					temperature = <105000>;
					hysteresis = <5000>;
					type = "passive";
				};

				gpu-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&gpu_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		q6-hvx-thermal {
			thermal-sensors = <&tsens0 10>;

			trips {
				q6-hvx-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		mdm-core-thermal {
			thermal-sensors = <&tsens0 11>;

			trips {
				mdm-core-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		camera-thermal {
			thermal-sensors = <&tsens0 12>;

			trips {
				camera-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		wlan-thermal {
			thermal-sensors = <&tsens0 13>;

			trips {
				wlan-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		display-thermal {
			thermal-sensors = <&tsens0 14>;

			trips {
				display-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		video-thermal {
			thermal-sensors = <&tsens0 15>;

			trips {
				video-critical {
					temperature = <115000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};
	};
};