1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <76800000>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32000>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo780"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 next-level-cache = <&L2_0>; 45 power-domains = <&CPU_PD0>; 46 power-domain-names = "psci"; 47 qcom,freq-domain = <&cpufreq_hw 0>; 48 L2_0: l2-cache { 49 compatible = "cache"; 50 next-level-cache = <&L3_0>; 51 L3_0: l3-cache { 52 compatible = "cache"; 53 }; 54 }; 55 }; 56 57 CPU1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "qcom,kryo780"; 60 reg = <0x0 0x100>; 61 enable-method = "psci"; 62 next-level-cache = <&L2_100>; 63 power-domains = <&CPU_PD1>; 64 power-domain-names = "psci"; 65 qcom,freq-domain = <&cpufreq_hw 0>; 66 L2_100: l2-cache { 67 compatible = "cache"; 68 next-level-cache = <&L3_0>; 69 }; 70 }; 71 72 CPU2: cpu@200 { 73 device_type = "cpu"; 74 compatible = "qcom,kryo780"; 75 reg = <0x0 0x200>; 76 enable-method = "psci"; 77 next-level-cache = <&L2_200>; 78 power-domains = <&CPU_PD2>; 79 power-domain-names = "psci"; 80 qcom,freq-domain = <&cpufreq_hw 0>; 81 L2_200: l2-cache { 82 compatible = "cache"; 83 next-level-cache = <&L3_0>; 84 }; 85 }; 86 87 CPU3: cpu@300 { 88 device_type = "cpu"; 89 compatible = "qcom,kryo780"; 90 reg = <0x0 0x300>; 91 enable-method = "psci"; 92 next-level-cache = <&L2_300>; 93 power-domains = <&CPU_PD3>; 94 power-domain-names = "psci"; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 L2_300: l2-cache { 97 compatible = "cache"; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU4: cpu@400 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo780"; 105 reg = <0x0 0x400>; 106 enable-method = "psci"; 107 next-level-cache = <&L2_400>; 108 power-domains = <&CPU_PD4>; 109 power-domain-names = "psci"; 110 qcom,freq-domain = <&cpufreq_hw 1>; 111 L2_400: l2-cache { 112 compatible = "cache"; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU5: cpu@500 { 118 device_type = "cpu"; 119 compatible = "qcom,kryo780"; 120 reg = <0x0 0x500>; 121 enable-method = "psci"; 122 next-level-cache = <&L2_500>; 123 power-domains = <&CPU_PD5>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 1>; 126 L2_500: l2-cache { 127 compatible = "cache"; 128 next-level-cache = <&L3_0>; 129 }; 130 131 }; 132 133 CPU6: cpu@600 { 134 device_type = "cpu"; 135 compatible = "qcom,kryo780"; 136 reg = <0x0 0x600>; 137 enable-method = "psci"; 138 next-level-cache = <&L2_600>; 139 power-domains = <&CPU_PD6>; 140 power-domain-names = "psci"; 141 qcom,freq-domain = <&cpufreq_hw 1>; 142 L2_600: l2-cache { 143 compatible = "cache"; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU7: cpu@700 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo780"; 151 reg = <0x0 0x700>; 152 enable-method = "psci"; 153 next-level-cache = <&L2_700>; 154 power-domains = <&CPU_PD7>; 155 power-domain-names = "psci"; 156 qcom,freq-domain = <&cpufreq_hw 2>; 157 L2_700: l2-cache { 158 compatible = "cache"; 159 next-level-cache = <&L3_0>; 160 }; 161 }; 162 163 cpu-map { 164 cluster0 { 165 core0 { 166 cpu = <&CPU0>; 167 }; 168 169 core1 { 170 cpu = <&CPU1>; 171 }; 172 173 core2 { 174 cpu = <&CPU2>; 175 }; 176 177 core3 { 178 cpu = <&CPU3>; 179 }; 180 181 core4 { 182 cpu = <&CPU4>; 183 }; 184 185 core5 { 186 cpu = <&CPU5>; 187 }; 188 189 core6 { 190 cpu = <&CPU6>; 191 }; 192 193 core7 { 194 cpu = <&CPU7>; 195 }; 196 }; 197 }; 198 199 idle-states { 200 entry-method = "psci"; 201 202 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 203 compatible = "arm,idle-state"; 204 idle-state-name = "silver-rail-power-collapse"; 205 arm,psci-suspend-param = <0x40000004>; 206 entry-latency-us = <274>; 207 exit-latency-us = <480>; 208 min-residency-us = <3934>; 209 local-timer-stop; 210 }; 211 212 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 213 compatible = "arm,idle-state"; 214 idle-state-name = "gold-rail-power-collapse"; 215 arm,psci-suspend-param = <0x40000004>; 216 entry-latency-us = <327>; 217 exit-latency-us = <1502>; 218 min-residency-us = <4488>; 219 local-timer-stop; 220 }; 221 }; 222 223 domain-idle-states { 224 CLUSTER_SLEEP_0: cluster-sleep-0 { 225 compatible = "domain-idle-state"; 226 idle-state-name = "cluster-l3-off"; 227 arm,psci-suspend-param = <0x4100c344>; 228 entry-latency-us = <584>; 229 exit-latency-us = <2332>; 230 min-residency-us = <6118>; 231 local-timer-stop; 232 }; 233 234 CLUSTER_SLEEP_1: cluster-sleep-1 { 235 compatible = "domain-idle-state"; 236 idle-state-name = "cluster-power-collapse"; 237 arm,psci-suspend-param = <0x4100c344>; 238 entry-latency-us = <2893>; 239 exit-latency-us = <4023>; 240 min-residency-us = <9987>; 241 local-timer-stop; 242 }; 243 }; 244 }; 245 246 firmware { 247 scm: scm { 248 compatible = "qcom,scm-sm8450", "qcom,scm"; 249 #reset-cells = <1>; 250 }; 251 }; 252 253 memory@a0000000 { 254 device_type = "memory"; 255 /* We expect the bootloader to fill in the size */ 256 reg = <0x0 0xa0000000 0x0 0x0>; 257 }; 258 259 pmu { 260 compatible = "arm,armv8-pmuv3"; 261 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 262 }; 263 264 psci { 265 compatible = "arm,psci-1.0"; 266 method = "smc"; 267 268 CPU_PD0: cpu0 { 269 #power-domain-cells = <0>; 270 power-domains = <&CLUSTER_PD>; 271 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 272 }; 273 274 CPU_PD1: cpu1 { 275 #power-domain-cells = <0>; 276 power-domains = <&CLUSTER_PD>; 277 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 278 }; 279 280 CPU_PD2: cpu2 { 281 #power-domain-cells = <0>; 282 power-domains = <&CLUSTER_PD>; 283 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 284 }; 285 286 CPU_PD3: cpu3 { 287 #power-domain-cells = <0>; 288 power-domains = <&CLUSTER_PD>; 289 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 290 }; 291 292 CPU_PD4: cpu4 { 293 #power-domain-cells = <0>; 294 power-domains = <&CLUSTER_PD>; 295 domain-idle-states = <&BIG_CPU_SLEEP_0>; 296 }; 297 298 CPU_PD5: cpu5 { 299 #power-domain-cells = <0>; 300 power-domains = <&CLUSTER_PD>; 301 domain-idle-states = <&BIG_CPU_SLEEP_0>; 302 }; 303 304 CPU_PD6: cpu6 { 305 #power-domain-cells = <0>; 306 power-domains = <&CLUSTER_PD>; 307 domain-idle-states = <&BIG_CPU_SLEEP_0>; 308 }; 309 310 CPU_PD7: cpu7 { 311 #power-domain-cells = <0>; 312 power-domains = <&CLUSTER_PD>; 313 domain-idle-states = <&BIG_CPU_SLEEP_0>; 314 }; 315 316 CLUSTER_PD: cpu-cluster0 { 317 #power-domain-cells = <0>; 318 domain-idle-states = <&CLUSTER_SLEEP_0>; 319 }; 320 }; 321 322 reserved_memory: reserved-memory { 323 #address-cells = <2>; 324 #size-cells = <2>; 325 ranges; 326 327 hyp_mem: memory@80000000 { 328 reg = <0x0 0x80000000 0x0 0x600000>; 329 no-map; 330 }; 331 332 xbl_dt_log_mem: memory@80600000 { 333 reg = <0x0 0x80600000 0x0 0x40000>; 334 no-map; 335 }; 336 337 xbl_ramdump_mem: memory@80640000 { 338 reg = <0x0 0x80640000 0x0 0x180000>; 339 no-map; 340 }; 341 342 xbl_sc_mem: memory@807c0000 { 343 reg = <0x0 0x807c0000 0x0 0x40000>; 344 no-map; 345 }; 346 347 aop_image_mem: memory@80800000 { 348 reg = <0x0 0x80800000 0x0 0x60000>; 349 no-map; 350 }; 351 352 aop_cmd_db_mem: memory@80860000 { 353 compatible = "qcom,cmd-db"; 354 reg = <0x0 0x80860000 0x0 0x20000>; 355 no-map; 356 }; 357 358 aop_config_mem: memory@80880000 { 359 reg = <0x0 0x80880000 0x0 0x20000>; 360 no-map; 361 }; 362 363 tme_crash_dump_mem: memory@808a0000 { 364 reg = <0x0 0x808a0000 0x0 0x40000>; 365 no-map; 366 }; 367 368 tme_log_mem: memory@808e0000 { 369 reg = <0x0 0x808e0000 0x0 0x4000>; 370 no-map; 371 }; 372 373 uefi_log_mem: memory@808e4000 { 374 reg = <0x0 0x808e4000 0x0 0x10000>; 375 no-map; 376 }; 377 378 /* secdata region can be reused by apps */ 379 smem: memory@80900000 { 380 compatible = "qcom,smem"; 381 reg = <0x0 0x80900000 0x0 0x200000>; 382 hwlocks = <&tcsr_mutex 3>; 383 no-map; 384 }; 385 386 cpucp_fw_mem: memory@80b00000 { 387 reg = <0x0 0x80b00000 0x0 0x100000>; 388 no-map; 389 }; 390 391 cdsp_secure_heap: memory@80c00000 { 392 reg = <0x0 0x80c00000 0x0 0x4600000>; 393 no-map; 394 }; 395 396 camera_mem: memory@85200000 { 397 reg = <0x0 0x85200000 0x0 0x500000>; 398 no-map; 399 }; 400 401 video_mem: memory@85700000 { 402 reg = <0x0 0x85700000 0x0 0x700000>; 403 no-map; 404 }; 405 406 adsp_mem: memory@85e00000 { 407 reg = <0x0 0x85e00000 0x0 0x2100000>; 408 no-map; 409 }; 410 411 slpi_mem: memory@88000000 { 412 reg = <0x0 0x88000000 0x0 0x1900000>; 413 no-map; 414 }; 415 416 cdsp_mem: memory@89900000 { 417 reg = <0x0 0x89900000 0x0 0x2000000>; 418 no-map; 419 }; 420 421 ipa_fw_mem: memory@8b900000 { 422 reg = <0x0 0x8b900000 0x0 0x10000>; 423 no-map; 424 }; 425 426 ipa_gsi_mem: memory@8b910000 { 427 reg = <0x0 0x8b910000 0x0 0xa000>; 428 no-map; 429 }; 430 431 gpu_micro_code_mem: memory@8b91a000 { 432 reg = <0x0 0x8b91a000 0x0 0x2000>; 433 no-map; 434 }; 435 436 spss_region_mem: memory@8ba00000 { 437 reg = <0x0 0x8ba00000 0x0 0x180000>; 438 no-map; 439 }; 440 441 /* First part of the "SPU secure shared memory" region */ 442 spu_tz_shared_mem: memory@8bb80000 { 443 reg = <0x0 0x8bb80000 0x0 0x60000>; 444 no-map; 445 }; 446 447 /* Second part of the "SPU secure shared memory" region */ 448 spu_modem_shared_mem: memory@8bbe0000 { 449 reg = <0x0 0x8bbe0000 0x0 0x20000>; 450 no-map; 451 }; 452 453 mpss_mem: memory@8bc00000 { 454 reg = <0x0 0x8bc00000 0x0 0x13200000>; 455 no-map; 456 }; 457 458 cvp_mem: memory@9ee00000 { 459 reg = <0x0 0x9ee00000 0x0 0x700000>; 460 no-map; 461 }; 462 463 global_sync_mem: memory@a6f00000 { 464 reg = <0x0 0xa6f00000 0x0 0x100000>; 465 no-map; 466 }; 467 468 /* uefi region can be reused by APPS */ 469 470 /* Linux kernel image is loaded at 0xa0000000 */ 471 472 oem_vm_mem: memory@bb000000 { 473 reg = <0x0 0xbb000000 0x0 0x5000000>; 474 no-map; 475 }; 476 477 mte_mem: memory@c0000000 { 478 reg = <0x0 0xc0000000 0x0 0x20000000>; 479 no-map; 480 }; 481 482 qheebsp_reserved_mem: memory@e0000000 { 483 reg = <0x0 0xe0000000 0x0 0x600000>; 484 no-map; 485 }; 486 487 cpusys_vm_mem: memory@e0600000 { 488 reg = <0x0 0xe0600000 0x0 0x400000>; 489 no-map; 490 }; 491 492 hyp_reserved_mem: memory@e0a00000 { 493 reg = <0x0 0xe0a00000 0x0 0x100000>; 494 no-map; 495 }; 496 497 trust_ui_vm_mem: memory@e0b00000 { 498 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 499 no-map; 500 }; 501 502 trust_ui_vm_qrtr: memory@e55f3000 { 503 reg = <0x0 0xe55f3000 0x0 0x9000>; 504 no-map; 505 }; 506 507 trust_ui_vm_vblk0_ring: memory@e55fc000 { 508 reg = <0x0 0xe55fc000 0x0 0x4000>; 509 no-map; 510 }; 511 512 trust_ui_vm_swiotlb: memory@e5600000 { 513 reg = <0x0 0xe5600000 0x0 0x100000>; 514 no-map; 515 }; 516 517 tz_stat_mem: memory@e8800000 { 518 reg = <0x0 0xe8800000 0x0 0x100000>; 519 no-map; 520 }; 521 522 tags_mem: memory@e8900000 { 523 reg = <0x0 0xe8900000 0x0 0x1200000>; 524 no-map; 525 }; 526 527 qtee_mem: memory@e9b00000 { 528 reg = <0x0 0xe9b00000 0x0 0x500000>; 529 no-map; 530 }; 531 532 trusted_apps_mem: memory@ea000000 { 533 reg = <0x0 0xea000000 0x0 0x3900000>; 534 no-map; 535 }; 536 537 trusted_apps_ext_mem: memory@ed900000 { 538 reg = <0x0 0xed900000 0x0 0x3b00000>; 539 no-map; 540 }; 541 }; 542 543 soc: soc@0 { 544 #address-cells = <2>; 545 #size-cells = <2>; 546 ranges = <0 0 0 0 0x10 0>; 547 dma-ranges = <0 0 0 0 0x10 0>; 548 compatible = "simple-bus"; 549 550 gcc: clock-controller@100000 { 551 compatible = "qcom,gcc-sm8450"; 552 reg = <0x0 0x00100000 0x0 0x1f4200>; 553 #clock-cells = <1>; 554 #reset-cells = <1>; 555 #power-domain-cells = <1>; 556 clock-names = "bi_tcxo", "sleep_clk"; 557 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 558 }; 559 560 qupv3_id_0: geniqup@9c0000 { 561 compatible = "qcom,geni-se-qup"; 562 reg = <0x0 0x009c0000 0x0 0x2000>; 563 clock-names = "m-ahb", "s-ahb"; 564 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 565 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 566 #address-cells = <2>; 567 #size-cells = <2>; 568 ranges; 569 status = "disabled"; 570 571 uart7: serial@99c000 { 572 compatible = "qcom,geni-debug-uart"; 573 reg = <0 0x0099c000 0 0x4000>; 574 clock-names = "se"; 575 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 578 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 }; 583 }; 584 585 qupv3_id_1: geniqup@ac0000 { 586 compatible = "qcom,geni-se-qup"; 587 reg = <0x0 0x00ac0000 0x0 0x6000>; 588 clock-names = "m-ahb", "s-ahb"; 589 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 590 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 591 #address-cells = <2>; 592 #size-cells = <2>; 593 ranges; 594 status = "disabled"; 595 596 i2c13: i2c@a94000 { 597 compatible = "qcom,geni-i2c"; 598 reg = <0 0x00a94000 0 0x4000>; 599 clock-names = "se"; 600 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&qup_i2c13_data_clk>; 603 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 status = "disabled"; 607 }; 608 609 i2c14: i2c@a98000 { 610 compatible = "qcom,geni-i2c"; 611 reg = <0 0x00a98000 0 0x4000>; 612 clock-names = "se"; 613 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&qup_i2c14_data_clk>; 616 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 status = "disabled"; 620 }; 621 }; 622 623 tcsr_mutex: hwlock@1f40000 { 624 compatible = "qcom,tcsr-mutex"; 625 reg = <0x0 0x01f40000 0x0 0x40000>; 626 #hwlock-cells = <1>; 627 }; 628 629 usb_1_hsphy: phy@88e3000 { 630 compatible = "qcom,sm8450-usb-hs-phy", 631 "qcom,usb-snps-hs-7nm-phy"; 632 reg = <0 0x088e3000 0 0x400>; 633 status = "disabled"; 634 #phy-cells = <0>; 635 636 clocks = <&rpmhcc RPMH_CXO_CLK>; 637 clock-names = "ref"; 638 639 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 640 }; 641 642 usb_1_qmpphy: phy-wrapper@88e9000 { 643 compatible = "qcom,sm8450-qmp-usb3-phy"; 644 reg = <0 0x088e9000 0 0x200>, 645 <0 0x088e8000 0 0x20>; 646 status = "disabled"; 647 #address-cells = <2>; 648 #size-cells = <2>; 649 ranges; 650 651 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 652 <&rpmhcc RPMH_CXO_CLK>, 653 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 654 clock-names = "aux", "ref_clk_src", "com_aux"; 655 656 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 657 <&gcc GCC_USB3_PHY_PRIM_BCR>; 658 reset-names = "phy", "common"; 659 660 usb_1_ssphy: phy@88e9200 { 661 reg = <0 0x088e9200 0 0x200>, 662 <0 0x088e9400 0 0x200>, 663 <0 0x088e9c00 0 0x400>, 664 <0 0x088e9600 0 0x200>, 665 <0 0x088e9800 0 0x200>, 666 <0 0x088e9a00 0 0x100>; 667 #phy-cells = <0>; 668 #clock-cells = <1>; 669 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 670 clock-names = "pipe0"; 671 clock-output-names = "usb3_phy_pipe_clk_src"; 672 }; 673 }; 674 675 pdc: interrupt-controller@b220000 { 676 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 677 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 678 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 679 <94 609 31>, <125 63 1>, <126 716 12>; 680 #interrupt-cells = <2>; 681 interrupt-parent = <&intc>; 682 interrupt-controller; 683 }; 684 685 tlmm: pinctrl@f100000 { 686 compatible = "qcom,sm8450-tlmm"; 687 reg = <0 0x0f100000 0 0x300000>; 688 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 689 gpio-controller; 690 #gpio-cells = <2>; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 gpio-ranges = <&tlmm 0 0 211>; 694 wakeup-parent = <&pdc>; 695 696 qup_i2c13_data_clk: qup-i2c13-data-clk { 697 pins = "gpio48", "gpio49"; 698 function = "qup13"; 699 drive-strength = <2>; 700 bias-pull-up; 701 }; 702 703 qup_i2c14_data_clk: qup-i2c14-data-clk { 704 pins = "gpio52", "gpio53"; 705 function = "qup14"; 706 drive-strength = <2>; 707 bias-pull-up; 708 }; 709 710 qup_uart7_rx: qup-uart7-rx { 711 pins = "gpio26"; 712 function = "qup7"; 713 drive-strength = <2>; 714 bias-disable; 715 }; 716 717 qup_uart7_tx: qup-uart7-tx { 718 pins = "gpio27"; 719 function = "qup7"; 720 drive-strength = <2>; 721 bias-disable; 722 }; 723 }; 724 725 apps_smmu: iommu@15000000 { 726 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 727 reg = <0 0x15000000 0 0x100000>; 728 #iommu-cells = <2>; 729 #global-interrupts = <1>; 730 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 827 }; 828 829 intc: interrupt-controller@17100000 { 830 compatible = "arm,gic-v3"; 831 #interrupt-cells = <3>; 832 interrupt-controller; 833 #redistributor-regions = <1>; 834 redistributor-stride = <0x0 0x40000>; 835 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 836 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 837 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 838 }; 839 840 timer@17420000 { 841 compatible = "arm,armv7-timer-mem"; 842 #address-cells = <2>; 843 #size-cells = <2>; 844 ranges; 845 reg = <0x0 0x17420000 0x0 0x1000>; 846 clock-frequency = <19200000>; 847 848 frame@17421000 { 849 frame-number = <0>; 850 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 852 reg = <0x0 0x17421000 0x0 0x1000>, 853 <0x0 0x17422000 0x0 0x1000>; 854 }; 855 856 frame@17423000 { 857 frame-number = <1>; 858 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 859 reg = <0x0 0x17423000 0x0 0x1000>; 860 status = "disabled"; 861 }; 862 863 frame@17425000 { 864 frame-number = <2>; 865 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 866 reg = <0x0 0x17425000 0x0 0x1000>; 867 status = "disabled"; 868 }; 869 870 frame@17427000 { 871 frame-number = <3>; 872 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 873 reg = <0x0 0x17427000 0x0 0x1000>; 874 status = "disabled"; 875 }; 876 877 frame@17429000 { 878 frame-number = <4>; 879 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 880 reg = <0x0 0x17429000 0x0 0x1000>; 881 status = "disabled"; 882 }; 883 884 frame@1742b000 { 885 frame-number = <5>; 886 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 887 reg = <0x0 0x1742b000 0x0 0x1000>; 888 status = "disabled"; 889 }; 890 891 frame@1742d000 { 892 frame-number = <6>; 893 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 894 reg = <0x0 0x1742d000 0x0 0x1000>; 895 status = "disabled"; 896 }; 897 }; 898 899 apps_rsc: rsc@17a00000 { 900 label = "apps_rsc"; 901 compatible = "qcom,rpmh-rsc"; 902 reg = <0x0 0x17a00000 0x0 0x10000>, 903 <0x0 0x17a10000 0x0 0x10000>, 904 <0x0 0x17a20000 0x0 0x10000>, 905 <0x0 0x17a30000 0x0 0x10000>; 906 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 907 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 910 qcom,tcs-offset = <0xd00>; 911 qcom,drv-id = <2>; 912 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 913 <WAKE_TCS 2>, <CONTROL_TCS 0>; 914 915 apps_bcm_voter: bcm-voter { 916 compatible = "qcom,bcm-voter"; 917 }; 918 919 rpmhcc: clock-controller { 920 compatible = "qcom,sm8450-rpmh-clk"; 921 #clock-cells = <1>; 922 clock-names = "xo"; 923 clocks = <&xo_board>; 924 }; 925 926 rpmhpd: power-controller { 927 compatible = "qcom,sm8450-rpmhpd"; 928 #power-domain-cells = <1>; 929 operating-points-v2 = <&rpmhpd_opp_table>; 930 931 rpmhpd_opp_table: opp-table { 932 compatible = "operating-points-v2"; 933 934 rpmhpd_opp_ret: opp1 { 935 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 936 }; 937 938 rpmhpd_opp_min_svs: opp2 { 939 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 940 }; 941 942 rpmhpd_opp_low_svs: opp3 { 943 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 944 }; 945 946 rpmhpd_opp_svs: opp4 { 947 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 948 }; 949 950 rpmhpd_opp_svs_l1: opp5 { 951 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 952 }; 953 954 rpmhpd_opp_nom: opp6 { 955 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 956 }; 957 958 rpmhpd_opp_nom_l1: opp7 { 959 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 960 }; 961 962 rpmhpd_opp_nom_l2: opp8 { 963 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 964 }; 965 966 rpmhpd_opp_turbo: opp9 { 967 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 968 }; 969 970 rpmhpd_opp_turbo_l1: opp10 { 971 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 972 }; 973 }; 974 }; 975 }; 976 977 cpufreq_hw: cpufreq@17d91000 { 978 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 979 reg = <0 0x17d91000 0 0x1000>, 980 <0 0x17d92000 0 0x1000>, 981 <0 0x17d93000 0 0x1000>; 982 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 983 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 984 clock-names = "xo", "alternate"; 985 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 988 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 989 #freq-domain-cells = <1>; 990 }; 991 992 ufs_mem_hc: ufshc@1d84000 { 993 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 994 "jedec,ufs-2.0"; 995 reg = <0 0x01d84000 0 0x3000>; 996 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 997 phys = <&ufs_mem_phy_lanes>; 998 phy-names = "ufsphy"; 999 lanes-per-direction = <2>; 1000 #reset-cells = <1>; 1001 resets = <&gcc GCC_UFS_PHY_BCR>; 1002 reset-names = "rst"; 1003 1004 power-domains = <&gcc UFS_PHY_GDSC>; 1005 1006 iommus = <&apps_smmu 0xe0 0x0>; 1007 1008 clock-names = 1009 "core_clk", 1010 "bus_aggr_clk", 1011 "iface_clk", 1012 "core_clk_unipro", 1013 "ref_clk", 1014 "tx_lane0_sync_clk", 1015 "rx_lane0_sync_clk", 1016 "rx_lane1_sync_clk"; 1017 clocks = 1018 <&gcc GCC_UFS_PHY_AXI_CLK>, 1019 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1020 <&gcc GCC_UFS_PHY_AHB_CLK>, 1021 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1022 <&rpmhcc RPMH_CXO_CLK>, 1023 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1024 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1025 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1026 freq-table-hz = 1027 <75000000 300000000>, 1028 <0 0>, 1029 <0 0>, 1030 <75000000 300000000>, 1031 <75000000 300000000>, 1032 <0 0>, 1033 <0 0>, 1034 <0 0>; 1035 status = "disabled"; 1036 }; 1037 1038 ufs_mem_phy: phy@1d87000 { 1039 compatible = "qcom,sm8450-qmp-ufs-phy"; 1040 reg = <0 0x01d87000 0 0xe10>; 1041 #address-cells = <2>; 1042 #size-cells = <2>; 1043 ranges; 1044 clock-names = "ref", "ref_aux", "qref"; 1045 clocks = <&rpmhcc RPMH_CXO_CLK>, 1046 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1047 <&gcc GCC_UFS_0_CLKREF_EN>; 1048 1049 resets = <&ufs_mem_hc 0>; 1050 reset-names = "ufsphy"; 1051 status = "disabled"; 1052 1053 ufs_mem_phy_lanes: lanes@1d87400 { 1054 reg = <0 0x01d87400 0 0x108>, 1055 <0 0x01d87600 0 0x1e0>, 1056 <0 0x01d87c00 0 0x1dc>, 1057 <0 0x01d87800 0 0x108>, 1058 <0 0x01d87a00 0 0x1e0>; 1059 #phy-cells = <0>; 1060 #clock-cells = <0>; 1061 }; 1062 }; 1063 1064 usb_1: usb@a6f8800 { 1065 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 1066 reg = <0 0x0a6f8800 0 0x400>; 1067 status = "disabled"; 1068 #address-cells = <2>; 1069 #size-cells = <2>; 1070 ranges; 1071 1072 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1073 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1074 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1075 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1076 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1077 <&gcc GCC_USB3_0_CLKREF_EN>; 1078 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1079 "sleep", "xo"; 1080 1081 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1082 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1083 assigned-clock-rates = <19200000>, <200000000>; 1084 1085 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1086 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1087 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1088 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1089 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1090 "dm_hs_phy_irq", "ss_phy_irq"; 1091 1092 power-domains = <&gcc USB30_PRIM_GDSC>; 1093 1094 resets = <&gcc GCC_USB30_PRIM_BCR>; 1095 1096 usb_1_dwc3: usb@a600000 { 1097 compatible = "snps,dwc3"; 1098 reg = <0 0x0a600000 0 0xcd00>; 1099 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1100 iommus = <&apps_smmu 0x0 0x0>; 1101 snps,dis_u2_susphy_quirk; 1102 snps,dis_enblslpm_quirk; 1103 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1104 phy-names = "usb2-phy", "usb3-phy"; 1105 }; 1106 }; 1107 }; 1108 1109 timer { 1110 compatible = "arm,armv8-timer"; 1111 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1114 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1115 clock-frequency = <19200000>; 1116 }; 1117}; 1118