xref: /freebsd/sys/contrib/device-tree/src/arm64/qcom/sm8350.dtsi (revision e67e85659c0de33e617e5fbf1028c6e8b49eee53) 
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, Linaro Limited
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,gcc-sm8350.h>
8#include <dt-bindings/clock/qcom,rpmh.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interconnect/qcom,sm8350.h>
11#include <dt-bindings/mailbox/qcom-ipcc.h>
12#include <dt-bindings/power/qcom-rpmpd.h>
13#include <dt-bindings/soc/qcom,rpmh-rsc.h>
14#include <dt-bindings/thermal/thermal.h>
15#include <dt-bindings/interconnect/qcom,sm8350.h>
16
17/ {
18	interrupt-parent = <&intc>;
19
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	chosen { };
24
25	clocks {
26		xo_board: xo-board {
27			compatible = "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <38400000>;
30			clock-output-names = "xo_board";
31		};
32
33		sleep_clk: sleep-clk {
34			compatible = "fixed-clock";
35			clock-frequency = <32000>;
36			#clock-cells = <0>;
37		};
38
39		ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
40			compatible = "fixed-clock";
41			clock-frequency = <1000>;
42			#clock-cells = <0>;
43		};
44
45		ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
46			compatible = "fixed-clock";
47			clock-frequency = <1000>;
48			#clock-cells = <0>;
49		};
50
51		ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
52			compatible = "fixed-clock";
53			clock-frequency = <1000>;
54			#clock-cells = <0>;
55		};
56	};
57
58	cpus {
59		#address-cells = <2>;
60		#size-cells = <0>;
61
62		CPU0: cpu@0 {
63			device_type = "cpu";
64			compatible = "qcom,kryo685";
65			reg = <0x0 0x0>;
66			enable-method = "psci";
67			next-level-cache = <&L2_0>;
68			qcom,freq-domain = <&cpufreq_hw 0>;
69			power-domains = <&CPU_PD0>;
70			power-domain-names = "psci";
71			#cooling-cells = <2>;
72			L2_0: l2-cache {
73			      compatible = "cache";
74			      next-level-cache = <&L3_0>;
75				L3_0: l3-cache {
76				      compatible = "cache";
77				};
78			};
79		};
80
81		CPU1: cpu@100 {
82			device_type = "cpu";
83			compatible = "qcom,kryo685";
84			reg = <0x0 0x100>;
85			enable-method = "psci";
86			next-level-cache = <&L2_100>;
87			qcom,freq-domain = <&cpufreq_hw 0>;
88			power-domains = <&CPU_PD1>;
89			power-domain-names = "psci";
90			#cooling-cells = <2>;
91			L2_100: l2-cache {
92			      compatible = "cache";
93			      next-level-cache = <&L3_0>;
94			};
95		};
96
97		CPU2: cpu@200 {
98			device_type = "cpu";
99			compatible = "qcom,kryo685";
100			reg = <0x0 0x200>;
101			enable-method = "psci";
102			next-level-cache = <&L2_200>;
103			qcom,freq-domain = <&cpufreq_hw 0>;
104			power-domains = <&CPU_PD2>;
105			power-domain-names = "psci";
106			#cooling-cells = <2>;
107			L2_200: l2-cache {
108			      compatible = "cache";
109			      next-level-cache = <&L3_0>;
110			};
111		};
112
113		CPU3: cpu@300 {
114			device_type = "cpu";
115			compatible = "qcom,kryo685";
116			reg = <0x0 0x300>;
117			enable-method = "psci";
118			next-level-cache = <&L2_300>;
119			qcom,freq-domain = <&cpufreq_hw 0>;
120			power-domains = <&CPU_PD3>;
121			power-domain-names = "psci";
122			#cooling-cells = <2>;
123			L2_300: l2-cache {
124			      compatible = "cache";
125			      next-level-cache = <&L3_0>;
126			};
127		};
128
129		CPU4: cpu@400 {
130			device_type = "cpu";
131			compatible = "qcom,kryo685";
132			reg = <0x0 0x400>;
133			enable-method = "psci";
134			next-level-cache = <&L2_400>;
135			qcom,freq-domain = <&cpufreq_hw 1>;
136			power-domains = <&CPU_PD4>;
137			power-domain-names = "psci";
138			#cooling-cells = <2>;
139			L2_400: l2-cache {
140			      compatible = "cache";
141			      next-level-cache = <&L3_0>;
142			};
143		};
144
145		CPU5: cpu@500 {
146			device_type = "cpu";
147			compatible = "qcom,kryo685";
148			reg = <0x0 0x500>;
149			enable-method = "psci";
150			next-level-cache = <&L2_500>;
151			qcom,freq-domain = <&cpufreq_hw 1>;
152			power-domains = <&CPU_PD5>;
153			power-domain-names = "psci";
154			#cooling-cells = <2>;
155			L2_500: l2-cache {
156			      compatible = "cache";
157			      next-level-cache = <&L3_0>;
158			};
159
160		};
161
162		CPU6: cpu@600 {
163			device_type = "cpu";
164			compatible = "qcom,kryo685";
165			reg = <0x0 0x600>;
166			enable-method = "psci";
167			next-level-cache = <&L2_600>;
168			qcom,freq-domain = <&cpufreq_hw 1>;
169			power-domains = <&CPU_PD6>;
170			power-domain-names = "psci";
171			#cooling-cells = <2>;
172			L2_600: l2-cache {
173			      compatible = "cache";
174			      next-level-cache = <&L3_0>;
175			};
176		};
177
178		CPU7: cpu@700 {
179			device_type = "cpu";
180			compatible = "qcom,kryo685";
181			reg = <0x0 0x700>;
182			enable-method = "psci";
183			next-level-cache = <&L2_700>;
184			qcom,freq-domain = <&cpufreq_hw 2>;
185			power-domains = <&CPU_PD7>;
186			power-domain-names = "psci";
187			#cooling-cells = <2>;
188			L2_700: l2-cache {
189			      compatible = "cache";
190			      next-level-cache = <&L3_0>;
191			};
192		};
193
194		cpu-map {
195			cluster0 {
196				core0 {
197					cpu = <&CPU0>;
198				};
199
200				core1 {
201					cpu = <&CPU1>;
202				};
203
204				core2 {
205					cpu = <&CPU2>;
206				};
207
208				core3 {
209					cpu = <&CPU3>;
210				};
211
212				core4 {
213					cpu = <&CPU4>;
214				};
215
216				core5 {
217					cpu = <&CPU5>;
218				};
219
220				core6 {
221					cpu = <&CPU6>;
222				};
223
224				core7 {
225					cpu = <&CPU7>;
226				};
227			};
228		};
229
230		idle-states {
231			entry-method = "psci";
232
233			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
234				compatible = "arm,idle-state";
235				idle-state-name = "silver-rail-power-collapse";
236				arm,psci-suspend-param = <0x40000004>;
237				entry-latency-us = <355>;
238				exit-latency-us = <909>;
239				min-residency-us = <3934>;
240				local-timer-stop;
241			};
242
243			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
244				compatible = "arm,idle-state";
245				idle-state-name = "gold-rail-power-collapse";
246				arm,psci-suspend-param = <0x40000004>;
247				entry-latency-us = <241>;
248				exit-latency-us = <1461>;
249				min-residency-us = <4488>;
250				local-timer-stop;
251			};
252		};
253
254		domain-idle-states {
255			CLUSTER_SLEEP_0: cluster-sleep-0 {
256				compatible = "domain-idle-state";
257				idle-state-name = "cluster-power-collapse";
258				arm,psci-suspend-param = <0x4100c344>;
259				entry-latency-us = <3263>;
260				exit-latency-us = <6562>;
261				min-residency-us = <9987>;
262				local-timer-stop;
263			};
264		};
265	};
266
267	firmware {
268		scm: scm {
269			compatible = "qcom,scm-sm8350", "qcom,scm";
270			#reset-cells = <1>;
271		};
272	};
273
274	memory@80000000 {
275		device_type = "memory";
276		/* We expect the bootloader to fill in the size */
277		reg = <0x0 0x80000000 0x0 0x0>;
278	};
279
280	pmu {
281		compatible = "arm,armv8-pmuv3";
282		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
283	};
284
285	psci {
286		compatible = "arm,psci-1.0";
287		method = "smc";
288
289		CPU_PD0: cpu0 {
290			#power-domain-cells = <0>;
291			power-domains = <&CLUSTER_PD>;
292			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
293		};
294
295		CPU_PD1: cpu1 {
296			#power-domain-cells = <0>;
297			power-domains = <&CLUSTER_PD>;
298			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
299		};
300
301		CPU_PD2: cpu2 {
302			#power-domain-cells = <0>;
303			power-domains = <&CLUSTER_PD>;
304			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
305		};
306
307		CPU_PD3: cpu3 {
308			#power-domain-cells = <0>;
309			power-domains = <&CLUSTER_PD>;
310			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
311		};
312
313		CPU_PD4: cpu4 {
314			#power-domain-cells = <0>;
315			power-domains = <&CLUSTER_PD>;
316			domain-idle-states = <&BIG_CPU_SLEEP_0>;
317		};
318
319		CPU_PD5: cpu5 {
320			#power-domain-cells = <0>;
321			power-domains = <&CLUSTER_PD>;
322			domain-idle-states = <&BIG_CPU_SLEEP_0>;
323		};
324
325		CPU_PD6: cpu6 {
326			#power-domain-cells = <0>;
327			power-domains = <&CLUSTER_PD>;
328			domain-idle-states = <&BIG_CPU_SLEEP_0>;
329		};
330
331		CPU_PD7: cpu7 {
332			#power-domain-cells = <0>;
333			power-domains = <&CLUSTER_PD>;
334			domain-idle-states = <&BIG_CPU_SLEEP_0>;
335		};
336
337		CLUSTER_PD: cpu-cluster0 {
338			#power-domain-cells = <0>;
339			domain-idle-states = <&CLUSTER_SLEEP_0>;
340		};
341	};
342
343	reserved_memory: reserved-memory {
344		#address-cells = <2>;
345		#size-cells = <2>;
346		ranges;
347
348		hyp_mem: memory@80000000 {
349			reg = <0x0 0x80000000 0x0 0x600000>;
350			no-map;
351		};
352
353		xbl_aop_mem: memory@80700000 {
354			no-map;
355			reg = <0x0 0x80700000 0x0 0x160000>;
356		};
357
358		cmd_db: memory@80860000 {
359			compatible = "qcom,cmd-db";
360			reg = <0x0 0x80860000 0x0 0x20000>;
361			no-map;
362		};
363
364		reserved_xbl_uefi_log: memory@80880000 {
365			reg = <0x0 0x80880000 0x0 0x14000>;
366			no-map;
367		};
368
369		smem_mem: memory@80900000 {
370			reg = <0x0 0x80900000 0x0 0x200000>;
371			no-map;
372		};
373
374		cpucp_fw_mem: memory@80b00000 {
375			reg = <0x0 0x80b00000 0x0 0x100000>;
376			no-map;
377		};
378
379		cdsp_secure_heap: memory@80c00000 {
380			reg = <0x0 0x80c00000 0x0 0x4600000>;
381			no-map;
382		};
383
384		pil_camera_mem: mmeory@85200000 {
385			reg = <0x0 0x85200000 0x0 0x500000>;
386			no-map;
387		};
388
389		pil_video_mem: memory@85700000 {
390			reg = <0x0 0x85700000 0x0 0x500000>;
391			no-map;
392		};
393
394		pil_cvp_mem: memory@85c00000 {
395			reg = <0x0 0x85c00000 0x0 0x500000>;
396			no-map;
397		};
398
399		pil_adsp_mem: memory@86100000 {
400			reg = <0x0 0x86100000 0x0 0x2100000>;
401			no-map;
402		};
403
404		pil_slpi_mem: memory@88200000 {
405			reg = <0x0 0x88200000 0x0 0x1500000>;
406			no-map;
407		};
408
409		pil_cdsp_mem: memory@89700000 {
410			reg = <0x0 0x89700000 0x0 0x1e00000>;
411			no-map;
412		};
413
414		pil_ipa_fw_mem: memory@8b500000 {
415			reg = <0x0 0x8b500000 0x0 0x10000>;
416			no-map;
417		};
418
419		pil_ipa_gsi_mem: memory@8b510000 {
420			reg = <0x0 0x8b510000 0x0 0xa000>;
421			no-map;
422		};
423
424		pil_gpu_mem: memory@8b51a000 {
425			reg = <0x0 0x8b51a000 0x0 0x2000>;
426			no-map;
427		};
428
429		pil_spss_mem: memory@8b600000 {
430			reg = <0x0 0x8b600000 0x0 0x100000>;
431			no-map;
432		};
433
434		pil_modem_mem: memory@8b800000 {
435			reg = <0x0 0x8b800000 0x0 0x10000000>;
436			no-map;
437		};
438
439		rmtfs_mem: memory@9b800000 {
440			compatible = "qcom,rmtfs-mem";
441			reg = <0x0 0x9b800000 0x0 0x280000>;
442			no-map;
443
444			qcom,client-id = <1>;
445			qcom,vmid = <15>;
446		};
447
448		hyp_reserved_mem: memory@d0000000 {
449			reg = <0x0 0xd0000000 0x0 0x800000>;
450			no-map;
451		};
452
453		pil_trustedvm_mem: memory@d0800000 {
454			reg = <0x0 0xd0800000 0x0 0x76f7000>;
455			no-map;
456		};
457
458		qrtr_shbuf: memory@d7ef7000 {
459			reg = <0x0 0xd7ef7000 0x0 0x9000>;
460			no-map;
461		};
462
463		chan0_shbuf: memory@d7f00000 {
464			reg = <0x0 0xd7f00000 0x0 0x80000>;
465			no-map;
466		};
467
468		chan1_shbuf: memory@d7f80000 {
469			reg = <0x0 0xd7f80000 0x0 0x80000>;
470			no-map;
471		};
472
473		removed_mem: memory@d8800000 {
474			reg = <0x0 0xd8800000 0x0 0x6800000>;
475			no-map;
476		};
477	};
478
479	smem: qcom,smem {
480		compatible = "qcom,smem";
481		memory-region = <&smem_mem>;
482		hwlocks = <&tcsr_mutex 3>;
483	};
484
485	smp2p-adsp {
486		compatible = "qcom,smp2p";
487		qcom,smem = <443>, <429>;
488		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
489					     IPCC_MPROC_SIGNAL_SMP2P
490					     IRQ_TYPE_EDGE_RISING>;
491		mboxes = <&ipcc IPCC_CLIENT_LPASS
492				IPCC_MPROC_SIGNAL_SMP2P>;
493
494		qcom,local-pid = <0>;
495		qcom,remote-pid = <2>;
496
497		smp2p_adsp_out: master-kernel {
498			qcom,entry-name = "master-kernel";
499			#qcom,smem-state-cells = <1>;
500		};
501
502		smp2p_adsp_in: slave-kernel {
503			qcom,entry-name = "slave-kernel";
504			interrupt-controller;
505			#interrupt-cells = <2>;
506		};
507	};
508
509	smp2p-cdsp {
510		compatible = "qcom,smp2p";
511		qcom,smem = <94>, <432>;
512		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
513					     IPCC_MPROC_SIGNAL_SMP2P
514					     IRQ_TYPE_EDGE_RISING>;
515		mboxes = <&ipcc IPCC_CLIENT_CDSP
516				IPCC_MPROC_SIGNAL_SMP2P>;
517
518		qcom,local-pid = <0>;
519		qcom,remote-pid = <5>;
520
521		smp2p_cdsp_out: master-kernel {
522			qcom,entry-name = "master-kernel";
523			#qcom,smem-state-cells = <1>;
524		};
525
526		smp2p_cdsp_in: slave-kernel {
527			qcom,entry-name = "slave-kernel";
528			interrupt-controller;
529			#interrupt-cells = <2>;
530		};
531	};
532
533	smp2p-modem {
534		compatible = "qcom,smp2p";
535		qcom,smem = <435>, <428>;
536		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
537					     IPCC_MPROC_SIGNAL_SMP2P
538					     IRQ_TYPE_EDGE_RISING>;
539		mboxes = <&ipcc IPCC_CLIENT_MPSS
540				IPCC_MPROC_SIGNAL_SMP2P>;
541
542		qcom,local-pid = <0>;
543		qcom,remote-pid = <1>;
544
545		smp2p_modem_out: master-kernel {
546			qcom,entry-name = "master-kernel";
547			#qcom,smem-state-cells = <1>;
548		};
549
550		smp2p_modem_in: slave-kernel {
551			qcom,entry-name = "slave-kernel";
552			interrupt-controller;
553			#interrupt-cells = <2>;
554		};
555
556		ipa_smp2p_out: ipa-ap-to-modem {
557			qcom,entry-name = "ipa";
558			#qcom,smem-state-cells = <1>;
559		};
560
561		ipa_smp2p_in: ipa-modem-to-ap {
562			qcom,entry-name = "ipa";
563			interrupt-controller;
564			#interrupt-cells = <2>;
565		};
566	};
567
568	smp2p-slpi {
569		compatible = "qcom,smp2p";
570		qcom,smem = <481>, <430>;
571		interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
572					     IPCC_MPROC_SIGNAL_SMP2P
573					     IRQ_TYPE_EDGE_RISING>;
574		mboxes = <&ipcc IPCC_CLIENT_SLPI
575				IPCC_MPROC_SIGNAL_SMP2P>;
576
577		qcom,local-pid = <0>;
578		qcom,remote-pid = <3>;
579
580		smp2p_slpi_out: master-kernel {
581			qcom,entry-name = "master-kernel";
582			#qcom,smem-state-cells = <1>;
583		};
584
585		smp2p_slpi_in: slave-kernel {
586			qcom,entry-name = "slave-kernel";
587			interrupt-controller;
588			#interrupt-cells = <2>;
589		};
590	};
591
592	soc: soc@0 {
593		#address-cells = <2>;
594		#size-cells = <2>;
595		ranges = <0 0 0 0 0x10 0>;
596		dma-ranges = <0 0 0 0 0x10 0>;
597		compatible = "simple-bus";
598
599		gcc: clock-controller@100000 {
600			compatible = "qcom,gcc-sm8350";
601			reg = <0x0 0x00100000 0x0 0x1f0000>;
602			#clock-cells = <1>;
603			#reset-cells = <1>;
604			#power-domain-cells = <1>;
605			clock-names = "bi_tcxo",
606				      "sleep_clk",
607				      "pcie_0_pipe_clk",
608				      "pcie_1_pipe_clk",
609				      "ufs_card_rx_symbol_0_clk",
610				      "ufs_card_rx_symbol_1_clk",
611				      "ufs_card_tx_symbol_0_clk",
612				      "ufs_phy_rx_symbol_0_clk",
613				      "ufs_phy_rx_symbol_1_clk",
614				      "ufs_phy_tx_symbol_0_clk",
615				      "usb3_phy_wrapper_gcc_usb30_pipe_clk",
616				      "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
617			clocks = <&rpmhcc RPMH_CXO_CLK>,
618				 <&sleep_clk>,
619				 <0>,
620				 <0>,
621				 <0>,
622				 <0>,
623				 <0>,
624				 <&ufs_phy_rx_symbol_0_clk>,
625				 <&ufs_phy_rx_symbol_1_clk>,
626				 <&ufs_phy_tx_symbol_0_clk>,
627				 <0>,
628				 <0>;
629		};
630
631		ipcc: mailbox@408000 {
632			compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
633			reg = <0 0x00408000 0 0x1000>;
634			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
635			interrupt-controller;
636			#interrupt-cells = <3>;
637			#mbox-cells = <2>;
638		};
639
640		qup_opp_table_100mhz: qup-100mhz-opp-table {
641			compatible = "operating-points-v2";
642
643			opp-50000000 {
644				opp-hz = /bits/ 64 <50000000>;
645				required-opps = <&rpmhpd_opp_min_svs>;
646			};
647
648			opp-75000000 {
649				opp-hz = /bits/ 64 <75000000>;
650				required-opps = <&rpmhpd_opp_low_svs>;
651			};
652
653			opp-100000000 {
654				opp-hz = /bits/ 64 <100000000>;
655				required-opps = <&rpmhpd_opp_svs>;
656			};
657		};
658
659		qup_opp_table_120mhz: qup-120mhz-opp-table {
660			compatible = "operating-points-v2";
661
662			opp-50000000 {
663				opp-hz = /bits/ 64 <50000000>;
664				required-opps = <&rpmhpd_opp_min_svs>;
665			};
666
667			opp-75000000 {
668				opp-hz = /bits/ 64 <75000000>;
669				required-opps = <&rpmhpd_opp_low_svs>;
670			};
671
672			opp-120000000 {
673				opp-hz = /bits/ 64 <120000000>;
674				required-opps = <&rpmhpd_opp_svs>;
675			};
676		};
677
678		qupv3_id_2: geniqup@8c0000 {
679			compatible = "qcom,geni-se-qup";
680			reg = <0x0 0x008c0000 0x0 0x6000>;
681			clock-names = "m-ahb", "s-ahb";
682			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
683				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
684			iommus = <&apps_smmu 0x5e3 0x0>;
685			#address-cells = <2>;
686			#size-cells = <2>;
687			ranges;
688			status = "disabled";
689
690			i2c14: i2c@880000 {
691				compatible = "qcom,geni-i2c";
692				reg = <0 0x00880000 0 0x4000>;
693				clock-names = "se";
694				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
695				pinctrl-names = "default";
696				pinctrl-0 = <&qup_i2c14_default>;
697				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
698				#address-cells = <1>;
699				#size-cells = <0>;
700				status = "disabled";
701			};
702
703			spi14: spi@880000 {
704				compatible = "qcom,geni-spi";
705				reg = <0 0x00880000 0 0x4000>;
706				clock-names = "se";
707				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
708				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
709				power-domains = <&rpmhpd SM8350_CX>;
710				operating-points-v2 = <&qup_opp_table_120mhz>;
711				#address-cells = <1>;
712				#size-cells = <0>;
713				status = "disabled";
714			};
715
716			i2c15: i2c@884000 {
717				compatible = "qcom,geni-i2c";
718				reg = <0 0x00884000 0 0x4000>;
719				clock-names = "se";
720				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
721				pinctrl-names = "default";
722				pinctrl-0 = <&qup_i2c15_default>;
723				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
724				#address-cells = <1>;
725				#size-cells = <0>;
726				status = "disabled";
727			};
728
729			spi15: spi@884000 {
730				compatible = "qcom,geni-spi";
731				reg = <0 0x00884000 0 0x4000>;
732				clock-names = "se";
733				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
734				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
735				power-domains = <&rpmhpd SM8350_CX>;
736				operating-points-v2 = <&qup_opp_table_120mhz>;
737				#address-cells = <1>;
738				#size-cells = <0>;
739				status = "disabled";
740			};
741
742			i2c16: i2c@888000 {
743				compatible = "qcom,geni-i2c";
744				reg = <0 0x00888000 0 0x4000>;
745				clock-names = "se";
746				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
747				pinctrl-names = "default";
748				pinctrl-0 = <&qup_i2c16_default>;
749				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
750				#address-cells = <1>;
751				#size-cells = <0>;
752				status = "disabled";
753			};
754
755			spi16: spi@888000 {
756				compatible = "qcom,geni-spi";
757				reg = <0 0x00888000 0 0x4000>;
758				clock-names = "se";
759				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
760				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
761				power-domains = <&rpmhpd SM8350_CX>;
762				operating-points-v2 = <&qup_opp_table_100mhz>;
763				#address-cells = <1>;
764				#size-cells = <0>;
765				status = "disabled";
766			};
767
768			i2c17: i2c@88c000 {
769				compatible = "qcom,geni-i2c";
770				reg = <0 0x0088c000 0 0x4000>;
771				clock-names = "se";
772				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
773				pinctrl-names = "default";
774				pinctrl-0 = <&qup_i2c17_default>;
775				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
776				#address-cells = <1>;
777				#size-cells = <0>;
778				status = "disabled";
779			};
780
781			spi17: spi@88c000 {
782				compatible = "qcom,geni-spi";
783				reg = <0 0x0088c000 0 0x4000>;
784				clock-names = "se";
785				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
786				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
787				power-domains = <&rpmhpd SM8350_CX>;
788				operating-points-v2 = <&qup_opp_table_100mhz>;
789				#address-cells = <1>;
790				#size-cells = <0>;
791				status = "disabled";
792			};
793
794			/* QUP no. 18 seems to be strictly SPI/UART-only */
795
796			spi18: spi@890000 {
797				compatible = "qcom,geni-spi";
798				reg = <0 0x00890000 0 0x4000>;
799				clock-names = "se";
800				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
801				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
802				power-domains = <&rpmhpd SM8350_CX>;
803				operating-points-v2 = <&qup_opp_table_100mhz>;
804				#address-cells = <1>;
805				#size-cells = <0>;
806				status = "disabled";
807			};
808
809			uart18: serial@890000 {
810				compatible = "qcom,geni-uart";
811				reg = <0 0x00890000 0 0x4000>;
812				clock-names = "se";
813				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
814				pinctrl-names = "default";
815				pinctrl-0 = <&qup_uart18_default>;
816				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
817				power-domains = <&rpmhpd SM8350_CX>;
818				operating-points-v2 = <&qup_opp_table_100mhz>;
819				status = "disabled";
820			};
821
822			i2c19: i2c@894000 {
823				compatible = "qcom,geni-i2c";
824				reg = <0 0x00894000 0 0x4000>;
825				clock-names = "se";
826				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
827				pinctrl-names = "default";
828				pinctrl-0 = <&qup_i2c19_default>;
829				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
830				#address-cells = <1>;
831				#size-cells = <0>;
832				status = "disabled";
833			};
834
835			spi19: spi@894000 {
836				compatible = "qcom,geni-spi";
837				reg = <0 0x00894000 0 0x4000>;
838				clock-names = "se";
839				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
840				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
841				power-domains = <&rpmhpd SM8350_CX>;
842				operating-points-v2 = <&qup_opp_table_100mhz>;
843				#address-cells = <1>;
844				#size-cells = <0>;
845				status = "disabled";
846			};
847		};
848
849		qupv3_id_0: geniqup@9c0000 {
850			compatible = "qcom,geni-se-qup";
851			reg = <0x0 0x009c0000 0x0 0x6000>;
852			clock-names = "m-ahb", "s-ahb";
853			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
854				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
855			iommus = <&apps_smmu 0x5a3 0>;
856			#address-cells = <2>;
857			#size-cells = <2>;
858			ranges;
859			status = "disabled";
860
861			i2c0: i2c@980000 {
862				compatible = "qcom,geni-i2c";
863				reg = <0 0x00980000 0 0x4000>;
864				clock-names = "se";
865				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
866				pinctrl-names = "default";
867				pinctrl-0 = <&qup_i2c0_default>;
868				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
869				#address-cells = <1>;
870				#size-cells = <0>;
871				status = "disabled";
872			};
873
874			spi0: spi@980000 {
875				compatible = "qcom,geni-spi";
876				reg = <0 0x00980000 0 0x4000>;
877				clock-names = "se";
878				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
879				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
880				power-domains = <&rpmhpd SM8350_CX>;
881				operating-points-v2 = <&qup_opp_table_100mhz>;
882				#address-cells = <1>;
883				#size-cells = <0>;
884				status = "disabled";
885			};
886
887			i2c1: i2c@984000 {
888				compatible = "qcom,geni-i2c";
889				reg = <0 0x00984000 0 0x4000>;
890				clock-names = "se";
891				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
892				pinctrl-names = "default";
893				pinctrl-0 = <&qup_i2c1_default>;
894				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
895				#address-cells = <1>;
896				#size-cells = <0>;
897				status = "disabled";
898			};
899
900			spi1: spi@984000 {
901				compatible = "qcom,geni-spi";
902				reg = <0 0x00984000 0 0x4000>;
903				clock-names = "se";
904				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
905				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
906				power-domains = <&rpmhpd SM8350_CX>;
907				operating-points-v2 = <&qup_opp_table_100mhz>;
908				#address-cells = <1>;
909				#size-cells = <0>;
910				status = "disabled";
911			};
912
913			i2c2: i2c@988000 {
914				compatible = "qcom,geni-i2c";
915				reg = <0 0x00988000 0 0x4000>;
916				clock-names = "se";
917				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
918				pinctrl-names = "default";
919				pinctrl-0 = <&qup_i2c2_default>;
920				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
921				#address-cells = <1>;
922				#size-cells = <0>;
923				status = "disabled";
924			};
925
926			spi2: spi@988000 {
927				compatible = "qcom,geni-spi";
928				reg = <0 0x00988000 0 0x4000>;
929				clock-names = "se";
930				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
931				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
932				power-domains = <&rpmhpd SM8350_CX>;
933				operating-points-v2 = <&qup_opp_table_100mhz>;
934				#address-cells = <1>;
935				#size-cells = <0>;
936				status = "disabled";
937			};
938
939			uart2: serial@98c000 {
940				compatible = "qcom,geni-debug-uart";
941				reg = <0 0x0098c000 0 0x4000>;
942				clock-names = "se";
943				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
944				pinctrl-names = "default";
945				pinctrl-0 = <&qup_uart3_default_state>;
946				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
947				power-domains = <&rpmhpd SM8350_CX>;
948				operating-points-v2 = <&qup_opp_table_100mhz>;
949				#address-cells = <1>;
950				#size-cells = <0>;
951				status = "disabled";
952			};
953
954			/* QUP no. 3 seems to be strictly SPI-only */
955
956			spi3: spi@98c000 {
957				compatible = "qcom,geni-spi";
958				reg = <0 0x0098c000 0 0x4000>;
959				clock-names = "se";
960				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
961				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
962				power-domains = <&rpmhpd SM8350_CX>;
963				operating-points-v2 = <&qup_opp_table_100mhz>;
964				#address-cells = <1>;
965				#size-cells = <0>;
966				status = "disabled";
967			};
968
969			i2c4: i2c@990000 {
970				compatible = "qcom,geni-i2c";
971				reg = <0 0x00990000 0 0x4000>;
972				clock-names = "se";
973				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
974				pinctrl-names = "default";
975				pinctrl-0 = <&qup_i2c4_default>;
976				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
977				#address-cells = <1>;
978				#size-cells = <0>;
979				status = "disabled";
980			};
981
982			spi4: spi@990000 {
983				compatible = "qcom,geni-spi";
984				reg = <0 0x00990000 0 0x4000>;
985				clock-names = "se";
986				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
987				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
988				power-domains = <&rpmhpd SM8350_CX>;
989				operating-points-v2 = <&qup_opp_table_100mhz>;
990				#address-cells = <1>;
991				#size-cells = <0>;
992				status = "disabled";
993			};
994
995			i2c5: i2c@994000 {
996				compatible = "qcom,geni-i2c";
997				reg = <0 0x00994000 0 0x4000>;
998				clock-names = "se";
999				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1000				pinctrl-names = "default";
1001				pinctrl-0 = <&qup_i2c5_default>;
1002				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1003				#address-cells = <1>;
1004				#size-cells = <0>;
1005				status = "disabled";
1006			};
1007
1008			spi5: spi@994000 {
1009				compatible = "qcom,geni-spi";
1010				reg = <0 0x00994000 0 0x4000>;
1011				clock-names = "se";
1012				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1013				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1014				power-domains = <&rpmhpd SM8350_CX>;
1015				operating-points-v2 = <&qup_opp_table_100mhz>;
1016				#address-cells = <1>;
1017				#size-cells = <0>;
1018				status = "disabled";
1019			};
1020
1021			i2c6: i2c@998000 {
1022				compatible = "qcom,geni-i2c";
1023				reg = <0 0x00998000 0 0x4000>;
1024				clock-names = "se";
1025				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1026				pinctrl-names = "default";
1027				pinctrl-0 = <&qup_i2c6_default>;
1028				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1029				#address-cells = <1>;
1030				#size-cells = <0>;
1031				status = "disabled";
1032			};
1033
1034			spi6: spi@998000 {
1035				compatible = "qcom,geni-spi";
1036				reg = <0 0x00998000 0 0x4000>;
1037				clock-names = "se";
1038				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1039				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1040				power-domains = <&rpmhpd SM8350_CX>;
1041				operating-points-v2 = <&qup_opp_table_100mhz>;
1042				#address-cells = <1>;
1043				#size-cells = <0>;
1044				status = "disabled";
1045			};
1046
1047			uart6: serial@998000 {
1048				compatible = "qcom,geni-uart";
1049				reg = <0 0x00998000 0 0x4000>;
1050				clock-names = "se";
1051				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1052				pinctrl-names = "default";
1053				pinctrl-0 = <&qup_uart6_default>;
1054				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1055				power-domains = <&rpmhpd SM8350_CX>;
1056				operating-points-v2 = <&qup_opp_table_100mhz>;
1057				status = "disabled";
1058			};
1059
1060			i2c7: i2c@99c000 {
1061				compatible = "qcom,geni-i2c";
1062				reg = <0 0x0099c000 0 0x4000>;
1063				clock-names = "se";
1064				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1065				pinctrl-names = "default";
1066				pinctrl-0 = <&qup_i2c7_default>;
1067				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1068				#address-cells = <1>;
1069				#size-cells = <0>;
1070				status = "disabled";
1071			};
1072
1073			spi7: spi@99c000 {
1074				compatible = "qcom,geni-spi";
1075				reg = <0 0x0099c000 0 0x4000>;
1076				clock-names = "se";
1077				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1078				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1079				power-domains = <&rpmhpd SM8350_CX>;
1080				operating-points-v2 = <&qup_opp_table_100mhz>;
1081				#address-cells = <1>;
1082				#size-cells = <0>;
1083				status = "disabled";
1084			};
1085		};
1086
1087		qupv3_id_1: geniqup@ac0000 {
1088			compatible = "qcom,geni-se-qup";
1089			reg = <0x0 0x00ac0000 0x0 0x6000>;
1090			clock-names = "m-ahb", "s-ahb";
1091			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1092				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1093			iommus = <&apps_smmu 0x43 0>;
1094			#address-cells = <2>;
1095			#size-cells = <2>;
1096			ranges;
1097			status = "disabled";
1098
1099			i2c8: i2c@a80000 {
1100				compatible = "qcom,geni-i2c";
1101				reg = <0 0x00a80000 0 0x4000>;
1102				clock-names = "se";
1103				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1104				pinctrl-names = "default";
1105				pinctrl-0 = <&qup_i2c8_default>;
1106				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1107				#address-cells = <1>;
1108				#size-cells = <0>;
1109				status = "disabled";
1110			};
1111
1112			spi8: spi@a80000 {
1113				compatible = "qcom,geni-spi";
1114				reg = <0 0x00a80000 0 0x4000>;
1115				clock-names = "se";
1116				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1117				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1118				power-domains = <&rpmhpd SM8350_CX>;
1119				operating-points-v2 = <&qup_opp_table_120mhz>;
1120				#address-cells = <1>;
1121				#size-cells = <0>;
1122				status = "disabled";
1123			};
1124
1125			i2c9: i2c@a84000 {
1126				compatible = "qcom,geni-i2c";
1127				reg = <0 0x00a84000 0 0x4000>;
1128				clock-names = "se";
1129				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1130				pinctrl-names = "default";
1131				pinctrl-0 = <&qup_i2c9_default>;
1132				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1133				#address-cells = <1>;
1134				#size-cells = <0>;
1135				status = "disabled";
1136			};
1137
1138			spi9: spi@a84000 {
1139				compatible = "qcom,geni-spi";
1140				reg = <0 0x00a84000 0 0x4000>;
1141				clock-names = "se";
1142				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1143				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1144				power-domains = <&rpmhpd SM8350_CX>;
1145				operating-points-v2 = <&qup_opp_table_100mhz>;
1146				#address-cells = <1>;
1147				#size-cells = <0>;
1148				status = "disabled";
1149			};
1150
1151			i2c10: i2c@a88000 {
1152				compatible = "qcom,geni-i2c";
1153				reg = <0 0x00a88000 0 0x4000>;
1154				clock-names = "se";
1155				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1156				pinctrl-names = "default";
1157				pinctrl-0 = <&qup_i2c10_default>;
1158				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1159				#address-cells = <1>;
1160				#size-cells = <0>;
1161				status = "disabled";
1162			};
1163
1164			spi10: spi@a88000 {
1165				compatible = "qcom,geni-spi";
1166				reg = <0 0x00a88000 0 0x4000>;
1167				clock-names = "se";
1168				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1169				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1170				power-domains = <&rpmhpd SM8350_CX>;
1171				operating-points-v2 = <&qup_opp_table_100mhz>;
1172				#address-cells = <1>;
1173				#size-cells = <0>;
1174				status = "disabled";
1175			};
1176
1177			i2c11: i2c@a8c000 {
1178				compatible = "qcom,geni-i2c";
1179				reg = <0 0x00a8c000 0 0x4000>;
1180				clock-names = "se";
1181				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1182				pinctrl-names = "default";
1183				pinctrl-0 = <&qup_i2c11_default>;
1184				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1185				#address-cells = <1>;
1186				#size-cells = <0>;
1187				status = "disabled";
1188			};
1189
1190			spi11: spi@a8c000 {
1191				compatible = "qcom,geni-spi";
1192				reg = <0 0x00a8c000 0 0x4000>;
1193				clock-names = "se";
1194				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1195				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1196				power-domains = <&rpmhpd SM8350_CX>;
1197				operating-points-v2 = <&qup_opp_table_100mhz>;
1198				#address-cells = <1>;
1199				#size-cells = <0>;
1200				status = "disabled";
1201			};
1202
1203			i2c12: i2c@a90000 {
1204				compatible = "qcom,geni-i2c";
1205				reg = <0 0x00a90000 0 0x4000>;
1206				clock-names = "se";
1207				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1208				pinctrl-names = "default";
1209				pinctrl-0 = <&qup_i2c12_default>;
1210				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1211				#address-cells = <1>;
1212				#size-cells = <0>;
1213				status = "disabled";
1214			};
1215
1216			spi12: spi@a90000 {
1217				compatible = "qcom,geni-spi";
1218				reg = <0 0x00a90000 0 0x4000>;
1219				clock-names = "se";
1220				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1221				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1222				power-domains = <&rpmhpd SM8350_CX>;
1223				operating-points-v2 = <&qup_opp_table_100mhz>;
1224				#address-cells = <1>;
1225				#size-cells = <0>;
1226				status = "disabled";
1227			};
1228
1229			i2c13: i2c@a94000 {
1230				compatible = "qcom,geni-i2c";
1231				reg = <0 0x00a94000 0 0x4000>;
1232				clock-names = "se";
1233				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1234				pinctrl-names = "default";
1235				pinctrl-0 = <&qup_i2c13_default>;
1236				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1237				#address-cells = <1>;
1238				#size-cells = <0>;
1239				status = "disabled";
1240			};
1241
1242			spi13: spi@a94000 {
1243				compatible = "qcom,geni-spi";
1244				reg = <0 0x00a94000 0 0x4000>;
1245				clock-names = "se";
1246				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1247				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1248				power-domains = <&rpmhpd SM8350_CX>;
1249				operating-points-v2 = <&qup_opp_table_100mhz>;
1250				#address-cells = <1>;
1251				#size-cells = <0>;
1252				status = "disabled";
1253			};
1254		};
1255
1256		apps_smmu: iommu@15000000 {
1257			compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
1258			reg = <0 0x15000000 0 0x100000>;
1259			#iommu-cells = <2>;
1260			#global-interrupts = <2>;
1261			interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1262					<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1263					<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1264					<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1265					<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1266					<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1267					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1268					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1269					<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1270					<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1271					<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1272					<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1273					<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1274					<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1275					<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1276					<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1277					<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1278					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1279					<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1280					<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1281					<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1282					<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1283					<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1284					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1285					<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1286					<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1287					<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1288					<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1289					<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1290					<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1291					<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1292					<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1293					<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1294					<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1295					<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1296					<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1297					<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1298					<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1299					<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1300					<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1301					<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1302					<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1303					<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1304					<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1305					<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1306					<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1307					<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1308					<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1309					<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1310					<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1311					<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1312					<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1313					<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1314					<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1315					<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1316					<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1317					<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1318					<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1319					<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1320					<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1321					<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1322					<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1323					<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1324					<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1325					<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1326					<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1327					<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1328					<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1329					<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1330					<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1331					<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1332					<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1333					<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1334					<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1335					<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1336					<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1337					<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1338					<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1339					<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1340					<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1341					<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1342					<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1343					<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1344					<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1345					<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1346					<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1347					<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1348					<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1349					<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1350					<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
1351					<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
1352					<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
1353					<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
1354					<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
1355					<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
1356					<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
1357					<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
1358					<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
1359		};
1360
1361		config_noc: interconnect@1500000 {
1362			compatible = "qcom,sm8350-config-noc";
1363			reg = <0 0x01500000 0 0xa580>;
1364			#interconnect-cells = <1>;
1365			qcom,bcm-voters = <&apps_bcm_voter>;
1366		};
1367
1368		mc_virt: interconnect@1580000 {
1369			compatible = "qcom,sm8350-mc-virt";
1370			reg = <0 0x01580000 0 0x1000>;
1371			#interconnect-cells = <1>;
1372			qcom,bcm-voters = <&apps_bcm_voter>;
1373		};
1374
1375		system_noc: interconnect@1680000 {
1376			compatible = "qcom,sm8350-system-noc";
1377			reg = <0 0x01680000 0 0x1c200>;
1378			#interconnect-cells = <1>;
1379			qcom,bcm-voters = <&apps_bcm_voter>;
1380		};
1381
1382		aggre1_noc: interconnect@16e0000 {
1383			compatible = "qcom,sm8350-aggre1-noc";
1384			reg = <0 0x016e0000 0 0x1f180>;
1385			#interconnect-cells = <1>;
1386			qcom,bcm-voters = <&apps_bcm_voter>;
1387		};
1388
1389		aggre2_noc: interconnect@1700000 {
1390			compatible = "qcom,sm8350-aggre2-noc";
1391			reg = <0 0x01700000 0 0x33000>;
1392			#interconnect-cells = <1>;
1393			qcom,bcm-voters = <&apps_bcm_voter>;
1394		};
1395
1396		mmss_noc: interconnect@1740000 {
1397			compatible = "qcom,sm8350-mmss-noc";
1398			reg = <0 0x01740000 0 0x1f080>;
1399			#interconnect-cells = <1>;
1400			qcom,bcm-voters = <&apps_bcm_voter>;
1401		};
1402
1403		lpass_ag_noc: interconnect@3c40000 {
1404			compatible = "qcom,sm8350-lpass-ag-noc";
1405			reg = <0 0x03c40000 0 0xf080>;
1406			#interconnect-cells = <1>;
1407			qcom,bcm-voters = <&apps_bcm_voter>;
1408		};
1409
1410		compute_noc: interconnect@a0c0000{
1411			compatible = "qcom,sm8350-compute-noc";
1412			reg = <0 0x0a0c0000 0 0xa180>;
1413			#interconnect-cells = <1>;
1414			qcom,bcm-voters = <&apps_bcm_voter>;
1415		};
1416
1417		ipa: ipa@1e40000 {
1418			compatible = "qcom,sm8350-ipa";
1419
1420			iommus = <&apps_smmu 0x5c0 0x0>,
1421				 <&apps_smmu 0x5c2 0x0>;
1422			reg = <0 0x1e40000 0 0x8000>,
1423			      <0 0x1e50000 0 0x4b20>,
1424			      <0 0x1e04000 0 0x23000>;
1425			reg-names = "ipa-reg",
1426				    "ipa-shared",
1427				    "gsi";
1428
1429			interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1430					      <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1431					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1432					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1433			interrupt-names = "ipa",
1434					  "gsi",
1435					  "ipa-clock-query",
1436					  "ipa-setup-ready";
1437
1438			clocks = <&rpmhcc RPMH_IPA_CLK>;
1439			clock-names = "core";
1440
1441			interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
1442					<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
1443			interconnect-names = "memory",
1444					     "config";
1445
1446			qcom,smem-states = <&ipa_smp2p_out 0>,
1447					   <&ipa_smp2p_out 1>;
1448			qcom,smem-state-names = "ipa-clock-enabled-valid",
1449						"ipa-clock-enabled";
1450
1451			status = "disabled";
1452		};
1453
1454		tcsr_mutex: hwlock@1f40000 {
1455			compatible = "qcom,tcsr-mutex";
1456			reg = <0x0 0x01f40000 0x0 0x40000>;
1457			#hwlock-cells = <1>;
1458		};
1459
1460		mpss: remoteproc@4080000 {
1461			compatible = "qcom,sm8350-mpss-pas";
1462			reg = <0x0 0x04080000 0x0 0x4040>;
1463
1464			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1465					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1466					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1467					      <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1468					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1469					      <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1470			interrupt-names = "wdog", "fatal", "ready", "handover",
1471					  "stop-ack", "shutdown-ack";
1472
1473			clocks = <&rpmhcc RPMH_CXO_CLK>;
1474			clock-names = "xo";
1475
1476			power-domains = <&rpmhpd 0>,
1477					<&rpmhpd 12>;
1478			power-domain-names = "cx", "mss";
1479
1480			interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
1481
1482			memory-region = <&pil_modem_mem>;
1483
1484			qcom,qmp = <&aoss_qmp>;
1485
1486			qcom,smem-states = <&smp2p_modem_out 0>;
1487			qcom,smem-state-names = "stop";
1488
1489			status = "disabled";
1490
1491			glink-edge {
1492				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1493							     IPCC_MPROC_SIGNAL_GLINK_QMP
1494							     IRQ_TYPE_EDGE_RISING>;
1495				mboxes = <&ipcc IPCC_CLIENT_MPSS
1496						IPCC_MPROC_SIGNAL_GLINK_QMP>;
1497				interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1498				label = "modem";
1499				qcom,remote-pid = <1>;
1500			};
1501		};
1502
1503		pdc: interrupt-controller@b220000 {
1504			compatible = "qcom,sm8350-pdc", "qcom,pdc";
1505			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1506			qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,   <55 306 4>,
1507					  <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
1508					  <69 86 1>,  <70 520 54>, <124 609 31>, <155 63 1>,
1509					  <156 716 12>;
1510			#interrupt-cells = <2>;
1511			interrupt-parent = <&intc>;
1512			interrupt-controller;
1513		};
1514
1515		tsens0: thermal-sensor@c263000 {
1516			compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1517			reg = <0 0x0c263000 0 0x1ff>, /* TM */
1518			      <0 0x0c222000 0 0x8>; /* SROT */
1519			#qcom,sensors = <15>;
1520			interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1521				     <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1522			interrupt-names = "uplow", "critical";
1523			#thermal-sensor-cells = <1>;
1524		};
1525
1526		tsens1: thermal-sensor@c265000 {
1527			compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1528			reg = <0 0x0c265000 0 0x1ff>, /* TM */
1529			      <0 0x0c223000 0 0x8>; /* SROT */
1530			#qcom,sensors = <14>;
1531			interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1532				     <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1533			interrupt-names = "uplow", "critical";
1534			#thermal-sensor-cells = <1>;
1535		};
1536
1537		aoss_qmp: power-controller@c300000 {
1538			compatible = "qcom,sm8350-aoss-qmp";
1539			reg = <0 0x0c300000 0 0x400>;
1540			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1541						     IRQ_TYPE_EDGE_RISING>;
1542			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1543
1544			#clock-cells = <0>;
1545		};
1546
1547		sram@c3f0000 {
1548			compatible = "qcom,rpmh-stats";
1549			reg = <0 0x0c3f0000 0 0x400>;
1550		};
1551
1552		spmi_bus: spmi@c440000 {
1553			compatible = "qcom,spmi-pmic-arb";
1554			reg = <0x0 0xc440000 0x0 0x1100>,
1555			      <0x0 0xc600000 0x0 0x2000000>,
1556			      <0x0 0xe600000 0x0 0x100000>,
1557			      <0x0 0xe700000 0x0 0xa0000>,
1558			      <0x0 0xc40a000 0x0 0x26000>;
1559			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1560			interrupt-names = "periph_irq";
1561			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1562			qcom,ee = <0>;
1563			qcom,channel = <0>;
1564			#address-cells = <2>;
1565			#size-cells = <0>;
1566			interrupt-controller;
1567			#interrupt-cells = <4>;
1568		};
1569
1570		tlmm: pinctrl@f100000 {
1571			compatible = "qcom,sm8350-tlmm";
1572			reg = <0 0x0f100000 0 0x300000>;
1573			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1574			gpio-controller;
1575			#gpio-cells = <2>;
1576			interrupt-controller;
1577			#interrupt-cells = <2>;
1578			gpio-ranges = <&tlmm 0 0 204>;
1579			wakeup-parent = <&pdc>;
1580
1581			qup_uart3_default_state: qup-uart3-default-state {
1582				rx {
1583					pins = "gpio18";
1584					function = "qup3";
1585				};
1586				tx {
1587					pins = "gpio19";
1588					function = "qup3";
1589				};
1590			};
1591
1592			qup_uart6_default: qup-uart6-default {
1593				pins = "gpio30", "gpio31";
1594				function = "qup6";
1595				drive-strength = <2>;
1596				bias-disable;
1597			};
1598
1599			qup_uart18_default: qup-uart18-default {
1600				pins = "gpio58", "gpio59";
1601				function = "qup18";
1602				drive-strength = <2>;
1603				bias-disable;
1604			};
1605
1606			qup_i2c0_default: qup-i2c0-default {
1607				pins = "gpio4", "gpio5";
1608				function = "qup0";
1609				drive-strength = <2>;
1610				bias-pull-up;
1611			};
1612
1613			qup_i2c1_default: qup-i2c1-default {
1614				pins = "gpio8", "gpio9";
1615				function = "qup1";
1616				drive-strength = <2>;
1617				bias-pull-up;
1618			};
1619
1620			qup_i2c2_default: qup-i2c2-default {
1621				pins = "gpio12", "gpio13";
1622				function = "qup2";
1623				drive-strength = <2>;
1624				bias-pull-up;
1625			};
1626
1627			qup_i2c4_default: qup-i2c4-default {
1628				pins = "gpio20", "gpio21";
1629				function = "qup4";
1630				drive-strength = <2>;
1631				bias-pull-up;
1632			};
1633
1634			qup_i2c5_default: qup-i2c5-default {
1635				pins = "gpio24", "gpio25";
1636				function = "qup5";
1637				drive-strength = <2>;
1638				bias-pull-up;
1639			};
1640
1641			qup_i2c6_default: qup-i2c6-default {
1642				pins = "gpio28", "gpio29";
1643				function = "qup6";
1644				drive-strength = <2>;
1645				bias-pull-up;
1646			};
1647
1648			qup_i2c7_default: qup-i2c7-default {
1649				pins = "gpio32", "gpio33";
1650				function = "qup7";
1651				drive-strength = <2>;
1652				bias-disable;
1653			};
1654
1655			qup_i2c8_default: qup-i2c8-default {
1656				pins = "gpio36", "gpio37";
1657				function = "qup8";
1658				drive-strength = <2>;
1659				bias-pull-up;
1660			};
1661
1662			qup_i2c9_default: qup-i2c9-default {
1663				pins = "gpio40", "gpio41";
1664				function = "qup9";
1665				drive-strength = <2>;
1666				bias-pull-up;
1667			};
1668
1669			qup_i2c10_default: qup-i2c10-default {
1670				pins = "gpio44", "gpio45";
1671				function = "qup10";
1672				drive-strength = <2>;
1673				bias-pull-up;
1674			};
1675
1676			qup_i2c11_default: qup-i2c11-default {
1677				pins = "gpio48", "gpio49";
1678				function = "qup11";
1679				drive-strength = <2>;
1680				bias-pull-up;
1681			};
1682
1683			qup_i2c12_default: qup-i2c12-default {
1684				pins = "gpio52", "gpio53";
1685				function = "qup12";
1686				drive-strength = <2>;
1687				bias-pull-up;
1688			};
1689
1690			qup_i2c13_default: qup-i2c13-default {
1691				pins = "gpio0", "gpio1";
1692				function = "qup13";
1693				drive-strength = <2>;
1694				bias-pull-up;
1695			};
1696
1697			qup_i2c14_default: qup-i2c14-default {
1698				pins = "gpio56", "gpio57";
1699				function = "qup14";
1700				drive-strength = <2>;
1701				bias-disable;
1702			};
1703
1704			qup_i2c15_default: qup-i2c15-default {
1705				pins = "gpio60", "gpio61";
1706				function = "qup15";
1707				drive-strength = <2>;
1708				bias-disable;
1709			};
1710
1711			qup_i2c16_default: qup-i2c16-default {
1712				pins = "gpio64", "gpio65";
1713				function = "qup16";
1714				drive-strength = <2>;
1715				bias-disable;
1716			};
1717
1718			qup_i2c17_default: qup-i2c17-default {
1719				pins = "gpio72", "gpio73";
1720				function = "qup17";
1721				drive-strength = <2>;
1722				bias-disable;
1723			};
1724
1725			qup_i2c19_default: qup-i2c19-default {
1726				pins = "gpio76", "gpio77";
1727				function = "qup19";
1728				drive-strength = <2>;
1729				bias-disable;
1730			};
1731		};
1732
1733		rng: rng@10d3000 {
1734			compatible = "qcom,prng-ee";
1735			reg = <0 0x010d3000 0 0x1000>;
1736			clocks = <&rpmhcc RPMH_HWKM_CLK>;
1737			clock-names = "core";
1738		};
1739
1740		intc: interrupt-controller@17a00000 {
1741			compatible = "arm,gic-v3";
1742			#interrupt-cells = <3>;
1743			interrupt-controller;
1744			#redistributor-regions = <1>;
1745			redistributor-stride = <0 0x20000>;
1746			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
1747			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
1748			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1749		};
1750
1751		timer@17c20000 {
1752			compatible = "arm,armv7-timer-mem";
1753			#address-cells = <2>;
1754			#size-cells = <2>;
1755			ranges;
1756			reg = <0x0 0x17c20000 0x0 0x1000>;
1757			clock-frequency = <19200000>;
1758
1759			frame@17c21000 {
1760				frame-number = <0>;
1761				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1762					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1763				reg = <0x0 0x17c21000 0x0 0x1000>,
1764				      <0x0 0x17c22000 0x0 0x1000>;
1765			};
1766
1767			frame@17c23000 {
1768				frame-number = <1>;
1769				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1770				reg = <0x0 0x17c23000 0x0 0x1000>;
1771				status = "disabled";
1772			};
1773
1774			frame@17c25000 {
1775				frame-number = <2>;
1776				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1777				reg = <0x0 0x17c25000 0x0 0x1000>;
1778				status = "disabled";
1779			};
1780
1781			frame@17c27000 {
1782				frame-number = <3>;
1783				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1784				reg = <0x0 0x17c27000 0x0 0x1000>;
1785				status = "disabled";
1786			};
1787
1788			frame@17c29000 {
1789				frame-number = <4>;
1790				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1791				reg = <0x0 0x17c29000 0x0 0x1000>;
1792				status = "disabled";
1793			};
1794
1795			frame@17c2b000 {
1796				frame-number = <5>;
1797				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1798				reg = <0x0 0x17c2b000 0x0 0x1000>;
1799				status = "disabled";
1800			};
1801
1802			frame@17c2d000 {
1803				frame-number = <6>;
1804				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1805				reg = <0x0 0x17c2d000 0x0 0x1000>;
1806				status = "disabled";
1807			};
1808		};
1809
1810		apps_rsc: rsc@18200000 {
1811			label = "apps_rsc";
1812			compatible = "qcom,rpmh-rsc";
1813			reg = <0x0 0x18200000 0x0 0x10000>,
1814				<0x0 0x18210000 0x0 0x10000>,
1815				<0x0 0x18220000 0x0 0x10000>;
1816			reg-names = "drv-0", "drv-1", "drv-2";
1817			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1818				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1819				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1820			qcom,tcs-offset = <0xd00>;
1821			qcom,drv-id = <2>;
1822			qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
1823					  <WAKE_TCS    3>, <CONTROL_TCS 1>;
1824
1825			rpmhcc: clock-controller {
1826				compatible = "qcom,sm8350-rpmh-clk";
1827				#clock-cells = <1>;
1828				clock-names = "xo";
1829				clocks = <&xo_board>;
1830			};
1831
1832			rpmhpd: power-controller {
1833				compatible = "qcom,sm8350-rpmhpd";
1834				#power-domain-cells = <1>;
1835				operating-points-v2 = <&rpmhpd_opp_table>;
1836
1837				rpmhpd_opp_table: opp-table {
1838					compatible = "operating-points-v2";
1839
1840					rpmhpd_opp_ret: opp1 {
1841						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1842					};
1843
1844					rpmhpd_opp_min_svs: opp2 {
1845						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1846					};
1847
1848					rpmhpd_opp_low_svs: opp3 {
1849						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1850					};
1851
1852					rpmhpd_opp_svs: opp4 {
1853						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1854					};
1855
1856					rpmhpd_opp_svs_l1: opp5 {
1857						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1858					};
1859
1860					rpmhpd_opp_nom: opp6 {
1861						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1862					};
1863
1864					rpmhpd_opp_nom_l1: opp7 {
1865						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1866					};
1867
1868					rpmhpd_opp_nom_l2: opp8 {
1869						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1870					};
1871
1872					rpmhpd_opp_turbo: opp9 {
1873						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1874					};
1875
1876					rpmhpd_opp_turbo_l1: opp10 {
1877						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1878					};
1879				};
1880			};
1881
1882			apps_bcm_voter: bcm_voter {
1883				compatible = "qcom,bcm-voter";
1884			};
1885		};
1886
1887		cpufreq_hw: cpufreq@18591000 {
1888			compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
1889			reg = <0 0x18591000 0 0x1000>,
1890			      <0 0x18592000 0 0x1000>,
1891			      <0 0x18593000 0 0x1000>;
1892			reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
1893
1894			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1895			clock-names = "xo", "alternate";
1896
1897			#freq-domain-cells = <1>;
1898		};
1899
1900		ufs_mem_hc: ufshc@1d84000 {
1901			compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1902				     "jedec,ufs-2.0";
1903			reg = <0 0x01d84000 0 0x3000>;
1904			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1905			phys = <&ufs_mem_phy_lanes>;
1906			phy-names = "ufsphy";
1907			lanes-per-direction = <2>;
1908			#reset-cells = <1>;
1909			resets = <&gcc GCC_UFS_PHY_BCR>;
1910			reset-names = "rst";
1911
1912			power-domains = <&gcc UFS_PHY_GDSC>;
1913
1914			iommus = <&apps_smmu 0xe0 0x0>;
1915
1916			clock-names =
1917				"ref_clk",
1918				"core_clk",
1919				"bus_aggr_clk",
1920				"iface_clk",
1921				"core_clk_unipro",
1922				"ref_clk",
1923				"tx_lane0_sync_clk",
1924				"rx_lane0_sync_clk",
1925				"rx_lane1_sync_clk";
1926			clocks =
1927				<&rpmhcc RPMH_CXO_CLK>,
1928				<&gcc GCC_UFS_PHY_AXI_CLK>,
1929				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1930				<&gcc GCC_UFS_PHY_AHB_CLK>,
1931				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1932				<&rpmhcc RPMH_CXO_CLK>,
1933				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1934				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1935				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1936			freq-table-hz =
1937				<75000000 300000000>,
1938				<75000000 300000000>,
1939				<0 0>,
1940				<0 0>,
1941				<75000000 300000000>,
1942				<0 0>,
1943				<0 0>,
1944				<0 0>,
1945				<0 0>;
1946			status = "disabled";
1947		};
1948
1949		ufs_mem_phy: phy@1d87000 {
1950			compatible = "qcom,sm8350-qmp-ufs-phy";
1951			reg = <0 0x01d87000 0 0xe10>;
1952			#address-cells = <2>;
1953			#size-cells = <2>;
1954			ranges;
1955			clock-names = "ref",
1956				      "ref_aux";
1957			clocks = <&rpmhcc RPMH_CXO_CLK>,
1958				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1959
1960			resets = <&ufs_mem_hc 0>;
1961			reset-names = "ufsphy";
1962			status = "disabled";
1963
1964			ufs_mem_phy_lanes: phy@1d87400 {
1965				reg = <0 0x01d87400 0 0x108>,
1966				      <0 0x01d87600 0 0x1e0>,
1967				      <0 0x01d87c00 0 0x1dc>,
1968				      <0 0x01d87800 0 0x108>,
1969				      <0 0x01d87a00 0 0x1e0>;
1970				#phy-cells = <0>;
1971				#clock-cells = <0>;
1972			};
1973		};
1974
1975		slpi: remoteproc@5c00000 {
1976			compatible = "qcom,sm8350-slpi-pas";
1977			reg = <0 0x05c00000 0 0x4000>;
1978
1979			interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1980					      <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1981					      <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1982					      <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1983					      <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1984			interrupt-names = "wdog", "fatal", "ready",
1985					  "handover", "stop-ack";
1986
1987			clocks = <&rpmhcc RPMH_CXO_CLK>;
1988			clock-names = "xo";
1989
1990			power-domains = <&rpmhpd 4>,
1991					<&rpmhpd 5>;
1992			power-domain-names = "lcx", "lmx";
1993
1994			memory-region = <&pil_slpi_mem>;
1995
1996			qcom,qmp = <&aoss_qmp>;
1997
1998			qcom,smem-states = <&smp2p_slpi_out 0>;
1999			qcom,smem-state-names = "stop";
2000
2001			status = "disabled";
2002
2003			glink-edge {
2004				interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2005							     IPCC_MPROC_SIGNAL_GLINK_QMP
2006							     IRQ_TYPE_EDGE_RISING>;
2007				mboxes = <&ipcc IPCC_CLIENT_SLPI
2008						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2009
2010				label = "slpi";
2011				qcom,remote-pid = <3>;
2012
2013				fastrpc {
2014					compatible = "qcom,fastrpc";
2015					qcom,glink-channels = "fastrpcglink-apps-dsp";
2016					label = "sdsp";
2017					#address-cells = <1>;
2018					#size-cells = <0>;
2019
2020					compute-cb@1 {
2021						compatible = "qcom,fastrpc-compute-cb";
2022						reg = <1>;
2023						iommus = <&apps_smmu 0x0541 0x0>;
2024					};
2025
2026					compute-cb@2 {
2027						compatible = "qcom,fastrpc-compute-cb";
2028						reg = <2>;
2029						iommus = <&apps_smmu 0x0542 0x0>;
2030					};
2031
2032					compute-cb@3 {
2033						compatible = "qcom,fastrpc-compute-cb";
2034						reg = <3>;
2035						iommus = <&apps_smmu 0x0543 0x0>;
2036						/* note: shared-cb = <4> in downstream */
2037					};
2038				};
2039			};
2040		};
2041
2042		cdsp: remoteproc@98900000 {
2043			compatible = "qcom,sm8350-cdsp-pas";
2044			reg = <0 0x098900000 0 0x1400000>;
2045
2046			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2047					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2048					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2049					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2050					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2051			interrupt-names = "wdog", "fatal", "ready",
2052					  "handover", "stop-ack";
2053
2054			clocks = <&rpmhcc RPMH_CXO_CLK>;
2055			clock-names = "xo";
2056
2057			power-domains = <&rpmhpd 0>,
2058					<&rpmhpd 10>;
2059			power-domain-names = "cx", "mxc";
2060
2061			interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
2062
2063			memory-region = <&pil_cdsp_mem>;
2064
2065			qcom,qmp = <&aoss_qmp>;
2066
2067			qcom,smem-states = <&smp2p_cdsp_out 0>;
2068			qcom,smem-state-names = "stop";
2069
2070			status = "disabled";
2071
2072			glink-edge {
2073				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2074							     IPCC_MPROC_SIGNAL_GLINK_QMP
2075							     IRQ_TYPE_EDGE_RISING>;
2076				mboxes = <&ipcc IPCC_CLIENT_CDSP
2077						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2078
2079				label = "cdsp";
2080				qcom,remote-pid = <5>;
2081
2082				fastrpc {
2083					compatible = "qcom,fastrpc";
2084					qcom,glink-channels = "fastrpcglink-apps-dsp";
2085					label = "cdsp";
2086					#address-cells = <1>;
2087					#size-cells = <0>;
2088
2089					compute-cb@1 {
2090						compatible = "qcom,fastrpc-compute-cb";
2091						reg = <1>;
2092						iommus = <&apps_smmu 0x2161 0x0400>,
2093							 <&apps_smmu 0x1181 0x0420>;
2094					};
2095
2096					compute-cb@2 {
2097						compatible = "qcom,fastrpc-compute-cb";
2098						reg = <2>;
2099						iommus = <&apps_smmu 0x2162 0x0400>,
2100							 <&apps_smmu 0x1182 0x0420>;
2101					};
2102
2103					compute-cb@3 {
2104						compatible = "qcom,fastrpc-compute-cb";
2105						reg = <3>;
2106						iommus = <&apps_smmu 0x2163 0x0400>,
2107							 <&apps_smmu 0x1183 0x0420>;
2108					};
2109
2110					compute-cb@4 {
2111						compatible = "qcom,fastrpc-compute-cb";
2112						reg = <4>;
2113						iommus = <&apps_smmu 0x2164 0x0400>,
2114							 <&apps_smmu 0x1184 0x0420>;
2115					};
2116
2117					compute-cb@5 {
2118						compatible = "qcom,fastrpc-compute-cb";
2119						reg = <5>;
2120						iommus = <&apps_smmu 0x2165 0x0400>,
2121							 <&apps_smmu 0x1185 0x0420>;
2122					};
2123
2124					compute-cb@6 {
2125						compatible = "qcom,fastrpc-compute-cb";
2126						reg = <6>;
2127						iommus = <&apps_smmu 0x2166 0x0400>,
2128							 <&apps_smmu 0x1186 0x0420>;
2129					};
2130
2131					compute-cb@7 {
2132						compatible = "qcom,fastrpc-compute-cb";
2133						reg = <7>;
2134						iommus = <&apps_smmu 0x2167 0x0400>,
2135							 <&apps_smmu 0x1187 0x0420>;
2136					};
2137
2138					compute-cb@8 {
2139						compatible = "qcom,fastrpc-compute-cb";
2140						reg = <8>;
2141						iommus = <&apps_smmu 0x2168 0x0400>,
2142							 <&apps_smmu 0x1188 0x0420>;
2143					};
2144
2145					/* note: secure cb9 in downstream */
2146				};
2147			};
2148		};
2149
2150		usb_1_hsphy: phy@88e3000 {
2151			compatible = "qcom,sm8350-usb-hs-phy",
2152				     "qcom,usb-snps-hs-7nm-phy";
2153			reg = <0 0x088e3000 0 0x400>;
2154			status = "disabled";
2155			#phy-cells = <0>;
2156
2157			clocks = <&rpmhcc RPMH_CXO_CLK>;
2158			clock-names = "ref";
2159
2160			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2161		};
2162
2163		usb_2_hsphy: phy@88e4000 {
2164			compatible = "qcom,sm8250-usb-hs-phy",
2165				     "qcom,usb-snps-hs-7nm-phy";
2166			reg = <0 0x088e4000 0 0x400>;
2167			status = "disabled";
2168			#phy-cells = <0>;
2169
2170			clocks = <&rpmhcc RPMH_CXO_CLK>;
2171			clock-names = "ref";
2172
2173			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2174		};
2175
2176		usb_1_qmpphy: phy-wrapper@88e9000 {
2177			compatible = "qcom,sm8350-qmp-usb3-phy";
2178			reg = <0 0x088e9000 0 0x200>,
2179			      <0 0x088e8000 0 0x20>;
2180			status = "disabled";
2181			#address-cells = <2>;
2182			#size-cells = <2>;
2183			ranges;
2184
2185			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2186				 <&rpmhcc RPMH_CXO_CLK>,
2187				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2188			clock-names = "aux", "ref_clk_src", "com_aux";
2189
2190			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2191				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2192			reset-names = "phy", "common";
2193
2194			usb_1_ssphy: phy@88e9200 {
2195				reg = <0 0x088e9200 0 0x200>,
2196				      <0 0x088e9400 0 0x200>,
2197				      <0 0x088e9c00 0 0x400>,
2198				      <0 0x088e9600 0 0x200>,
2199				      <0 0x088e9800 0 0x200>,
2200				      <0 0x088e9a00 0 0x100>;
2201				#phy-cells = <0>;
2202				#clock-cells = <1>;
2203				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2204				clock-names = "pipe0";
2205				clock-output-names = "usb3_phy_pipe_clk_src";
2206			};
2207		};
2208
2209		usb_2_qmpphy: phy-wrapper@88eb000 {
2210			compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2211			reg = <0 0x088eb000 0 0x200>;
2212			status = "disabled";
2213			#address-cells = <2>;
2214			#size-cells = <2>;
2215			ranges;
2216
2217			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2218				 <&rpmhcc RPMH_CXO_CLK>,
2219				 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2220				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2221			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2222
2223			resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2224				 <&gcc GCC_USB3_PHY_SEC_BCR>;
2225			reset-names = "phy", "common";
2226
2227			usb_2_ssphy: phy@88ebe00 {
2228				reg = <0 0x088ebe00 0 0x200>,
2229				      <0 0x088ec000 0 0x200>,
2230				      <0 0x088eb200 0 0x1100>;
2231				#phy-cells = <0>;
2232				#clock-cells = <1>;
2233				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2234				clock-names = "pipe0";
2235				clock-output-names = "usb3_uni_phy_pipe_clk_src";
2236			};
2237		};
2238
2239		dc_noc: interconnect@90c0000 {
2240			compatible = "qcom,sm8350-dc-noc";
2241			reg = <0 0x090c0000 0 0x4200>;
2242			#interconnect-cells = <1>;
2243			qcom,bcm-voters = <&apps_bcm_voter>;
2244		};
2245
2246		gem_noc: interconnect@9100000 {
2247			compatible = "qcom,sm8350-gem-noc";
2248			reg = <0 0x09100000 0 0xb4000>;
2249			#interconnect-cells = <1>;
2250			qcom,bcm-voters = <&apps_bcm_voter>;
2251		};
2252
2253		system-cache-controller@9200000 {
2254			compatible = "qcom,sm8350-llcc";
2255			reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2256			reg-names = "llcc_base", "llcc_broadcast_base";
2257		};
2258
2259		usb_1: usb@a6f8800 {
2260			compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2261			reg = <0 0x0a6f8800 0 0x400>;
2262			status = "disabled";
2263			#address-cells = <2>;
2264			#size-cells = <2>;
2265			ranges;
2266
2267			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2268				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2269				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2270				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2271				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2272			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2273				      "sleep";
2274
2275			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2276					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2277			assigned-clock-rates = <19200000>, <200000000>;
2278
2279			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2280					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2281					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2282					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2283			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2284					  "dm_hs_phy_irq", "ss_phy_irq";
2285
2286			power-domains = <&gcc USB30_PRIM_GDSC>;
2287
2288			resets = <&gcc GCC_USB30_PRIM_BCR>;
2289
2290			usb_1_dwc3: usb@a600000 {
2291				compatible = "snps,dwc3";
2292				reg = <0 0x0a600000 0 0xcd00>;
2293				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2294				iommus = <&apps_smmu 0x0 0x0>;
2295				snps,dis_u2_susphy_quirk;
2296				snps,dis_enblslpm_quirk;
2297				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2298				phy-names = "usb2-phy", "usb3-phy";
2299			};
2300		};
2301
2302		usb_2: usb@a8f8800 {
2303			compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2304			reg = <0 0x0a8f8800 0 0x400>;
2305			status = "disabled";
2306			#address-cells = <2>;
2307			#size-cells = <2>;
2308			ranges;
2309
2310			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2311				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2312				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2313				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2314				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2315				 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2316			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2317				      "sleep", "xo";
2318
2319			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2320					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
2321			assigned-clock-rates = <19200000>, <200000000>;
2322
2323			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2324					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2325					      <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2326					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2327			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2328					  "dm_hs_phy_irq", "ss_phy_irq";
2329
2330			power-domains = <&gcc USB30_SEC_GDSC>;
2331
2332			resets = <&gcc GCC_USB30_SEC_BCR>;
2333
2334			usb_2_dwc3: usb@a800000 {
2335				compatible = "snps,dwc3";
2336				reg = <0 0x0a800000 0 0xcd00>;
2337				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2338				iommus = <&apps_smmu 0x20 0x0>;
2339				snps,dis_u2_susphy_quirk;
2340				snps,dis_enblslpm_quirk;
2341				phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2342				phy-names = "usb2-phy", "usb3-phy";
2343			};
2344		};
2345
2346		adsp: remoteproc@17300000 {
2347			compatible = "qcom,sm8350-adsp-pas";
2348			reg = <0 0x17300000 0 0x100>;
2349
2350			interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2351					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2352					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2353					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2354					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2355			interrupt-names = "wdog", "fatal", "ready",
2356					  "handover", "stop-ack";
2357
2358			clocks = <&rpmhcc RPMH_CXO_CLK>;
2359			clock-names = "xo";
2360
2361			power-domains = <&rpmhpd 4>,
2362					<&rpmhpd 5>;
2363			power-domain-names = "lcx", "lmx";
2364
2365			memory-region = <&pil_adsp_mem>;
2366
2367			qcom,qmp = <&aoss_qmp>;
2368
2369			qcom,smem-states = <&smp2p_adsp_out 0>;
2370			qcom,smem-state-names = "stop";
2371
2372			status = "disabled";
2373
2374			glink-edge {
2375				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2376							     IPCC_MPROC_SIGNAL_GLINK_QMP
2377							     IRQ_TYPE_EDGE_RISING>;
2378				mboxes = <&ipcc IPCC_CLIENT_LPASS
2379						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2380
2381				label = "lpass";
2382				qcom,remote-pid = <2>;
2383
2384				fastrpc {
2385					compatible = "qcom,fastrpc";
2386					qcom,glink-channels = "fastrpcglink-apps-dsp";
2387					label = "adsp";
2388					#address-cells = <1>;
2389					#size-cells = <0>;
2390
2391					compute-cb@3 {
2392						compatible = "qcom,fastrpc-compute-cb";
2393						reg = <3>;
2394						iommus = <&apps_smmu 0x1803 0x0>;
2395					};
2396
2397					compute-cb@4 {
2398						compatible = "qcom,fastrpc-compute-cb";
2399						reg = <4>;
2400						iommus = <&apps_smmu 0x1804 0x0>;
2401					};
2402
2403					compute-cb@5 {
2404						compatible = "qcom,fastrpc-compute-cb";
2405						reg = <5>;
2406						iommus = <&apps_smmu 0x1805 0x0>;
2407					};
2408				};
2409			};
2410		};
2411	};
2412
2413	thermal_zones: thermal-zones {
2414		cpu0-thermal {
2415			polling-delay-passive = <250>;
2416			polling-delay = <1000>;
2417
2418			thermal-sensors = <&tsens0 1>;
2419
2420			trips {
2421				cpu0_alert0: trip-point0 {
2422					temperature = <90000>;
2423					hysteresis = <2000>;
2424					type = "passive";
2425				};
2426
2427				cpu0_alert1: trip-point1 {
2428					temperature = <95000>;
2429					hysteresis = <2000>;
2430					type = "passive";
2431				};
2432
2433				cpu0_crit: cpu_crit {
2434					temperature = <110000>;
2435					hysteresis = <1000>;
2436					type = "critical";
2437				};
2438			};
2439
2440			cooling-maps {
2441				map0 {
2442					trip = <&cpu0_alert0>;
2443					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2444							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2445							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2446							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2447				};
2448				map1 {
2449					trip = <&cpu0_alert1>;
2450					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2451							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2452							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2453							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2454				};
2455			};
2456		};
2457
2458		cpu1-thermal {
2459			polling-delay-passive = <250>;
2460			polling-delay = <1000>;
2461
2462			thermal-sensors = <&tsens0 2>;
2463
2464			trips {
2465				cpu1_alert0: trip-point0 {
2466					temperature = <90000>;
2467					hysteresis = <2000>;
2468					type = "passive";
2469				};
2470
2471				cpu1_alert1: trip-point1 {
2472					temperature = <95000>;
2473					hysteresis = <2000>;
2474					type = "passive";
2475				};
2476
2477				cpu1_crit: cpu_crit {
2478					temperature = <110000>;
2479					hysteresis = <1000>;
2480					type = "critical";
2481				};
2482			};
2483
2484			cooling-maps {
2485				map0 {
2486					trip = <&cpu1_alert0>;
2487					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2488							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2489							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2490							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2491				};
2492				map1 {
2493					trip = <&cpu1_alert1>;
2494					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2495							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2496							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2497							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2498				};
2499			};
2500		};
2501
2502		cpu2-thermal {
2503			polling-delay-passive = <250>;
2504			polling-delay = <1000>;
2505
2506			thermal-sensors = <&tsens0 3>;
2507
2508			trips {
2509				cpu2_alert0: trip-point0 {
2510					temperature = <90000>;
2511					hysteresis = <2000>;
2512					type = "passive";
2513				};
2514
2515				cpu2_alert1: trip-point1 {
2516					temperature = <95000>;
2517					hysteresis = <2000>;
2518					type = "passive";
2519				};
2520
2521				cpu2_crit: cpu_crit {
2522					temperature = <110000>;
2523					hysteresis = <1000>;
2524					type = "critical";
2525				};
2526			};
2527
2528			cooling-maps {
2529				map0 {
2530					trip = <&cpu2_alert0>;
2531					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2532							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2533							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2534							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2535				};
2536				map1 {
2537					trip = <&cpu2_alert1>;
2538					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2539							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2540							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2541							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2542				};
2543			};
2544		};
2545
2546		cpu3-thermal {
2547			polling-delay-passive = <250>;
2548			polling-delay = <1000>;
2549
2550			thermal-sensors = <&tsens0 4>;
2551
2552			trips {
2553				cpu3_alert0: trip-point0 {
2554					temperature = <90000>;
2555					hysteresis = <2000>;
2556					type = "passive";
2557				};
2558
2559				cpu3_alert1: trip-point1 {
2560					temperature = <95000>;
2561					hysteresis = <2000>;
2562					type = "passive";
2563				};
2564
2565				cpu3_crit: cpu_crit {
2566					temperature = <110000>;
2567					hysteresis = <1000>;
2568					type = "critical";
2569				};
2570			};
2571
2572			cooling-maps {
2573				map0 {
2574					trip = <&cpu3_alert0>;
2575					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2576							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2577							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2578							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2579				};
2580				map1 {
2581					trip = <&cpu3_alert1>;
2582					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2583							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2584							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2585							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2586				};
2587			};
2588		};
2589
2590		cpu4-top-thermal {
2591			polling-delay-passive = <250>;
2592			polling-delay = <1000>;
2593
2594			thermal-sensors = <&tsens0 7>;
2595
2596			trips {
2597				cpu4_top_alert0: trip-point0 {
2598					temperature = <90000>;
2599					hysteresis = <2000>;
2600					type = "passive";
2601				};
2602
2603				cpu4_top_alert1: trip-point1 {
2604					temperature = <95000>;
2605					hysteresis = <2000>;
2606					type = "passive";
2607				};
2608
2609				cpu4_top_crit: cpu_crit {
2610					temperature = <110000>;
2611					hysteresis = <1000>;
2612					type = "critical";
2613				};
2614			};
2615
2616			cooling-maps {
2617				map0 {
2618					trip = <&cpu4_top_alert0>;
2619					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2620							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2621							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2622							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2623				};
2624				map1 {
2625					trip = <&cpu4_top_alert1>;
2626					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2627							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2628							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2629							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2630				};
2631			};
2632		};
2633
2634		cpu5-top-thermal {
2635			polling-delay-passive = <250>;
2636			polling-delay = <1000>;
2637
2638			thermal-sensors = <&tsens0 8>;
2639
2640			trips {
2641				cpu5_top_alert0: trip-point0 {
2642					temperature = <90000>;
2643					hysteresis = <2000>;
2644					type = "passive";
2645				};
2646
2647				cpu5_top_alert1: trip-point1 {
2648					temperature = <95000>;
2649					hysteresis = <2000>;
2650					type = "passive";
2651				};
2652
2653				cpu5_top_crit: cpu_crit {
2654					temperature = <110000>;
2655					hysteresis = <1000>;
2656					type = "critical";
2657				};
2658			};
2659
2660			cooling-maps {
2661				map0 {
2662					trip = <&cpu5_top_alert0>;
2663					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2664							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2665							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2666							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2667				};
2668				map1 {
2669					trip = <&cpu5_top_alert1>;
2670					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2671							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2672							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2673							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2674				};
2675			};
2676		};
2677
2678		cpu6-top-thermal {
2679			polling-delay-passive = <250>;
2680			polling-delay = <1000>;
2681
2682			thermal-sensors = <&tsens0 9>;
2683
2684			trips {
2685				cpu6_top_alert0: trip-point0 {
2686					temperature = <90000>;
2687					hysteresis = <2000>;
2688					type = "passive";
2689				};
2690
2691				cpu6_top_alert1: trip-point1 {
2692					temperature = <95000>;
2693					hysteresis = <2000>;
2694					type = "passive";
2695				};
2696
2697				cpu6_top_crit: cpu_crit {
2698					temperature = <110000>;
2699					hysteresis = <1000>;
2700					type = "critical";
2701				};
2702			};
2703
2704			cooling-maps {
2705				map0 {
2706					trip = <&cpu6_top_alert0>;
2707					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2708							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2709							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2710							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2711				};
2712				map1 {
2713					trip = <&cpu6_top_alert1>;
2714					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2715							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2716							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2717							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2718				};
2719			};
2720		};
2721
2722		cpu7-top-thermal {
2723			polling-delay-passive = <250>;
2724			polling-delay = <1000>;
2725
2726			thermal-sensors = <&tsens0 10>;
2727
2728			trips {
2729				cpu7_top_alert0: trip-point0 {
2730					temperature = <90000>;
2731					hysteresis = <2000>;
2732					type = "passive";
2733				};
2734
2735				cpu7_top_alert1: trip-point1 {
2736					temperature = <95000>;
2737					hysteresis = <2000>;
2738					type = "passive";
2739				};
2740
2741				cpu7_top_crit: cpu_crit {
2742					temperature = <110000>;
2743					hysteresis = <1000>;
2744					type = "critical";
2745				};
2746			};
2747
2748			cooling-maps {
2749				map0 {
2750					trip = <&cpu7_top_alert0>;
2751					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2752							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2753							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2754							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2755				};
2756				map1 {
2757					trip = <&cpu7_top_alert1>;
2758					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2759							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2760							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2761							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2762				};
2763			};
2764		};
2765
2766		cpu4-bottom-thermal {
2767			polling-delay-passive = <250>;
2768			polling-delay = <1000>;
2769
2770			thermal-sensors = <&tsens0 11>;
2771
2772			trips {
2773				cpu4_bottom_alert0: trip-point0 {
2774					temperature = <90000>;
2775					hysteresis = <2000>;
2776					type = "passive";
2777				};
2778
2779				cpu4_bottom_alert1: trip-point1 {
2780					temperature = <95000>;
2781					hysteresis = <2000>;
2782					type = "passive";
2783				};
2784
2785				cpu4_bottom_crit: cpu_crit {
2786					temperature = <110000>;
2787					hysteresis = <1000>;
2788					type = "critical";
2789				};
2790			};
2791
2792			cooling-maps {
2793				map0 {
2794					trip = <&cpu4_bottom_alert0>;
2795					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2796							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2797							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2798							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2799				};
2800				map1 {
2801					trip = <&cpu4_bottom_alert1>;
2802					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2803							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2804							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2805							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2806				};
2807			};
2808		};
2809
2810		cpu5-bottom-thermal {
2811			polling-delay-passive = <250>;
2812			polling-delay = <1000>;
2813
2814			thermal-sensors = <&tsens0 12>;
2815
2816			trips {
2817				cpu5_bottom_alert0: trip-point0 {
2818					temperature = <90000>;
2819					hysteresis = <2000>;
2820					type = "passive";
2821				};
2822
2823				cpu5_bottom_alert1: trip-point1 {
2824					temperature = <95000>;
2825					hysteresis = <2000>;
2826					type = "passive";
2827				};
2828
2829				cpu5_bottom_crit: cpu_crit {
2830					temperature = <110000>;
2831					hysteresis = <1000>;
2832					type = "critical";
2833				};
2834			};
2835
2836			cooling-maps {
2837				map0 {
2838					trip = <&cpu5_bottom_alert0>;
2839					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2840							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2841							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2842							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2843				};
2844				map1 {
2845					trip = <&cpu5_bottom_alert1>;
2846					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2847							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2848							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2849							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2850				};
2851			};
2852		};
2853
2854		cpu6-bottom-thermal {
2855			polling-delay-passive = <250>;
2856			polling-delay = <1000>;
2857
2858			thermal-sensors = <&tsens0 13>;
2859
2860			trips {
2861				cpu6_bottom_alert0: trip-point0 {
2862					temperature = <90000>;
2863					hysteresis = <2000>;
2864					type = "passive";
2865				};
2866
2867				cpu6_bottom_alert1: trip-point1 {
2868					temperature = <95000>;
2869					hysteresis = <2000>;
2870					type = "passive";
2871				};
2872
2873				cpu6_bottom_crit: cpu_crit {
2874					temperature = <110000>;
2875					hysteresis = <1000>;
2876					type = "critical";
2877				};
2878			};
2879
2880			cooling-maps {
2881				map0 {
2882					trip = <&cpu6_bottom_alert0>;
2883					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2884							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2885							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2886							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2887				};
2888				map1 {
2889					trip = <&cpu6_bottom_alert1>;
2890					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2891							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2892							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2893							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2894				};
2895			};
2896		};
2897
2898		cpu7-bottom-thermal {
2899			polling-delay-passive = <250>;
2900			polling-delay = <1000>;
2901
2902			thermal-sensors = <&tsens0 14>;
2903
2904			trips {
2905				cpu7_bottom_alert0: trip-point0 {
2906					temperature = <90000>;
2907					hysteresis = <2000>;
2908					type = "passive";
2909				};
2910
2911				cpu7_bottom_alert1: trip-point1 {
2912					temperature = <95000>;
2913					hysteresis = <2000>;
2914					type = "passive";
2915				};
2916
2917				cpu7_bottom_crit: cpu_crit {
2918					temperature = <110000>;
2919					hysteresis = <1000>;
2920					type = "critical";
2921				};
2922			};
2923
2924			cooling-maps {
2925				map0 {
2926					trip = <&cpu7_bottom_alert0>;
2927					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2928							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2929							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2930							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2931				};
2932				map1 {
2933					trip = <&cpu7_bottom_alert1>;
2934					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2935							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2936							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2937							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2938				};
2939			};
2940		};
2941
2942		aoss0-thermal {
2943			polling-delay-passive = <250>;
2944			polling-delay = <1000>;
2945
2946			thermal-sensors = <&tsens0 0>;
2947
2948			trips {
2949				aoss0_alert0: trip-point0 {
2950					temperature = <90000>;
2951					hysteresis = <2000>;
2952					type = "hot";
2953				};
2954			};
2955		};
2956
2957		cluster0-thermal {
2958			polling-delay-passive = <250>;
2959			polling-delay = <1000>;
2960
2961			thermal-sensors = <&tsens0 5>;
2962
2963			trips {
2964				cluster0_alert0: trip-point0 {
2965					temperature = <90000>;
2966					hysteresis = <2000>;
2967					type = "hot";
2968				};
2969				cluster0_crit: cluster0_crit {
2970					temperature = <110000>;
2971					hysteresis = <2000>;
2972					type = "critical";
2973				};
2974			};
2975		};
2976
2977		cluster1-thermal {
2978			polling-delay-passive = <250>;
2979			polling-delay = <1000>;
2980
2981			thermal-sensors = <&tsens0 6>;
2982
2983			trips {
2984				cluster1_alert0: trip-point0 {
2985					temperature = <90000>;
2986					hysteresis = <2000>;
2987					type = "hot";
2988				};
2989				cluster1_crit: cluster1_crit {
2990					temperature = <110000>;
2991					hysteresis = <2000>;
2992					type = "critical";
2993				};
2994			};
2995		};
2996
2997		aoss1-thermal {
2998			polling-delay-passive = <250>;
2999			polling-delay = <1000>;
3000
3001			thermal-sensors = <&tsens1 0>;
3002
3003			trips {
3004				aoss1_alert0: trip-point0 {
3005					temperature = <90000>;
3006					hysteresis = <2000>;
3007					type = "hot";
3008				};
3009			};
3010		};
3011
3012		gpu-thermal-top {
3013			polling-delay-passive = <250>;
3014			polling-delay = <1000>;
3015
3016			thermal-sensors = <&tsens1 1>;
3017
3018			trips {
3019				gpu1_alert0: trip-point0 {
3020					temperature = <90000>;
3021					hysteresis = <1000>;
3022					type = "hot";
3023				};
3024			};
3025		};
3026
3027		gpu-thermal-bottom {
3028			polling-delay-passive = <250>;
3029			polling-delay = <1000>;
3030
3031			thermal-sensors = <&tsens1 2>;
3032
3033			trips {
3034				gpu2_alert0: trip-point0 {
3035					temperature = <90000>;
3036					hysteresis = <1000>;
3037					type = "hot";
3038				};
3039			};
3040		};
3041
3042		nspss1-thermal {
3043			polling-delay-passive = <250>;
3044			polling-delay = <1000>;
3045
3046			thermal-sensors = <&tsens1 3>;
3047
3048			trips {
3049				nspss1_alert0: trip-point0 {
3050					temperature = <90000>;
3051					hysteresis = <1000>;
3052					type = "hot";
3053				};
3054			};
3055		};
3056
3057		nspss2-thermal {
3058			polling-delay-passive = <250>;
3059			polling-delay = <1000>;
3060
3061			thermal-sensors = <&tsens1 4>;
3062
3063			trips {
3064				nspss2_alert0: trip-point0 {
3065					temperature = <90000>;
3066					hysteresis = <1000>;
3067					type = "hot";
3068				};
3069			};
3070		};
3071
3072		nspss3-thermal {
3073			polling-delay-passive = <250>;
3074			polling-delay = <1000>;
3075
3076			thermal-sensors = <&tsens1 5>;
3077
3078			trips {
3079				nspss3_alert0: trip-point0 {
3080					temperature = <90000>;
3081					hysteresis = <1000>;
3082					type = "hot";
3083				};
3084			};
3085		};
3086
3087		video-thermal {
3088			polling-delay-passive = <250>;
3089			polling-delay = <1000>;
3090
3091			thermal-sensors = <&tsens1 6>;
3092
3093			trips {
3094				video_alert0: trip-point0 {
3095					temperature = <90000>;
3096					hysteresis = <2000>;
3097					type = "hot";
3098				};
3099			};
3100		};
3101
3102		mem-thermal {
3103			polling-delay-passive = <250>;
3104			polling-delay = <1000>;
3105
3106			thermal-sensors = <&tsens1 7>;
3107
3108			trips {
3109				mem_alert0: trip-point0 {
3110					temperature = <90000>;
3111					hysteresis = <2000>;
3112					type = "hot";
3113				};
3114			};
3115		};
3116
3117		modem1-thermal-top {
3118			polling-delay-passive = <250>;
3119			polling-delay = <1000>;
3120
3121			thermal-sensors = <&tsens1 8>;
3122
3123			trips {
3124				modem1_alert0: trip-point0 {
3125					temperature = <90000>;
3126					hysteresis = <2000>;
3127					type = "hot";
3128				};
3129			};
3130		};
3131
3132		modem2-thermal-top {
3133			polling-delay-passive = <250>;
3134			polling-delay = <1000>;
3135
3136			thermal-sensors = <&tsens1 9>;
3137
3138			trips {
3139				modem2_alert0: trip-point0 {
3140					temperature = <90000>;
3141					hysteresis = <2000>;
3142					type = "hot";
3143				};
3144			};
3145		};
3146
3147		modem3-thermal-top {
3148			polling-delay-passive = <250>;
3149			polling-delay = <1000>;
3150
3151			thermal-sensors = <&tsens1 10>;
3152
3153			trips {
3154				modem3_alert0: trip-point0 {
3155					temperature = <90000>;
3156					hysteresis = <2000>;
3157					type = "hot";
3158				};
3159			};
3160		};
3161
3162		modem4-thermal-top {
3163			polling-delay-passive = <250>;
3164			polling-delay = <1000>;
3165
3166			thermal-sensors = <&tsens1 11>;
3167
3168			trips {
3169				modem4_alert0: trip-point0 {
3170					temperature = <90000>;
3171					hysteresis = <2000>;
3172					type = "hot";
3173				};
3174			};
3175		};
3176
3177		camera-thermal-top {
3178			polling-delay-passive = <250>;
3179			polling-delay = <1000>;
3180
3181			thermal-sensors = <&tsens1 12>;
3182
3183			trips {
3184				camera1_alert0: trip-point0 {
3185					temperature = <90000>;
3186					hysteresis = <2000>;
3187					type = "hot";
3188				};
3189			};
3190		};
3191
3192		cam-thermal-bottom {
3193			polling-delay-passive = <250>;
3194			polling-delay = <1000>;
3195
3196			thermal-sensors = <&tsens1 13>;
3197
3198			trips {
3199				camera2_alert0: trip-point0 {
3200					temperature = <90000>;
3201					hysteresis = <2000>;
3202					type = "hot";
3203				};
3204			};
3205		};
3206	};
3207
3208	timer {
3209		compatible = "arm,armv8-timer";
3210		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3211			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3212			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3213			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3214	};
3215};
3216