1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 8#include <dt-bindings/clock/qcom,gcc-sm8350.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,sm8350.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/interconnect/qcom,sm8350.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 clock-frequency = <32000>; 38 #clock-cells = <0>; 39 }; 40 41 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { 42 compatible = "fixed-clock"; 43 clock-frequency = <1000>; 44 #clock-cells = <0>; 45 }; 46 47 ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { 48 compatible = "fixed-clock"; 49 clock-frequency = <1000>; 50 #clock-cells = <0>; 51 }; 52 53 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { 54 compatible = "fixed-clock"; 55 clock-frequency = <1000>; 56 #clock-cells = <0>; 57 }; 58 }; 59 60 cpus { 61 #address-cells = <2>; 62 #size-cells = <0>; 63 64 CPU0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo685"; 67 reg = <0x0 0x0>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_0>; 70 qcom,freq-domain = <&cpufreq_hw 0>; 71 power-domains = <&CPU_PD0>; 72 power-domain-names = "psci"; 73 #cooling-cells = <2>; 74 L2_0: l2-cache { 75 compatible = "cache"; 76 next-level-cache = <&L3_0>; 77 L3_0: l3-cache { 78 compatible = "cache"; 79 }; 80 }; 81 }; 82 83 CPU1: cpu@100 { 84 device_type = "cpu"; 85 compatible = "qcom,kryo685"; 86 reg = <0x0 0x100>; 87 enable-method = "psci"; 88 next-level-cache = <&L2_100>; 89 qcom,freq-domain = <&cpufreq_hw 0>; 90 power-domains = <&CPU_PD1>; 91 power-domain-names = "psci"; 92 #cooling-cells = <2>; 93 L2_100: l2-cache { 94 compatible = "cache"; 95 next-level-cache = <&L3_0>; 96 }; 97 }; 98 99 CPU2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "qcom,kryo685"; 102 reg = <0x0 0x200>; 103 enable-method = "psci"; 104 next-level-cache = <&L2_200>; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 power-domains = <&CPU_PD2>; 107 power-domain-names = "psci"; 108 #cooling-cells = <2>; 109 L2_200: l2-cache { 110 compatible = "cache"; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo685"; 118 reg = <0x0 0x300>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 power-domains = <&CPU_PD3>; 123 power-domain-names = "psci"; 124 #cooling-cells = <2>; 125 L2_300: l2-cache { 126 compatible = "cache"; 127 next-level-cache = <&L3_0>; 128 }; 129 }; 130 131 CPU4: cpu@400 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo685"; 134 reg = <0x0 0x400>; 135 enable-method = "psci"; 136 next-level-cache = <&L2_400>; 137 qcom,freq-domain = <&cpufreq_hw 1>; 138 power-domains = <&CPU_PD4>; 139 power-domain-names = "psci"; 140 #cooling-cells = <2>; 141 L2_400: l2-cache { 142 compatible = "cache"; 143 next-level-cache = <&L3_0>; 144 }; 145 }; 146 147 CPU5: cpu@500 { 148 device_type = "cpu"; 149 compatible = "qcom,kryo685"; 150 reg = <0x0 0x500>; 151 enable-method = "psci"; 152 next-level-cache = <&L2_500>; 153 qcom,freq-domain = <&cpufreq_hw 1>; 154 power-domains = <&CPU_PD5>; 155 power-domain-names = "psci"; 156 #cooling-cells = <2>; 157 L2_500: l2-cache { 158 compatible = "cache"; 159 next-level-cache = <&L3_0>; 160 }; 161 162 }; 163 164 CPU6: cpu@600 { 165 device_type = "cpu"; 166 compatible = "qcom,kryo685"; 167 reg = <0x0 0x600>; 168 enable-method = "psci"; 169 next-level-cache = <&L2_600>; 170 qcom,freq-domain = <&cpufreq_hw 1>; 171 power-domains = <&CPU_PD6>; 172 power-domain-names = "psci"; 173 #cooling-cells = <2>; 174 L2_600: l2-cache { 175 compatible = "cache"; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU7: cpu@700 { 181 device_type = "cpu"; 182 compatible = "qcom,kryo685"; 183 reg = <0x0 0x700>; 184 enable-method = "psci"; 185 next-level-cache = <&L2_700>; 186 qcom,freq-domain = <&cpufreq_hw 2>; 187 power-domains = <&CPU_PD7>; 188 power-domain-names = "psci"; 189 #cooling-cells = <2>; 190 L2_700: l2-cache { 191 compatible = "cache"; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 cpu-map { 197 cluster0 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 214 core4 { 215 cpu = <&CPU4>; 216 }; 217 218 core5 { 219 cpu = <&CPU5>; 220 }; 221 222 core6 { 223 cpu = <&CPU6>; 224 }; 225 226 core7 { 227 cpu = <&CPU7>; 228 }; 229 }; 230 }; 231 232 idle-states { 233 entry-method = "psci"; 234 235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 236 compatible = "arm,idle-state"; 237 idle-state-name = "silver-rail-power-collapse"; 238 arm,psci-suspend-param = <0x40000004>; 239 entry-latency-us = <355>; 240 exit-latency-us = <909>; 241 min-residency-us = <3934>; 242 local-timer-stop; 243 }; 244 245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "gold-rail-power-collapse"; 248 arm,psci-suspend-param = <0x40000004>; 249 entry-latency-us = <241>; 250 exit-latency-us = <1461>; 251 min-residency-us = <4488>; 252 local-timer-stop; 253 }; 254 }; 255 256 domain-idle-states { 257 CLUSTER_SLEEP_0: cluster-sleep-0 { 258 compatible = "domain-idle-state"; 259 idle-state-name = "cluster-power-collapse"; 260 arm,psci-suspend-param = <0x4100c344>; 261 entry-latency-us = <3263>; 262 exit-latency-us = <6562>; 263 min-residency-us = <9987>; 264 local-timer-stop; 265 }; 266 }; 267 }; 268 269 firmware { 270 scm: scm { 271 compatible = "qcom,scm-sm8350", "qcom,scm"; 272 #reset-cells = <1>; 273 }; 274 }; 275 276 memory@80000000 { 277 device_type = "memory"; 278 /* We expect the bootloader to fill in the size */ 279 reg = <0x0 0x80000000 0x0 0x0>; 280 }; 281 282 pmu { 283 compatible = "arm,armv8-pmuv3"; 284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 285 }; 286 287 psci { 288 compatible = "arm,psci-1.0"; 289 method = "smc"; 290 291 CPU_PD0: cpu0 { 292 #power-domain-cells = <0>; 293 power-domains = <&CLUSTER_PD>; 294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 295 }; 296 297 CPU_PD1: cpu1 { 298 #power-domain-cells = <0>; 299 power-domains = <&CLUSTER_PD>; 300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 301 }; 302 303 CPU_PD2: cpu2 { 304 #power-domain-cells = <0>; 305 power-domains = <&CLUSTER_PD>; 306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 307 }; 308 309 CPU_PD3: cpu3 { 310 #power-domain-cells = <0>; 311 power-domains = <&CLUSTER_PD>; 312 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 313 }; 314 315 CPU_PD4: cpu4 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_PD>; 318 domain-idle-states = <&BIG_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD5: cpu5 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_PD>; 324 domain-idle-states = <&BIG_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD6: cpu6 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_PD>; 330 domain-idle-states = <&BIG_CPU_SLEEP_0>; 331 }; 332 333 CPU_PD7: cpu7 { 334 #power-domain-cells = <0>; 335 power-domains = <&CLUSTER_PD>; 336 domain-idle-states = <&BIG_CPU_SLEEP_0>; 337 }; 338 339 CLUSTER_PD: cpu-cluster0 { 340 #power-domain-cells = <0>; 341 domain-idle-states = <&CLUSTER_SLEEP_0>; 342 }; 343 }; 344 345 qup_opp_table_100mhz: opp-table-qup100mhz { 346 compatible = "operating-points-v2"; 347 348 opp-50000000 { 349 opp-hz = /bits/ 64 <50000000>; 350 required-opps = <&rpmhpd_opp_min_svs>; 351 }; 352 353 opp-75000000 { 354 opp-hz = /bits/ 64 <75000000>; 355 required-opps = <&rpmhpd_opp_low_svs>; 356 }; 357 358 opp-100000000 { 359 opp-hz = /bits/ 64 <100000000>; 360 required-opps = <&rpmhpd_opp_svs>; 361 }; 362 }; 363 364 qup_opp_table_120mhz: opp-table-qup120mhz { 365 compatible = "operating-points-v2"; 366 367 opp-50000000 { 368 opp-hz = /bits/ 64 <50000000>; 369 required-opps = <&rpmhpd_opp_min_svs>; 370 }; 371 372 opp-75000000 { 373 opp-hz = /bits/ 64 <75000000>; 374 required-opps = <&rpmhpd_opp_low_svs>; 375 }; 376 377 opp-120000000 { 378 opp-hz = /bits/ 64 <120000000>; 379 required-opps = <&rpmhpd_opp_svs>; 380 }; 381 }; 382 383 reserved_memory: reserved-memory { 384 #address-cells = <2>; 385 #size-cells = <2>; 386 ranges; 387 388 hyp_mem: memory@80000000 { 389 reg = <0x0 0x80000000 0x0 0x600000>; 390 no-map; 391 }; 392 393 xbl_aop_mem: memory@80700000 { 394 no-map; 395 reg = <0x0 0x80700000 0x0 0x160000>; 396 }; 397 398 cmd_db: memory@80860000 { 399 compatible = "qcom,cmd-db"; 400 reg = <0x0 0x80860000 0x0 0x20000>; 401 no-map; 402 }; 403 404 reserved_xbl_uefi_log: memory@80880000 { 405 reg = <0x0 0x80880000 0x0 0x14000>; 406 no-map; 407 }; 408 409 smem_mem: memory@80900000 { 410 reg = <0x0 0x80900000 0x0 0x200000>; 411 no-map; 412 }; 413 414 cpucp_fw_mem: memory@80b00000 { 415 reg = <0x0 0x80b00000 0x0 0x100000>; 416 no-map; 417 }; 418 419 cdsp_secure_heap: memory@80c00000 { 420 reg = <0x0 0x80c00000 0x0 0x4600000>; 421 no-map; 422 }; 423 424 pil_camera_mem: mmeory@85200000 { 425 reg = <0x0 0x85200000 0x0 0x500000>; 426 no-map; 427 }; 428 429 pil_video_mem: memory@85700000 { 430 reg = <0x0 0x85700000 0x0 0x500000>; 431 no-map; 432 }; 433 434 pil_cvp_mem: memory@85c00000 { 435 reg = <0x0 0x85c00000 0x0 0x500000>; 436 no-map; 437 }; 438 439 pil_adsp_mem: memory@86100000 { 440 reg = <0x0 0x86100000 0x0 0x2100000>; 441 no-map; 442 }; 443 444 pil_slpi_mem: memory@88200000 { 445 reg = <0x0 0x88200000 0x0 0x1500000>; 446 no-map; 447 }; 448 449 pil_cdsp_mem: memory@89700000 { 450 reg = <0x0 0x89700000 0x0 0x1e00000>; 451 no-map; 452 }; 453 454 pil_ipa_fw_mem: memory@8b500000 { 455 reg = <0x0 0x8b500000 0x0 0x10000>; 456 no-map; 457 }; 458 459 pil_ipa_gsi_mem: memory@8b510000 { 460 reg = <0x0 0x8b510000 0x0 0xa000>; 461 no-map; 462 }; 463 464 pil_gpu_mem: memory@8b51a000 { 465 reg = <0x0 0x8b51a000 0x0 0x2000>; 466 no-map; 467 }; 468 469 pil_spss_mem: memory@8b600000 { 470 reg = <0x0 0x8b600000 0x0 0x100000>; 471 no-map; 472 }; 473 474 pil_modem_mem: memory@8b800000 { 475 reg = <0x0 0x8b800000 0x0 0x10000000>; 476 no-map; 477 }; 478 479 rmtfs_mem: memory@9b800000 { 480 compatible = "qcom,rmtfs-mem"; 481 reg = <0x0 0x9b800000 0x0 0x280000>; 482 no-map; 483 484 qcom,client-id = <1>; 485 qcom,vmid = <15>; 486 }; 487 488 hyp_reserved_mem: memory@d0000000 { 489 reg = <0x0 0xd0000000 0x0 0x800000>; 490 no-map; 491 }; 492 493 pil_trustedvm_mem: memory@d0800000 { 494 reg = <0x0 0xd0800000 0x0 0x76f7000>; 495 no-map; 496 }; 497 498 qrtr_shbuf: memory@d7ef7000 { 499 reg = <0x0 0xd7ef7000 0x0 0x9000>; 500 no-map; 501 }; 502 503 chan0_shbuf: memory@d7f00000 { 504 reg = <0x0 0xd7f00000 0x0 0x80000>; 505 no-map; 506 }; 507 508 chan1_shbuf: memory@d7f80000 { 509 reg = <0x0 0xd7f80000 0x0 0x80000>; 510 no-map; 511 }; 512 513 removed_mem: memory@d8800000 { 514 reg = <0x0 0xd8800000 0x0 0x6800000>; 515 no-map; 516 }; 517 }; 518 519 smem: qcom,smem { 520 compatible = "qcom,smem"; 521 memory-region = <&smem_mem>; 522 hwlocks = <&tcsr_mutex 3>; 523 }; 524 525 smp2p-adsp { 526 compatible = "qcom,smp2p"; 527 qcom,smem = <443>, <429>; 528 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 529 IPCC_MPROC_SIGNAL_SMP2P 530 IRQ_TYPE_EDGE_RISING>; 531 mboxes = <&ipcc IPCC_CLIENT_LPASS 532 IPCC_MPROC_SIGNAL_SMP2P>; 533 534 qcom,local-pid = <0>; 535 qcom,remote-pid = <2>; 536 537 smp2p_adsp_out: master-kernel { 538 qcom,entry-name = "master-kernel"; 539 #qcom,smem-state-cells = <1>; 540 }; 541 542 smp2p_adsp_in: slave-kernel { 543 qcom,entry-name = "slave-kernel"; 544 interrupt-controller; 545 #interrupt-cells = <2>; 546 }; 547 }; 548 549 smp2p-cdsp { 550 compatible = "qcom,smp2p"; 551 qcom,smem = <94>, <432>; 552 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 553 IPCC_MPROC_SIGNAL_SMP2P 554 IRQ_TYPE_EDGE_RISING>; 555 mboxes = <&ipcc IPCC_CLIENT_CDSP 556 IPCC_MPROC_SIGNAL_SMP2P>; 557 558 qcom,local-pid = <0>; 559 qcom,remote-pid = <5>; 560 561 smp2p_cdsp_out: master-kernel { 562 qcom,entry-name = "master-kernel"; 563 #qcom,smem-state-cells = <1>; 564 }; 565 566 smp2p_cdsp_in: slave-kernel { 567 qcom,entry-name = "slave-kernel"; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 }; 571 }; 572 573 smp2p-modem { 574 compatible = "qcom,smp2p"; 575 qcom,smem = <435>, <428>; 576 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 577 IPCC_MPROC_SIGNAL_SMP2P 578 IRQ_TYPE_EDGE_RISING>; 579 mboxes = <&ipcc IPCC_CLIENT_MPSS 580 IPCC_MPROC_SIGNAL_SMP2P>; 581 582 qcom,local-pid = <0>; 583 qcom,remote-pid = <1>; 584 585 smp2p_modem_out: master-kernel { 586 qcom,entry-name = "master-kernel"; 587 #qcom,smem-state-cells = <1>; 588 }; 589 590 smp2p_modem_in: slave-kernel { 591 qcom,entry-name = "slave-kernel"; 592 interrupt-controller; 593 #interrupt-cells = <2>; 594 }; 595 596 ipa_smp2p_out: ipa-ap-to-modem { 597 qcom,entry-name = "ipa"; 598 #qcom,smem-state-cells = <1>; 599 }; 600 601 ipa_smp2p_in: ipa-modem-to-ap { 602 qcom,entry-name = "ipa"; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 }; 606 }; 607 608 smp2p-slpi { 609 compatible = "qcom,smp2p"; 610 qcom,smem = <481>, <430>; 611 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 612 IPCC_MPROC_SIGNAL_SMP2P 613 IRQ_TYPE_EDGE_RISING>; 614 mboxes = <&ipcc IPCC_CLIENT_SLPI 615 IPCC_MPROC_SIGNAL_SMP2P>; 616 617 qcom,local-pid = <0>; 618 qcom,remote-pid = <3>; 619 620 smp2p_slpi_out: master-kernel { 621 qcom,entry-name = "master-kernel"; 622 #qcom,smem-state-cells = <1>; 623 }; 624 625 smp2p_slpi_in: slave-kernel { 626 qcom,entry-name = "slave-kernel"; 627 interrupt-controller; 628 #interrupt-cells = <2>; 629 }; 630 }; 631 632 soc: soc@0 { 633 #address-cells = <2>; 634 #size-cells = <2>; 635 ranges = <0 0 0 0 0x10 0>; 636 dma-ranges = <0 0 0 0 0x10 0>; 637 compatible = "simple-bus"; 638 639 gcc: clock-controller@100000 { 640 compatible = "qcom,gcc-sm8350"; 641 reg = <0x0 0x00100000 0x0 0x1f0000>; 642 #clock-cells = <1>; 643 #reset-cells = <1>; 644 #power-domain-cells = <1>; 645 clock-names = "bi_tcxo", 646 "sleep_clk", 647 "pcie_0_pipe_clk", 648 "pcie_1_pipe_clk", 649 "ufs_card_rx_symbol_0_clk", 650 "ufs_card_rx_symbol_1_clk", 651 "ufs_card_tx_symbol_0_clk", 652 "ufs_phy_rx_symbol_0_clk", 653 "ufs_phy_rx_symbol_1_clk", 654 "ufs_phy_tx_symbol_0_clk", 655 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 656 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 657 clocks = <&rpmhcc RPMH_CXO_CLK>, 658 <&sleep_clk>, 659 <0>, 660 <0>, 661 <0>, 662 <0>, 663 <0>, 664 <&ufs_phy_rx_symbol_0_clk>, 665 <&ufs_phy_rx_symbol_1_clk>, 666 <&ufs_phy_tx_symbol_0_clk>, 667 <0>, 668 <0>; 669 }; 670 671 ipcc: mailbox@408000 { 672 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 673 reg = <0 0x00408000 0 0x1000>; 674 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 675 interrupt-controller; 676 #interrupt-cells = <3>; 677 #mbox-cells = <2>; 678 }; 679 680 gpi_dma2: dma-controller@800000 { 681 compatible = "qcom,sm8350-gpi-dma"; 682 reg = <0 0x00800000 0 0x60000>; 683 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 695 dma-channels = <12>; 696 dma-channel-mask = <0xff>; 697 iommus = <&apps_smmu 0x5f6 0x0>; 698 #dma-cells = <3>; 699 status = "disabled"; 700 }; 701 702 qupv3_id_2: geniqup@8c0000 { 703 compatible = "qcom,geni-se-qup"; 704 reg = <0x0 0x008c0000 0x0 0x6000>; 705 clock-names = "m-ahb", "s-ahb"; 706 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 707 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 708 iommus = <&apps_smmu 0x5e3 0x0>; 709 #address-cells = <2>; 710 #size-cells = <2>; 711 ranges; 712 status = "disabled"; 713 714 i2c14: i2c@880000 { 715 compatible = "qcom,geni-i2c"; 716 reg = <0 0x00880000 0 0x4000>; 717 clock-names = "se"; 718 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&qup_i2c14_default>; 721 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 722 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 723 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 724 dma-names = "tx", "rx"; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 status = "disabled"; 728 }; 729 730 spi14: spi@880000 { 731 compatible = "qcom,geni-spi"; 732 reg = <0 0x00880000 0 0x4000>; 733 clock-names = "se"; 734 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 735 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 736 power-domains = <&rpmhpd SM8350_CX>; 737 operating-points-v2 = <&qup_opp_table_120mhz>; 738 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 739 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 740 dma-names = "tx", "rx"; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 status = "disabled"; 744 }; 745 746 i2c15: i2c@884000 { 747 compatible = "qcom,geni-i2c"; 748 reg = <0 0x00884000 0 0x4000>; 749 clock-names = "se"; 750 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&qup_i2c15_default>; 753 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 754 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 755 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 756 dma-names = "tx", "rx"; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 status = "disabled"; 760 }; 761 762 spi15: spi@884000 { 763 compatible = "qcom,geni-spi"; 764 reg = <0 0x00884000 0 0x4000>; 765 clock-names = "se"; 766 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 767 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 768 power-domains = <&rpmhpd SM8350_CX>; 769 operating-points-v2 = <&qup_opp_table_120mhz>; 770 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 771 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 772 dma-names = "tx", "rx"; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 i2c16: i2c@888000 { 779 compatible = "qcom,geni-i2c"; 780 reg = <0 0x00888000 0 0x4000>; 781 clock-names = "se"; 782 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&qup_i2c16_default>; 785 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 786 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 787 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 788 dma-names = "tx", "rx"; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 794 spi16: spi@888000 { 795 compatible = "qcom,geni-spi"; 796 reg = <0 0x00888000 0 0x4000>; 797 clock-names = "se"; 798 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 799 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 800 power-domains = <&rpmhpd SM8350_CX>; 801 operating-points-v2 = <&qup_opp_table_100mhz>; 802 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 803 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 804 dma-names = "tx", "rx"; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 810 i2c17: i2c@88c000 { 811 compatible = "qcom,geni-i2c"; 812 reg = <0 0x0088c000 0 0x4000>; 813 clock-names = "se"; 814 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&qup_i2c17_default>; 817 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 818 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 819 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 820 dma-names = "tx", "rx"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 spi17: spi@88c000 { 827 compatible = "qcom,geni-spi"; 828 reg = <0 0x0088c000 0 0x4000>; 829 clock-names = "se"; 830 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 831 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 832 power-domains = <&rpmhpd SM8350_CX>; 833 operating-points-v2 = <&qup_opp_table_100mhz>; 834 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 835 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 836 dma-names = "tx", "rx"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 /* QUP no. 18 seems to be strictly SPI/UART-only */ 843 844 spi18: spi@890000 { 845 compatible = "qcom,geni-spi"; 846 reg = <0 0x00890000 0 0x4000>; 847 clock-names = "se"; 848 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 849 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 850 power-domains = <&rpmhpd SM8350_CX>; 851 operating-points-v2 = <&qup_opp_table_100mhz>; 852 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 853 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 854 dma-names = "tx", "rx"; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 status = "disabled"; 858 }; 859 860 uart18: serial@890000 { 861 compatible = "qcom,geni-uart"; 862 reg = <0 0x00890000 0 0x4000>; 863 clock-names = "se"; 864 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 865 pinctrl-names = "default"; 866 pinctrl-0 = <&qup_uart18_default>; 867 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 868 power-domains = <&rpmhpd SM8350_CX>; 869 operating-points-v2 = <&qup_opp_table_100mhz>; 870 status = "disabled"; 871 }; 872 873 i2c19: i2c@894000 { 874 compatible = "qcom,geni-i2c"; 875 reg = <0 0x00894000 0 0x4000>; 876 clock-names = "se"; 877 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&qup_i2c19_default>; 880 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 881 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 882 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 883 dma-names = "tx", "rx"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 status = "disabled"; 887 }; 888 889 spi19: spi@894000 { 890 compatible = "qcom,geni-spi"; 891 reg = <0 0x00894000 0 0x4000>; 892 clock-names = "se"; 893 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 894 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 895 power-domains = <&rpmhpd SM8350_CX>; 896 operating-points-v2 = <&qup_opp_table_100mhz>; 897 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 898 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 899 dma-names = "tx", "rx"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 }; 905 906 gpi_dma0: dma-controller@900000 { 907 compatible = "qcom,sm8350-gpi-dma"; 908 reg = <0 0x09800000 0 0x60000>; 909 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 921 dma-channels = <12>; 922 dma-channel-mask = <0x7e>; 923 iommus = <&apps_smmu 0x5b6 0x0>; 924 #dma-cells = <3>; 925 status = "disabled"; 926 }; 927 928 qupv3_id_0: geniqup@9c0000 { 929 compatible = "qcom,geni-se-qup"; 930 reg = <0x0 0x009c0000 0x0 0x6000>; 931 clock-names = "m-ahb", "s-ahb"; 932 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 933 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 934 iommus = <&apps_smmu 0x5a3 0>; 935 #address-cells = <2>; 936 #size-cells = <2>; 937 ranges; 938 status = "disabled"; 939 940 i2c0: i2c@980000 { 941 compatible = "qcom,geni-i2c"; 942 reg = <0 0x00980000 0 0x4000>; 943 clock-names = "se"; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 945 pinctrl-names = "default"; 946 pinctrl-0 = <&qup_i2c0_default>; 947 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 948 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 949 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 950 dma-names = "tx", "rx"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 status = "disabled"; 954 }; 955 956 spi0: spi@980000 { 957 compatible = "qcom,geni-spi"; 958 reg = <0 0x00980000 0 0x4000>; 959 clock-names = "se"; 960 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 961 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 962 power-domains = <&rpmhpd SM8350_CX>; 963 operating-points-v2 = <&qup_opp_table_100mhz>; 964 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 965 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 966 dma-names = "tx", "rx"; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 status = "disabled"; 970 }; 971 972 i2c1: i2c@984000 { 973 compatible = "qcom,geni-i2c"; 974 reg = <0 0x00984000 0 0x4000>; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&qup_i2c1_default>; 979 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 980 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 981 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 982 dma-names = "tx", "rx"; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 status = "disabled"; 986 }; 987 988 spi1: spi@984000 { 989 compatible = "qcom,geni-spi"; 990 reg = <0 0x00984000 0 0x4000>; 991 clock-names = "se"; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 993 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 994 power-domains = <&rpmhpd SM8350_CX>; 995 operating-points-v2 = <&qup_opp_table_100mhz>; 996 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 997 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 998 dma-names = "tx", "rx"; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 i2c2: i2c@988000 { 1005 compatible = "qcom,geni-i2c"; 1006 reg = <0 0x00988000 0 0x4000>; 1007 clock-names = "se"; 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&qup_i2c2_default>; 1011 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1012 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1013 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1014 dma-names = "tx", "rx"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 spi2: spi@988000 { 1021 compatible = "qcom,geni-spi"; 1022 reg = <0 0x00988000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1025 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1026 power-domains = <&rpmhpd SM8350_CX>; 1027 operating-points-v2 = <&qup_opp_table_100mhz>; 1028 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1029 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1030 dma-names = "tx", "rx"; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 status = "disabled"; 1034 }; 1035 1036 uart2: serial@98c000 { 1037 compatible = "qcom,geni-debug-uart"; 1038 reg = <0 0x0098c000 0 0x4000>; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&qup_uart3_default_state>; 1043 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd SM8350_CX>; 1045 operating-points-v2 = <&qup_opp_table_100mhz>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 /* QUP no. 3 seems to be strictly SPI-only */ 1052 1053 spi3: spi@98c000 { 1054 compatible = "qcom,geni-spi"; 1055 reg = <0 0x0098c000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1058 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1059 power-domains = <&rpmhpd SM8350_CX>; 1060 operating-points-v2 = <&qup_opp_table_100mhz>; 1061 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1062 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1063 dma-names = "tx", "rx"; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 i2c4: i2c@990000 { 1070 compatible = "qcom,geni-i2c"; 1071 reg = <0 0x00990000 0 0x4000>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_i2c4_default>; 1076 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1077 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1078 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 spi4: spi@990000 { 1086 compatible = "qcom,geni-spi"; 1087 reg = <0 0x00990000 0 0x4000>; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1090 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1091 power-domains = <&rpmhpd SM8350_CX>; 1092 operating-points-v2 = <&qup_opp_table_100mhz>; 1093 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1094 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1095 dma-names = "tx", "rx"; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 status = "disabled"; 1099 }; 1100 1101 i2c5: i2c@994000 { 1102 compatible = "qcom,geni-i2c"; 1103 reg = <0 0x00994000 0 0x4000>; 1104 clock-names = "se"; 1105 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&qup_i2c5_default>; 1108 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1109 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1110 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1111 dma-names = "tx", "rx"; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 spi5: spi@994000 { 1118 compatible = "qcom,geni-spi"; 1119 reg = <0 0x00994000 0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1122 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1123 power-domains = <&rpmhpd SM8350_CX>; 1124 operating-points-v2 = <&qup_opp_table_100mhz>; 1125 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1126 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1127 dma-names = "tx", "rx"; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 i2c6: i2c@998000 { 1134 compatible = "qcom,geni-i2c"; 1135 reg = <0 0x00998000 0 0x4000>; 1136 clock-names = "se"; 1137 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_i2c6_default>; 1140 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1141 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1142 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1143 dma-names = "tx", "rx"; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 status = "disabled"; 1147 }; 1148 1149 spi6: spi@998000 { 1150 compatible = "qcom,geni-spi"; 1151 reg = <0 0x00998000 0 0x4000>; 1152 clock-names = "se"; 1153 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1154 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1155 power-domains = <&rpmhpd SM8350_CX>; 1156 operating-points-v2 = <&qup_opp_table_100mhz>; 1157 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1158 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1159 dma-names = "tx", "rx"; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 status = "disabled"; 1163 }; 1164 1165 uart6: serial@998000 { 1166 compatible = "qcom,geni-uart"; 1167 reg = <0 0x00998000 0 0x4000>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&qup_uart6_default>; 1172 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1173 power-domains = <&rpmhpd SM8350_CX>; 1174 operating-points-v2 = <&qup_opp_table_100mhz>; 1175 status = "disabled"; 1176 }; 1177 1178 i2c7: i2c@99c000 { 1179 compatible = "qcom,geni-i2c"; 1180 reg = <0 0x0099c000 0 0x4000>; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_i2c7_default>; 1185 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1186 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1187 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1188 dma-names = "tx", "rx"; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 status = "disabled"; 1192 }; 1193 1194 spi7: spi@99c000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0 0x0099c000 0 0x4000>; 1197 clock-names = "se"; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1199 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1200 power-domains = <&rpmhpd SM8350_CX>; 1201 operating-points-v2 = <&qup_opp_table_100mhz>; 1202 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1203 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1204 dma-names = "tx", "rx"; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 status = "disabled"; 1208 }; 1209 }; 1210 1211 gpi_dma1: dma-controller@a00000 { 1212 compatible = "qcom,sm8350-gpi-dma"; 1213 reg = <0 0x00a00000 0 0x60000>; 1214 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1226 dma-channels = <12>; 1227 dma-channel-mask = <0xff>; 1228 iommus = <&apps_smmu 0x56 0x0>; 1229 #dma-cells = <3>; 1230 status = "disabled"; 1231 }; 1232 1233 qupv3_id_1: geniqup@ac0000 { 1234 compatible = "qcom,geni-se-qup"; 1235 reg = <0x0 0x00ac0000 0x0 0x6000>; 1236 clock-names = "m-ahb", "s-ahb"; 1237 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1238 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1239 iommus = <&apps_smmu 0x43 0>; 1240 #address-cells = <2>; 1241 #size-cells = <2>; 1242 ranges; 1243 status = "disabled"; 1244 1245 i2c8: i2c@a80000 { 1246 compatible = "qcom,geni-i2c"; 1247 reg = <0 0x00a80000 0 0x4000>; 1248 clock-names = "se"; 1249 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_i2c8_default>; 1252 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1253 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1254 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1255 dma-names = "tx", "rx"; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 status = "disabled"; 1259 }; 1260 1261 spi8: spi@a80000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0 0x00a80000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1266 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1267 power-domains = <&rpmhpd SM8350_CX>; 1268 operating-points-v2 = <&qup_opp_table_120mhz>; 1269 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1270 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1271 dma-names = "tx", "rx"; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 i2c9: i2c@a84000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0 0x00a84000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_i2c9_default>; 1284 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1285 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1286 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1287 dma-names = "tx", "rx"; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 spi9: spi@a84000 { 1294 compatible = "qcom,geni-spi"; 1295 reg = <0 0x00a84000 0 0x4000>; 1296 clock-names = "se"; 1297 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1298 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1299 power-domains = <&rpmhpd SM8350_CX>; 1300 operating-points-v2 = <&qup_opp_table_100mhz>; 1301 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1302 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1303 dma-names = "tx", "rx"; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 i2c10: i2c@a88000 { 1310 compatible = "qcom,geni-i2c"; 1311 reg = <0 0x00a88000 0 0x4000>; 1312 clock-names = "se"; 1313 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1314 pinctrl-names = "default"; 1315 pinctrl-0 = <&qup_i2c10_default>; 1316 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1317 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1318 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1319 dma-names = "tx", "rx"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 spi10: spi@a88000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0 0x00a88000 0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1330 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1331 power-domains = <&rpmhpd SM8350_CX>; 1332 operating-points-v2 = <&qup_opp_table_100mhz>; 1333 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1334 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1335 dma-names = "tx", "rx"; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 status = "disabled"; 1339 }; 1340 1341 i2c11: i2c@a8c000 { 1342 compatible = "qcom,geni-i2c"; 1343 reg = <0 0x00a8c000 0 0x4000>; 1344 clock-names = "se"; 1345 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1346 pinctrl-names = "default"; 1347 pinctrl-0 = <&qup_i2c11_default>; 1348 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1349 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1350 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1351 dma-names = "tx", "rx"; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 status = "disabled"; 1355 }; 1356 1357 spi11: spi@a8c000 { 1358 compatible = "qcom,geni-spi"; 1359 reg = <0 0x00a8c000 0 0x4000>; 1360 clock-names = "se"; 1361 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1362 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1363 power-domains = <&rpmhpd SM8350_CX>; 1364 operating-points-v2 = <&qup_opp_table_100mhz>; 1365 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1366 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1367 dma-names = "tx", "rx"; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 i2c12: i2c@a90000 { 1374 compatible = "qcom,geni-i2c"; 1375 reg = <0 0x00a90000 0 0x4000>; 1376 clock-names = "se"; 1377 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1378 pinctrl-names = "default"; 1379 pinctrl-0 = <&qup_i2c12_default>; 1380 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1381 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1382 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1383 dma-names = "tx", "rx"; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 status = "disabled"; 1387 }; 1388 1389 spi12: spi@a90000 { 1390 compatible = "qcom,geni-spi"; 1391 reg = <0 0x00a90000 0 0x4000>; 1392 clock-names = "se"; 1393 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1394 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1395 power-domains = <&rpmhpd SM8350_CX>; 1396 operating-points-v2 = <&qup_opp_table_100mhz>; 1397 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1398 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1399 dma-names = "tx", "rx"; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 i2c13: i2c@a94000 { 1406 compatible = "qcom,geni-i2c"; 1407 reg = <0 0x00a94000 0 0x4000>; 1408 clock-names = "se"; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&qup_i2c13_default>; 1412 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1413 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1414 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1415 dma-names = "tx", "rx"; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 spi13: spi@a94000 { 1422 compatible = "qcom,geni-spi"; 1423 reg = <0 0x00a94000 0 0x4000>; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1426 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1427 power-domains = <&rpmhpd SM8350_CX>; 1428 operating-points-v2 = <&qup_opp_table_100mhz>; 1429 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1430 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1431 dma-names = "tx", "rx"; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 status = "disabled"; 1435 }; 1436 }; 1437 1438 apps_smmu: iommu@15000000 { 1439 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 1440 reg = <0 0x15000000 0 0x100000>; 1441 #iommu-cells = <2>; 1442 #global-interrupts = <2>; 1443 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 1541 }; 1542 1543 config_noc: interconnect@1500000 { 1544 compatible = "qcom,sm8350-config-noc"; 1545 reg = <0 0x01500000 0 0xa580>; 1546 #interconnect-cells = <1>; 1547 qcom,bcm-voters = <&apps_bcm_voter>; 1548 }; 1549 1550 mc_virt: interconnect@1580000 { 1551 compatible = "qcom,sm8350-mc-virt"; 1552 reg = <0 0x01580000 0 0x1000>; 1553 #interconnect-cells = <1>; 1554 qcom,bcm-voters = <&apps_bcm_voter>; 1555 }; 1556 1557 system_noc: interconnect@1680000 { 1558 compatible = "qcom,sm8350-system-noc"; 1559 reg = <0 0x01680000 0 0x1c200>; 1560 #interconnect-cells = <1>; 1561 qcom,bcm-voters = <&apps_bcm_voter>; 1562 }; 1563 1564 aggre1_noc: interconnect@16e0000 { 1565 compatible = "qcom,sm8350-aggre1-noc"; 1566 reg = <0 0x016e0000 0 0x1f180>; 1567 #interconnect-cells = <1>; 1568 qcom,bcm-voters = <&apps_bcm_voter>; 1569 }; 1570 1571 aggre2_noc: interconnect@1700000 { 1572 compatible = "qcom,sm8350-aggre2-noc"; 1573 reg = <0 0x01700000 0 0x33000>; 1574 #interconnect-cells = <1>; 1575 qcom,bcm-voters = <&apps_bcm_voter>; 1576 }; 1577 1578 mmss_noc: interconnect@1740000 { 1579 compatible = "qcom,sm8350-mmss-noc"; 1580 reg = <0 0x01740000 0 0x1f080>; 1581 #interconnect-cells = <1>; 1582 qcom,bcm-voters = <&apps_bcm_voter>; 1583 }; 1584 1585 lpass_ag_noc: interconnect@3c40000 { 1586 compatible = "qcom,sm8350-lpass-ag-noc"; 1587 reg = <0 0x03c40000 0 0xf080>; 1588 #interconnect-cells = <1>; 1589 qcom,bcm-voters = <&apps_bcm_voter>; 1590 }; 1591 1592 compute_noc: interconnect@a0c0000{ 1593 compatible = "qcom,sm8350-compute-noc"; 1594 reg = <0 0x0a0c0000 0 0xa180>; 1595 #interconnect-cells = <1>; 1596 qcom,bcm-voters = <&apps_bcm_voter>; 1597 }; 1598 1599 ipa: ipa@1e40000 { 1600 compatible = "qcom,sm8350-ipa"; 1601 1602 iommus = <&apps_smmu 0x5c0 0x0>, 1603 <&apps_smmu 0x5c2 0x0>; 1604 reg = <0 0x1e40000 0 0x8000>, 1605 <0 0x1e50000 0 0x4b20>, 1606 <0 0x1e04000 0 0x23000>; 1607 reg-names = "ipa-reg", 1608 "ipa-shared", 1609 "gsi"; 1610 1611 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1612 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1613 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1614 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1615 interrupt-names = "ipa", 1616 "gsi", 1617 "ipa-clock-query", 1618 "ipa-setup-ready"; 1619 1620 clocks = <&rpmhcc RPMH_IPA_CLK>; 1621 clock-names = "core"; 1622 1623 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, 1624 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; 1625 interconnect-names = "memory", 1626 "config"; 1627 1628 qcom,qmp = <&aoss_qmp>; 1629 1630 qcom,smem-states = <&ipa_smp2p_out 0>, 1631 <&ipa_smp2p_out 1>; 1632 qcom,smem-state-names = "ipa-clock-enabled-valid", 1633 "ipa-clock-enabled"; 1634 1635 status = "disabled"; 1636 }; 1637 1638 tcsr_mutex: hwlock@1f40000 { 1639 compatible = "qcom,tcsr-mutex"; 1640 reg = <0x0 0x01f40000 0x0 0x40000>; 1641 #hwlock-cells = <1>; 1642 }; 1643 1644 mpss: remoteproc@4080000 { 1645 compatible = "qcom,sm8350-mpss-pas"; 1646 reg = <0x0 0x04080000 0x0 0x4040>; 1647 1648 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1649 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1650 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1651 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1652 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1653 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1654 interrupt-names = "wdog", "fatal", "ready", "handover", 1655 "stop-ack", "shutdown-ack"; 1656 1657 clocks = <&rpmhcc RPMH_CXO_CLK>; 1658 clock-names = "xo"; 1659 1660 power-domains = <&rpmhpd SM8350_CX>, 1661 <&rpmhpd SM8350_MSS>; 1662 power-domain-names = "cx", "mss"; 1663 1664 interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; 1665 1666 memory-region = <&pil_modem_mem>; 1667 1668 qcom,qmp = <&aoss_qmp>; 1669 1670 qcom,smem-states = <&smp2p_modem_out 0>; 1671 qcom,smem-state-names = "stop"; 1672 1673 status = "disabled"; 1674 1675 glink-edge { 1676 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1677 IPCC_MPROC_SIGNAL_GLINK_QMP 1678 IRQ_TYPE_EDGE_RISING>; 1679 mboxes = <&ipcc IPCC_CLIENT_MPSS 1680 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1681 label = "modem"; 1682 qcom,remote-pid = <1>; 1683 }; 1684 }; 1685 1686 pdc: interrupt-controller@b220000 { 1687 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 1688 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 1689 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 1690 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 1691 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 1692 <156 716 12>; 1693 #interrupt-cells = <2>; 1694 interrupt-parent = <&intc>; 1695 interrupt-controller; 1696 }; 1697 1698 tsens0: thermal-sensor@c263000 { 1699 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 1700 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1701 <0 0x0c222000 0 0x8>; /* SROT */ 1702 #qcom,sensors = <15>; 1703 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1704 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1705 interrupt-names = "uplow", "critical"; 1706 #thermal-sensor-cells = <1>; 1707 }; 1708 1709 tsens1: thermal-sensor@c265000 { 1710 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 1711 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1712 <0 0x0c223000 0 0x8>; /* SROT */ 1713 #qcom,sensors = <14>; 1714 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1715 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1716 interrupt-names = "uplow", "critical"; 1717 #thermal-sensor-cells = <1>; 1718 }; 1719 1720 aoss_qmp: power-controller@c300000 { 1721 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 1722 reg = <0 0x0c300000 0 0x400>; 1723 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1724 IRQ_TYPE_EDGE_RISING>; 1725 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1726 1727 #clock-cells = <0>; 1728 }; 1729 1730 sram@c3f0000 { 1731 compatible = "qcom,rpmh-stats"; 1732 reg = <0 0x0c3f0000 0 0x400>; 1733 }; 1734 1735 spmi_bus: spmi@c440000 { 1736 compatible = "qcom,spmi-pmic-arb"; 1737 reg = <0x0 0xc440000 0x0 0x1100>, 1738 <0x0 0xc600000 0x0 0x2000000>, 1739 <0x0 0xe600000 0x0 0x100000>, 1740 <0x0 0xe700000 0x0 0xa0000>, 1741 <0x0 0xc40a000 0x0 0x26000>; 1742 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1743 interrupt-names = "periph_irq"; 1744 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1745 qcom,ee = <0>; 1746 qcom,channel = <0>; 1747 #address-cells = <2>; 1748 #size-cells = <0>; 1749 interrupt-controller; 1750 #interrupt-cells = <4>; 1751 }; 1752 1753 tlmm: pinctrl@f100000 { 1754 compatible = "qcom,sm8350-tlmm"; 1755 reg = <0 0x0f100000 0 0x300000>; 1756 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1757 gpio-controller; 1758 #gpio-cells = <2>; 1759 interrupt-controller; 1760 #interrupt-cells = <2>; 1761 gpio-ranges = <&tlmm 0 0 204>; 1762 wakeup-parent = <&pdc>; 1763 1764 qup_uart3_default_state: qup-uart3-default-state { 1765 rx { 1766 pins = "gpio18"; 1767 function = "qup3"; 1768 }; 1769 tx { 1770 pins = "gpio19"; 1771 function = "qup3"; 1772 }; 1773 }; 1774 1775 qup_uart6_default: qup-uart6-default { 1776 pins = "gpio30", "gpio31"; 1777 function = "qup6"; 1778 drive-strength = <2>; 1779 bias-disable; 1780 }; 1781 1782 qup_uart18_default: qup-uart18-default { 1783 pins = "gpio58", "gpio59"; 1784 function = "qup18"; 1785 drive-strength = <2>; 1786 bias-disable; 1787 }; 1788 1789 qup_i2c0_default: qup-i2c0-default { 1790 pins = "gpio4", "gpio5"; 1791 function = "qup0"; 1792 drive-strength = <2>; 1793 bias-pull-up; 1794 }; 1795 1796 qup_i2c1_default: qup-i2c1-default { 1797 pins = "gpio8", "gpio9"; 1798 function = "qup1"; 1799 drive-strength = <2>; 1800 bias-pull-up; 1801 }; 1802 1803 qup_i2c2_default: qup-i2c2-default { 1804 pins = "gpio12", "gpio13"; 1805 function = "qup2"; 1806 drive-strength = <2>; 1807 bias-pull-up; 1808 }; 1809 1810 qup_i2c4_default: qup-i2c4-default { 1811 pins = "gpio20", "gpio21"; 1812 function = "qup4"; 1813 drive-strength = <2>; 1814 bias-pull-up; 1815 }; 1816 1817 qup_i2c5_default: qup-i2c5-default { 1818 pins = "gpio24", "gpio25"; 1819 function = "qup5"; 1820 drive-strength = <2>; 1821 bias-pull-up; 1822 }; 1823 1824 qup_i2c6_default: qup-i2c6-default { 1825 pins = "gpio28", "gpio29"; 1826 function = "qup6"; 1827 drive-strength = <2>; 1828 bias-pull-up; 1829 }; 1830 1831 qup_i2c7_default: qup-i2c7-default { 1832 pins = "gpio32", "gpio33"; 1833 function = "qup7"; 1834 drive-strength = <2>; 1835 bias-disable; 1836 }; 1837 1838 qup_i2c8_default: qup-i2c8-default { 1839 pins = "gpio36", "gpio37"; 1840 function = "qup8"; 1841 drive-strength = <2>; 1842 bias-pull-up; 1843 }; 1844 1845 qup_i2c9_default: qup-i2c9-default { 1846 pins = "gpio40", "gpio41"; 1847 function = "qup9"; 1848 drive-strength = <2>; 1849 bias-pull-up; 1850 }; 1851 1852 qup_i2c10_default: qup-i2c10-default { 1853 pins = "gpio44", "gpio45"; 1854 function = "qup10"; 1855 drive-strength = <2>; 1856 bias-pull-up; 1857 }; 1858 1859 qup_i2c11_default: qup-i2c11-default { 1860 pins = "gpio48", "gpio49"; 1861 function = "qup11"; 1862 drive-strength = <2>; 1863 bias-pull-up; 1864 }; 1865 1866 qup_i2c12_default: qup-i2c12-default { 1867 pins = "gpio52", "gpio53"; 1868 function = "qup12"; 1869 drive-strength = <2>; 1870 bias-pull-up; 1871 }; 1872 1873 qup_i2c13_default: qup-i2c13-default { 1874 pins = "gpio0", "gpio1"; 1875 function = "qup13"; 1876 drive-strength = <2>; 1877 bias-pull-up; 1878 }; 1879 1880 qup_i2c14_default: qup-i2c14-default { 1881 pins = "gpio56", "gpio57"; 1882 function = "qup14"; 1883 drive-strength = <2>; 1884 bias-disable; 1885 }; 1886 1887 qup_i2c15_default: qup-i2c15-default { 1888 pins = "gpio60", "gpio61"; 1889 function = "qup15"; 1890 drive-strength = <2>; 1891 bias-disable; 1892 }; 1893 1894 qup_i2c16_default: qup-i2c16-default { 1895 pins = "gpio64", "gpio65"; 1896 function = "qup16"; 1897 drive-strength = <2>; 1898 bias-disable; 1899 }; 1900 1901 qup_i2c17_default: qup-i2c17-default { 1902 pins = "gpio72", "gpio73"; 1903 function = "qup17"; 1904 drive-strength = <2>; 1905 bias-disable; 1906 }; 1907 1908 qup_i2c19_default: qup-i2c19-default { 1909 pins = "gpio76", "gpio77"; 1910 function = "qup19"; 1911 drive-strength = <2>; 1912 bias-disable; 1913 }; 1914 }; 1915 1916 rng: rng@10d3000 { 1917 compatible = "qcom,prng-ee"; 1918 reg = <0 0x010d3000 0 0x1000>; 1919 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1920 clock-names = "core"; 1921 }; 1922 1923 intc: interrupt-controller@17a00000 { 1924 compatible = "arm,gic-v3"; 1925 #interrupt-cells = <3>; 1926 interrupt-controller; 1927 #redistributor-regions = <1>; 1928 redistributor-stride = <0 0x20000>; 1929 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1930 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1931 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1932 }; 1933 1934 timer@17c20000 { 1935 compatible = "arm,armv7-timer-mem"; 1936 #address-cells = <1>; 1937 #size-cells = <1>; 1938 ranges = <0 0 0 0x20000000>; 1939 reg = <0x0 0x17c20000 0x0 0x1000>; 1940 clock-frequency = <19200000>; 1941 1942 frame@17c21000 { 1943 frame-number = <0>; 1944 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1946 reg = <0x17c21000 0x1000>, 1947 <0x17c22000 0x1000>; 1948 }; 1949 1950 frame@17c23000 { 1951 frame-number = <1>; 1952 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1953 reg = <0x17c23000 0x1000>; 1954 status = "disabled"; 1955 }; 1956 1957 frame@17c25000 { 1958 frame-number = <2>; 1959 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1960 reg = <0x17c25000 0x1000>; 1961 status = "disabled"; 1962 }; 1963 1964 frame@17c27000 { 1965 frame-number = <3>; 1966 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1967 reg = <0x17c27000 0x1000>; 1968 status = "disabled"; 1969 }; 1970 1971 frame@17c29000 { 1972 frame-number = <4>; 1973 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1974 reg = <0x17c29000 0x1000>; 1975 status = "disabled"; 1976 }; 1977 1978 frame@17c2b000 { 1979 frame-number = <5>; 1980 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1981 reg = <0x17c2b000 0x1000>; 1982 status = "disabled"; 1983 }; 1984 1985 frame@17c2d000 { 1986 frame-number = <6>; 1987 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1988 reg = <0x17c2d000 0x1000>; 1989 status = "disabled"; 1990 }; 1991 }; 1992 1993 apps_rsc: rsc@18200000 { 1994 label = "apps_rsc"; 1995 compatible = "qcom,rpmh-rsc"; 1996 reg = <0x0 0x18200000 0x0 0x10000>, 1997 <0x0 0x18210000 0x0 0x10000>, 1998 <0x0 0x18220000 0x0 0x10000>; 1999 reg-names = "drv-0", "drv-1", "drv-2"; 2000 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2003 qcom,tcs-offset = <0xd00>; 2004 qcom,drv-id = <2>; 2005 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2006 <WAKE_TCS 3>, <CONTROL_TCS 0>; 2007 2008 rpmhcc: clock-controller { 2009 compatible = "qcom,sm8350-rpmh-clk"; 2010 #clock-cells = <1>; 2011 clock-names = "xo"; 2012 clocks = <&xo_board>; 2013 }; 2014 2015 rpmhpd: power-controller { 2016 compatible = "qcom,sm8350-rpmhpd"; 2017 #power-domain-cells = <1>; 2018 operating-points-v2 = <&rpmhpd_opp_table>; 2019 2020 rpmhpd_opp_table: opp-table { 2021 compatible = "operating-points-v2"; 2022 2023 rpmhpd_opp_ret: opp1 { 2024 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2025 }; 2026 2027 rpmhpd_opp_min_svs: opp2 { 2028 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2029 }; 2030 2031 rpmhpd_opp_low_svs: opp3 { 2032 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2033 }; 2034 2035 rpmhpd_opp_svs: opp4 { 2036 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2037 }; 2038 2039 rpmhpd_opp_svs_l1: opp5 { 2040 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2041 }; 2042 2043 rpmhpd_opp_nom: opp6 { 2044 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2045 }; 2046 2047 rpmhpd_opp_nom_l1: opp7 { 2048 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2049 }; 2050 2051 rpmhpd_opp_nom_l2: opp8 { 2052 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2053 }; 2054 2055 rpmhpd_opp_turbo: opp9 { 2056 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2057 }; 2058 2059 rpmhpd_opp_turbo_l1: opp10 { 2060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2061 }; 2062 }; 2063 }; 2064 2065 apps_bcm_voter: bcm-voter { 2066 compatible = "qcom,bcm-voter"; 2067 }; 2068 }; 2069 2070 cpufreq_hw: cpufreq@18591000 { 2071 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 2072 reg = <0 0x18591000 0 0x1000>, 2073 <0 0x18592000 0 0x1000>, 2074 <0 0x18593000 0 0x1000>; 2075 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 2076 2077 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2078 clock-names = "xo", "alternate"; 2079 2080 #freq-domain-cells = <1>; 2081 }; 2082 2083 ufs_mem_hc: ufshc@1d84000 { 2084 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 2085 "jedec,ufs-2.0"; 2086 reg = <0 0x01d84000 0 0x3000>; 2087 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2088 phys = <&ufs_mem_phy_lanes>; 2089 phy-names = "ufsphy"; 2090 lanes-per-direction = <2>; 2091 #reset-cells = <1>; 2092 resets = <&gcc GCC_UFS_PHY_BCR>; 2093 reset-names = "rst"; 2094 2095 power-domains = <&gcc UFS_PHY_GDSC>; 2096 2097 iommus = <&apps_smmu 0xe0 0x0>; 2098 2099 clock-names = 2100 "core_clk", 2101 "bus_aggr_clk", 2102 "iface_clk", 2103 "core_clk_unipro", 2104 "ref_clk", 2105 "tx_lane0_sync_clk", 2106 "rx_lane0_sync_clk", 2107 "rx_lane1_sync_clk"; 2108 clocks = 2109 <&gcc GCC_UFS_PHY_AXI_CLK>, 2110 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2111 <&gcc GCC_UFS_PHY_AHB_CLK>, 2112 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2113 <&rpmhcc RPMH_CXO_CLK>, 2114 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2115 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2116 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2117 freq-table-hz = 2118 <75000000 300000000>, 2119 <0 0>, 2120 <0 0>, 2121 <75000000 300000000>, 2122 <0 0>, 2123 <0 0>, 2124 <0 0>, 2125 <0 0>; 2126 status = "disabled"; 2127 }; 2128 2129 ufs_mem_phy: phy@1d87000 { 2130 compatible = "qcom,sm8350-qmp-ufs-phy"; 2131 reg = <0 0x01d87000 0 0x1c4>; 2132 #address-cells = <2>; 2133 #size-cells = <2>; 2134 ranges; 2135 clock-names = "ref", 2136 "ref_aux"; 2137 clocks = <&rpmhcc RPMH_CXO_CLK>, 2138 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2139 2140 resets = <&ufs_mem_hc 0>; 2141 reset-names = "ufsphy"; 2142 status = "disabled"; 2143 2144 ufs_mem_phy_lanes: phy@1d87400 { 2145 reg = <0 0x01d87400 0 0x108>, 2146 <0 0x01d87600 0 0x1e0>, 2147 <0 0x01d87c00 0 0x1dc>, 2148 <0 0x01d87800 0 0x108>, 2149 <0 0x01d87a00 0 0x1e0>; 2150 #phy-cells = <0>; 2151 }; 2152 }; 2153 2154 slpi: remoteproc@5c00000 { 2155 compatible = "qcom,sm8350-slpi-pas"; 2156 reg = <0 0x05c00000 0 0x4000>; 2157 2158 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2159 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2160 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2161 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2162 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2163 interrupt-names = "wdog", "fatal", "ready", 2164 "handover", "stop-ack"; 2165 2166 clocks = <&rpmhcc RPMH_CXO_CLK>; 2167 clock-names = "xo"; 2168 2169 power-domains = <&rpmhpd SM8350_LCX>, 2170 <&rpmhpd SM8350_LMX>; 2171 power-domain-names = "lcx", "lmx"; 2172 2173 memory-region = <&pil_slpi_mem>; 2174 2175 qcom,qmp = <&aoss_qmp>; 2176 2177 qcom,smem-states = <&smp2p_slpi_out 0>; 2178 qcom,smem-state-names = "stop"; 2179 2180 status = "disabled"; 2181 2182 glink-edge { 2183 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2184 IPCC_MPROC_SIGNAL_GLINK_QMP 2185 IRQ_TYPE_EDGE_RISING>; 2186 mboxes = <&ipcc IPCC_CLIENT_SLPI 2187 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2188 2189 label = "slpi"; 2190 qcom,remote-pid = <3>; 2191 2192 fastrpc { 2193 compatible = "qcom,fastrpc"; 2194 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2195 label = "sdsp"; 2196 qcom,non-secure-domain; 2197 #address-cells = <1>; 2198 #size-cells = <0>; 2199 2200 compute-cb@1 { 2201 compatible = "qcom,fastrpc-compute-cb"; 2202 reg = <1>; 2203 iommus = <&apps_smmu 0x0541 0x0>; 2204 }; 2205 2206 compute-cb@2 { 2207 compatible = "qcom,fastrpc-compute-cb"; 2208 reg = <2>; 2209 iommus = <&apps_smmu 0x0542 0x0>; 2210 }; 2211 2212 compute-cb@3 { 2213 compatible = "qcom,fastrpc-compute-cb"; 2214 reg = <3>; 2215 iommus = <&apps_smmu 0x0543 0x0>; 2216 /* note: shared-cb = <4> in downstream */ 2217 }; 2218 }; 2219 }; 2220 }; 2221 2222 cdsp: remoteproc@98900000 { 2223 compatible = "qcom,sm8350-cdsp-pas"; 2224 reg = <0 0x098900000 0 0x1400000>; 2225 2226 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2227 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2228 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2229 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2230 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2231 interrupt-names = "wdog", "fatal", "ready", 2232 "handover", "stop-ack"; 2233 2234 clocks = <&rpmhcc RPMH_CXO_CLK>; 2235 clock-names = "xo"; 2236 2237 power-domains = <&rpmhpd SM8350_CX>, 2238 <&rpmhpd SM8350_MXC>; 2239 power-domain-names = "cx", "mxc"; 2240 2241 interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; 2242 2243 memory-region = <&pil_cdsp_mem>; 2244 2245 qcom,qmp = <&aoss_qmp>; 2246 2247 qcom,smem-states = <&smp2p_cdsp_out 0>; 2248 qcom,smem-state-names = "stop"; 2249 2250 status = "disabled"; 2251 2252 glink-edge { 2253 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2254 IPCC_MPROC_SIGNAL_GLINK_QMP 2255 IRQ_TYPE_EDGE_RISING>; 2256 mboxes = <&ipcc IPCC_CLIENT_CDSP 2257 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2258 2259 label = "cdsp"; 2260 qcom,remote-pid = <5>; 2261 2262 fastrpc { 2263 compatible = "qcom,fastrpc"; 2264 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2265 label = "cdsp"; 2266 qcom,non-secure-domain; 2267 #address-cells = <1>; 2268 #size-cells = <0>; 2269 2270 compute-cb@1 { 2271 compatible = "qcom,fastrpc-compute-cb"; 2272 reg = <1>; 2273 iommus = <&apps_smmu 0x2161 0x0400>, 2274 <&apps_smmu 0x1181 0x0420>; 2275 }; 2276 2277 compute-cb@2 { 2278 compatible = "qcom,fastrpc-compute-cb"; 2279 reg = <2>; 2280 iommus = <&apps_smmu 0x2162 0x0400>, 2281 <&apps_smmu 0x1182 0x0420>; 2282 }; 2283 2284 compute-cb@3 { 2285 compatible = "qcom,fastrpc-compute-cb"; 2286 reg = <3>; 2287 iommus = <&apps_smmu 0x2163 0x0400>, 2288 <&apps_smmu 0x1183 0x0420>; 2289 }; 2290 2291 compute-cb@4 { 2292 compatible = "qcom,fastrpc-compute-cb"; 2293 reg = <4>; 2294 iommus = <&apps_smmu 0x2164 0x0400>, 2295 <&apps_smmu 0x1184 0x0420>; 2296 }; 2297 2298 compute-cb@5 { 2299 compatible = "qcom,fastrpc-compute-cb"; 2300 reg = <5>; 2301 iommus = <&apps_smmu 0x2165 0x0400>, 2302 <&apps_smmu 0x1185 0x0420>; 2303 }; 2304 2305 compute-cb@6 { 2306 compatible = "qcom,fastrpc-compute-cb"; 2307 reg = <6>; 2308 iommus = <&apps_smmu 0x2166 0x0400>, 2309 <&apps_smmu 0x1186 0x0420>; 2310 }; 2311 2312 compute-cb@7 { 2313 compatible = "qcom,fastrpc-compute-cb"; 2314 reg = <7>; 2315 iommus = <&apps_smmu 0x2167 0x0400>, 2316 <&apps_smmu 0x1187 0x0420>; 2317 }; 2318 2319 compute-cb@8 { 2320 compatible = "qcom,fastrpc-compute-cb"; 2321 reg = <8>; 2322 iommus = <&apps_smmu 0x2168 0x0400>, 2323 <&apps_smmu 0x1188 0x0420>; 2324 }; 2325 2326 /* note: secure cb9 in downstream */ 2327 }; 2328 }; 2329 }; 2330 2331 usb_1_hsphy: phy@88e3000 { 2332 compatible = "qcom,sm8350-usb-hs-phy", 2333 "qcom,usb-snps-hs-7nm-phy"; 2334 reg = <0 0x088e3000 0 0x400>; 2335 status = "disabled"; 2336 #phy-cells = <0>; 2337 2338 clocks = <&rpmhcc RPMH_CXO_CLK>; 2339 clock-names = "ref"; 2340 2341 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2342 }; 2343 2344 usb_2_hsphy: phy@88e4000 { 2345 compatible = "qcom,sm8250-usb-hs-phy", 2346 "qcom,usb-snps-hs-7nm-phy"; 2347 reg = <0 0x088e4000 0 0x400>; 2348 status = "disabled"; 2349 #phy-cells = <0>; 2350 2351 clocks = <&rpmhcc RPMH_CXO_CLK>; 2352 clock-names = "ref"; 2353 2354 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2355 }; 2356 2357 usb_1_qmpphy: phy-wrapper@88e9000 { 2358 compatible = "qcom,sm8350-qmp-usb3-phy"; 2359 reg = <0 0x088e9000 0 0x200>, 2360 <0 0x088e8000 0 0x20>; 2361 status = "disabled"; 2362 #address-cells = <2>; 2363 #size-cells = <2>; 2364 ranges; 2365 2366 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2367 <&rpmhcc RPMH_CXO_CLK>, 2368 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2369 clock-names = "aux", "ref_clk_src", "com_aux"; 2370 2371 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2372 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2373 reset-names = "phy", "common"; 2374 2375 usb_1_ssphy: phy@88e9200 { 2376 reg = <0 0x088e9200 0 0x200>, 2377 <0 0x088e9400 0 0x200>, 2378 <0 0x088e9c00 0 0x400>, 2379 <0 0x088e9600 0 0x200>, 2380 <0 0x088e9800 0 0x200>, 2381 <0 0x088e9a00 0 0x100>; 2382 #phy-cells = <0>; 2383 #clock-cells = <0>; 2384 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2385 clock-names = "pipe0"; 2386 clock-output-names = "usb3_phy_pipe_clk_src"; 2387 }; 2388 }; 2389 2390 usb_2_qmpphy: phy-wrapper@88eb000 { 2391 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2392 reg = <0 0x088eb000 0 0x200>; 2393 status = "disabled"; 2394 #address-cells = <2>; 2395 #size-cells = <2>; 2396 ranges; 2397 2398 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2399 <&rpmhcc RPMH_CXO_CLK>, 2400 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2401 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2402 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2403 2404 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2405 <&gcc GCC_USB3_PHY_SEC_BCR>; 2406 reset-names = "phy", "common"; 2407 2408 usb_2_ssphy: phy@88ebe00 { 2409 reg = <0 0x088ebe00 0 0x200>, 2410 <0 0x088ec000 0 0x200>, 2411 <0 0x088eb200 0 0x1100>; 2412 #phy-cells = <0>; 2413 #clock-cells = <0>; 2414 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2415 clock-names = "pipe0"; 2416 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2417 }; 2418 }; 2419 2420 dc_noc: interconnect@90c0000 { 2421 compatible = "qcom,sm8350-dc-noc"; 2422 reg = <0 0x090c0000 0 0x4200>; 2423 #interconnect-cells = <1>; 2424 qcom,bcm-voters = <&apps_bcm_voter>; 2425 }; 2426 2427 gem_noc: interconnect@9100000 { 2428 compatible = "qcom,sm8350-gem-noc"; 2429 reg = <0 0x09100000 0 0xb4000>; 2430 #interconnect-cells = <1>; 2431 qcom,bcm-voters = <&apps_bcm_voter>; 2432 }; 2433 2434 system-cache-controller@9200000 { 2435 compatible = "qcom,sm8350-llcc"; 2436 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2437 reg-names = "llcc_base", "llcc_broadcast_base"; 2438 }; 2439 2440 usb_1: usb@a6f8800 { 2441 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2442 reg = <0 0x0a6f8800 0 0x400>; 2443 status = "disabled"; 2444 #address-cells = <2>; 2445 #size-cells = <2>; 2446 ranges; 2447 2448 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2449 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2450 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2451 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2452 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2453 clock-names = "cfg_noc", 2454 "core", 2455 "iface", 2456 "sleep", 2457 "mock_utmi"; 2458 2459 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2460 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2461 assigned-clock-rates = <19200000>, <200000000>; 2462 2463 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2464 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2465 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2466 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2467 interrupt-names = "hs_phy_irq", 2468 "ss_phy_irq", 2469 "dm_hs_phy_irq", 2470 "dp_hs_phy_irq"; 2471 2472 power-domains = <&gcc USB30_PRIM_GDSC>; 2473 2474 resets = <&gcc GCC_USB30_PRIM_BCR>; 2475 2476 usb_1_dwc3: usb@a600000 { 2477 compatible = "snps,dwc3"; 2478 reg = <0 0x0a600000 0 0xcd00>; 2479 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2480 iommus = <&apps_smmu 0x0 0x0>; 2481 snps,dis_u2_susphy_quirk; 2482 snps,dis_enblslpm_quirk; 2483 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2484 phy-names = "usb2-phy", "usb3-phy"; 2485 }; 2486 }; 2487 2488 usb_2: usb@a8f8800 { 2489 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2490 reg = <0 0x0a8f8800 0 0x400>; 2491 status = "disabled"; 2492 #address-cells = <2>; 2493 #size-cells = <2>; 2494 ranges; 2495 2496 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2497 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2498 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2499 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2500 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2501 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2502 clock-names = "cfg_noc", 2503 "core", 2504 "iface", 2505 "sleep", 2506 "mock_utmi", 2507 "xo"; 2508 2509 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2510 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2511 assigned-clock-rates = <19200000>, <200000000>; 2512 2513 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2514 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2515 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2516 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2517 interrupt-names = "hs_phy_irq", 2518 "ss_phy_irq", 2519 "dm_hs_phy_irq", 2520 "dp_hs_phy_irq"; 2521 2522 power-domains = <&gcc USB30_SEC_GDSC>; 2523 2524 resets = <&gcc GCC_USB30_SEC_BCR>; 2525 2526 usb_2_dwc3: usb@a800000 { 2527 compatible = "snps,dwc3"; 2528 reg = <0 0x0a800000 0 0xcd00>; 2529 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2530 iommus = <&apps_smmu 0x20 0x0>; 2531 snps,dis_u2_susphy_quirk; 2532 snps,dis_enblslpm_quirk; 2533 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2534 phy-names = "usb2-phy", "usb3-phy"; 2535 }; 2536 }; 2537 2538 dispcc: clock-controller@af00000 { 2539 compatible = "qcom,sm8350-dispcc"; 2540 reg = <0 0x0af00000 0 0x10000>; 2541 clocks = <&rpmhcc RPMH_CXO_CLK>, 2542 <0>, 2543 <0>, 2544 <0>, 2545 <0>, 2546 <0>, 2547 <0>; 2548 clock-names = "bi_tcxo", 2549 "dsi0_phy_pll_out_byteclk", 2550 "dsi0_phy_pll_out_dsiclk", 2551 "dsi1_phy_pll_out_byteclk", 2552 "dsi1_phy_pll_out_dsiclk", 2553 "dp_phy_pll_link_clk", 2554 "dp_phy_pll_vco_div_clk"; 2555 #clock-cells = <1>; 2556 #reset-cells = <1>; 2557 #power-domain-cells = <1>; 2558 2559 power-domains = <&rpmhpd SM8350_MMCX>; 2560 power-domain-names = "mmcx"; 2561 }; 2562 2563 adsp: remoteproc@17300000 { 2564 compatible = "qcom,sm8350-adsp-pas"; 2565 reg = <0 0x17300000 0 0x100>; 2566 2567 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2568 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2569 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2570 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2571 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2572 interrupt-names = "wdog", "fatal", "ready", 2573 "handover", "stop-ack"; 2574 2575 clocks = <&rpmhcc RPMH_CXO_CLK>; 2576 clock-names = "xo"; 2577 2578 power-domains = <&rpmhpd SM8350_LCX>, 2579 <&rpmhpd SM8350_LMX>; 2580 power-domain-names = "lcx", "lmx"; 2581 2582 memory-region = <&pil_adsp_mem>; 2583 2584 qcom,qmp = <&aoss_qmp>; 2585 2586 qcom,smem-states = <&smp2p_adsp_out 0>; 2587 qcom,smem-state-names = "stop"; 2588 2589 status = "disabled"; 2590 2591 glink-edge { 2592 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2593 IPCC_MPROC_SIGNAL_GLINK_QMP 2594 IRQ_TYPE_EDGE_RISING>; 2595 mboxes = <&ipcc IPCC_CLIENT_LPASS 2596 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2597 2598 label = "lpass"; 2599 qcom,remote-pid = <2>; 2600 2601 fastrpc { 2602 compatible = "qcom,fastrpc"; 2603 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2604 label = "adsp"; 2605 qcom,non-secure-domain; 2606 #address-cells = <1>; 2607 #size-cells = <0>; 2608 2609 compute-cb@3 { 2610 compatible = "qcom,fastrpc-compute-cb"; 2611 reg = <3>; 2612 iommus = <&apps_smmu 0x1803 0x0>; 2613 }; 2614 2615 compute-cb@4 { 2616 compatible = "qcom,fastrpc-compute-cb"; 2617 reg = <4>; 2618 iommus = <&apps_smmu 0x1804 0x0>; 2619 }; 2620 2621 compute-cb@5 { 2622 compatible = "qcom,fastrpc-compute-cb"; 2623 reg = <5>; 2624 iommus = <&apps_smmu 0x1805 0x0>; 2625 }; 2626 }; 2627 }; 2628 }; 2629 }; 2630 2631 thermal_zones: thermal-zones { 2632 cpu0-thermal { 2633 polling-delay-passive = <250>; 2634 polling-delay = <1000>; 2635 2636 thermal-sensors = <&tsens0 1>; 2637 2638 trips { 2639 cpu0_alert0: trip-point0 { 2640 temperature = <90000>; 2641 hysteresis = <2000>; 2642 type = "passive"; 2643 }; 2644 2645 cpu0_alert1: trip-point1 { 2646 temperature = <95000>; 2647 hysteresis = <2000>; 2648 type = "passive"; 2649 }; 2650 2651 cpu0_crit: cpu_crit { 2652 temperature = <110000>; 2653 hysteresis = <1000>; 2654 type = "critical"; 2655 }; 2656 }; 2657 2658 cooling-maps { 2659 map0 { 2660 trip = <&cpu0_alert0>; 2661 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2662 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2663 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2664 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2665 }; 2666 map1 { 2667 trip = <&cpu0_alert1>; 2668 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2669 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2670 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2671 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2672 }; 2673 }; 2674 }; 2675 2676 cpu1-thermal { 2677 polling-delay-passive = <250>; 2678 polling-delay = <1000>; 2679 2680 thermal-sensors = <&tsens0 2>; 2681 2682 trips { 2683 cpu1_alert0: trip-point0 { 2684 temperature = <90000>; 2685 hysteresis = <2000>; 2686 type = "passive"; 2687 }; 2688 2689 cpu1_alert1: trip-point1 { 2690 temperature = <95000>; 2691 hysteresis = <2000>; 2692 type = "passive"; 2693 }; 2694 2695 cpu1_crit: cpu_crit { 2696 temperature = <110000>; 2697 hysteresis = <1000>; 2698 type = "critical"; 2699 }; 2700 }; 2701 2702 cooling-maps { 2703 map0 { 2704 trip = <&cpu1_alert0>; 2705 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2706 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2707 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2708 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2709 }; 2710 map1 { 2711 trip = <&cpu1_alert1>; 2712 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2713 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2714 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2715 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2716 }; 2717 }; 2718 }; 2719 2720 cpu2-thermal { 2721 polling-delay-passive = <250>; 2722 polling-delay = <1000>; 2723 2724 thermal-sensors = <&tsens0 3>; 2725 2726 trips { 2727 cpu2_alert0: trip-point0 { 2728 temperature = <90000>; 2729 hysteresis = <2000>; 2730 type = "passive"; 2731 }; 2732 2733 cpu2_alert1: trip-point1 { 2734 temperature = <95000>; 2735 hysteresis = <2000>; 2736 type = "passive"; 2737 }; 2738 2739 cpu2_crit: cpu_crit { 2740 temperature = <110000>; 2741 hysteresis = <1000>; 2742 type = "critical"; 2743 }; 2744 }; 2745 2746 cooling-maps { 2747 map0 { 2748 trip = <&cpu2_alert0>; 2749 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2750 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2751 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2752 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2753 }; 2754 map1 { 2755 trip = <&cpu2_alert1>; 2756 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2757 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2758 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2759 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2760 }; 2761 }; 2762 }; 2763 2764 cpu3-thermal { 2765 polling-delay-passive = <250>; 2766 polling-delay = <1000>; 2767 2768 thermal-sensors = <&tsens0 4>; 2769 2770 trips { 2771 cpu3_alert0: trip-point0 { 2772 temperature = <90000>; 2773 hysteresis = <2000>; 2774 type = "passive"; 2775 }; 2776 2777 cpu3_alert1: trip-point1 { 2778 temperature = <95000>; 2779 hysteresis = <2000>; 2780 type = "passive"; 2781 }; 2782 2783 cpu3_crit: cpu_crit { 2784 temperature = <110000>; 2785 hysteresis = <1000>; 2786 type = "critical"; 2787 }; 2788 }; 2789 2790 cooling-maps { 2791 map0 { 2792 trip = <&cpu3_alert0>; 2793 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2794 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2795 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2796 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2797 }; 2798 map1 { 2799 trip = <&cpu3_alert1>; 2800 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2801 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2802 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2803 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2804 }; 2805 }; 2806 }; 2807 2808 cpu4-top-thermal { 2809 polling-delay-passive = <250>; 2810 polling-delay = <1000>; 2811 2812 thermal-sensors = <&tsens0 7>; 2813 2814 trips { 2815 cpu4_top_alert0: trip-point0 { 2816 temperature = <90000>; 2817 hysteresis = <2000>; 2818 type = "passive"; 2819 }; 2820 2821 cpu4_top_alert1: trip-point1 { 2822 temperature = <95000>; 2823 hysteresis = <2000>; 2824 type = "passive"; 2825 }; 2826 2827 cpu4_top_crit: cpu_crit { 2828 temperature = <110000>; 2829 hysteresis = <1000>; 2830 type = "critical"; 2831 }; 2832 }; 2833 2834 cooling-maps { 2835 map0 { 2836 trip = <&cpu4_top_alert0>; 2837 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2838 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2839 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2840 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2841 }; 2842 map1 { 2843 trip = <&cpu4_top_alert1>; 2844 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2845 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2846 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2847 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2848 }; 2849 }; 2850 }; 2851 2852 cpu5-top-thermal { 2853 polling-delay-passive = <250>; 2854 polling-delay = <1000>; 2855 2856 thermal-sensors = <&tsens0 8>; 2857 2858 trips { 2859 cpu5_top_alert0: trip-point0 { 2860 temperature = <90000>; 2861 hysteresis = <2000>; 2862 type = "passive"; 2863 }; 2864 2865 cpu5_top_alert1: trip-point1 { 2866 temperature = <95000>; 2867 hysteresis = <2000>; 2868 type = "passive"; 2869 }; 2870 2871 cpu5_top_crit: cpu_crit { 2872 temperature = <110000>; 2873 hysteresis = <1000>; 2874 type = "critical"; 2875 }; 2876 }; 2877 2878 cooling-maps { 2879 map0 { 2880 trip = <&cpu5_top_alert0>; 2881 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2882 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2883 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2884 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2885 }; 2886 map1 { 2887 trip = <&cpu5_top_alert1>; 2888 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2889 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2890 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2891 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2892 }; 2893 }; 2894 }; 2895 2896 cpu6-top-thermal { 2897 polling-delay-passive = <250>; 2898 polling-delay = <1000>; 2899 2900 thermal-sensors = <&tsens0 9>; 2901 2902 trips { 2903 cpu6_top_alert0: trip-point0 { 2904 temperature = <90000>; 2905 hysteresis = <2000>; 2906 type = "passive"; 2907 }; 2908 2909 cpu6_top_alert1: trip-point1 { 2910 temperature = <95000>; 2911 hysteresis = <2000>; 2912 type = "passive"; 2913 }; 2914 2915 cpu6_top_crit: cpu_crit { 2916 temperature = <110000>; 2917 hysteresis = <1000>; 2918 type = "critical"; 2919 }; 2920 }; 2921 2922 cooling-maps { 2923 map0 { 2924 trip = <&cpu6_top_alert0>; 2925 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2926 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2927 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2928 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2929 }; 2930 map1 { 2931 trip = <&cpu6_top_alert1>; 2932 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2933 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2934 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2935 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2936 }; 2937 }; 2938 }; 2939 2940 cpu7-top-thermal { 2941 polling-delay-passive = <250>; 2942 polling-delay = <1000>; 2943 2944 thermal-sensors = <&tsens0 10>; 2945 2946 trips { 2947 cpu7_top_alert0: trip-point0 { 2948 temperature = <90000>; 2949 hysteresis = <2000>; 2950 type = "passive"; 2951 }; 2952 2953 cpu7_top_alert1: trip-point1 { 2954 temperature = <95000>; 2955 hysteresis = <2000>; 2956 type = "passive"; 2957 }; 2958 2959 cpu7_top_crit: cpu_crit { 2960 temperature = <110000>; 2961 hysteresis = <1000>; 2962 type = "critical"; 2963 }; 2964 }; 2965 2966 cooling-maps { 2967 map0 { 2968 trip = <&cpu7_top_alert0>; 2969 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2970 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2971 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2972 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2973 }; 2974 map1 { 2975 trip = <&cpu7_top_alert1>; 2976 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2977 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2978 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2979 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2980 }; 2981 }; 2982 }; 2983 2984 cpu4-bottom-thermal { 2985 polling-delay-passive = <250>; 2986 polling-delay = <1000>; 2987 2988 thermal-sensors = <&tsens0 11>; 2989 2990 trips { 2991 cpu4_bottom_alert0: trip-point0 { 2992 temperature = <90000>; 2993 hysteresis = <2000>; 2994 type = "passive"; 2995 }; 2996 2997 cpu4_bottom_alert1: trip-point1 { 2998 temperature = <95000>; 2999 hysteresis = <2000>; 3000 type = "passive"; 3001 }; 3002 3003 cpu4_bottom_crit: cpu_crit { 3004 temperature = <110000>; 3005 hysteresis = <1000>; 3006 type = "critical"; 3007 }; 3008 }; 3009 3010 cooling-maps { 3011 map0 { 3012 trip = <&cpu4_bottom_alert0>; 3013 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3014 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3015 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3016 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3017 }; 3018 map1 { 3019 trip = <&cpu4_bottom_alert1>; 3020 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3021 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3022 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3023 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3024 }; 3025 }; 3026 }; 3027 3028 cpu5-bottom-thermal { 3029 polling-delay-passive = <250>; 3030 polling-delay = <1000>; 3031 3032 thermal-sensors = <&tsens0 12>; 3033 3034 trips { 3035 cpu5_bottom_alert0: trip-point0 { 3036 temperature = <90000>; 3037 hysteresis = <2000>; 3038 type = "passive"; 3039 }; 3040 3041 cpu5_bottom_alert1: trip-point1 { 3042 temperature = <95000>; 3043 hysteresis = <2000>; 3044 type = "passive"; 3045 }; 3046 3047 cpu5_bottom_crit: cpu_crit { 3048 temperature = <110000>; 3049 hysteresis = <1000>; 3050 type = "critical"; 3051 }; 3052 }; 3053 3054 cooling-maps { 3055 map0 { 3056 trip = <&cpu5_bottom_alert0>; 3057 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3058 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3059 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3060 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3061 }; 3062 map1 { 3063 trip = <&cpu5_bottom_alert1>; 3064 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3065 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3066 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3067 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3068 }; 3069 }; 3070 }; 3071 3072 cpu6-bottom-thermal { 3073 polling-delay-passive = <250>; 3074 polling-delay = <1000>; 3075 3076 thermal-sensors = <&tsens0 13>; 3077 3078 trips { 3079 cpu6_bottom_alert0: trip-point0 { 3080 temperature = <90000>; 3081 hysteresis = <2000>; 3082 type = "passive"; 3083 }; 3084 3085 cpu6_bottom_alert1: trip-point1 { 3086 temperature = <95000>; 3087 hysteresis = <2000>; 3088 type = "passive"; 3089 }; 3090 3091 cpu6_bottom_crit: cpu_crit { 3092 temperature = <110000>; 3093 hysteresis = <1000>; 3094 type = "critical"; 3095 }; 3096 }; 3097 3098 cooling-maps { 3099 map0 { 3100 trip = <&cpu6_bottom_alert0>; 3101 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3102 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3103 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3104 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3105 }; 3106 map1 { 3107 trip = <&cpu6_bottom_alert1>; 3108 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3109 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3110 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3111 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3112 }; 3113 }; 3114 }; 3115 3116 cpu7-bottom-thermal { 3117 polling-delay-passive = <250>; 3118 polling-delay = <1000>; 3119 3120 thermal-sensors = <&tsens0 14>; 3121 3122 trips { 3123 cpu7_bottom_alert0: trip-point0 { 3124 temperature = <90000>; 3125 hysteresis = <2000>; 3126 type = "passive"; 3127 }; 3128 3129 cpu7_bottom_alert1: trip-point1 { 3130 temperature = <95000>; 3131 hysteresis = <2000>; 3132 type = "passive"; 3133 }; 3134 3135 cpu7_bottom_crit: cpu_crit { 3136 temperature = <110000>; 3137 hysteresis = <1000>; 3138 type = "critical"; 3139 }; 3140 }; 3141 3142 cooling-maps { 3143 map0 { 3144 trip = <&cpu7_bottom_alert0>; 3145 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3146 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3147 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3148 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3149 }; 3150 map1 { 3151 trip = <&cpu7_bottom_alert1>; 3152 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3153 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3154 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3155 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3156 }; 3157 }; 3158 }; 3159 3160 aoss0-thermal { 3161 polling-delay-passive = <250>; 3162 polling-delay = <1000>; 3163 3164 thermal-sensors = <&tsens0 0>; 3165 3166 trips { 3167 aoss0_alert0: trip-point0 { 3168 temperature = <90000>; 3169 hysteresis = <2000>; 3170 type = "hot"; 3171 }; 3172 }; 3173 }; 3174 3175 cluster0-thermal { 3176 polling-delay-passive = <250>; 3177 polling-delay = <1000>; 3178 3179 thermal-sensors = <&tsens0 5>; 3180 3181 trips { 3182 cluster0_alert0: trip-point0 { 3183 temperature = <90000>; 3184 hysteresis = <2000>; 3185 type = "hot"; 3186 }; 3187 cluster0_crit: cluster0_crit { 3188 temperature = <110000>; 3189 hysteresis = <2000>; 3190 type = "critical"; 3191 }; 3192 }; 3193 }; 3194 3195 cluster1-thermal { 3196 polling-delay-passive = <250>; 3197 polling-delay = <1000>; 3198 3199 thermal-sensors = <&tsens0 6>; 3200 3201 trips { 3202 cluster1_alert0: trip-point0 { 3203 temperature = <90000>; 3204 hysteresis = <2000>; 3205 type = "hot"; 3206 }; 3207 cluster1_crit: cluster1_crit { 3208 temperature = <110000>; 3209 hysteresis = <2000>; 3210 type = "critical"; 3211 }; 3212 }; 3213 }; 3214 3215 aoss1-thermal { 3216 polling-delay-passive = <250>; 3217 polling-delay = <1000>; 3218 3219 thermal-sensors = <&tsens1 0>; 3220 3221 trips { 3222 aoss1_alert0: trip-point0 { 3223 temperature = <90000>; 3224 hysteresis = <2000>; 3225 type = "hot"; 3226 }; 3227 }; 3228 }; 3229 3230 gpu-top-thermal { 3231 polling-delay-passive = <250>; 3232 polling-delay = <1000>; 3233 3234 thermal-sensors = <&tsens1 1>; 3235 3236 trips { 3237 gpu1_alert0: trip-point0 { 3238 temperature = <90000>; 3239 hysteresis = <1000>; 3240 type = "hot"; 3241 }; 3242 }; 3243 }; 3244 3245 gpu-bottom-thermal { 3246 polling-delay-passive = <250>; 3247 polling-delay = <1000>; 3248 3249 thermal-sensors = <&tsens1 2>; 3250 3251 trips { 3252 gpu2_alert0: trip-point0 { 3253 temperature = <90000>; 3254 hysteresis = <1000>; 3255 type = "hot"; 3256 }; 3257 }; 3258 }; 3259 3260 nspss1-thermal { 3261 polling-delay-passive = <250>; 3262 polling-delay = <1000>; 3263 3264 thermal-sensors = <&tsens1 3>; 3265 3266 trips { 3267 nspss1_alert0: trip-point0 { 3268 temperature = <90000>; 3269 hysteresis = <1000>; 3270 type = "hot"; 3271 }; 3272 }; 3273 }; 3274 3275 nspss2-thermal { 3276 polling-delay-passive = <250>; 3277 polling-delay = <1000>; 3278 3279 thermal-sensors = <&tsens1 4>; 3280 3281 trips { 3282 nspss2_alert0: trip-point0 { 3283 temperature = <90000>; 3284 hysteresis = <1000>; 3285 type = "hot"; 3286 }; 3287 }; 3288 }; 3289 3290 nspss3-thermal { 3291 polling-delay-passive = <250>; 3292 polling-delay = <1000>; 3293 3294 thermal-sensors = <&tsens1 5>; 3295 3296 trips { 3297 nspss3_alert0: trip-point0 { 3298 temperature = <90000>; 3299 hysteresis = <1000>; 3300 type = "hot"; 3301 }; 3302 }; 3303 }; 3304 3305 video-thermal { 3306 polling-delay-passive = <250>; 3307 polling-delay = <1000>; 3308 3309 thermal-sensors = <&tsens1 6>; 3310 3311 trips { 3312 video_alert0: trip-point0 { 3313 temperature = <90000>; 3314 hysteresis = <2000>; 3315 type = "hot"; 3316 }; 3317 }; 3318 }; 3319 3320 mem-thermal { 3321 polling-delay-passive = <250>; 3322 polling-delay = <1000>; 3323 3324 thermal-sensors = <&tsens1 7>; 3325 3326 trips { 3327 mem_alert0: trip-point0 { 3328 temperature = <90000>; 3329 hysteresis = <2000>; 3330 type = "hot"; 3331 }; 3332 }; 3333 }; 3334 3335 modem1-top-thermal { 3336 polling-delay-passive = <250>; 3337 polling-delay = <1000>; 3338 3339 thermal-sensors = <&tsens1 8>; 3340 3341 trips { 3342 modem1_alert0: trip-point0 { 3343 temperature = <90000>; 3344 hysteresis = <2000>; 3345 type = "hot"; 3346 }; 3347 }; 3348 }; 3349 3350 modem2-top-thermal { 3351 polling-delay-passive = <250>; 3352 polling-delay = <1000>; 3353 3354 thermal-sensors = <&tsens1 9>; 3355 3356 trips { 3357 modem2_alert0: trip-point0 { 3358 temperature = <90000>; 3359 hysteresis = <2000>; 3360 type = "hot"; 3361 }; 3362 }; 3363 }; 3364 3365 modem3-top-thermal { 3366 polling-delay-passive = <250>; 3367 polling-delay = <1000>; 3368 3369 thermal-sensors = <&tsens1 10>; 3370 3371 trips { 3372 modem3_alert0: trip-point0 { 3373 temperature = <90000>; 3374 hysteresis = <2000>; 3375 type = "hot"; 3376 }; 3377 }; 3378 }; 3379 3380 modem4-top-thermal { 3381 polling-delay-passive = <250>; 3382 polling-delay = <1000>; 3383 3384 thermal-sensors = <&tsens1 11>; 3385 3386 trips { 3387 modem4_alert0: trip-point0 { 3388 temperature = <90000>; 3389 hysteresis = <2000>; 3390 type = "hot"; 3391 }; 3392 }; 3393 }; 3394 3395 camera-top-thermal { 3396 polling-delay-passive = <250>; 3397 polling-delay = <1000>; 3398 3399 thermal-sensors = <&tsens1 12>; 3400 3401 trips { 3402 camera1_alert0: trip-point0 { 3403 temperature = <90000>; 3404 hysteresis = <2000>; 3405 type = "hot"; 3406 }; 3407 }; 3408 }; 3409 3410 cam-bottom-thermal { 3411 polling-delay-passive = <250>; 3412 polling-delay = <1000>; 3413 3414 thermal-sensors = <&tsens1 13>; 3415 3416 trips { 3417 camera2_alert0: trip-point0 { 3418 temperature = <90000>; 3419 hysteresis = <2000>; 3420 type = "hot"; 3421 }; 3422 }; 3423 }; 3424 }; 3425 3426 timer { 3427 compatible = "arm,armv8-timer"; 3428 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3429 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3430 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3431 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3432 }; 3433}; 3434