1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,sm8350.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24#include <dt-bindings/interconnect/qcom,sm8350.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 clocks { 35 xo_board: xo-board { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <38400000>; 39 clock-output-names = "xo_board"; 40 }; 41 42 sleep_clk: sleep-clk { 43 compatible = "fixed-clock"; 44 clock-frequency = <32000>; 45 #clock-cells = <0>; 46 }; 47 }; 48 49 cpus { 50 #address-cells = <2>; 51 #size-cells = <0>; 52 53 CPU0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x0 0x0>; 57 clocks = <&cpufreq_hw 0>; 58 enable-method = "psci"; 59 next-level-cache = <&L2_0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 power-domains = <&CPU_PD0>; 62 power-domain-names = "psci"; 63 #cooling-cells = <2>; 64 L2_0: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&L3_0>; 69 L3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 CPU1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_100>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 power-domains = <&CPU_PD1>; 86 power-domain-names = "psci"; 87 #cooling-cells = <2>; 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 }; 95 96 CPU2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a55"; 99 reg = <0x0 0x200>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_200>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x0 0x300>; 119 clocks = <&cpufreq_hw 0>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_300>; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 power-domains = <&CPU_PD3>; 124 power-domain-names = "psci"; 125 #cooling-cells = <2>; 126 L2_300: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a78"; 137 reg = <0x0 0x400>; 138 clocks = <&cpufreq_hw 1>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_400>; 141 qcom,freq-domain = <&cpufreq_hw 1>; 142 power-domains = <&CPU_PD4>; 143 power-domain-names = "psci"; 144 #cooling-cells = <2>; 145 L2_400: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU5: cpu@500 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a78"; 156 reg = <0x0 0x500>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_500>; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 power-domains = <&CPU_PD5>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 L2_500: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a78"; 175 reg = <0x0 0x600>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 power-domains = <&CPU_PD6>; 181 power-domain-names = "psci"; 182 #cooling-cells = <2>; 183 L2_600: l2-cache { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-unified; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU7: cpu@700 { 192 device_type = "cpu"; 193 compatible = "arm,cortex-x1"; 194 reg = <0x0 0x700>; 195 clocks = <&cpufreq_hw 2>; 196 enable-method = "psci"; 197 next-level-cache = <&L2_700>; 198 qcom,freq-domain = <&cpufreq_hw 2>; 199 power-domains = <&CPU_PD7>; 200 power-domain-names = "psci"; 201 #cooling-cells = <2>; 202 L2_700: l2-cache { 203 compatible = "cache"; 204 cache-level = <2>; 205 cache-unified; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 cpu-map { 211 cluster0 { 212 core0 { 213 cpu = <&CPU0>; 214 }; 215 216 core1 { 217 cpu = <&CPU1>; 218 }; 219 220 core2 { 221 cpu = <&CPU2>; 222 }; 223 224 core3 { 225 cpu = <&CPU3>; 226 }; 227 228 core4 { 229 cpu = <&CPU4>; 230 }; 231 232 core5 { 233 cpu = <&CPU5>; 234 }; 235 236 core6 { 237 cpu = <&CPU6>; 238 }; 239 240 core7 { 241 cpu = <&CPU7>; 242 }; 243 }; 244 }; 245 246 idle-states { 247 entry-method = "psci"; 248 249 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 250 compatible = "arm,idle-state"; 251 idle-state-name = "silver-rail-power-collapse"; 252 arm,psci-suspend-param = <0x40000004>; 253 entry-latency-us = <360>; 254 exit-latency-us = <531>; 255 min-residency-us = <3934>; 256 local-timer-stop; 257 }; 258 259 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 260 compatible = "arm,idle-state"; 261 idle-state-name = "gold-rail-power-collapse"; 262 arm,psci-suspend-param = <0x40000004>; 263 entry-latency-us = <702>; 264 exit-latency-us = <1061>; 265 min-residency-us = <4488>; 266 local-timer-stop; 267 }; 268 }; 269 270 domain-idle-states { 271 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 272 compatible = "domain-idle-state"; 273 arm,psci-suspend-param = <0x41000044>; 274 entry-latency-us = <2752>; 275 exit-latency-us = <3048>; 276 min-residency-us = <6118>; 277 }; 278 279 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 280 compatible = "domain-idle-state"; 281 arm,psci-suspend-param = <0x4100c344>; 282 entry-latency-us = <3263>; 283 exit-latency-us = <6562>; 284 min-residency-us = <9987>; 285 }; 286 }; 287 }; 288 289 firmware { 290 scm: scm { 291 compatible = "qcom,scm-sm8350", "qcom,scm"; 292 qcom,dload-mode = <&tcsr 0x13000>; 293 #reset-cells = <1>; 294 }; 295 }; 296 297 memory@80000000 { 298 device_type = "memory"; 299 /* We expect the bootloader to fill in the size */ 300 reg = <0x0 0x80000000 0x0 0x0>; 301 }; 302 303 pmu { 304 compatible = "arm,armv8-pmuv3"; 305 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 306 }; 307 308 psci { 309 compatible = "arm,psci-1.0"; 310 method = "smc"; 311 312 CPU_PD0: power-domain-cpu0 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 316 }; 317 318 CPU_PD1: power-domain-cpu1 { 319 #power-domain-cells = <0>; 320 power-domains = <&CLUSTER_PD>; 321 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 322 }; 323 324 CPU_PD2: power-domain-cpu2 { 325 #power-domain-cells = <0>; 326 power-domains = <&CLUSTER_PD>; 327 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 328 }; 329 330 CPU_PD3: power-domain-cpu3 { 331 #power-domain-cells = <0>; 332 power-domains = <&CLUSTER_PD>; 333 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 334 }; 335 336 CPU_PD4: power-domain-cpu4 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&BIG_CPU_SLEEP_0>; 340 }; 341 342 CPU_PD5: power-domain-cpu5 { 343 #power-domain-cells = <0>; 344 power-domains = <&CLUSTER_PD>; 345 domain-idle-states = <&BIG_CPU_SLEEP_0>; 346 }; 347 348 CPU_PD6: power-domain-cpu6 { 349 #power-domain-cells = <0>; 350 power-domains = <&CLUSTER_PD>; 351 domain-idle-states = <&BIG_CPU_SLEEP_0>; 352 }; 353 354 CPU_PD7: power-domain-cpu7 { 355 #power-domain-cells = <0>; 356 power-domains = <&CLUSTER_PD>; 357 domain-idle-states = <&BIG_CPU_SLEEP_0>; 358 }; 359 360 CLUSTER_PD: power-domain-cpu-cluster0 { 361 #power-domain-cells = <0>; 362 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 363 }; 364 }; 365 366 qup_opp_table_100mhz: opp-table-qup100mhz { 367 compatible = "operating-points-v2"; 368 369 opp-50000000 { 370 opp-hz = /bits/ 64 <50000000>; 371 required-opps = <&rpmhpd_opp_min_svs>; 372 }; 373 374 opp-75000000 { 375 opp-hz = /bits/ 64 <75000000>; 376 required-opps = <&rpmhpd_opp_low_svs>; 377 }; 378 379 opp-100000000 { 380 opp-hz = /bits/ 64 <100000000>; 381 required-opps = <&rpmhpd_opp_svs>; 382 }; 383 }; 384 385 qup_opp_table_120mhz: opp-table-qup120mhz { 386 compatible = "operating-points-v2"; 387 388 opp-50000000 { 389 opp-hz = /bits/ 64 <50000000>; 390 required-opps = <&rpmhpd_opp_min_svs>; 391 }; 392 393 opp-75000000 { 394 opp-hz = /bits/ 64 <75000000>; 395 required-opps = <&rpmhpd_opp_low_svs>; 396 }; 397 398 opp-120000000 { 399 opp-hz = /bits/ 64 <120000000>; 400 required-opps = <&rpmhpd_opp_svs>; 401 }; 402 }; 403 404 reserved_memory: reserved-memory { 405 #address-cells = <2>; 406 #size-cells = <2>; 407 ranges; 408 409 hyp_mem: memory@80000000 { 410 reg = <0x0 0x80000000 0x0 0x600000>; 411 no-map; 412 }; 413 414 xbl_aop_mem: memory@80700000 { 415 no-map; 416 reg = <0x0 0x80700000 0x0 0x160000>; 417 }; 418 419 cmd_db: memory@80860000 { 420 compatible = "qcom,cmd-db"; 421 reg = <0x0 0x80860000 0x0 0x20000>; 422 no-map; 423 }; 424 425 reserved_xbl_uefi_log: memory@80880000 { 426 reg = <0x0 0x80880000 0x0 0x14000>; 427 no-map; 428 }; 429 430 smem@80900000 { 431 compatible = "qcom,smem"; 432 reg = <0x0 0x80900000 0x0 0x200000>; 433 hwlocks = <&tcsr_mutex 3>; 434 no-map; 435 }; 436 437 cpucp_fw_mem: memory@80b00000 { 438 reg = <0x0 0x80b00000 0x0 0x100000>; 439 no-map; 440 }; 441 442 cdsp_secure_heap: memory@80c00000 { 443 reg = <0x0 0x80c00000 0x0 0x4600000>; 444 no-map; 445 }; 446 447 pil_camera_mem: mmeory@85200000 { 448 reg = <0x0 0x85200000 0x0 0x500000>; 449 no-map; 450 }; 451 452 pil_video_mem: memory@85700000 { 453 reg = <0x0 0x85700000 0x0 0x500000>; 454 no-map; 455 }; 456 457 pil_cvp_mem: memory@85c00000 { 458 reg = <0x0 0x85c00000 0x0 0x500000>; 459 no-map; 460 }; 461 462 pil_adsp_mem: memory@86100000 { 463 reg = <0x0 0x86100000 0x0 0x2100000>; 464 no-map; 465 }; 466 467 pil_slpi_mem: memory@88200000 { 468 reg = <0x0 0x88200000 0x0 0x1500000>; 469 no-map; 470 }; 471 472 pil_cdsp_mem: memory@89700000 { 473 reg = <0x0 0x89700000 0x0 0x1e00000>; 474 no-map; 475 }; 476 477 pil_ipa_fw_mem: memory@8b500000 { 478 reg = <0x0 0x8b500000 0x0 0x10000>; 479 no-map; 480 }; 481 482 pil_ipa_gsi_mem: memory@8b510000 { 483 reg = <0x0 0x8b510000 0x0 0xa000>; 484 no-map; 485 }; 486 487 pil_gpu_mem: memory@8b51a000 { 488 reg = <0x0 0x8b51a000 0x0 0x2000>; 489 no-map; 490 }; 491 492 pil_spss_mem: memory@8b600000 { 493 reg = <0x0 0x8b600000 0x0 0x100000>; 494 no-map; 495 }; 496 497 pil_modem_mem: memory@8b800000 { 498 reg = <0x0 0x8b800000 0x0 0x10000000>; 499 no-map; 500 }; 501 502 rmtfs_mem: memory@9b800000 { 503 compatible = "qcom,rmtfs-mem"; 504 reg = <0x0 0x9b800000 0x0 0x280000>; 505 no-map; 506 507 qcom,client-id = <1>; 508 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 509 }; 510 511 hyp_reserved_mem: memory@d0000000 { 512 reg = <0x0 0xd0000000 0x0 0x800000>; 513 no-map; 514 }; 515 516 pil_trustedvm_mem: memory@d0800000 { 517 reg = <0x0 0xd0800000 0x0 0x76f7000>; 518 no-map; 519 }; 520 521 qrtr_shbuf: memory@d7ef7000 { 522 reg = <0x0 0xd7ef7000 0x0 0x9000>; 523 no-map; 524 }; 525 526 chan0_shbuf: memory@d7f00000 { 527 reg = <0x0 0xd7f00000 0x0 0x80000>; 528 no-map; 529 }; 530 531 chan1_shbuf: memory@d7f80000 { 532 reg = <0x0 0xd7f80000 0x0 0x80000>; 533 no-map; 534 }; 535 536 removed_mem: memory@d8800000 { 537 reg = <0x0 0xd8800000 0x0 0x6800000>; 538 no-map; 539 }; 540 }; 541 542 smp2p-adsp { 543 compatible = "qcom,smp2p"; 544 qcom,smem = <443>, <429>; 545 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 546 IPCC_MPROC_SIGNAL_SMP2P 547 IRQ_TYPE_EDGE_RISING>; 548 mboxes = <&ipcc IPCC_CLIENT_LPASS 549 IPCC_MPROC_SIGNAL_SMP2P>; 550 551 qcom,local-pid = <0>; 552 qcom,remote-pid = <2>; 553 554 smp2p_adsp_out: master-kernel { 555 qcom,entry-name = "master-kernel"; 556 #qcom,smem-state-cells = <1>; 557 }; 558 559 smp2p_adsp_in: slave-kernel { 560 qcom,entry-name = "slave-kernel"; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 }; 564 }; 565 566 smp2p-cdsp { 567 compatible = "qcom,smp2p"; 568 qcom,smem = <94>, <432>; 569 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 570 IPCC_MPROC_SIGNAL_SMP2P 571 IRQ_TYPE_EDGE_RISING>; 572 mboxes = <&ipcc IPCC_CLIENT_CDSP 573 IPCC_MPROC_SIGNAL_SMP2P>; 574 575 qcom,local-pid = <0>; 576 qcom,remote-pid = <5>; 577 578 smp2p_cdsp_out: master-kernel { 579 qcom,entry-name = "master-kernel"; 580 #qcom,smem-state-cells = <1>; 581 }; 582 583 smp2p_cdsp_in: slave-kernel { 584 qcom,entry-name = "slave-kernel"; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 }; 589 590 smp2p-modem { 591 compatible = "qcom,smp2p"; 592 qcom,smem = <435>, <428>; 593 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 594 IPCC_MPROC_SIGNAL_SMP2P 595 IRQ_TYPE_EDGE_RISING>; 596 mboxes = <&ipcc IPCC_CLIENT_MPSS 597 IPCC_MPROC_SIGNAL_SMP2P>; 598 599 qcom,local-pid = <0>; 600 qcom,remote-pid = <1>; 601 602 smp2p_modem_out: master-kernel { 603 qcom,entry-name = "master-kernel"; 604 #qcom,smem-state-cells = <1>; 605 }; 606 607 smp2p_modem_in: slave-kernel { 608 qcom,entry-name = "slave-kernel"; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 }; 612 613 ipa_smp2p_out: ipa-ap-to-modem { 614 qcom,entry-name = "ipa"; 615 #qcom,smem-state-cells = <1>; 616 }; 617 618 ipa_smp2p_in: ipa-modem-to-ap { 619 qcom,entry-name = "ipa"; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 }; 624 625 smp2p-slpi { 626 compatible = "qcom,smp2p"; 627 qcom,smem = <481>, <430>; 628 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 629 IPCC_MPROC_SIGNAL_SMP2P 630 IRQ_TYPE_EDGE_RISING>; 631 mboxes = <&ipcc IPCC_CLIENT_SLPI 632 IPCC_MPROC_SIGNAL_SMP2P>; 633 634 qcom,local-pid = <0>; 635 qcom,remote-pid = <3>; 636 637 smp2p_slpi_out: master-kernel { 638 qcom,entry-name = "master-kernel"; 639 #qcom,smem-state-cells = <1>; 640 }; 641 642 smp2p_slpi_in: slave-kernel { 643 qcom,entry-name = "slave-kernel"; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 }; 648 649 soc: soc@0 { 650 #address-cells = <2>; 651 #size-cells = <2>; 652 ranges = <0 0 0 0 0x10 0>; 653 dma-ranges = <0 0 0 0 0x10 0>; 654 compatible = "simple-bus"; 655 656 gcc: clock-controller@100000 { 657 compatible = "qcom,gcc-sm8350"; 658 reg = <0x0 0x00100000 0x0 0x1f0000>; 659 #clock-cells = <1>; 660 #reset-cells = <1>; 661 #power-domain-cells = <1>; 662 clock-names = "bi_tcxo", 663 "sleep_clk", 664 "pcie_0_pipe_clk", 665 "pcie_1_pipe_clk", 666 "ufs_card_rx_symbol_0_clk", 667 "ufs_card_rx_symbol_1_clk", 668 "ufs_card_tx_symbol_0_clk", 669 "ufs_phy_rx_symbol_0_clk", 670 "ufs_phy_rx_symbol_1_clk", 671 "ufs_phy_tx_symbol_0_clk", 672 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 673 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 674 clocks = <&rpmhcc RPMH_CXO_CLK>, 675 <&sleep_clk>, 676 <&pcie0_phy>, 677 <&pcie1_phy>, 678 <0>, 679 <0>, 680 <0>, 681 <&ufs_mem_phy 0>, 682 <&ufs_mem_phy 1>, 683 <&ufs_mem_phy 2>, 684 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 685 <0>; 686 }; 687 688 ipcc: mailbox@408000 { 689 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 690 reg = <0 0x00408000 0 0x1000>; 691 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 692 interrupt-controller; 693 #interrupt-cells = <3>; 694 #mbox-cells = <2>; 695 }; 696 697 gpi_dma2: dma-controller@800000 { 698 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 699 reg = <0 0x00800000 0 0x60000>; 700 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 712 dma-channels = <12>; 713 dma-channel-mask = <0xff>; 714 iommus = <&apps_smmu 0x5f6 0x0>; 715 #dma-cells = <3>; 716 status = "disabled"; 717 }; 718 719 qupv3_id_2: geniqup@8c0000 { 720 compatible = "qcom,geni-se-qup"; 721 reg = <0x0 0x008c0000 0x0 0x6000>; 722 clock-names = "m-ahb", "s-ahb"; 723 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 724 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 725 iommus = <&apps_smmu 0x5e3 0x0>; 726 #address-cells = <2>; 727 #size-cells = <2>; 728 ranges; 729 status = "disabled"; 730 731 i2c14: i2c@880000 { 732 compatible = "qcom,geni-i2c"; 733 reg = <0 0x00880000 0 0x4000>; 734 clock-names = "se"; 735 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&qup_i2c14_default>; 738 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 739 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 740 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 741 dma-names = "tx", "rx"; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 status = "disabled"; 745 }; 746 747 spi14: spi@880000 { 748 compatible = "qcom,geni-spi"; 749 reg = <0 0x00880000 0 0x4000>; 750 clock-names = "se"; 751 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 752 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 753 power-domains = <&rpmhpd RPMHPD_CX>; 754 operating-points-v2 = <&qup_opp_table_120mhz>; 755 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 756 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 757 dma-names = "tx", "rx"; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 i2c15: i2c@884000 { 764 compatible = "qcom,geni-i2c"; 765 reg = <0 0x00884000 0 0x4000>; 766 clock-names = "se"; 767 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&qup_i2c15_default>; 770 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 771 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 772 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 773 dma-names = "tx", "rx"; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 status = "disabled"; 777 }; 778 779 spi15: spi@884000 { 780 compatible = "qcom,geni-spi"; 781 reg = <0 0x00884000 0 0x4000>; 782 clock-names = "se"; 783 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 784 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 785 power-domains = <&rpmhpd RPMHPD_CX>; 786 operating-points-v2 = <&qup_opp_table_120mhz>; 787 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 788 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 789 dma-names = "tx", "rx"; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 status = "disabled"; 793 }; 794 795 i2c16: i2c@888000 { 796 compatible = "qcom,geni-i2c"; 797 reg = <0 0x00888000 0 0x4000>; 798 clock-names = "se"; 799 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&qup_i2c16_default>; 802 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 803 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 804 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 805 dma-names = "tx", "rx"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 }; 810 811 spi16: spi@888000 { 812 compatible = "qcom,geni-spi"; 813 reg = <0 0x00888000 0 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 816 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 817 power-domains = <&rpmhpd RPMHPD_CX>; 818 operating-points-v2 = <&qup_opp_table_100mhz>; 819 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 820 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 821 dma-names = "tx", "rx"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 status = "disabled"; 825 }; 826 827 i2c17: i2c@88c000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x0088c000 0 0x4000>; 830 clock-names = "se"; 831 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c17_default>; 834 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 835 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 836 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 837 dma-names = "tx", "rx"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 status = "disabled"; 841 }; 842 843 spi17: spi@88c000 { 844 compatible = "qcom,geni-spi"; 845 reg = <0 0x0088c000 0 0x4000>; 846 clock-names = "se"; 847 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 848 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 849 power-domains = <&rpmhpd RPMHPD_CX>; 850 operating-points-v2 = <&qup_opp_table_100mhz>; 851 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 852 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 853 dma-names = "tx", "rx"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 status = "disabled"; 857 }; 858 859 /* QUP no. 18 seems to be strictly SPI/UART-only */ 860 861 spi18: spi@890000 { 862 compatible = "qcom,geni-spi"; 863 reg = <0 0x00890000 0 0x4000>; 864 clock-names = "se"; 865 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 866 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 867 power-domains = <&rpmhpd RPMHPD_CX>; 868 operating-points-v2 = <&qup_opp_table_100mhz>; 869 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 870 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 871 dma-names = "tx", "rx"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 status = "disabled"; 875 }; 876 877 uart18: serial@890000 { 878 compatible = "qcom,geni-uart"; 879 reg = <0 0x00890000 0 0x4000>; 880 clock-names = "se"; 881 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&qup_uart18_default>; 884 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 885 power-domains = <&rpmhpd RPMHPD_CX>; 886 operating-points-v2 = <&qup_opp_table_100mhz>; 887 status = "disabled"; 888 }; 889 890 i2c19: i2c@894000 { 891 compatible = "qcom,geni-i2c"; 892 reg = <0 0x00894000 0 0x4000>; 893 clock-names = "se"; 894 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&qup_i2c19_default>; 897 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 898 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 899 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 900 dma-names = "tx", "rx"; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 spi19: spi@894000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0 0x00894000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 911 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 912 power-domains = <&rpmhpd RPMHPD_CX>; 913 operating-points-v2 = <&qup_opp_table_100mhz>; 914 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 915 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 916 dma-names = "tx", "rx"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 }; 922 923 gpi_dma0: dma-controller@900000 { 924 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 925 reg = <0 0x00900000 0 0x60000>; 926 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 938 dma-channels = <12>; 939 dma-channel-mask = <0x7e>; 940 iommus = <&apps_smmu 0x5b6 0x0>; 941 #dma-cells = <3>; 942 status = "disabled"; 943 }; 944 945 qupv3_id_0: geniqup@9c0000 { 946 compatible = "qcom,geni-se-qup"; 947 reg = <0x0 0x009c0000 0x0 0x6000>; 948 clock-names = "m-ahb", "s-ahb"; 949 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 950 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 951 iommus = <&apps_smmu 0x5a3 0>; 952 #address-cells = <2>; 953 #size-cells = <2>; 954 ranges; 955 status = "disabled"; 956 957 i2c0: i2c@980000 { 958 compatible = "qcom,geni-i2c"; 959 reg = <0 0x00980000 0 0x4000>; 960 clock-names = "se"; 961 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 962 pinctrl-names = "default"; 963 pinctrl-0 = <&qup_i2c0_default>; 964 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 965 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 966 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 967 dma-names = "tx", "rx"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 status = "disabled"; 971 }; 972 973 spi0: spi@980000 { 974 compatible = "qcom,geni-spi"; 975 reg = <0 0x00980000 0 0x4000>; 976 clock-names = "se"; 977 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 978 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 979 power-domains = <&rpmhpd RPMHPD_CX>; 980 operating-points-v2 = <&qup_opp_table_100mhz>; 981 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 982 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 983 dma-names = "tx", "rx"; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 status = "disabled"; 987 }; 988 989 i2c1: i2c@984000 { 990 compatible = "qcom,geni-i2c"; 991 reg = <0 0x00984000 0 0x4000>; 992 clock-names = "se"; 993 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_i2c1_default>; 996 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 997 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 998 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 999 dma-names = "tx", "rx"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 spi1: spi@984000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0 0x00984000 0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1010 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1011 power-domains = <&rpmhpd RPMHPD_CX>; 1012 operating-points-v2 = <&qup_opp_table_100mhz>; 1013 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1014 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1015 dma-names = "tx", "rx"; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 status = "disabled"; 1019 }; 1020 1021 i2c2: i2c@988000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0 0x00988000 0 0x4000>; 1024 clock-names = "se"; 1025 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&qup_i2c2_default>; 1028 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1029 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1030 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1031 dma-names = "tx", "rx"; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 spi2: spi@988000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0 0x00988000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1042 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1043 power-domains = <&rpmhpd RPMHPD_CX>; 1044 operating-points-v2 = <&qup_opp_table_100mhz>; 1045 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1046 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1047 dma-names = "tx", "rx"; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 status = "disabled"; 1051 }; 1052 1053 uart2: serial@98c000 { 1054 compatible = "qcom,geni-debug-uart"; 1055 reg = <0 0x0098c000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_uart3_default_state>; 1060 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1061 power-domains = <&rpmhpd RPMHPD_CX>; 1062 operating-points-v2 = <&qup_opp_table_100mhz>; 1063 status = "disabled"; 1064 }; 1065 1066 /* QUP no. 3 seems to be strictly SPI-only */ 1067 1068 spi3: spi@98c000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x0098c000 0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1073 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1074 power-domains = <&rpmhpd RPMHPD_CX>; 1075 operating-points-v2 = <&qup_opp_table_100mhz>; 1076 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1077 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1078 dma-names = "tx", "rx"; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 status = "disabled"; 1082 }; 1083 1084 i2c4: i2c@990000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00990000 0 0x4000>; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_i2c4_default>; 1091 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1092 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1093 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1094 dma-names = "tx", "rx"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 spi4: spi@990000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x00990000 0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1105 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1106 power-domains = <&rpmhpd RPMHPD_CX>; 1107 operating-points-v2 = <&qup_opp_table_100mhz>; 1108 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1109 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1110 dma-names = "tx", "rx"; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 i2c5: i2c@994000 { 1117 compatible = "qcom,geni-i2c"; 1118 reg = <0 0x00994000 0 0x4000>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&qup_i2c5_default>; 1123 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1124 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1125 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1126 dma-names = "tx", "rx"; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 spi5: spi@994000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x00994000 0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1137 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmhpd RPMHPD_CX>; 1139 operating-points-v2 = <&qup_opp_table_100mhz>; 1140 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1141 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1142 dma-names = "tx", "rx"; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 i2c6: i2c@998000 { 1149 compatible = "qcom,geni-i2c"; 1150 reg = <0 0x00998000 0 0x4000>; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_i2c6_default>; 1155 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1156 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1157 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1158 dma-names = "tx", "rx"; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 status = "disabled"; 1162 }; 1163 1164 spi6: spi@998000 { 1165 compatible = "qcom,geni-spi"; 1166 reg = <0 0x00998000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1169 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1170 power-domains = <&rpmhpd RPMHPD_CX>; 1171 operating-points-v2 = <&qup_opp_table_100mhz>; 1172 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1173 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1174 dma-names = "tx", "rx"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 uart6: serial@998000 { 1181 compatible = "qcom,geni-uart"; 1182 reg = <0 0x00998000 0 0x4000>; 1183 clock-names = "se"; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1185 pinctrl-names = "default"; 1186 pinctrl-0 = <&qup_uart6_default>; 1187 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1188 power-domains = <&rpmhpd RPMHPD_CX>; 1189 operating-points-v2 = <&qup_opp_table_100mhz>; 1190 status = "disabled"; 1191 }; 1192 1193 i2c7: i2c@99c000 { 1194 compatible = "qcom,geni-i2c"; 1195 reg = <0 0x0099c000 0 0x4000>; 1196 clock-names = "se"; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_i2c7_default>; 1200 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1201 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1202 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1203 dma-names = "tx", "rx"; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 status = "disabled"; 1207 }; 1208 1209 spi7: spi@99c000 { 1210 compatible = "qcom,geni-spi"; 1211 reg = <0 0x0099c000 0 0x4000>; 1212 clock-names = "se"; 1213 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1214 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd RPMHPD_CX>; 1216 operating-points-v2 = <&qup_opp_table_100mhz>; 1217 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1218 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1219 dma-names = "tx", "rx"; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 }; 1225 1226 gpi_dma1: dma-controller@a00000 { 1227 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1228 reg = <0 0x00a00000 0 0x60000>; 1229 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1241 dma-channels = <12>; 1242 dma-channel-mask = <0xff>; 1243 iommus = <&apps_smmu 0x56 0x0>; 1244 #dma-cells = <3>; 1245 status = "disabled"; 1246 }; 1247 1248 qupv3_id_1: geniqup@ac0000 { 1249 compatible = "qcom,geni-se-qup"; 1250 reg = <0x0 0x00ac0000 0x0 0x6000>; 1251 clock-names = "m-ahb", "s-ahb"; 1252 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1253 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1254 iommus = <&apps_smmu 0x43 0>; 1255 #address-cells = <2>; 1256 #size-cells = <2>; 1257 ranges; 1258 status = "disabled"; 1259 1260 i2c8: i2c@a80000 { 1261 compatible = "qcom,geni-i2c"; 1262 reg = <0 0x00a80000 0 0x4000>; 1263 clock-names = "se"; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&qup_i2c8_default>; 1267 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1268 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1269 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1270 dma-names = "tx", "rx"; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 status = "disabled"; 1274 }; 1275 1276 spi8: spi@a80000 { 1277 compatible = "qcom,geni-spi"; 1278 reg = <0 0x00a80000 0 0x4000>; 1279 clock-names = "se"; 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1281 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&rpmhpd RPMHPD_CX>; 1283 operating-points-v2 = <&qup_opp_table_120mhz>; 1284 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1285 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1286 dma-names = "tx", "rx"; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 status = "disabled"; 1290 }; 1291 1292 i2c9: i2c@a84000 { 1293 compatible = "qcom,geni-i2c"; 1294 reg = <0 0x00a84000 0 0x4000>; 1295 clock-names = "se"; 1296 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_i2c9_default>; 1299 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1300 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1301 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1302 dma-names = "tx", "rx"; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 status = "disabled"; 1306 }; 1307 1308 spi9: spi@a84000 { 1309 compatible = "qcom,geni-spi"; 1310 reg = <0 0x00a84000 0 0x4000>; 1311 clock-names = "se"; 1312 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1313 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1314 power-domains = <&rpmhpd RPMHPD_CX>; 1315 operating-points-v2 = <&qup_opp_table_100mhz>; 1316 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1317 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1318 dma-names = "tx", "rx"; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 i2c10: i2c@a88000 { 1325 compatible = "qcom,geni-i2c"; 1326 reg = <0 0x00a88000 0 0x4000>; 1327 clock-names = "se"; 1328 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_i2c10_default>; 1331 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1332 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1333 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1334 dma-names = "tx", "rx"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 spi10: spi@a88000 { 1341 compatible = "qcom,geni-spi"; 1342 reg = <0 0x00a88000 0 0x4000>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1345 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1346 power-domains = <&rpmhpd RPMHPD_CX>; 1347 operating-points-v2 = <&qup_opp_table_100mhz>; 1348 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1349 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1350 dma-names = "tx", "rx"; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 status = "disabled"; 1354 }; 1355 1356 i2c11: i2c@a8c000 { 1357 compatible = "qcom,geni-i2c"; 1358 reg = <0 0x00a8c000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_i2c11_default>; 1363 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1364 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1365 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1366 dma-names = "tx", "rx"; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 status = "disabled"; 1370 }; 1371 1372 spi11: spi@a8c000 { 1373 compatible = "qcom,geni-spi"; 1374 reg = <0 0x00a8c000 0 0x4000>; 1375 clock-names = "se"; 1376 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1377 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1378 power-domains = <&rpmhpd RPMHPD_CX>; 1379 operating-points-v2 = <&qup_opp_table_100mhz>; 1380 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1381 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1382 dma-names = "tx", "rx"; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 status = "disabled"; 1386 }; 1387 1388 i2c12: i2c@a90000 { 1389 compatible = "qcom,geni-i2c"; 1390 reg = <0 0x00a90000 0 0x4000>; 1391 clock-names = "se"; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_i2c12_default>; 1395 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1396 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1397 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1398 dma-names = "tx", "rx"; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 status = "disabled"; 1402 }; 1403 1404 spi12: spi@a90000 { 1405 compatible = "qcom,geni-spi"; 1406 reg = <0 0x00a90000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1409 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1410 power-domains = <&rpmhpd RPMHPD_CX>; 1411 operating-points-v2 = <&qup_opp_table_100mhz>; 1412 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1413 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1414 dma-names = "tx", "rx"; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 status = "disabled"; 1418 }; 1419 1420 i2c13: i2c@a94000 { 1421 compatible = "qcom,geni-i2c"; 1422 reg = <0 0x00a94000 0 0x4000>; 1423 clock-names = "se"; 1424 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1425 pinctrl-names = "default"; 1426 pinctrl-0 = <&qup_i2c13_default>; 1427 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1428 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1429 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1430 dma-names = "tx", "rx"; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 status = "disabled"; 1434 }; 1435 1436 spi13: spi@a94000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x00a94000 0 0x4000>; 1439 clock-names = "se"; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1441 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1442 power-domains = <&rpmhpd RPMHPD_CX>; 1443 operating-points-v2 = <&qup_opp_table_100mhz>; 1444 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1445 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1446 dma-names = "tx", "rx"; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 }; 1452 1453 rng: rng@10d3000 { 1454 compatible = "qcom,prng-ee"; 1455 reg = <0 0x010d3000 0 0x1000>; 1456 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1457 clock-names = "core"; 1458 }; 1459 1460 config_noc: interconnect@1500000 { 1461 compatible = "qcom,sm8350-config-noc"; 1462 reg = <0 0x01500000 0 0xa580>; 1463 #interconnect-cells = <2>; 1464 qcom,bcm-voters = <&apps_bcm_voter>; 1465 }; 1466 1467 mc_virt: interconnect@1580000 { 1468 compatible = "qcom,sm8350-mc-virt"; 1469 reg = <0 0x01580000 0 0x1000>; 1470 #interconnect-cells = <2>; 1471 qcom,bcm-voters = <&apps_bcm_voter>; 1472 }; 1473 1474 system_noc: interconnect@1680000 { 1475 compatible = "qcom,sm8350-system-noc"; 1476 reg = <0 0x01680000 0 0x1c200>; 1477 #interconnect-cells = <2>; 1478 qcom,bcm-voters = <&apps_bcm_voter>; 1479 }; 1480 1481 aggre1_noc: interconnect@16e0000 { 1482 compatible = "qcom,sm8350-aggre1-noc"; 1483 reg = <0 0x016e0000 0 0x1f180>; 1484 #interconnect-cells = <2>; 1485 qcom,bcm-voters = <&apps_bcm_voter>; 1486 }; 1487 1488 aggre2_noc: interconnect@1700000 { 1489 compatible = "qcom,sm8350-aggre2-noc"; 1490 reg = <0 0x01700000 0 0x33000>; 1491 #interconnect-cells = <2>; 1492 qcom,bcm-voters = <&apps_bcm_voter>; 1493 }; 1494 1495 mmss_noc: interconnect@1740000 { 1496 compatible = "qcom,sm8350-mmss-noc"; 1497 reg = <0 0x01740000 0 0x1f080>; 1498 #interconnect-cells = <2>; 1499 qcom,bcm-voters = <&apps_bcm_voter>; 1500 }; 1501 1502 pcie0: pcie@1c00000 { 1503 compatible = "qcom,pcie-sm8350"; 1504 reg = <0 0x01c00000 0 0x3000>, 1505 <0 0x60000000 0 0xf1d>, 1506 <0 0x60000f20 0 0xa8>, 1507 <0 0x60001000 0 0x1000>, 1508 <0 0x60100000 0 0x100000>; 1509 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1510 device_type = "pci"; 1511 linux,pci-domain = <0>; 1512 bus-range = <0x00 0xff>; 1513 num-lanes = <1>; 1514 1515 #address-cells = <3>; 1516 #size-cells = <2>; 1517 1518 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1519 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1520 1521 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1529 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1530 "msi4", "msi5", "msi6", "msi7"; 1531 #interrupt-cells = <1>; 1532 interrupt-map-mask = <0 0 0 0x7>; 1533 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1534 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1535 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1536 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1537 1538 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1539 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1540 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1541 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1542 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1543 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1544 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1545 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1546 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1547 clock-names = "aux", 1548 "cfg", 1549 "bus_master", 1550 "bus_slave", 1551 "slave_q2a", 1552 "tbu", 1553 "ddrss_sf_tbu", 1554 "aggre1", 1555 "aggre0"; 1556 1557 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1558 <0x100 &apps_smmu 0x1c01 0x1>; 1559 1560 resets = <&gcc GCC_PCIE_0_BCR>; 1561 reset-names = "pci"; 1562 1563 power-domains = <&gcc PCIE_0_GDSC>; 1564 1565 phys = <&pcie0_phy>; 1566 phy-names = "pciephy"; 1567 1568 status = "disabled"; 1569 }; 1570 1571 pcie0_phy: phy@1c06000 { 1572 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1573 reg = <0 0x01c06000 0 0x2000>; 1574 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1575 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1576 <&gcc GCC_PCIE_0_CLKREF_EN>, 1577 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1578 <&gcc GCC_PCIE_0_PIPE_CLK>; 1579 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1580 1581 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1582 reset-names = "phy"; 1583 1584 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1585 assigned-clock-rates = <100000000>; 1586 1587 #clock-cells = <0>; 1588 clock-output-names = "pcie_0_pipe_clk"; 1589 1590 #phy-cells = <0>; 1591 1592 status = "disabled"; 1593 }; 1594 1595 pcie1: pcie@1c08000 { 1596 compatible = "qcom,pcie-sm8350"; 1597 reg = <0 0x01c08000 0 0x3000>, 1598 <0 0x40000000 0 0xf1d>, 1599 <0 0x40000f20 0 0xa8>, 1600 <0 0x40001000 0 0x1000>, 1601 <0 0x40100000 0 0x100000>; 1602 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1603 device_type = "pci"; 1604 linux,pci-domain = <1>; 1605 bus-range = <0x00 0xff>; 1606 num-lanes = <2>; 1607 1608 #address-cells = <3>; 1609 #size-cells = <2>; 1610 1611 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1612 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1613 1614 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1615 interrupt-names = "msi"; 1616 #interrupt-cells = <1>; 1617 interrupt-map-mask = <0 0 0 0x7>; 1618 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1619 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1620 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1621 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1622 1623 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1624 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1625 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1626 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1627 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1628 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1629 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1630 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1631 clock-names = "aux", 1632 "cfg", 1633 "bus_master", 1634 "bus_slave", 1635 "slave_q2a", 1636 "tbu", 1637 "ddrss_sf_tbu", 1638 "aggre1"; 1639 1640 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1641 <0x100 &apps_smmu 0x1c81 0x1>; 1642 1643 resets = <&gcc GCC_PCIE_1_BCR>; 1644 reset-names = "pci"; 1645 1646 power-domains = <&gcc PCIE_1_GDSC>; 1647 1648 phys = <&pcie1_phy>; 1649 phy-names = "pciephy"; 1650 1651 status = "disabled"; 1652 }; 1653 1654 pcie1_phy: phy@1c0e000 { 1655 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1656 reg = <0 0x01c0e000 0 0x2000>; 1657 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1658 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1659 <&gcc GCC_PCIE_1_CLKREF_EN>, 1660 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1661 <&gcc GCC_PCIE_1_PIPE_CLK>; 1662 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1663 1664 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1665 reset-names = "phy"; 1666 1667 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1668 assigned-clock-rates = <100000000>; 1669 1670 #clock-cells = <0>; 1671 clock-output-names = "pcie_1_pipe_clk"; 1672 1673 #phy-cells = <0>; 1674 1675 status = "disabled"; 1676 }; 1677 1678 ufs_mem_hc: ufshc@1d84000 { 1679 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1680 "jedec,ufs-2.0"; 1681 reg = <0 0x01d84000 0 0x3000>; 1682 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1683 phys = <&ufs_mem_phy>; 1684 phy-names = "ufsphy"; 1685 lanes-per-direction = <2>; 1686 #reset-cells = <1>; 1687 resets = <&gcc GCC_UFS_PHY_BCR>; 1688 reset-names = "rst"; 1689 1690 power-domains = <&gcc UFS_PHY_GDSC>; 1691 1692 iommus = <&apps_smmu 0xe0 0x0>; 1693 dma-coherent; 1694 1695 clock-names = 1696 "core_clk", 1697 "bus_aggr_clk", 1698 "iface_clk", 1699 "core_clk_unipro", 1700 "ref_clk", 1701 "tx_lane0_sync_clk", 1702 "rx_lane0_sync_clk", 1703 "rx_lane1_sync_clk"; 1704 clocks = 1705 <&gcc GCC_UFS_PHY_AXI_CLK>, 1706 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1707 <&gcc GCC_UFS_PHY_AHB_CLK>, 1708 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1709 <&rpmhcc RPMH_CXO_CLK>, 1710 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1711 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1712 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1713 freq-table-hz = 1714 <75000000 300000000>, 1715 <0 0>, 1716 <0 0>, 1717 <75000000 300000000>, 1718 <0 0>, 1719 <0 0>, 1720 <0 0>, 1721 <0 0>; 1722 status = "disabled"; 1723 }; 1724 1725 ufs_mem_phy: phy@1d87000 { 1726 compatible = "qcom,sm8350-qmp-ufs-phy"; 1727 reg = <0 0x01d87000 0 0x1000>; 1728 1729 clock-names = "ref", 1730 "ref_aux"; 1731 clocks = <&rpmhcc RPMH_CXO_CLK>, 1732 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1733 1734 resets = <&ufs_mem_hc 0>; 1735 reset-names = "ufsphy"; 1736 1737 #clock-cells = <1>; 1738 #phy-cells = <0>; 1739 1740 status = "disabled"; 1741 }; 1742 1743 cryptobam: dma-controller@1dc4000 { 1744 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1745 reg = <0 0x01dc4000 0 0x24000>; 1746 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1747 #dma-cells = <1>; 1748 qcom,ee = <0>; 1749 qcom,controlled-remotely; 1750 iommus = <&apps_smmu 0x594 0x0011>, 1751 <&apps_smmu 0x596 0x0011>; 1752 /* FIXME: Probing BAM DMA causes some abort and system hang */ 1753 status = "fail"; 1754 }; 1755 1756 crypto: crypto@1dfa000 { 1757 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1758 reg = <0 0x01dfa000 0 0x6000>; 1759 dmas = <&cryptobam 4>, <&cryptobam 5>; 1760 dma-names = "rx", "tx"; 1761 iommus = <&apps_smmu 0x594 0x0011>, 1762 <&apps_smmu 0x596 0x0011>; 1763 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1764 interconnect-names = "memory"; 1765 /* FIXME: dependency BAM DMA is disabled */ 1766 status = "disabled"; 1767 }; 1768 1769 ipa: ipa@1e40000 { 1770 compatible = "qcom,sm8350-ipa"; 1771 1772 iommus = <&apps_smmu 0x5c0 0x0>, 1773 <&apps_smmu 0x5c2 0x0>; 1774 reg = <0 0x01e40000 0 0x8000>, 1775 <0 0x01e50000 0 0x4b20>, 1776 <0 0x01e04000 0 0x23000>; 1777 reg-names = "ipa-reg", 1778 "ipa-shared", 1779 "gsi"; 1780 1781 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1782 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1783 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1784 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1785 interrupt-names = "ipa", 1786 "gsi", 1787 "ipa-clock-query", 1788 "ipa-setup-ready"; 1789 1790 clocks = <&rpmhcc RPMH_IPA_CLK>; 1791 clock-names = "core"; 1792 1793 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1794 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1795 interconnect-names = "memory", 1796 "config"; 1797 1798 qcom,qmp = <&aoss_qmp>; 1799 1800 qcom,smem-states = <&ipa_smp2p_out 0>, 1801 <&ipa_smp2p_out 1>; 1802 qcom,smem-state-names = "ipa-clock-enabled-valid", 1803 "ipa-clock-enabled"; 1804 1805 status = "disabled"; 1806 }; 1807 1808 tcsr_mutex: hwlock@1f40000 { 1809 compatible = "qcom,tcsr-mutex"; 1810 reg = <0x0 0x01f40000 0x0 0x40000>; 1811 #hwlock-cells = <1>; 1812 }; 1813 1814 tcsr: syscon@1fc0000 { 1815 compatible = "qcom,sm8350-tcsr", "syscon"; 1816 reg = <0x0 0x1fc0000 0x0 0x30000>; 1817 }; 1818 1819 lpass_tlmm: pinctrl@33c0000 { 1820 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 1821 reg = <0 0x033c0000 0 0x20000>, 1822 <0 0x03550000 0 0x10000>; 1823 1824 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1825 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1826 clock-names = "core", "audio"; 1827 1828 gpio-controller; 1829 #gpio-cells = <2>; 1830 gpio-ranges = <&lpass_tlmm 0 0 15>; 1831 }; 1832 1833 gpu: gpu@3d00000 { 1834 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1835 1836 reg = <0 0x03d00000 0 0x40000>, 1837 <0 0x03d9e000 0 0x1000>, 1838 <0 0x03d61000 0 0x800>; 1839 reg-names = "kgsl_3d0_reg_memory", 1840 "cx_mem", 1841 "cx_dbgc"; 1842 1843 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1844 1845 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1846 1847 operating-points-v2 = <&gpu_opp_table>; 1848 1849 qcom,gmu = <&gmu>; 1850 1851 status = "disabled"; 1852 1853 zap-shader { 1854 memory-region = <&pil_gpu_mem>; 1855 }; 1856 1857 /* note: downstream checks gpu binning for 670 Mhz */ 1858 gpu_opp_table: opp-table { 1859 compatible = "operating-points-v2"; 1860 1861 opp-840000000 { 1862 opp-hz = /bits/ 64 <840000000>; 1863 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1864 }; 1865 1866 opp-778000000 { 1867 opp-hz = /bits/ 64 <778000000>; 1868 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1869 }; 1870 1871 opp-738000000 { 1872 opp-hz = /bits/ 64 <738000000>; 1873 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1874 }; 1875 1876 opp-676000000 { 1877 opp-hz = /bits/ 64 <676000000>; 1878 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1879 }; 1880 1881 opp-608000000 { 1882 opp-hz = /bits/ 64 <608000000>; 1883 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1884 }; 1885 1886 opp-540000000 { 1887 opp-hz = /bits/ 64 <540000000>; 1888 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1889 }; 1890 1891 opp-491000000 { 1892 opp-hz = /bits/ 64 <491000000>; 1893 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1894 }; 1895 1896 opp-443000000 { 1897 opp-hz = /bits/ 64 <443000000>; 1898 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1899 }; 1900 1901 opp-379000000 { 1902 opp-hz = /bits/ 64 <379000000>; 1903 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1904 }; 1905 1906 opp-315000000 { 1907 opp-hz = /bits/ 64 <315000000>; 1908 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1909 }; 1910 }; 1911 }; 1912 1913 gmu: gmu@3d6a000 { 1914 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1915 1916 reg = <0 0x03d6a000 0 0x34000>, 1917 <0 0x03de0000 0 0x10000>, 1918 <0 0x0b290000 0 0x10000>; 1919 reg-names = "gmu", "rscc", "gmu_pdc"; 1920 1921 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1923 interrupt-names = "hfi", "gmu"; 1924 1925 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1926 <&gpucc GPU_CC_CXO_CLK>, 1927 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1928 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1929 <&gpucc GPU_CC_AHB_CLK>, 1930 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1931 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1932 clock-names = "gmu", 1933 "cxo", 1934 "axi", 1935 "memnoc", 1936 "ahb", 1937 "hub", 1938 "smmu_vote"; 1939 1940 power-domains = <&gpucc GPU_CX_GDSC>, 1941 <&gpucc GPU_GX_GDSC>; 1942 power-domain-names = "cx", 1943 "gx"; 1944 1945 iommus = <&adreno_smmu 5 0x400>; 1946 1947 operating-points-v2 = <&gmu_opp_table>; 1948 1949 gmu_opp_table: opp-table { 1950 compatible = "operating-points-v2"; 1951 1952 opp-200000000 { 1953 opp-hz = /bits/ 64 <200000000>; 1954 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1955 }; 1956 }; 1957 }; 1958 1959 gpucc: clock-controller@3d90000 { 1960 compatible = "qcom,sm8350-gpucc"; 1961 reg = <0 0x03d90000 0 0x9000>; 1962 clocks = <&rpmhcc RPMH_CXO_CLK>, 1963 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1964 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1965 clock-names = "bi_tcxo", 1966 "gcc_gpu_gpll0_clk_src", 1967 "gcc_gpu_gpll0_div_clk_src"; 1968 #clock-cells = <1>; 1969 #reset-cells = <1>; 1970 #power-domain-cells = <1>; 1971 }; 1972 1973 adreno_smmu: iommu@3da0000 { 1974 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1975 "qcom,smmu-500", "arm,mmu-500"; 1976 reg = <0 0x03da0000 0 0x20000>; 1977 #iommu-cells = <2>; 1978 #global-interrupts = <2>; 1979 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1991 1992 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1993 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1994 <&gpucc GPU_CC_AHB_CLK>, 1995 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1996 <&gpucc GPU_CC_CX_GMU_CLK>, 1997 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1998 <&gpucc GPU_CC_HUB_AON_CLK>; 1999 clock-names = "bus", 2000 "iface", 2001 "ahb", 2002 "hlos1_vote_gpu_smmu", 2003 "cx_gmu", 2004 "hub_cx_int", 2005 "hub_aon"; 2006 2007 power-domains = <&gpucc GPU_CX_GDSC>; 2008 dma-coherent; 2009 }; 2010 2011 lpass_ag_noc: interconnect@3c40000 { 2012 compatible = "qcom,sm8350-lpass-ag-noc"; 2013 reg = <0 0x03c40000 0 0xf080>; 2014 #interconnect-cells = <2>; 2015 qcom,bcm-voters = <&apps_bcm_voter>; 2016 }; 2017 2018 mpss: remoteproc@4080000 { 2019 compatible = "qcom,sm8350-mpss-pas"; 2020 reg = <0x0 0x04080000 0x0 0x4040>; 2021 2022 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2023 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2024 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2025 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2026 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2027 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2028 interrupt-names = "wdog", "fatal", "ready", "handover", 2029 "stop-ack", "shutdown-ack"; 2030 2031 clocks = <&rpmhcc RPMH_CXO_CLK>; 2032 clock-names = "xo"; 2033 2034 power-domains = <&rpmhpd RPMHPD_CX>, 2035 <&rpmhpd RPMHPD_MSS>; 2036 power-domain-names = "cx", "mss"; 2037 2038 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2039 2040 memory-region = <&pil_modem_mem>; 2041 2042 qcom,qmp = <&aoss_qmp>; 2043 2044 qcom,smem-states = <&smp2p_modem_out 0>; 2045 qcom,smem-state-names = "stop"; 2046 2047 status = "disabled"; 2048 2049 glink-edge { 2050 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2051 IPCC_MPROC_SIGNAL_GLINK_QMP 2052 IRQ_TYPE_EDGE_RISING>; 2053 mboxes = <&ipcc IPCC_CLIENT_MPSS 2054 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2055 label = "modem"; 2056 qcom,remote-pid = <1>; 2057 }; 2058 }; 2059 2060 slpi: remoteproc@5c00000 { 2061 compatible = "qcom,sm8350-slpi-pas"; 2062 reg = <0 0x05c00000 0 0x4000>; 2063 2064 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2065 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2066 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2067 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2068 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2069 interrupt-names = "wdog", "fatal", "ready", 2070 "handover", "stop-ack"; 2071 2072 clocks = <&rpmhcc RPMH_CXO_CLK>; 2073 clock-names = "xo"; 2074 2075 power-domains = <&rpmhpd RPMHPD_LCX>, 2076 <&rpmhpd RPMHPD_LMX>; 2077 power-domain-names = "lcx", "lmx"; 2078 2079 memory-region = <&pil_slpi_mem>; 2080 2081 qcom,qmp = <&aoss_qmp>; 2082 2083 qcom,smem-states = <&smp2p_slpi_out 0>; 2084 qcom,smem-state-names = "stop"; 2085 2086 status = "disabled"; 2087 2088 glink-edge { 2089 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2090 IPCC_MPROC_SIGNAL_GLINK_QMP 2091 IRQ_TYPE_EDGE_RISING>; 2092 mboxes = <&ipcc IPCC_CLIENT_SLPI 2093 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2094 2095 label = "slpi"; 2096 qcom,remote-pid = <3>; 2097 2098 fastrpc { 2099 compatible = "qcom,fastrpc"; 2100 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2101 label = "sdsp"; 2102 qcom,non-secure-domain; 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 compute-cb@1 { 2107 compatible = "qcom,fastrpc-compute-cb"; 2108 reg = <1>; 2109 iommus = <&apps_smmu 0x0541 0x0>; 2110 }; 2111 2112 compute-cb@2 { 2113 compatible = "qcom,fastrpc-compute-cb"; 2114 reg = <2>; 2115 iommus = <&apps_smmu 0x0542 0x0>; 2116 }; 2117 2118 compute-cb@3 { 2119 compatible = "qcom,fastrpc-compute-cb"; 2120 reg = <3>; 2121 iommus = <&apps_smmu 0x0543 0x0>; 2122 /* note: shared-cb = <4> in downstream */ 2123 }; 2124 }; 2125 }; 2126 }; 2127 2128 sdhc_2: mmc@8804000 { 2129 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2130 reg = <0 0x08804000 0 0x1000>; 2131 2132 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2134 interrupt-names = "hc_irq", "pwr_irq"; 2135 2136 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2137 <&gcc GCC_SDCC2_APPS_CLK>, 2138 <&rpmhcc RPMH_CXO_CLK>; 2139 clock-names = "iface", "core", "xo"; 2140 resets = <&gcc GCC_SDCC2_BCR>; 2141 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2143 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2144 iommus = <&apps_smmu 0x4a0 0x0>; 2145 power-domains = <&rpmhpd RPMHPD_CX>; 2146 operating-points-v2 = <&sdhc2_opp_table>; 2147 bus-width = <4>; 2148 dma-coherent; 2149 2150 status = "disabled"; 2151 2152 sdhc2_opp_table: opp-table { 2153 compatible = "operating-points-v2"; 2154 2155 opp-100000000 { 2156 opp-hz = /bits/ 64 <100000000>; 2157 required-opps = <&rpmhpd_opp_low_svs>; 2158 }; 2159 2160 opp-202000000 { 2161 opp-hz = /bits/ 64 <202000000>; 2162 required-opps = <&rpmhpd_opp_svs_l1>; 2163 }; 2164 }; 2165 }; 2166 2167 usb_1_hsphy: phy@88e3000 { 2168 compatible = "qcom,sm8350-usb-hs-phy", 2169 "qcom,usb-snps-hs-7nm-phy"; 2170 reg = <0 0x088e3000 0 0x400>; 2171 status = "disabled"; 2172 #phy-cells = <0>; 2173 2174 clocks = <&rpmhcc RPMH_CXO_CLK>; 2175 clock-names = "ref"; 2176 2177 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2178 }; 2179 2180 usb_2_hsphy: phy@88e4000 { 2181 compatible = "qcom,sm8250-usb-hs-phy", 2182 "qcom,usb-snps-hs-7nm-phy"; 2183 reg = <0 0x088e4000 0 0x400>; 2184 status = "disabled"; 2185 #phy-cells = <0>; 2186 2187 clocks = <&rpmhcc RPMH_CXO_CLK>; 2188 clock-names = "ref"; 2189 2190 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2191 }; 2192 2193 usb_1_qmpphy: phy@88e8000 { 2194 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2195 reg = <0 0x088e8000 0 0x3000>; 2196 2197 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2198 <&rpmhcc RPMH_CXO_CLK>, 2199 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2200 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2201 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2202 2203 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2204 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2205 reset-names = "phy", "common"; 2206 2207 #clock-cells = <1>; 2208 #phy-cells = <1>; 2209 2210 status = "disabled"; 2211 2212 ports { 2213 #address-cells = <1>; 2214 #size-cells = <0>; 2215 2216 port@0 { 2217 reg = <0>; 2218 2219 usb_1_qmpphy_out: endpoint { 2220 }; 2221 }; 2222 2223 port@1 { 2224 reg = <1>; 2225 2226 usb_1_qmpphy_usb_ss_in: endpoint { 2227 }; 2228 }; 2229 2230 port@2 { 2231 reg = <2>; 2232 2233 usb_1_qmpphy_dp_in: endpoint { 2234 }; 2235 }; 2236 }; 2237 }; 2238 2239 usb_2_qmpphy: phy@88eb000 { 2240 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2241 reg = <0 0x088eb000 0 0x2000>; 2242 status = "disabled"; 2243 2244 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2245 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2246 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2247 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2248 clock-names = "aux", 2249 "ref", 2250 "com_aux", 2251 "pipe"; 2252 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2253 #clock-cells = <0>; 2254 #phy-cells = <0>; 2255 2256 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2257 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2258 reset-names = "phy", 2259 "phy_phy"; 2260 }; 2261 2262 dc_noc: interconnect@90c0000 { 2263 compatible = "qcom,sm8350-dc-noc"; 2264 reg = <0 0x090c0000 0 0x4200>; 2265 #interconnect-cells = <2>; 2266 qcom,bcm-voters = <&apps_bcm_voter>; 2267 }; 2268 2269 gem_noc: interconnect@9100000 { 2270 compatible = "qcom,sm8350-gem-noc"; 2271 reg = <0 0x09100000 0 0xb4000>; 2272 #interconnect-cells = <2>; 2273 qcom,bcm-voters = <&apps_bcm_voter>; 2274 }; 2275 2276 system-cache-controller@9200000 { 2277 compatible = "qcom,sm8350-llcc"; 2278 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2279 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2280 <0 0x09600000 0 0x58000>; 2281 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2282 "llcc3_base", "llcc_broadcast_base"; 2283 }; 2284 2285 compute_noc: interconnect@a0c0000 { 2286 compatible = "qcom,sm8350-compute-noc"; 2287 reg = <0 0x0a0c0000 0 0xa180>; 2288 #interconnect-cells = <2>; 2289 qcom,bcm-voters = <&apps_bcm_voter>; 2290 }; 2291 2292 usb_1: usb@a6f8800 { 2293 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2294 reg = <0 0x0a6f8800 0 0x400>; 2295 status = "disabled"; 2296 #address-cells = <2>; 2297 #size-cells = <2>; 2298 ranges; 2299 2300 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2301 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2302 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2303 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2304 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2305 clock-names = "cfg_noc", 2306 "core", 2307 "iface", 2308 "sleep", 2309 "mock_utmi"; 2310 2311 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2312 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2313 assigned-clock-rates = <19200000>, <200000000>; 2314 2315 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2316 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2317 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2318 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2319 interrupt-names = "hs_phy_irq", 2320 "ss_phy_irq", 2321 "dm_hs_phy_irq", 2322 "dp_hs_phy_irq"; 2323 2324 power-domains = <&gcc USB30_PRIM_GDSC>; 2325 2326 resets = <&gcc GCC_USB30_PRIM_BCR>; 2327 2328 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2329 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2330 interconnect-names = "usb-ddr", "apps-usb"; 2331 2332 usb_1_dwc3: usb@a600000 { 2333 compatible = "snps,dwc3"; 2334 reg = <0 0x0a600000 0 0xcd00>; 2335 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2336 iommus = <&apps_smmu 0x0 0x0>; 2337 snps,dis_u2_susphy_quirk; 2338 snps,dis_enblslpm_quirk; 2339 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2340 phy-names = "usb2-phy", "usb3-phy"; 2341 2342 ports { 2343 #address-cells = <1>; 2344 #size-cells = <0>; 2345 2346 port@0 { 2347 reg = <0>; 2348 2349 usb_1_dwc3_hs: endpoint { 2350 }; 2351 }; 2352 2353 port@1 { 2354 reg = <1>; 2355 2356 usb_1_dwc3_ss: endpoint { 2357 }; 2358 }; 2359 }; 2360 }; 2361 }; 2362 2363 usb_2: usb@a8f8800 { 2364 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2365 reg = <0 0x0a8f8800 0 0x400>; 2366 status = "disabled"; 2367 #address-cells = <2>; 2368 #size-cells = <2>; 2369 ranges; 2370 2371 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2372 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2373 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2374 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2375 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2376 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2377 clock-names = "cfg_noc", 2378 "core", 2379 "iface", 2380 "sleep", 2381 "mock_utmi", 2382 "xo"; 2383 2384 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2385 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2386 assigned-clock-rates = <19200000>, <200000000>; 2387 2388 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2389 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2390 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2391 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2392 interrupt-names = "hs_phy_irq", 2393 "ss_phy_irq", 2394 "dm_hs_phy_irq", 2395 "dp_hs_phy_irq"; 2396 2397 power-domains = <&gcc USB30_SEC_GDSC>; 2398 2399 resets = <&gcc GCC_USB30_SEC_BCR>; 2400 2401 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2402 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2403 interconnect-names = "usb-ddr", "apps-usb"; 2404 2405 usb_2_dwc3: usb@a800000 { 2406 compatible = "snps,dwc3"; 2407 reg = <0 0x0a800000 0 0xcd00>; 2408 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2409 iommus = <&apps_smmu 0x20 0x0>; 2410 snps,dis_u2_susphy_quirk; 2411 snps,dis_enblslpm_quirk; 2412 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2413 phy-names = "usb2-phy", "usb3-phy"; 2414 }; 2415 }; 2416 2417 mdss: display-subsystem@ae00000 { 2418 compatible = "qcom,sm8350-mdss"; 2419 reg = <0 0x0ae00000 0 0x1000>; 2420 reg-names = "mdss"; 2421 2422 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2423 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2424 interconnect-names = "mdp0-mem", "mdp1-mem"; 2425 2426 power-domains = <&dispcc MDSS_GDSC>; 2427 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2428 2429 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2430 <&gcc GCC_DISP_HF_AXI_CLK>, 2431 <&gcc GCC_DISP_SF_AXI_CLK>, 2432 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2433 clock-names = "iface", "bus", "nrt_bus", "core"; 2434 2435 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2436 interrupt-controller; 2437 #interrupt-cells = <1>; 2438 2439 iommus = <&apps_smmu 0x820 0x402>; 2440 2441 status = "disabled"; 2442 2443 #address-cells = <2>; 2444 #size-cells = <2>; 2445 ranges; 2446 2447 mdss_mdp: display-controller@ae01000 { 2448 compatible = "qcom,sm8350-dpu"; 2449 reg = <0 0x0ae01000 0 0x8f000>, 2450 <0 0x0aeb0000 0 0x2008>; 2451 reg-names = "mdp", "vbif"; 2452 2453 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2454 <&gcc GCC_DISP_SF_AXI_CLK>, 2455 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2456 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2457 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2458 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2459 clock-names = "bus", 2460 "nrt_bus", 2461 "iface", 2462 "lut", 2463 "core", 2464 "vsync"; 2465 2466 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2467 assigned-clock-rates = <19200000>; 2468 2469 operating-points-v2 = <&dpu_opp_table>; 2470 power-domains = <&rpmhpd RPMHPD_MMCX>; 2471 2472 interrupt-parent = <&mdss>; 2473 interrupts = <0>; 2474 2475 dpu_opp_table: opp-table { 2476 compatible = "operating-points-v2"; 2477 2478 /* TODO: opp-200000000 should work with 2479 * &rpmhpd_opp_low_svs, but one some of 2480 * sm8350_hdk boards reboot using this 2481 * opp. 2482 */ 2483 opp-200000000 { 2484 opp-hz = /bits/ 64 <200000000>; 2485 required-opps = <&rpmhpd_opp_svs>; 2486 }; 2487 2488 opp-300000000 { 2489 opp-hz = /bits/ 64 <300000000>; 2490 required-opps = <&rpmhpd_opp_svs>; 2491 }; 2492 2493 opp-345000000 { 2494 opp-hz = /bits/ 64 <345000000>; 2495 required-opps = <&rpmhpd_opp_svs_l1>; 2496 }; 2497 2498 opp-460000000 { 2499 opp-hz = /bits/ 64 <460000000>; 2500 required-opps = <&rpmhpd_opp_nom>; 2501 }; 2502 }; 2503 2504 ports { 2505 #address-cells = <1>; 2506 #size-cells = <0>; 2507 2508 port@0 { 2509 reg = <0>; 2510 dpu_intf1_out: endpoint { 2511 remote-endpoint = <&mdss_dsi0_in>; 2512 }; 2513 }; 2514 2515 port@1 { 2516 reg = <1>; 2517 dpu_intf2_out: endpoint { 2518 remote-endpoint = <&mdss_dsi1_in>; 2519 }; 2520 }; 2521 2522 port@2 { 2523 reg = <2>; 2524 dpu_intf0_out: endpoint { 2525 remote-endpoint = <&mdss_dp_in>; 2526 }; 2527 }; 2528 }; 2529 }; 2530 2531 mdss_dp: displayport-controller@ae90000 { 2532 compatible = "qcom,sm8350-dp"; 2533 reg = <0 0xae90000 0 0x200>, 2534 <0 0xae90200 0 0x200>, 2535 <0 0xae90400 0 0x600>, 2536 <0 0xae91000 0 0x400>, 2537 <0 0xae91400 0 0x400>; 2538 interrupt-parent = <&mdss>; 2539 interrupts = <12>; 2540 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2541 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2542 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2543 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2544 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2545 clock-names = "core_iface", 2546 "core_aux", 2547 "ctrl_link", 2548 "ctrl_link_iface", 2549 "stream_pixel"; 2550 2551 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2552 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2553 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2554 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2555 2556 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2557 phy-names = "dp"; 2558 2559 #sound-dai-cells = <0>; 2560 2561 operating-points-v2 = <&dp_opp_table>; 2562 power-domains = <&rpmhpd RPMHPD_MMCX>; 2563 2564 status = "disabled"; 2565 2566 ports { 2567 #address-cells = <1>; 2568 #size-cells = <0>; 2569 2570 port@0 { 2571 reg = <0>; 2572 mdss_dp_in: endpoint { 2573 remote-endpoint = <&dpu_intf0_out>; 2574 }; 2575 }; 2576 }; 2577 2578 dp_opp_table: opp-table { 2579 compatible = "operating-points-v2"; 2580 2581 opp-160000000 { 2582 opp-hz = /bits/ 64 <160000000>; 2583 required-opps = <&rpmhpd_opp_low_svs>; 2584 }; 2585 2586 opp-270000000 { 2587 opp-hz = /bits/ 64 <270000000>; 2588 required-opps = <&rpmhpd_opp_svs>; 2589 }; 2590 2591 opp-540000000 { 2592 opp-hz = /bits/ 64 <540000000>; 2593 required-opps = <&rpmhpd_opp_svs_l1>; 2594 }; 2595 2596 opp-810000000 { 2597 opp-hz = /bits/ 64 <810000000>; 2598 required-opps = <&rpmhpd_opp_nom>; 2599 }; 2600 }; 2601 }; 2602 2603 mdss_dsi0: dsi@ae94000 { 2604 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2605 reg = <0 0x0ae94000 0 0x400>; 2606 reg-names = "dsi_ctrl"; 2607 2608 interrupt-parent = <&mdss>; 2609 interrupts = <4>; 2610 2611 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2612 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2613 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2614 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2615 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2616 <&gcc GCC_DISP_HF_AXI_CLK>; 2617 clock-names = "byte", 2618 "byte_intf", 2619 "pixel", 2620 "core", 2621 "iface", 2622 "bus"; 2623 2624 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2625 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2626 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2627 <&mdss_dsi0_phy 1>; 2628 2629 operating-points-v2 = <&dsi0_opp_table>; 2630 power-domains = <&rpmhpd RPMHPD_MMCX>; 2631 2632 phys = <&mdss_dsi0_phy>; 2633 2634 #address-cells = <1>; 2635 #size-cells = <0>; 2636 2637 status = "disabled"; 2638 2639 dsi0_opp_table: opp-table { 2640 compatible = "operating-points-v2"; 2641 2642 /* TODO: opp-187500000 should work with 2643 * &rpmhpd_opp_low_svs, but one some of 2644 * sm8350_hdk boards reboot using this 2645 * opp. 2646 */ 2647 opp-187500000 { 2648 opp-hz = /bits/ 64 <187500000>; 2649 required-opps = <&rpmhpd_opp_svs>; 2650 }; 2651 2652 opp-300000000 { 2653 opp-hz = /bits/ 64 <300000000>; 2654 required-opps = <&rpmhpd_opp_svs>; 2655 }; 2656 2657 opp-358000000 { 2658 opp-hz = /bits/ 64 <358000000>; 2659 required-opps = <&rpmhpd_opp_svs_l1>; 2660 }; 2661 }; 2662 2663 ports { 2664 #address-cells = <1>; 2665 #size-cells = <0>; 2666 2667 port@0 { 2668 reg = <0>; 2669 mdss_dsi0_in: endpoint { 2670 remote-endpoint = <&dpu_intf1_out>; 2671 }; 2672 }; 2673 2674 port@1 { 2675 reg = <1>; 2676 mdss_dsi0_out: endpoint { 2677 }; 2678 }; 2679 }; 2680 }; 2681 2682 mdss_dsi0_phy: phy@ae94400 { 2683 compatible = "qcom,sm8350-dsi-phy-5nm"; 2684 reg = <0 0x0ae94400 0 0x200>, 2685 <0 0x0ae94600 0 0x280>, 2686 <0 0x0ae94900 0 0x27c>; 2687 reg-names = "dsi_phy", 2688 "dsi_phy_lane", 2689 "dsi_pll"; 2690 2691 #clock-cells = <1>; 2692 #phy-cells = <0>; 2693 2694 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2695 <&rpmhcc RPMH_CXO_CLK>; 2696 clock-names = "iface", "ref"; 2697 2698 status = "disabled"; 2699 }; 2700 2701 mdss_dsi1: dsi@ae96000 { 2702 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2703 reg = <0 0x0ae96000 0 0x400>; 2704 reg-names = "dsi_ctrl"; 2705 2706 interrupt-parent = <&mdss>; 2707 interrupts = <5>; 2708 2709 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2710 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2711 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2712 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2713 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2714 <&gcc GCC_DISP_HF_AXI_CLK>; 2715 clock-names = "byte", 2716 "byte_intf", 2717 "pixel", 2718 "core", 2719 "iface", 2720 "bus"; 2721 2722 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2723 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2724 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2725 <&mdss_dsi1_phy 1>; 2726 2727 operating-points-v2 = <&dsi1_opp_table>; 2728 power-domains = <&rpmhpd RPMHPD_MMCX>; 2729 2730 phys = <&mdss_dsi1_phy>; 2731 2732 #address-cells = <1>; 2733 #size-cells = <0>; 2734 2735 status = "disabled"; 2736 2737 dsi1_opp_table: opp-table { 2738 compatible = "operating-points-v2"; 2739 2740 /* TODO: opp-187500000 should work with 2741 * &rpmhpd_opp_low_svs, but one some of 2742 * sm8350_hdk boards reboot using this 2743 * opp. 2744 */ 2745 opp-187500000 { 2746 opp-hz = /bits/ 64 <187500000>; 2747 required-opps = <&rpmhpd_opp_svs>; 2748 }; 2749 2750 opp-300000000 { 2751 opp-hz = /bits/ 64 <300000000>; 2752 required-opps = <&rpmhpd_opp_svs>; 2753 }; 2754 2755 opp-358000000 { 2756 opp-hz = /bits/ 64 <358000000>; 2757 required-opps = <&rpmhpd_opp_svs_l1>; 2758 }; 2759 }; 2760 2761 ports { 2762 #address-cells = <1>; 2763 #size-cells = <0>; 2764 2765 port@0 { 2766 reg = <0>; 2767 mdss_dsi1_in: endpoint { 2768 remote-endpoint = <&dpu_intf2_out>; 2769 }; 2770 }; 2771 2772 port@1 { 2773 reg = <1>; 2774 mdss_dsi1_out: endpoint { 2775 }; 2776 }; 2777 }; 2778 }; 2779 2780 mdss_dsi1_phy: phy@ae96400 { 2781 compatible = "qcom,sm8350-dsi-phy-5nm"; 2782 reg = <0 0x0ae96400 0 0x200>, 2783 <0 0x0ae96600 0 0x280>, 2784 <0 0x0ae96900 0 0x27c>; 2785 reg-names = "dsi_phy", 2786 "dsi_phy_lane", 2787 "dsi_pll"; 2788 2789 #clock-cells = <1>; 2790 #phy-cells = <0>; 2791 2792 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2793 <&rpmhcc RPMH_CXO_CLK>; 2794 clock-names = "iface", "ref"; 2795 2796 status = "disabled"; 2797 }; 2798 }; 2799 2800 dispcc: clock-controller@af00000 { 2801 compatible = "qcom,sm8350-dispcc"; 2802 reg = <0 0x0af00000 0 0x10000>; 2803 clocks = <&rpmhcc RPMH_CXO_CLK>, 2804 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2805 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2806 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2807 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2808 clock-names = "bi_tcxo", 2809 "dsi0_phy_pll_out_byteclk", 2810 "dsi0_phy_pll_out_dsiclk", 2811 "dsi1_phy_pll_out_byteclk", 2812 "dsi1_phy_pll_out_dsiclk", 2813 "dp_phy_pll_link_clk", 2814 "dp_phy_pll_vco_div_clk"; 2815 #clock-cells = <1>; 2816 #reset-cells = <1>; 2817 #power-domain-cells = <1>; 2818 2819 power-domains = <&rpmhpd RPMHPD_MMCX>; 2820 }; 2821 2822 pdc: interrupt-controller@b220000 { 2823 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2824 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2825 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2826 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2827 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2828 <156 716 12>; 2829 #interrupt-cells = <2>; 2830 interrupt-parent = <&intc>; 2831 interrupt-controller; 2832 }; 2833 2834 tsens0: thermal-sensor@c263000 { 2835 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2836 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2837 <0 0x0c222000 0 0x8>; /* SROT */ 2838 #qcom,sensors = <15>; 2839 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2840 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2841 interrupt-names = "uplow", "critical"; 2842 #thermal-sensor-cells = <1>; 2843 }; 2844 2845 tsens1: thermal-sensor@c265000 { 2846 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2847 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2848 <0 0x0c223000 0 0x8>; /* SROT */ 2849 #qcom,sensors = <14>; 2850 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2851 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2852 interrupt-names = "uplow", "critical"; 2853 #thermal-sensor-cells = <1>; 2854 }; 2855 2856 aoss_qmp: power-management@c300000 { 2857 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2858 reg = <0 0x0c300000 0 0x400>; 2859 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2860 IRQ_TYPE_EDGE_RISING>; 2861 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2862 2863 #clock-cells = <0>; 2864 }; 2865 2866 sram@c3f0000 { 2867 compatible = "qcom,rpmh-stats"; 2868 reg = <0 0x0c3f0000 0 0x400>; 2869 }; 2870 2871 spmi_bus: spmi@c440000 { 2872 compatible = "qcom,spmi-pmic-arb"; 2873 reg = <0x0 0x0c440000 0x0 0x1100>, 2874 <0x0 0x0c600000 0x0 0x2000000>, 2875 <0x0 0x0e600000 0x0 0x100000>, 2876 <0x0 0x0e700000 0x0 0xa0000>, 2877 <0x0 0x0c40a000 0x0 0x26000>; 2878 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2879 interrupt-names = "periph_irq"; 2880 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2881 qcom,ee = <0>; 2882 qcom,channel = <0>; 2883 #address-cells = <2>; 2884 #size-cells = <0>; 2885 interrupt-controller; 2886 #interrupt-cells = <4>; 2887 }; 2888 2889 tlmm: pinctrl@f100000 { 2890 compatible = "qcom,sm8350-tlmm"; 2891 reg = <0 0x0f100000 0 0x300000>; 2892 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2893 gpio-controller; 2894 #gpio-cells = <2>; 2895 interrupt-controller; 2896 #interrupt-cells = <2>; 2897 gpio-ranges = <&tlmm 0 0 204>; 2898 wakeup-parent = <&pdc>; 2899 2900 sdc2_default_state: sdc2-default-state { 2901 clk-pins { 2902 pins = "sdc2_clk"; 2903 drive-strength = <16>; 2904 bias-disable; 2905 }; 2906 2907 cmd-pins { 2908 pins = "sdc2_cmd"; 2909 drive-strength = <16>; 2910 bias-pull-up; 2911 }; 2912 2913 data-pins { 2914 pins = "sdc2_data"; 2915 drive-strength = <16>; 2916 bias-pull-up; 2917 }; 2918 }; 2919 2920 sdc2_sleep_state: sdc2-sleep-state { 2921 clk-pins { 2922 pins = "sdc2_clk"; 2923 drive-strength = <2>; 2924 bias-disable; 2925 }; 2926 2927 cmd-pins { 2928 pins = "sdc2_cmd"; 2929 drive-strength = <2>; 2930 bias-pull-up; 2931 }; 2932 2933 data-pins { 2934 pins = "sdc2_data"; 2935 drive-strength = <2>; 2936 bias-pull-up; 2937 }; 2938 }; 2939 2940 qup_uart3_default_state: qup-uart3-default-state { 2941 rx-pins { 2942 pins = "gpio18"; 2943 function = "qup3"; 2944 }; 2945 tx-pins { 2946 pins = "gpio19"; 2947 function = "qup3"; 2948 }; 2949 }; 2950 2951 qup_uart6_default: qup-uart6-default-state { 2952 pins = "gpio30", "gpio31"; 2953 function = "qup6"; 2954 drive-strength = <2>; 2955 bias-disable; 2956 }; 2957 2958 qup_uart18_default: qup-uart18-default-state { 2959 pins = "gpio68", "gpio69"; 2960 function = "qup18"; 2961 drive-strength = <2>; 2962 bias-disable; 2963 }; 2964 2965 qup_i2c0_default: qup-i2c0-default-state { 2966 pins = "gpio4", "gpio5"; 2967 function = "qup0"; 2968 drive-strength = <2>; 2969 bias-pull-up; 2970 }; 2971 2972 qup_i2c1_default: qup-i2c1-default-state { 2973 pins = "gpio8", "gpio9"; 2974 function = "qup1"; 2975 drive-strength = <2>; 2976 bias-pull-up; 2977 }; 2978 2979 qup_i2c2_default: qup-i2c2-default-state { 2980 pins = "gpio12", "gpio13"; 2981 function = "qup2"; 2982 drive-strength = <2>; 2983 bias-pull-up; 2984 }; 2985 2986 qup_i2c4_default: qup-i2c4-default-state { 2987 pins = "gpio20", "gpio21"; 2988 function = "qup4"; 2989 drive-strength = <2>; 2990 bias-pull-up; 2991 }; 2992 2993 qup_i2c5_default: qup-i2c5-default-state { 2994 pins = "gpio24", "gpio25"; 2995 function = "qup5"; 2996 drive-strength = <2>; 2997 bias-pull-up; 2998 }; 2999 3000 qup_i2c6_default: qup-i2c6-default-state { 3001 pins = "gpio28", "gpio29"; 3002 function = "qup6"; 3003 drive-strength = <2>; 3004 bias-pull-up; 3005 }; 3006 3007 qup_i2c7_default: qup-i2c7-default-state { 3008 pins = "gpio32", "gpio33"; 3009 function = "qup7"; 3010 drive-strength = <2>; 3011 bias-disable; 3012 }; 3013 3014 qup_i2c8_default: qup-i2c8-default-state { 3015 pins = "gpio36", "gpio37"; 3016 function = "qup8"; 3017 drive-strength = <2>; 3018 bias-pull-up; 3019 }; 3020 3021 qup_i2c9_default: qup-i2c9-default-state { 3022 pins = "gpio40", "gpio41"; 3023 function = "qup9"; 3024 drive-strength = <2>; 3025 bias-pull-up; 3026 }; 3027 3028 qup_i2c10_default: qup-i2c10-default-state { 3029 pins = "gpio44", "gpio45"; 3030 function = "qup10"; 3031 drive-strength = <2>; 3032 bias-pull-up; 3033 }; 3034 3035 qup_i2c11_default: qup-i2c11-default-state { 3036 pins = "gpio48", "gpio49"; 3037 function = "qup11"; 3038 drive-strength = <2>; 3039 bias-pull-up; 3040 }; 3041 3042 qup_i2c12_default: qup-i2c12-default-state { 3043 pins = "gpio52", "gpio53"; 3044 function = "qup12"; 3045 drive-strength = <2>; 3046 bias-pull-up; 3047 }; 3048 3049 qup_i2c13_default: qup-i2c13-default-state { 3050 pins = "gpio0", "gpio1"; 3051 function = "qup13"; 3052 drive-strength = <2>; 3053 bias-pull-up; 3054 }; 3055 3056 qup_i2c14_default: qup-i2c14-default-state { 3057 pins = "gpio56", "gpio57"; 3058 function = "qup14"; 3059 drive-strength = <2>; 3060 bias-disable; 3061 }; 3062 3063 qup_i2c15_default: qup-i2c15-default-state { 3064 pins = "gpio60", "gpio61"; 3065 function = "qup15"; 3066 drive-strength = <2>; 3067 bias-disable; 3068 }; 3069 3070 qup_i2c16_default: qup-i2c16-default-state { 3071 pins = "gpio64", "gpio65"; 3072 function = "qup16"; 3073 drive-strength = <2>; 3074 bias-disable; 3075 }; 3076 3077 qup_i2c17_default: qup-i2c17-default-state { 3078 pins = "gpio72", "gpio73"; 3079 function = "qup17"; 3080 drive-strength = <2>; 3081 bias-disable; 3082 }; 3083 3084 qup_i2c19_default: qup-i2c19-default-state { 3085 pins = "gpio76", "gpio77"; 3086 function = "qup19"; 3087 drive-strength = <2>; 3088 bias-disable; 3089 }; 3090 }; 3091 3092 apps_smmu: iommu@15000000 { 3093 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3094 reg = <0 0x15000000 0 0x100000>; 3095 #iommu-cells = <2>; 3096 #global-interrupts = <2>; 3097 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3195 }; 3196 3197 adsp: remoteproc@17300000 { 3198 compatible = "qcom,sm8350-adsp-pas"; 3199 reg = <0 0x17300000 0 0x100>; 3200 3201 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3202 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3203 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3204 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3205 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3206 interrupt-names = "wdog", "fatal", "ready", 3207 "handover", "stop-ack"; 3208 3209 clocks = <&rpmhcc RPMH_CXO_CLK>; 3210 clock-names = "xo"; 3211 3212 power-domains = <&rpmhpd RPMHPD_LCX>, 3213 <&rpmhpd RPMHPD_LMX>; 3214 power-domain-names = "lcx", "lmx"; 3215 3216 memory-region = <&pil_adsp_mem>; 3217 3218 qcom,qmp = <&aoss_qmp>; 3219 3220 qcom,smem-states = <&smp2p_adsp_out 0>; 3221 qcom,smem-state-names = "stop"; 3222 3223 status = "disabled"; 3224 3225 glink-edge { 3226 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3227 IPCC_MPROC_SIGNAL_GLINK_QMP 3228 IRQ_TYPE_EDGE_RISING>; 3229 mboxes = <&ipcc IPCC_CLIENT_LPASS 3230 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3231 3232 label = "lpass"; 3233 qcom,remote-pid = <2>; 3234 3235 apr { 3236 compatible = "qcom,apr-v2"; 3237 qcom,glink-channels = "apr_audio_svc"; 3238 qcom,domain = <APR_DOMAIN_ADSP>; 3239 #address-cells = <1>; 3240 #size-cells = <0>; 3241 3242 service@3 { 3243 reg = <APR_SVC_ADSP_CORE>; 3244 compatible = "qcom,q6core"; 3245 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3246 }; 3247 3248 q6afe: service@4 { 3249 compatible = "qcom,q6afe"; 3250 reg = <APR_SVC_AFE>; 3251 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3252 3253 q6afedai: dais { 3254 compatible = "qcom,q6afe-dais"; 3255 #address-cells = <1>; 3256 #size-cells = <0>; 3257 #sound-dai-cells = <1>; 3258 }; 3259 3260 q6afecc: clock-controller { 3261 compatible = "qcom,q6afe-clocks"; 3262 #clock-cells = <2>; 3263 }; 3264 }; 3265 3266 q6asm: service@7 { 3267 compatible = "qcom,q6asm"; 3268 reg = <APR_SVC_ASM>; 3269 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3270 3271 q6asmdai: dais { 3272 compatible = "qcom,q6asm-dais"; 3273 #address-cells = <1>; 3274 #size-cells = <0>; 3275 #sound-dai-cells = <1>; 3276 iommus = <&apps_smmu 0x1801 0x0>; 3277 3278 dai@0 { 3279 reg = <0>; 3280 }; 3281 3282 dai@1 { 3283 reg = <1>; 3284 }; 3285 3286 dai@2 { 3287 reg = <2>; 3288 }; 3289 }; 3290 }; 3291 3292 q6adm: service@8 { 3293 compatible = "qcom,q6adm"; 3294 reg = <APR_SVC_ADM>; 3295 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3296 3297 q6routing: routing { 3298 compatible = "qcom,q6adm-routing"; 3299 #sound-dai-cells = <0>; 3300 }; 3301 }; 3302 }; 3303 3304 fastrpc { 3305 compatible = "qcom,fastrpc"; 3306 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3307 label = "adsp"; 3308 qcom,non-secure-domain; 3309 #address-cells = <1>; 3310 #size-cells = <0>; 3311 3312 compute-cb@3 { 3313 compatible = "qcom,fastrpc-compute-cb"; 3314 reg = <3>; 3315 iommus = <&apps_smmu 0x1803 0x0>; 3316 }; 3317 3318 compute-cb@4 { 3319 compatible = "qcom,fastrpc-compute-cb"; 3320 reg = <4>; 3321 iommus = <&apps_smmu 0x1804 0x0>; 3322 }; 3323 3324 compute-cb@5 { 3325 compatible = "qcom,fastrpc-compute-cb"; 3326 reg = <5>; 3327 iommus = <&apps_smmu 0x1805 0x0>; 3328 }; 3329 }; 3330 }; 3331 }; 3332 3333 intc: interrupt-controller@17a00000 { 3334 compatible = "arm,gic-v3"; 3335 #interrupt-cells = <3>; 3336 interrupt-controller; 3337 #redistributor-regions = <1>; 3338 redistributor-stride = <0 0x20000>; 3339 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3340 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3341 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3342 }; 3343 3344 timer@17c20000 { 3345 compatible = "arm,armv7-timer-mem"; 3346 #address-cells = <1>; 3347 #size-cells = <1>; 3348 ranges = <0 0 0 0x20000000>; 3349 reg = <0x0 0x17c20000 0x0 0x1000>; 3350 clock-frequency = <19200000>; 3351 3352 frame@17c21000 { 3353 frame-number = <0>; 3354 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3356 reg = <0x17c21000 0x1000>, 3357 <0x17c22000 0x1000>; 3358 }; 3359 3360 frame@17c23000 { 3361 frame-number = <1>; 3362 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3363 reg = <0x17c23000 0x1000>; 3364 status = "disabled"; 3365 }; 3366 3367 frame@17c25000 { 3368 frame-number = <2>; 3369 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3370 reg = <0x17c25000 0x1000>; 3371 status = "disabled"; 3372 }; 3373 3374 frame@17c27000 { 3375 frame-number = <3>; 3376 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3377 reg = <0x17c27000 0x1000>; 3378 status = "disabled"; 3379 }; 3380 3381 frame@17c29000 { 3382 frame-number = <4>; 3383 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3384 reg = <0x17c29000 0x1000>; 3385 status = "disabled"; 3386 }; 3387 3388 frame@17c2b000 { 3389 frame-number = <5>; 3390 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3391 reg = <0x17c2b000 0x1000>; 3392 status = "disabled"; 3393 }; 3394 3395 frame@17c2d000 { 3396 frame-number = <6>; 3397 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3398 reg = <0x17c2d000 0x1000>; 3399 status = "disabled"; 3400 }; 3401 }; 3402 3403 apps_rsc: rsc@18200000 { 3404 label = "apps_rsc"; 3405 compatible = "qcom,rpmh-rsc"; 3406 reg = <0x0 0x18200000 0x0 0x10000>, 3407 <0x0 0x18210000 0x0 0x10000>, 3408 <0x0 0x18220000 0x0 0x10000>; 3409 reg-names = "drv-0", "drv-1", "drv-2"; 3410 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3413 qcom,tcs-offset = <0xd00>; 3414 qcom,drv-id = <2>; 3415 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3416 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3417 power-domains = <&CLUSTER_PD>; 3418 3419 rpmhcc: clock-controller { 3420 compatible = "qcom,sm8350-rpmh-clk"; 3421 #clock-cells = <1>; 3422 clock-names = "xo"; 3423 clocks = <&xo_board>; 3424 }; 3425 3426 rpmhpd: power-controller { 3427 compatible = "qcom,sm8350-rpmhpd"; 3428 #power-domain-cells = <1>; 3429 operating-points-v2 = <&rpmhpd_opp_table>; 3430 3431 rpmhpd_opp_table: opp-table { 3432 compatible = "operating-points-v2"; 3433 3434 rpmhpd_opp_ret: opp1 { 3435 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3436 }; 3437 3438 rpmhpd_opp_min_svs: opp2 { 3439 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3440 }; 3441 3442 rpmhpd_opp_low_svs: opp3 { 3443 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3444 }; 3445 3446 rpmhpd_opp_svs: opp4 { 3447 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3448 }; 3449 3450 rpmhpd_opp_svs_l1: opp5 { 3451 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3452 }; 3453 3454 rpmhpd_opp_nom: opp6 { 3455 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3456 }; 3457 3458 rpmhpd_opp_nom_l1: opp7 { 3459 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3460 }; 3461 3462 rpmhpd_opp_nom_l2: opp8 { 3463 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3464 }; 3465 3466 rpmhpd_opp_turbo: opp9 { 3467 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3468 }; 3469 3470 rpmhpd_opp_turbo_l1: opp10 { 3471 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3472 }; 3473 }; 3474 }; 3475 3476 apps_bcm_voter: bcm-voter { 3477 compatible = "qcom,bcm-voter"; 3478 }; 3479 }; 3480 3481 cpufreq_hw: cpufreq@18591000 { 3482 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3483 reg = <0 0x18591000 0 0x1000>, 3484 <0 0x18592000 0 0x1000>, 3485 <0 0x18593000 0 0x1000>; 3486 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3487 3488 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3491 interrupt-names = "dcvsh-irq-0", 3492 "dcvsh-irq-1", 3493 "dcvsh-irq-2"; 3494 3495 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3496 clock-names = "xo", "alternate"; 3497 3498 #freq-domain-cells = <1>; 3499 #clock-cells = <1>; 3500 }; 3501 3502 cdsp: remoteproc@98900000 { 3503 compatible = "qcom,sm8350-cdsp-pas"; 3504 reg = <0 0x98900000 0 0x1400000>; 3505 3506 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3507 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3508 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3509 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3510 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3511 interrupt-names = "wdog", "fatal", "ready", 3512 "handover", "stop-ack"; 3513 3514 clocks = <&rpmhcc RPMH_CXO_CLK>; 3515 clock-names = "xo"; 3516 3517 power-domains = <&rpmhpd RPMHPD_CX>, 3518 <&rpmhpd RPMHPD_MXC>; 3519 power-domain-names = "cx", "mxc"; 3520 3521 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3522 3523 memory-region = <&pil_cdsp_mem>; 3524 3525 qcom,qmp = <&aoss_qmp>; 3526 3527 qcom,smem-states = <&smp2p_cdsp_out 0>; 3528 qcom,smem-state-names = "stop"; 3529 3530 status = "disabled"; 3531 3532 glink-edge { 3533 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3534 IPCC_MPROC_SIGNAL_GLINK_QMP 3535 IRQ_TYPE_EDGE_RISING>; 3536 mboxes = <&ipcc IPCC_CLIENT_CDSP 3537 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3538 3539 label = "cdsp"; 3540 qcom,remote-pid = <5>; 3541 3542 fastrpc { 3543 compatible = "qcom,fastrpc"; 3544 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3545 label = "cdsp"; 3546 qcom,non-secure-domain; 3547 #address-cells = <1>; 3548 #size-cells = <0>; 3549 3550 compute-cb@1 { 3551 compatible = "qcom,fastrpc-compute-cb"; 3552 reg = <1>; 3553 iommus = <&apps_smmu 0x2161 0x0400>, 3554 <&apps_smmu 0x1181 0x0420>; 3555 }; 3556 3557 compute-cb@2 { 3558 compatible = "qcom,fastrpc-compute-cb"; 3559 reg = <2>; 3560 iommus = <&apps_smmu 0x2162 0x0400>, 3561 <&apps_smmu 0x1182 0x0420>; 3562 }; 3563 3564 compute-cb@3 { 3565 compatible = "qcom,fastrpc-compute-cb"; 3566 reg = <3>; 3567 iommus = <&apps_smmu 0x2163 0x0400>, 3568 <&apps_smmu 0x1183 0x0420>; 3569 }; 3570 3571 compute-cb@4 { 3572 compatible = "qcom,fastrpc-compute-cb"; 3573 reg = <4>; 3574 iommus = <&apps_smmu 0x2164 0x0400>, 3575 <&apps_smmu 0x1184 0x0420>; 3576 }; 3577 3578 compute-cb@5 { 3579 compatible = "qcom,fastrpc-compute-cb"; 3580 reg = <5>; 3581 iommus = <&apps_smmu 0x2165 0x0400>, 3582 <&apps_smmu 0x1185 0x0420>; 3583 }; 3584 3585 compute-cb@6 { 3586 compatible = "qcom,fastrpc-compute-cb"; 3587 reg = <6>; 3588 iommus = <&apps_smmu 0x2166 0x0400>, 3589 <&apps_smmu 0x1186 0x0420>; 3590 }; 3591 3592 compute-cb@7 { 3593 compatible = "qcom,fastrpc-compute-cb"; 3594 reg = <7>; 3595 iommus = <&apps_smmu 0x2167 0x0400>, 3596 <&apps_smmu 0x1187 0x0420>; 3597 }; 3598 3599 compute-cb@8 { 3600 compatible = "qcom,fastrpc-compute-cb"; 3601 reg = <8>; 3602 iommus = <&apps_smmu 0x2168 0x0400>, 3603 <&apps_smmu 0x1188 0x0420>; 3604 }; 3605 3606 /* note: secure cb9 in downstream */ 3607 }; 3608 }; 3609 }; 3610 }; 3611 3612 thermal_zones: thermal-zones { 3613 cpu0-thermal { 3614 polling-delay-passive = <250>; 3615 polling-delay = <1000>; 3616 3617 thermal-sensors = <&tsens0 1>; 3618 3619 trips { 3620 cpu0_alert0: trip-point0 { 3621 temperature = <90000>; 3622 hysteresis = <2000>; 3623 type = "passive"; 3624 }; 3625 3626 cpu0_alert1: trip-point1 { 3627 temperature = <95000>; 3628 hysteresis = <2000>; 3629 type = "passive"; 3630 }; 3631 3632 cpu0_crit: cpu-crit { 3633 temperature = <110000>; 3634 hysteresis = <1000>; 3635 type = "critical"; 3636 }; 3637 }; 3638 3639 cooling-maps { 3640 map0 { 3641 trip = <&cpu0_alert0>; 3642 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3643 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3644 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3645 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3646 }; 3647 map1 { 3648 trip = <&cpu0_alert1>; 3649 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3650 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3651 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3652 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3653 }; 3654 }; 3655 }; 3656 3657 cpu1-thermal { 3658 polling-delay-passive = <250>; 3659 polling-delay = <1000>; 3660 3661 thermal-sensors = <&tsens0 2>; 3662 3663 trips { 3664 cpu1_alert0: trip-point0 { 3665 temperature = <90000>; 3666 hysteresis = <2000>; 3667 type = "passive"; 3668 }; 3669 3670 cpu1_alert1: trip-point1 { 3671 temperature = <95000>; 3672 hysteresis = <2000>; 3673 type = "passive"; 3674 }; 3675 3676 cpu1_crit: cpu-crit { 3677 temperature = <110000>; 3678 hysteresis = <1000>; 3679 type = "critical"; 3680 }; 3681 }; 3682 3683 cooling-maps { 3684 map0 { 3685 trip = <&cpu1_alert0>; 3686 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3687 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3688 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3689 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3690 }; 3691 map1 { 3692 trip = <&cpu1_alert1>; 3693 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3694 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3695 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3696 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3697 }; 3698 }; 3699 }; 3700 3701 cpu2-thermal { 3702 polling-delay-passive = <250>; 3703 polling-delay = <1000>; 3704 3705 thermal-sensors = <&tsens0 3>; 3706 3707 trips { 3708 cpu2_alert0: trip-point0 { 3709 temperature = <90000>; 3710 hysteresis = <2000>; 3711 type = "passive"; 3712 }; 3713 3714 cpu2_alert1: trip-point1 { 3715 temperature = <95000>; 3716 hysteresis = <2000>; 3717 type = "passive"; 3718 }; 3719 3720 cpu2_crit: cpu-crit { 3721 temperature = <110000>; 3722 hysteresis = <1000>; 3723 type = "critical"; 3724 }; 3725 }; 3726 3727 cooling-maps { 3728 map0 { 3729 trip = <&cpu2_alert0>; 3730 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3731 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3732 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3733 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3734 }; 3735 map1 { 3736 trip = <&cpu2_alert1>; 3737 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3738 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3739 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3740 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3741 }; 3742 }; 3743 }; 3744 3745 cpu3-thermal { 3746 polling-delay-passive = <250>; 3747 polling-delay = <1000>; 3748 3749 thermal-sensors = <&tsens0 4>; 3750 3751 trips { 3752 cpu3_alert0: trip-point0 { 3753 temperature = <90000>; 3754 hysteresis = <2000>; 3755 type = "passive"; 3756 }; 3757 3758 cpu3_alert1: trip-point1 { 3759 temperature = <95000>; 3760 hysteresis = <2000>; 3761 type = "passive"; 3762 }; 3763 3764 cpu3_crit: cpu-crit { 3765 temperature = <110000>; 3766 hysteresis = <1000>; 3767 type = "critical"; 3768 }; 3769 }; 3770 3771 cooling-maps { 3772 map0 { 3773 trip = <&cpu3_alert0>; 3774 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3776 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3777 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3778 }; 3779 map1 { 3780 trip = <&cpu3_alert1>; 3781 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3782 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3783 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3785 }; 3786 }; 3787 }; 3788 3789 cpu4-top-thermal { 3790 polling-delay-passive = <250>; 3791 polling-delay = <1000>; 3792 3793 thermal-sensors = <&tsens0 7>; 3794 3795 trips { 3796 cpu4_top_alert0: trip-point0 { 3797 temperature = <90000>; 3798 hysteresis = <2000>; 3799 type = "passive"; 3800 }; 3801 3802 cpu4_top_alert1: trip-point1 { 3803 temperature = <95000>; 3804 hysteresis = <2000>; 3805 type = "passive"; 3806 }; 3807 3808 cpu4_top_crit: cpu-crit { 3809 temperature = <110000>; 3810 hysteresis = <1000>; 3811 type = "critical"; 3812 }; 3813 }; 3814 3815 cooling-maps { 3816 map0 { 3817 trip = <&cpu4_top_alert0>; 3818 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3819 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3820 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3821 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3822 }; 3823 map1 { 3824 trip = <&cpu4_top_alert1>; 3825 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3826 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3827 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3828 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3829 }; 3830 }; 3831 }; 3832 3833 cpu5-top-thermal { 3834 polling-delay-passive = <250>; 3835 polling-delay = <1000>; 3836 3837 thermal-sensors = <&tsens0 8>; 3838 3839 trips { 3840 cpu5_top_alert0: trip-point0 { 3841 temperature = <90000>; 3842 hysteresis = <2000>; 3843 type = "passive"; 3844 }; 3845 3846 cpu5_top_alert1: trip-point1 { 3847 temperature = <95000>; 3848 hysteresis = <2000>; 3849 type = "passive"; 3850 }; 3851 3852 cpu5_top_crit: cpu-crit { 3853 temperature = <110000>; 3854 hysteresis = <1000>; 3855 type = "critical"; 3856 }; 3857 }; 3858 3859 cooling-maps { 3860 map0 { 3861 trip = <&cpu5_top_alert0>; 3862 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3863 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3864 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3865 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3866 }; 3867 map1 { 3868 trip = <&cpu5_top_alert1>; 3869 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3870 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3873 }; 3874 }; 3875 }; 3876 3877 cpu6-top-thermal { 3878 polling-delay-passive = <250>; 3879 polling-delay = <1000>; 3880 3881 thermal-sensors = <&tsens0 9>; 3882 3883 trips { 3884 cpu6_top_alert0: trip-point0 { 3885 temperature = <90000>; 3886 hysteresis = <2000>; 3887 type = "passive"; 3888 }; 3889 3890 cpu6_top_alert1: trip-point1 { 3891 temperature = <95000>; 3892 hysteresis = <2000>; 3893 type = "passive"; 3894 }; 3895 3896 cpu6_top_crit: cpu-crit { 3897 temperature = <110000>; 3898 hysteresis = <1000>; 3899 type = "critical"; 3900 }; 3901 }; 3902 3903 cooling-maps { 3904 map0 { 3905 trip = <&cpu6_top_alert0>; 3906 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3907 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3908 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3909 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3910 }; 3911 map1 { 3912 trip = <&cpu6_top_alert1>; 3913 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3914 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3915 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3916 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3917 }; 3918 }; 3919 }; 3920 3921 cpu7-top-thermal { 3922 polling-delay-passive = <250>; 3923 polling-delay = <1000>; 3924 3925 thermal-sensors = <&tsens0 10>; 3926 3927 trips { 3928 cpu7_top_alert0: trip-point0 { 3929 temperature = <90000>; 3930 hysteresis = <2000>; 3931 type = "passive"; 3932 }; 3933 3934 cpu7_top_alert1: trip-point1 { 3935 temperature = <95000>; 3936 hysteresis = <2000>; 3937 type = "passive"; 3938 }; 3939 3940 cpu7_top_crit: cpu-crit { 3941 temperature = <110000>; 3942 hysteresis = <1000>; 3943 type = "critical"; 3944 }; 3945 }; 3946 3947 cooling-maps { 3948 map0 { 3949 trip = <&cpu7_top_alert0>; 3950 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3951 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3952 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3953 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3954 }; 3955 map1 { 3956 trip = <&cpu7_top_alert1>; 3957 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3958 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3959 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3960 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3961 }; 3962 }; 3963 }; 3964 3965 cpu4-bottom-thermal { 3966 polling-delay-passive = <250>; 3967 polling-delay = <1000>; 3968 3969 thermal-sensors = <&tsens0 11>; 3970 3971 trips { 3972 cpu4_bottom_alert0: trip-point0 { 3973 temperature = <90000>; 3974 hysteresis = <2000>; 3975 type = "passive"; 3976 }; 3977 3978 cpu4_bottom_alert1: trip-point1 { 3979 temperature = <95000>; 3980 hysteresis = <2000>; 3981 type = "passive"; 3982 }; 3983 3984 cpu4_bottom_crit: cpu-crit { 3985 temperature = <110000>; 3986 hysteresis = <1000>; 3987 type = "critical"; 3988 }; 3989 }; 3990 3991 cooling-maps { 3992 map0 { 3993 trip = <&cpu4_bottom_alert0>; 3994 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3995 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3996 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3997 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3998 }; 3999 map1 { 4000 trip = <&cpu4_bottom_alert1>; 4001 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4002 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4003 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4004 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4005 }; 4006 }; 4007 }; 4008 4009 cpu5-bottom-thermal { 4010 polling-delay-passive = <250>; 4011 polling-delay = <1000>; 4012 4013 thermal-sensors = <&tsens0 12>; 4014 4015 trips { 4016 cpu5_bottom_alert0: trip-point0 { 4017 temperature = <90000>; 4018 hysteresis = <2000>; 4019 type = "passive"; 4020 }; 4021 4022 cpu5_bottom_alert1: trip-point1 { 4023 temperature = <95000>; 4024 hysteresis = <2000>; 4025 type = "passive"; 4026 }; 4027 4028 cpu5_bottom_crit: cpu-crit { 4029 temperature = <110000>; 4030 hysteresis = <1000>; 4031 type = "critical"; 4032 }; 4033 }; 4034 4035 cooling-maps { 4036 map0 { 4037 trip = <&cpu5_bottom_alert0>; 4038 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4039 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4040 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4041 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4042 }; 4043 map1 { 4044 trip = <&cpu5_bottom_alert1>; 4045 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4046 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4047 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4048 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4049 }; 4050 }; 4051 }; 4052 4053 cpu6-bottom-thermal { 4054 polling-delay-passive = <250>; 4055 polling-delay = <1000>; 4056 4057 thermal-sensors = <&tsens0 13>; 4058 4059 trips { 4060 cpu6_bottom_alert0: trip-point0 { 4061 temperature = <90000>; 4062 hysteresis = <2000>; 4063 type = "passive"; 4064 }; 4065 4066 cpu6_bottom_alert1: trip-point1 { 4067 temperature = <95000>; 4068 hysteresis = <2000>; 4069 type = "passive"; 4070 }; 4071 4072 cpu6_bottom_crit: cpu-crit { 4073 temperature = <110000>; 4074 hysteresis = <1000>; 4075 type = "critical"; 4076 }; 4077 }; 4078 4079 cooling-maps { 4080 map0 { 4081 trip = <&cpu6_bottom_alert0>; 4082 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4083 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4084 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4085 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4086 }; 4087 map1 { 4088 trip = <&cpu6_bottom_alert1>; 4089 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4090 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4091 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4092 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4093 }; 4094 }; 4095 }; 4096 4097 cpu7-bottom-thermal { 4098 polling-delay-passive = <250>; 4099 polling-delay = <1000>; 4100 4101 thermal-sensors = <&tsens0 14>; 4102 4103 trips { 4104 cpu7_bottom_alert0: trip-point0 { 4105 temperature = <90000>; 4106 hysteresis = <2000>; 4107 type = "passive"; 4108 }; 4109 4110 cpu7_bottom_alert1: trip-point1 { 4111 temperature = <95000>; 4112 hysteresis = <2000>; 4113 type = "passive"; 4114 }; 4115 4116 cpu7_bottom_crit: cpu-crit { 4117 temperature = <110000>; 4118 hysteresis = <1000>; 4119 type = "critical"; 4120 }; 4121 }; 4122 4123 cooling-maps { 4124 map0 { 4125 trip = <&cpu7_bottom_alert0>; 4126 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4127 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4128 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4129 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4130 }; 4131 map1 { 4132 trip = <&cpu7_bottom_alert1>; 4133 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4134 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4135 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4136 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4137 }; 4138 }; 4139 }; 4140 4141 aoss0-thermal { 4142 polling-delay-passive = <250>; 4143 polling-delay = <1000>; 4144 4145 thermal-sensors = <&tsens0 0>; 4146 4147 trips { 4148 aoss0_alert0: trip-point0 { 4149 temperature = <90000>; 4150 hysteresis = <2000>; 4151 type = "hot"; 4152 }; 4153 }; 4154 }; 4155 4156 cluster0-thermal { 4157 polling-delay-passive = <250>; 4158 polling-delay = <1000>; 4159 4160 thermal-sensors = <&tsens0 5>; 4161 4162 trips { 4163 cluster0_alert0: trip-point0 { 4164 temperature = <90000>; 4165 hysteresis = <2000>; 4166 type = "hot"; 4167 }; 4168 cluster0_crit: cluster0_crit { 4169 temperature = <110000>; 4170 hysteresis = <2000>; 4171 type = "critical"; 4172 }; 4173 }; 4174 }; 4175 4176 cluster1-thermal { 4177 polling-delay-passive = <250>; 4178 polling-delay = <1000>; 4179 4180 thermal-sensors = <&tsens0 6>; 4181 4182 trips { 4183 cluster1_alert0: trip-point0 { 4184 temperature = <90000>; 4185 hysteresis = <2000>; 4186 type = "hot"; 4187 }; 4188 cluster1_crit: cluster1_crit { 4189 temperature = <110000>; 4190 hysteresis = <2000>; 4191 type = "critical"; 4192 }; 4193 }; 4194 }; 4195 4196 aoss1-thermal { 4197 polling-delay-passive = <250>; 4198 polling-delay = <1000>; 4199 4200 thermal-sensors = <&tsens1 0>; 4201 4202 trips { 4203 aoss1_alert0: trip-point0 { 4204 temperature = <90000>; 4205 hysteresis = <2000>; 4206 type = "hot"; 4207 }; 4208 }; 4209 }; 4210 4211 gpu-top-thermal { 4212 polling-delay-passive = <250>; 4213 polling-delay = <1000>; 4214 4215 thermal-sensors = <&tsens1 1>; 4216 4217 trips { 4218 gpu1_alert0: trip-point0 { 4219 temperature = <90000>; 4220 hysteresis = <1000>; 4221 type = "hot"; 4222 }; 4223 }; 4224 }; 4225 4226 gpu-bottom-thermal { 4227 polling-delay-passive = <250>; 4228 polling-delay = <1000>; 4229 4230 thermal-sensors = <&tsens1 2>; 4231 4232 trips { 4233 gpu2_alert0: trip-point0 { 4234 temperature = <90000>; 4235 hysteresis = <1000>; 4236 type = "hot"; 4237 }; 4238 }; 4239 }; 4240 4241 nspss1-thermal { 4242 polling-delay-passive = <250>; 4243 polling-delay = <1000>; 4244 4245 thermal-sensors = <&tsens1 3>; 4246 4247 trips { 4248 nspss1_alert0: trip-point0 { 4249 temperature = <90000>; 4250 hysteresis = <1000>; 4251 type = "hot"; 4252 }; 4253 }; 4254 }; 4255 4256 nspss2-thermal { 4257 polling-delay-passive = <250>; 4258 polling-delay = <1000>; 4259 4260 thermal-sensors = <&tsens1 4>; 4261 4262 trips { 4263 nspss2_alert0: trip-point0 { 4264 temperature = <90000>; 4265 hysteresis = <1000>; 4266 type = "hot"; 4267 }; 4268 }; 4269 }; 4270 4271 nspss3-thermal { 4272 polling-delay-passive = <250>; 4273 polling-delay = <1000>; 4274 4275 thermal-sensors = <&tsens1 5>; 4276 4277 trips { 4278 nspss3_alert0: trip-point0 { 4279 temperature = <90000>; 4280 hysteresis = <1000>; 4281 type = "hot"; 4282 }; 4283 }; 4284 }; 4285 4286 video-thermal { 4287 polling-delay-passive = <250>; 4288 polling-delay = <1000>; 4289 4290 thermal-sensors = <&tsens1 6>; 4291 4292 trips { 4293 video_alert0: trip-point0 { 4294 temperature = <90000>; 4295 hysteresis = <2000>; 4296 type = "hot"; 4297 }; 4298 }; 4299 }; 4300 4301 mem-thermal { 4302 polling-delay-passive = <250>; 4303 polling-delay = <1000>; 4304 4305 thermal-sensors = <&tsens1 7>; 4306 4307 trips { 4308 mem_alert0: trip-point0 { 4309 temperature = <90000>; 4310 hysteresis = <2000>; 4311 type = "hot"; 4312 }; 4313 }; 4314 }; 4315 4316 modem1-top-thermal { 4317 polling-delay-passive = <250>; 4318 polling-delay = <1000>; 4319 4320 thermal-sensors = <&tsens1 8>; 4321 4322 trips { 4323 modem1_alert0: trip-point0 { 4324 temperature = <90000>; 4325 hysteresis = <2000>; 4326 type = "hot"; 4327 }; 4328 }; 4329 }; 4330 4331 modem2-top-thermal { 4332 polling-delay-passive = <250>; 4333 polling-delay = <1000>; 4334 4335 thermal-sensors = <&tsens1 9>; 4336 4337 trips { 4338 modem2_alert0: trip-point0 { 4339 temperature = <90000>; 4340 hysteresis = <2000>; 4341 type = "hot"; 4342 }; 4343 }; 4344 }; 4345 4346 modem3-top-thermal { 4347 polling-delay-passive = <250>; 4348 polling-delay = <1000>; 4349 4350 thermal-sensors = <&tsens1 10>; 4351 4352 trips { 4353 modem3_alert0: trip-point0 { 4354 temperature = <90000>; 4355 hysteresis = <2000>; 4356 type = "hot"; 4357 }; 4358 }; 4359 }; 4360 4361 modem4-top-thermal { 4362 polling-delay-passive = <250>; 4363 polling-delay = <1000>; 4364 4365 thermal-sensors = <&tsens1 11>; 4366 4367 trips { 4368 modem4_alert0: trip-point0 { 4369 temperature = <90000>; 4370 hysteresis = <2000>; 4371 type = "hot"; 4372 }; 4373 }; 4374 }; 4375 4376 camera-top-thermal { 4377 polling-delay-passive = <250>; 4378 polling-delay = <1000>; 4379 4380 thermal-sensors = <&tsens1 12>; 4381 4382 trips { 4383 camera1_alert0: trip-point0 { 4384 temperature = <90000>; 4385 hysteresis = <2000>; 4386 type = "hot"; 4387 }; 4388 }; 4389 }; 4390 4391 cam-bottom-thermal { 4392 polling-delay-passive = <250>; 4393 polling-delay = <1000>; 4394 4395 thermal-sensors = <&tsens1 13>; 4396 4397 trips { 4398 camera2_alert0: trip-point0 { 4399 temperature = <90000>; 4400 hysteresis = <2000>; 4401 type = "hot"; 4402 }; 4403 }; 4404 }; 4405 }; 4406 4407 timer { 4408 compatible = "arm,armv8-timer"; 4409 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4410 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4411 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4412 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4413 }; 4414}; 4415