1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm8250.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/soc/qcom,apr.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/sound/qcom,q6afe.h> 20#include <dt-bindings/thermal/thermal.h> 21#include <dt-bindings/clock/qcom,videocc-sm8250.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 i2c4 = &i2c4; 35 i2c5 = &i2c5; 36 i2c6 = &i2c6; 37 i2c7 = &i2c7; 38 i2c8 = &i2c8; 39 i2c9 = &i2c9; 40 i2c10 = &i2c10; 41 i2c11 = &i2c11; 42 i2c12 = &i2c12; 43 i2c13 = &i2c13; 44 i2c14 = &i2c14; 45 i2c15 = &i2c15; 46 i2c16 = &i2c16; 47 i2c17 = &i2c17; 48 i2c18 = &i2c18; 49 i2c19 = &i2c19; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 spi16 = &spi16; 67 spi17 = &spi17; 68 spi18 = &spi18; 69 spi19 = &spi19; 70 }; 71 72 chosen { }; 73 74 clocks { 75 xo_board: xo-board { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <38400000>; 79 clock-output-names = "xo_board"; 80 }; 81 82 sleep_clk: sleep-clk { 83 compatible = "fixed-clock"; 84 clock-frequency = <32768>; 85 #clock-cells = <0>; 86 }; 87 }; 88 89 cpus { 90 #address-cells = <2>; 91 #size-cells = <0>; 92 93 CPU0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo485"; 96 reg = <0x0 0x0>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <448>; 99 dynamic-power-coefficient = <205>; 100 next-level-cache = <&L2_0>; 101 power-domains = <&CPU_PD0>; 102 power-domain-names = "psci"; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 operating-points-v2 = <&cpu0_opp_table>; 105 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 106 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 107 #cooling-cells = <2>; 108 L2_0: l2-cache { 109 compatible = "cache"; 110 next-level-cache = <&L3_0>; 111 L3_0: l3-cache { 112 compatible = "cache"; 113 }; 114 }; 115 }; 116 117 CPU1: cpu@100 { 118 device_type = "cpu"; 119 compatible = "qcom,kryo485"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <448>; 123 dynamic-power-coefficient = <205>; 124 next-level-cache = <&L2_100>; 125 power-domains = <&CPU_PD1>; 126 power-domain-names = "psci"; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 operating-points-v2 = <&cpu0_opp_table>; 129 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 130 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 131 #cooling-cells = <2>; 132 L2_100: l2-cache { 133 compatible = "cache"; 134 next-level-cache = <&L3_0>; 135 }; 136 }; 137 138 CPU2: cpu@200 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo485"; 141 reg = <0x0 0x200>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <448>; 144 dynamic-power-coefficient = <205>; 145 next-level-cache = <&L2_200>; 146 power-domains = <&CPU_PD2>; 147 power-domain-names = "psci"; 148 qcom,freq-domain = <&cpufreq_hw 0>; 149 operating-points-v2 = <&cpu0_opp_table>; 150 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 151 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 152 #cooling-cells = <2>; 153 L2_200: l2-cache { 154 compatible = "cache"; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU3: cpu@300 { 160 device_type = "cpu"; 161 compatible = "qcom,kryo485"; 162 reg = <0x0 0x300>; 163 enable-method = "psci"; 164 capacity-dmips-mhz = <448>; 165 dynamic-power-coefficient = <205>; 166 next-level-cache = <&L2_300>; 167 power-domains = <&CPU_PD3>; 168 power-domain-names = "psci"; 169 qcom,freq-domain = <&cpufreq_hw 0>; 170 operating-points-v2 = <&cpu0_opp_table>; 171 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 172 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 173 #cooling-cells = <2>; 174 L2_300: l2-cache { 175 compatible = "cache"; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU4: cpu@400 { 181 device_type = "cpu"; 182 compatible = "qcom,kryo485"; 183 reg = <0x0 0x400>; 184 enable-method = "psci"; 185 capacity-dmips-mhz = <1024>; 186 dynamic-power-coefficient = <379>; 187 next-level-cache = <&L2_400>; 188 power-domains = <&CPU_PD4>; 189 power-domain-names = "psci"; 190 qcom,freq-domain = <&cpufreq_hw 1>; 191 operating-points-v2 = <&cpu4_opp_table>; 192 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 193 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 194 #cooling-cells = <2>; 195 L2_400: l2-cache { 196 compatible = "cache"; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU5: cpu@500 { 202 device_type = "cpu"; 203 compatible = "qcom,kryo485"; 204 reg = <0x0 0x500>; 205 enable-method = "psci"; 206 capacity-dmips-mhz = <1024>; 207 dynamic-power-coefficient = <379>; 208 next-level-cache = <&L2_500>; 209 power-domains = <&CPU_PD5>; 210 power-domain-names = "psci"; 211 qcom,freq-domain = <&cpufreq_hw 1>; 212 operating-points-v2 = <&cpu4_opp_table>; 213 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 214 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 215 #cooling-cells = <2>; 216 L2_500: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 221 }; 222 223 CPU6: cpu@600 { 224 device_type = "cpu"; 225 compatible = "qcom,kryo485"; 226 reg = <0x0 0x600>; 227 enable-method = "psci"; 228 capacity-dmips-mhz = <1024>; 229 dynamic-power-coefficient = <379>; 230 next-level-cache = <&L2_600>; 231 power-domains = <&CPU_PD6>; 232 power-domain-names = "psci"; 233 qcom,freq-domain = <&cpufreq_hw 1>; 234 operating-points-v2 = <&cpu4_opp_table>; 235 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 236 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 237 #cooling-cells = <2>; 238 L2_600: l2-cache { 239 compatible = "cache"; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 CPU7: cpu@700 { 245 device_type = "cpu"; 246 compatible = "qcom,kryo485"; 247 reg = <0x0 0x700>; 248 enable-method = "psci"; 249 capacity-dmips-mhz = <1024>; 250 dynamic-power-coefficient = <444>; 251 next-level-cache = <&L2_700>; 252 power-domains = <&CPU_PD7>; 253 power-domain-names = "psci"; 254 qcom,freq-domain = <&cpufreq_hw 2>; 255 operating-points-v2 = <&cpu7_opp_table>; 256 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 257 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 258 #cooling-cells = <2>; 259 L2_700: l2-cache { 260 compatible = "cache"; 261 next-level-cache = <&L3_0>; 262 }; 263 }; 264 265 cpu-map { 266 cluster0 { 267 core0 { 268 cpu = <&CPU0>; 269 }; 270 271 core1 { 272 cpu = <&CPU1>; 273 }; 274 275 core2 { 276 cpu = <&CPU2>; 277 }; 278 279 core3 { 280 cpu = <&CPU3>; 281 }; 282 283 core4 { 284 cpu = <&CPU4>; 285 }; 286 287 core5 { 288 cpu = <&CPU5>; 289 }; 290 291 core6 { 292 cpu = <&CPU6>; 293 }; 294 295 core7 { 296 cpu = <&CPU7>; 297 }; 298 }; 299 }; 300 301 idle-states { 302 entry-method = "psci"; 303 304 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "silver-rail-power-collapse"; 307 arm,psci-suspend-param = <0x40000004>; 308 entry-latency-us = <360>; 309 exit-latency-us = <531>; 310 min-residency-us = <3934>; 311 local-timer-stop; 312 }; 313 314 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 315 compatible = "arm,idle-state"; 316 idle-state-name = "gold-rail-power-collapse"; 317 arm,psci-suspend-param = <0x40000004>; 318 entry-latency-us = <702>; 319 exit-latency-us = <1061>; 320 min-residency-us = <4488>; 321 local-timer-stop; 322 }; 323 }; 324 325 domain-idle-states { 326 CLUSTER_SLEEP_0: cluster-sleep-0 { 327 compatible = "domain-idle-state"; 328 idle-state-name = "cluster-llcc-off"; 329 arm,psci-suspend-param = <0x4100c244>; 330 entry-latency-us = <3264>; 331 exit-latency-us = <6562>; 332 min-residency-us = <9987>; 333 local-timer-stop; 334 }; 335 }; 336 }; 337 338 cpu0_opp_table: cpu0_opp_table { 339 compatible = "operating-points-v2"; 340 opp-shared; 341 342 cpu0_opp1: opp-300000000 { 343 opp-hz = /bits/ 64 <300000000>; 344 opp-peak-kBps = <800000 9600000>; 345 }; 346 347 cpu0_opp2: opp-403200000 { 348 opp-hz = /bits/ 64 <403200000>; 349 opp-peak-kBps = <800000 9600000>; 350 }; 351 352 cpu0_opp3: opp-518400000 { 353 opp-hz = /bits/ 64 <518400000>; 354 opp-peak-kBps = <800000 16588800>; 355 }; 356 357 cpu0_opp4: opp-614400000 { 358 opp-hz = /bits/ 64 <614400000>; 359 opp-peak-kBps = <800000 16588800>; 360 }; 361 362 cpu0_opp5: opp-691200000 { 363 opp-hz = /bits/ 64 <691200000>; 364 opp-peak-kBps = <800000 19660800>; 365 }; 366 367 cpu0_opp6: opp-787200000 { 368 opp-hz = /bits/ 64 <787200000>; 369 opp-peak-kBps = <1804000 19660800>; 370 }; 371 372 cpu0_opp7: opp-883200000 { 373 opp-hz = /bits/ 64 <883200000>; 374 opp-peak-kBps = <1804000 23347200>; 375 }; 376 377 cpu0_opp8: opp-979200000 { 378 opp-hz = /bits/ 64 <979200000>; 379 opp-peak-kBps = <1804000 26419200>; 380 }; 381 382 cpu0_opp9: opp-1075200000 { 383 opp-hz = /bits/ 64 <1075200000>; 384 opp-peak-kBps = <1804000 29491200>; 385 }; 386 387 cpu0_opp10: opp-1171200000 { 388 opp-hz = /bits/ 64 <1171200000>; 389 opp-peak-kBps = <1804000 32563200>; 390 }; 391 392 cpu0_opp11: opp-1248000000 { 393 opp-hz = /bits/ 64 <1248000000>; 394 opp-peak-kBps = <1804000 36249600>; 395 }; 396 397 cpu0_opp12: opp-1344000000 { 398 opp-hz = /bits/ 64 <1344000000>; 399 opp-peak-kBps = <2188000 36249600>; 400 }; 401 402 cpu0_opp13: opp-1420800000 { 403 opp-hz = /bits/ 64 <1420800000>; 404 opp-peak-kBps = <2188000 39321600>; 405 }; 406 407 cpu0_opp14: opp-1516800000 { 408 opp-hz = /bits/ 64 <1516800000>; 409 opp-peak-kBps = <3072000 42393600>; 410 }; 411 412 cpu0_opp15: opp-1612800000 { 413 opp-hz = /bits/ 64 <1612800000>; 414 opp-peak-kBps = <3072000 42393600>; 415 }; 416 417 cpu0_opp16: opp-1708800000 { 418 opp-hz = /bits/ 64 <1708800000>; 419 opp-peak-kBps = <4068000 42393600>; 420 }; 421 422 cpu0_opp17: opp-1804800000 { 423 opp-hz = /bits/ 64 <1804800000>; 424 opp-peak-kBps = <4068000 42393600>; 425 }; 426 }; 427 428 cpu4_opp_table: cpu4_opp_table { 429 compatible = "operating-points-v2"; 430 opp-shared; 431 432 cpu4_opp1: opp-710400000 { 433 opp-hz = /bits/ 64 <710400000>; 434 opp-peak-kBps = <1804000 19660800>; 435 }; 436 437 cpu4_opp2: opp-825600000 { 438 opp-hz = /bits/ 64 <825600000>; 439 opp-peak-kBps = <2188000 23347200>; 440 }; 441 442 cpu4_opp3: opp-940800000 { 443 opp-hz = /bits/ 64 <940800000>; 444 opp-peak-kBps = <2188000 26419200>; 445 }; 446 447 cpu4_opp4: opp-1056000000 { 448 opp-hz = /bits/ 64 <1056000000>; 449 opp-peak-kBps = <3072000 26419200>; 450 }; 451 452 cpu4_opp5: opp-1171200000 { 453 opp-hz = /bits/ 64 <1171200000>; 454 opp-peak-kBps = <3072000 29491200>; 455 }; 456 457 cpu4_opp6: opp-1286400000 { 458 opp-hz = /bits/ 64 <1286400000>; 459 opp-peak-kBps = <4068000 29491200>; 460 }; 461 462 cpu4_opp7: opp-1382400000 { 463 opp-hz = /bits/ 64 <1382400000>; 464 opp-peak-kBps = <4068000 32563200>; 465 }; 466 467 cpu4_opp8: opp-1478400000 { 468 opp-hz = /bits/ 64 <1478400000>; 469 opp-peak-kBps = <4068000 32563200>; 470 }; 471 472 cpu4_opp9: opp-1574400000 { 473 opp-hz = /bits/ 64 <1574400000>; 474 opp-peak-kBps = <5412000 39321600>; 475 }; 476 477 cpu4_opp10: opp-1670400000 { 478 opp-hz = /bits/ 64 <1670400000>; 479 opp-peak-kBps = <5412000 42393600>; 480 }; 481 482 cpu4_opp11: opp-1766400000 { 483 opp-hz = /bits/ 64 <1766400000>; 484 opp-peak-kBps = <5412000 45465600>; 485 }; 486 487 cpu4_opp12: opp-1862400000 { 488 opp-hz = /bits/ 64 <1862400000>; 489 opp-peak-kBps = <6220000 45465600>; 490 }; 491 492 cpu4_opp13: opp-1958400000 { 493 opp-hz = /bits/ 64 <1958400000>; 494 opp-peak-kBps = <6220000 48537600>; 495 }; 496 497 cpu4_opp14: opp-2054400000 { 498 opp-hz = /bits/ 64 <2054400000>; 499 opp-peak-kBps = <7216000 48537600>; 500 }; 501 502 cpu4_opp15: opp-2150400000 { 503 opp-hz = /bits/ 64 <2150400000>; 504 opp-peak-kBps = <7216000 51609600>; 505 }; 506 507 cpu4_opp16: opp-2246400000 { 508 opp-hz = /bits/ 64 <2246400000>; 509 opp-peak-kBps = <7216000 51609600>; 510 }; 511 512 cpu4_opp17: opp-2342400000 { 513 opp-hz = /bits/ 64 <2342400000>; 514 opp-peak-kBps = <8368000 51609600>; 515 }; 516 517 cpu4_opp18: opp-2419200000 { 518 opp-hz = /bits/ 64 <2419200000>; 519 opp-peak-kBps = <8368000 51609600>; 520 }; 521 }; 522 523 cpu7_opp_table: cpu7_opp_table { 524 compatible = "operating-points-v2"; 525 opp-shared; 526 527 cpu7_opp1: opp-844800000 { 528 opp-hz = /bits/ 64 <844800000>; 529 opp-peak-kBps = <2188000 19660800>; 530 }; 531 532 cpu7_opp2: opp-960000000 { 533 opp-hz = /bits/ 64 <960000000>; 534 opp-peak-kBps = <2188000 26419200>; 535 }; 536 537 cpu7_opp3: opp-1075200000 { 538 opp-hz = /bits/ 64 <1075200000>; 539 opp-peak-kBps = <3072000 26419200>; 540 }; 541 542 cpu7_opp4: opp-1190400000 { 543 opp-hz = /bits/ 64 <1190400000>; 544 opp-peak-kBps = <3072000 29491200>; 545 }; 546 547 cpu7_opp5: opp-1305600000 { 548 opp-hz = /bits/ 64 <1305600000>; 549 opp-peak-kBps = <4068000 32563200>; 550 }; 551 552 cpu7_opp6: opp-1401600000 { 553 opp-hz = /bits/ 64 <1401600000>; 554 opp-peak-kBps = <4068000 32563200>; 555 }; 556 557 cpu7_opp7: opp-1516800000 { 558 opp-hz = /bits/ 64 <1516800000>; 559 opp-peak-kBps = <4068000 36249600>; 560 }; 561 562 cpu7_opp8: opp-1632000000 { 563 opp-hz = /bits/ 64 <1632000000>; 564 opp-peak-kBps = <5412000 39321600>; 565 }; 566 567 cpu7_opp9: opp-1747200000 { 568 opp-hz = /bits/ 64 <1708800000>; 569 opp-peak-kBps = <5412000 42393600>; 570 }; 571 572 cpu7_opp10: opp-1862400000 { 573 opp-hz = /bits/ 64 <1862400000>; 574 opp-peak-kBps = <6220000 45465600>; 575 }; 576 577 cpu7_opp11: opp-1977600000 { 578 opp-hz = /bits/ 64 <1977600000>; 579 opp-peak-kBps = <6220000 48537600>; 580 }; 581 582 cpu7_opp12: opp-2073600000 { 583 opp-hz = /bits/ 64 <2073600000>; 584 opp-peak-kBps = <7216000 48537600>; 585 }; 586 587 cpu7_opp13: opp-2169600000 { 588 opp-hz = /bits/ 64 <2169600000>; 589 opp-peak-kBps = <7216000 51609600>; 590 }; 591 592 cpu7_opp14: opp-2265600000 { 593 opp-hz = /bits/ 64 <2265600000>; 594 opp-peak-kBps = <7216000 51609600>; 595 }; 596 597 cpu7_opp15: opp-2361600000 { 598 opp-hz = /bits/ 64 <2361600000>; 599 opp-peak-kBps = <8368000 51609600>; 600 }; 601 602 cpu7_opp16: opp-2457600000 { 603 opp-hz = /bits/ 64 <2457600000>; 604 opp-peak-kBps = <8368000 51609600>; 605 }; 606 607 cpu7_opp17: opp-2553600000 { 608 opp-hz = /bits/ 64 <2553600000>; 609 opp-peak-kBps = <8368000 51609600>; 610 }; 611 612 cpu7_opp18: opp-2649600000 { 613 opp-hz = /bits/ 64 <2649600000>; 614 opp-peak-kBps = <8368000 51609600>; 615 }; 616 617 cpu7_opp19: opp-2745600000 { 618 opp-hz = /bits/ 64 <2745600000>; 619 opp-peak-kBps = <8368000 51609600>; 620 }; 621 622 cpu7_opp20: opp-2841600000 { 623 opp-hz = /bits/ 64 <2841600000>; 624 opp-peak-kBps = <8368000 51609600>; 625 }; 626 }; 627 628 firmware { 629 scm: scm { 630 compatible = "qcom,scm"; 631 #reset-cells = <1>; 632 }; 633 }; 634 635 memory@80000000 { 636 device_type = "memory"; 637 /* We expect the bootloader to fill in the size */ 638 reg = <0x0 0x80000000 0x0 0x0>; 639 }; 640 641 pmu { 642 compatible = "arm,armv8-pmuv3"; 643 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 644 }; 645 646 psci { 647 compatible = "arm,psci-1.0"; 648 method = "smc"; 649 650 CPU_PD0: cpu0 { 651 #power-domain-cells = <0>; 652 power-domains = <&CLUSTER_PD>; 653 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 654 }; 655 656 CPU_PD1: cpu1 { 657 #power-domain-cells = <0>; 658 power-domains = <&CLUSTER_PD>; 659 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 660 }; 661 662 CPU_PD2: cpu2 { 663 #power-domain-cells = <0>; 664 power-domains = <&CLUSTER_PD>; 665 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 666 }; 667 668 CPU_PD3: cpu3 { 669 #power-domain-cells = <0>; 670 power-domains = <&CLUSTER_PD>; 671 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 672 }; 673 674 CPU_PD4: cpu4 { 675 #power-domain-cells = <0>; 676 power-domains = <&CLUSTER_PD>; 677 domain-idle-states = <&BIG_CPU_SLEEP_0>; 678 }; 679 680 CPU_PD5: cpu5 { 681 #power-domain-cells = <0>; 682 power-domains = <&CLUSTER_PD>; 683 domain-idle-states = <&BIG_CPU_SLEEP_0>; 684 }; 685 686 CPU_PD6: cpu6 { 687 #power-domain-cells = <0>; 688 power-domains = <&CLUSTER_PD>; 689 domain-idle-states = <&BIG_CPU_SLEEP_0>; 690 }; 691 692 CPU_PD7: cpu7 { 693 #power-domain-cells = <0>; 694 power-domains = <&CLUSTER_PD>; 695 domain-idle-states = <&BIG_CPU_SLEEP_0>; 696 }; 697 698 CLUSTER_PD: cpu-cluster0 { 699 #power-domain-cells = <0>; 700 domain-idle-states = <&CLUSTER_SLEEP_0>; 701 }; 702 }; 703 704 reserved-memory { 705 #address-cells = <2>; 706 #size-cells = <2>; 707 ranges; 708 709 hyp_mem: memory@80000000 { 710 reg = <0x0 0x80000000 0x0 0x600000>; 711 no-map; 712 }; 713 714 xbl_aop_mem: memory@80700000 { 715 reg = <0x0 0x80700000 0x0 0x160000>; 716 no-map; 717 }; 718 719 cmd_db: memory@80860000 { 720 compatible = "qcom,cmd-db"; 721 reg = <0x0 0x80860000 0x0 0x20000>; 722 no-map; 723 }; 724 725 smem_mem: memory@80900000 { 726 reg = <0x0 0x80900000 0x0 0x200000>; 727 no-map; 728 }; 729 730 removed_mem: memory@80b00000 { 731 reg = <0x0 0x80b00000 0x0 0x5300000>; 732 no-map; 733 }; 734 735 camera_mem: memory@86200000 { 736 reg = <0x0 0x86200000 0x0 0x500000>; 737 no-map; 738 }; 739 740 wlan_mem: memory@86700000 { 741 reg = <0x0 0x86700000 0x0 0x100000>; 742 no-map; 743 }; 744 745 ipa_fw_mem: memory@86800000 { 746 reg = <0x0 0x86800000 0x0 0x10000>; 747 no-map; 748 }; 749 750 ipa_gsi_mem: memory@86810000 { 751 reg = <0x0 0x86810000 0x0 0xa000>; 752 no-map; 753 }; 754 755 gpu_mem: memory@8681a000 { 756 reg = <0x0 0x8681a000 0x0 0x2000>; 757 no-map; 758 }; 759 760 npu_mem: memory@86900000 { 761 reg = <0x0 0x86900000 0x0 0x500000>; 762 no-map; 763 }; 764 765 video_mem: memory@86e00000 { 766 reg = <0x0 0x86e00000 0x0 0x500000>; 767 no-map; 768 }; 769 770 cvp_mem: memory@87300000 { 771 reg = <0x0 0x87300000 0x0 0x500000>; 772 no-map; 773 }; 774 775 cdsp_mem: memory@87800000 { 776 reg = <0x0 0x87800000 0x0 0x1400000>; 777 no-map; 778 }; 779 780 slpi_mem: memory@88c00000 { 781 reg = <0x0 0x88c00000 0x0 0x1500000>; 782 no-map; 783 }; 784 785 adsp_mem: memory@8a100000 { 786 reg = <0x0 0x8a100000 0x0 0x1d00000>; 787 no-map; 788 }; 789 790 spss_mem: memory@8be00000 { 791 reg = <0x0 0x8be00000 0x0 0x100000>; 792 no-map; 793 }; 794 795 cdsp_secure_heap: memory@8bf00000 { 796 reg = <0x0 0x8bf00000 0x0 0x4600000>; 797 no-map; 798 }; 799 }; 800 801 smem { 802 compatible = "qcom,smem"; 803 memory-region = <&smem_mem>; 804 hwlocks = <&tcsr_mutex 3>; 805 }; 806 807 smp2p-adsp { 808 compatible = "qcom,smp2p"; 809 qcom,smem = <443>, <429>; 810 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 811 IPCC_MPROC_SIGNAL_SMP2P 812 IRQ_TYPE_EDGE_RISING>; 813 mboxes = <&ipcc IPCC_CLIENT_LPASS 814 IPCC_MPROC_SIGNAL_SMP2P>; 815 816 qcom,local-pid = <0>; 817 qcom,remote-pid = <2>; 818 819 smp2p_adsp_out: master-kernel { 820 qcom,entry-name = "master-kernel"; 821 #qcom,smem-state-cells = <1>; 822 }; 823 824 smp2p_adsp_in: slave-kernel { 825 qcom,entry-name = "slave-kernel"; 826 interrupt-controller; 827 #interrupt-cells = <2>; 828 }; 829 }; 830 831 smp2p-cdsp { 832 compatible = "qcom,smp2p"; 833 qcom,smem = <94>, <432>; 834 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 835 IPCC_MPROC_SIGNAL_SMP2P 836 IRQ_TYPE_EDGE_RISING>; 837 mboxes = <&ipcc IPCC_CLIENT_CDSP 838 IPCC_MPROC_SIGNAL_SMP2P>; 839 840 qcom,local-pid = <0>; 841 qcom,remote-pid = <5>; 842 843 smp2p_cdsp_out: master-kernel { 844 qcom,entry-name = "master-kernel"; 845 #qcom,smem-state-cells = <1>; 846 }; 847 848 smp2p_cdsp_in: slave-kernel { 849 qcom,entry-name = "slave-kernel"; 850 interrupt-controller; 851 #interrupt-cells = <2>; 852 }; 853 }; 854 855 smp2p-slpi { 856 compatible = "qcom,smp2p"; 857 qcom,smem = <481>, <430>; 858 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 859 IPCC_MPROC_SIGNAL_SMP2P 860 IRQ_TYPE_EDGE_RISING>; 861 mboxes = <&ipcc IPCC_CLIENT_SLPI 862 IPCC_MPROC_SIGNAL_SMP2P>; 863 864 qcom,local-pid = <0>; 865 qcom,remote-pid = <3>; 866 867 smp2p_slpi_out: master-kernel { 868 qcom,entry-name = "master-kernel"; 869 #qcom,smem-state-cells = <1>; 870 }; 871 872 smp2p_slpi_in: slave-kernel { 873 qcom,entry-name = "slave-kernel"; 874 interrupt-controller; 875 #interrupt-cells = <2>; 876 }; 877 }; 878 879 soc: soc@0 { 880 #address-cells = <2>; 881 #size-cells = <2>; 882 ranges = <0 0 0 0 0x10 0>; 883 dma-ranges = <0 0 0 0 0x10 0>; 884 compatible = "simple-bus"; 885 886 gcc: clock-controller@100000 { 887 compatible = "qcom,gcc-sm8250"; 888 reg = <0x0 0x00100000 0x0 0x1f0000>; 889 #clock-cells = <1>; 890 #reset-cells = <1>; 891 #power-domain-cells = <1>; 892 clock-names = "bi_tcxo", 893 "bi_tcxo_ao", 894 "sleep_clk"; 895 clocks = <&rpmhcc RPMH_CXO_CLK>, 896 <&rpmhcc RPMH_CXO_CLK_A>, 897 <&sleep_clk>; 898 }; 899 900 ipcc: mailbox@408000 { 901 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 902 reg = <0 0x00408000 0 0x1000>; 903 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-controller; 905 #interrupt-cells = <3>; 906 #mbox-cells = <2>; 907 }; 908 909 rng: rng@793000 { 910 compatible = "qcom,prng-ee"; 911 reg = <0 0x00793000 0 0x1000>; 912 clocks = <&gcc GCC_PRNG_AHB_CLK>; 913 clock-names = "core"; 914 }; 915 916 qup_opp_table: qup-opp-table { 917 compatible = "operating-points-v2"; 918 919 opp-50000000 { 920 opp-hz = /bits/ 64 <50000000>; 921 required-opps = <&rpmhpd_opp_min_svs>; 922 }; 923 924 opp-75000000 { 925 opp-hz = /bits/ 64 <75000000>; 926 required-opps = <&rpmhpd_opp_low_svs>; 927 }; 928 929 opp-120000000 { 930 opp-hz = /bits/ 64 <120000000>; 931 required-opps = <&rpmhpd_opp_svs>; 932 }; 933 }; 934 935 gpi_dma2: dma-controller@800000 { 936 compatible = "qcom,sm8250-gpi-dma"; 937 reg = <0 0x00800000 0 0x70000>; 938 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 948 dma-channels = <10>; 949 dma-channel-mask = <0x3f>; 950 iommus = <&apps_smmu 0x76 0x0>; 951 #dma-cells = <3>; 952 status = "disabled"; 953 }; 954 955 qupv3_id_2: geniqup@8c0000 { 956 compatible = "qcom,geni-se-qup"; 957 reg = <0x0 0x008c0000 0x0 0x6000>; 958 clock-names = "m-ahb", "s-ahb"; 959 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 960 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 961 #address-cells = <2>; 962 #size-cells = <2>; 963 iommus = <&apps_smmu 0x63 0x0>; 964 ranges; 965 status = "disabled"; 966 967 i2c14: i2c@880000 { 968 compatible = "qcom,geni-i2c"; 969 reg = <0 0x00880000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_i2c14_default>; 974 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 975 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 976 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 977 dma-names = "tx", "rx"; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 status = "disabled"; 981 }; 982 983 spi14: spi@880000 { 984 compatible = "qcom,geni-spi"; 985 reg = <0 0x00880000 0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 988 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 989 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 990 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 991 dma-names = "tx", "rx"; 992 power-domains = <&rpmhpd SM8250_CX>; 993 operating-points-v2 = <&qup_opp_table>; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 i2c15: i2c@884000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0 0x00884000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&qup_i2c15_default>; 1006 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1007 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1008 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1009 dma-names = "tx", "rx"; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 spi15: spi@884000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0 0x00884000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1020 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1021 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1022 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1023 dma-names = "tx", "rx"; 1024 power-domains = <&rpmhpd SM8250_CX>; 1025 operating-points-v2 = <&qup_opp_table>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 i2c16: i2c@888000 { 1032 compatible = "qcom,geni-i2c"; 1033 reg = <0 0x00888000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_i2c16_default>; 1038 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1039 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1040 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1041 dma-names = "tx", "rx"; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 spi16: spi@888000 { 1048 compatible = "qcom,geni-spi"; 1049 reg = <0 0x00888000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1052 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1053 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1054 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1055 dma-names = "tx", "rx"; 1056 power-domains = <&rpmhpd SM8250_CX>; 1057 operating-points-v2 = <&qup_opp_table>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 1063 i2c17: i2c@88c000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x0088c000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_i2c17_default>; 1070 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1071 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1072 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1073 dma-names = "tx", "rx"; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 spi17: spi@88c000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x0088c000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1084 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1085 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1086 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1087 dma-names = "tx", "rx"; 1088 power-domains = <&rpmhpd SM8250_CX>; 1089 operating-points-v2 = <&qup_opp_table>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 uart17: serial@88c000 { 1096 compatible = "qcom,geni-uart"; 1097 reg = <0 0x0088c000 0 0x4000>; 1098 clock-names = "se"; 1099 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&qup_uart17_default>; 1102 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1103 power-domains = <&rpmhpd SM8250_CX>; 1104 operating-points-v2 = <&qup_opp_table>; 1105 status = "disabled"; 1106 }; 1107 1108 i2c18: i2c@890000 { 1109 compatible = "qcom,geni-i2c"; 1110 reg = <0 0x00890000 0 0x4000>; 1111 clock-names = "se"; 1112 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&qup_i2c18_default>; 1115 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1116 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1117 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1118 dma-names = "tx", "rx"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 spi18: spi@890000 { 1125 compatible = "qcom,geni-spi"; 1126 reg = <0 0x00890000 0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1129 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1130 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1131 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1132 dma-names = "tx", "rx"; 1133 power-domains = <&rpmhpd SM8250_CX>; 1134 operating-points-v2 = <&qup_opp_table>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 uart18: serial@890000 { 1141 compatible = "qcom,geni-uart"; 1142 reg = <0 0x00890000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_uart18_default>; 1147 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1148 power-domains = <&rpmhpd SM8250_CX>; 1149 operating-points-v2 = <&qup_opp_table>; 1150 status = "disabled"; 1151 }; 1152 1153 i2c19: i2c@894000 { 1154 compatible = "qcom,geni-i2c"; 1155 reg = <0 0x00894000 0 0x4000>; 1156 clock-names = "se"; 1157 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&qup_i2c19_default>; 1160 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1161 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1162 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1163 dma-names = "tx", "rx"; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 status = "disabled"; 1167 }; 1168 1169 spi19: spi@894000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x00894000 0 0x4000>; 1172 clock-names = "se"; 1173 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1174 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1175 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1176 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1177 dma-names = "tx", "rx"; 1178 power-domains = <&rpmhpd SM8250_CX>; 1179 operating-points-v2 = <&qup_opp_table>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 status = "disabled"; 1183 }; 1184 }; 1185 1186 gpi_dma0: dma-controller@900000 { 1187 compatible = "qcom,sm8250-gpi-dma"; 1188 reg = <0 0x00900000 0 0x70000>; 1189 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1202 dma-channels = <15>; 1203 dma-channel-mask = <0x7ff>; 1204 iommus = <&apps_smmu 0x5b6 0x0>; 1205 #dma-cells = <3>; 1206 status = "disabled"; 1207 }; 1208 1209 qupv3_id_0: geniqup@9c0000 { 1210 compatible = "qcom,geni-se-qup"; 1211 reg = <0x0 0x009c0000 0x0 0x6000>; 1212 clock-names = "m-ahb", "s-ahb"; 1213 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1214 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1215 #address-cells = <2>; 1216 #size-cells = <2>; 1217 iommus = <&apps_smmu 0x5a3 0x0>; 1218 ranges; 1219 status = "disabled"; 1220 1221 i2c0: i2c@980000 { 1222 compatible = "qcom,geni-i2c"; 1223 reg = <0 0x00980000 0 0x4000>; 1224 clock-names = "se"; 1225 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&qup_i2c0_default>; 1228 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1229 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1230 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1231 dma-names = "tx", "rx"; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 spi0: spi@980000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0 0x00980000 0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1242 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1243 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1244 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1245 dma-names = "tx", "rx"; 1246 power-domains = <&rpmhpd SM8250_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 i2c1: i2c@984000 { 1254 compatible = "qcom,geni-i2c"; 1255 reg = <0 0x00984000 0 0x4000>; 1256 clock-names = "se"; 1257 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1258 pinctrl-names = "default"; 1259 pinctrl-0 = <&qup_i2c1_default>; 1260 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1261 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1262 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1263 dma-names = "tx", "rx"; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 status = "disabled"; 1267 }; 1268 1269 spi1: spi@984000 { 1270 compatible = "qcom,geni-spi"; 1271 reg = <0 0x00984000 0 0x4000>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1274 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1275 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1276 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1277 dma-names = "tx", "rx"; 1278 power-domains = <&rpmhpd SM8250_CX>; 1279 operating-points-v2 = <&qup_opp_table>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 1285 i2c2: i2c@988000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x00988000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_i2c2_default>; 1292 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1293 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1294 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1295 dma-names = "tx", "rx"; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 spi2: spi@988000 { 1302 compatible = "qcom,geni-spi"; 1303 reg = <0 0x00988000 0 0x4000>; 1304 clock-names = "se"; 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1306 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1307 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1308 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1309 dma-names = "tx", "rx"; 1310 power-domains = <&rpmhpd SM8250_CX>; 1311 operating-points-v2 = <&qup_opp_table>; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 status = "disabled"; 1315 }; 1316 1317 uart2: serial@988000 { 1318 compatible = "qcom,geni-debug-uart"; 1319 reg = <0 0x00988000 0 0x4000>; 1320 clock-names = "se"; 1321 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1322 pinctrl-names = "default"; 1323 pinctrl-0 = <&qup_uart2_default>; 1324 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1325 power-domains = <&rpmhpd SM8250_CX>; 1326 operating-points-v2 = <&qup_opp_table>; 1327 status = "disabled"; 1328 }; 1329 1330 i2c3: i2c@98c000 { 1331 compatible = "qcom,geni-i2c"; 1332 reg = <0 0x0098c000 0 0x4000>; 1333 clock-names = "se"; 1334 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&qup_i2c3_default>; 1337 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1338 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1339 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1340 dma-names = "tx", "rx"; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 spi3: spi@98c000 { 1347 compatible = "qcom,geni-spi"; 1348 reg = <0 0x0098c000 0 0x4000>; 1349 clock-names = "se"; 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1351 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1352 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1353 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1354 dma-names = "tx", "rx"; 1355 power-domains = <&rpmhpd SM8250_CX>; 1356 operating-points-v2 = <&qup_opp_table>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 status = "disabled"; 1360 }; 1361 1362 i2c4: i2c@990000 { 1363 compatible = "qcom,geni-i2c"; 1364 reg = <0 0x00990000 0 0x4000>; 1365 clock-names = "se"; 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1367 pinctrl-names = "default"; 1368 pinctrl-0 = <&qup_i2c4_default>; 1369 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1370 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1371 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1372 dma-names = "tx", "rx"; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 status = "disabled"; 1376 }; 1377 1378 spi4: spi@990000 { 1379 compatible = "qcom,geni-spi"; 1380 reg = <0 0x00990000 0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1383 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1384 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1385 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1386 dma-names = "tx", "rx"; 1387 power-domains = <&rpmhpd SM8250_CX>; 1388 operating-points-v2 = <&qup_opp_table>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 1394 i2c5: i2c@994000 { 1395 compatible = "qcom,geni-i2c"; 1396 reg = <0 0x00994000 0 0x4000>; 1397 clock-names = "se"; 1398 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1399 pinctrl-names = "default"; 1400 pinctrl-0 = <&qup_i2c5_default>; 1401 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1402 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1403 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1404 dma-names = "tx", "rx"; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 status = "disabled"; 1408 }; 1409 1410 spi5: spi@994000 { 1411 compatible = "qcom,geni-spi"; 1412 reg = <0 0x00994000 0 0x4000>; 1413 clock-names = "se"; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1415 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1416 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1417 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1418 dma-names = "tx", "rx"; 1419 power-domains = <&rpmhpd SM8250_CX>; 1420 operating-points-v2 = <&qup_opp_table>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 status = "disabled"; 1424 }; 1425 1426 i2c6: i2c@998000 { 1427 compatible = "qcom,geni-i2c"; 1428 reg = <0 0x00998000 0 0x4000>; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&qup_i2c6_default>; 1433 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1434 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1435 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1436 dma-names = "tx", "rx"; 1437 #address-cells = <1>; 1438 #size-cells = <0>; 1439 status = "disabled"; 1440 }; 1441 1442 spi6: spi@998000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00998000 0 0x4000>; 1445 clock-names = "se"; 1446 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1447 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1448 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1449 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1450 dma-names = "tx", "rx"; 1451 power-domains = <&rpmhpd SM8250_CX>; 1452 operating-points-v2 = <&qup_opp_table>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 status = "disabled"; 1456 }; 1457 1458 uart6: serial@998000 { 1459 compatible = "qcom,geni-uart"; 1460 reg = <0 0x00998000 0 0x4000>; 1461 clock-names = "se"; 1462 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_uart6_default>; 1465 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1466 power-domains = <&rpmhpd SM8250_CX>; 1467 operating-points-v2 = <&qup_opp_table>; 1468 status = "disabled"; 1469 }; 1470 1471 i2c7: i2c@99c000 { 1472 compatible = "qcom,geni-i2c"; 1473 reg = <0 0x0099c000 0 0x4000>; 1474 clock-names = "se"; 1475 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1476 pinctrl-names = "default"; 1477 pinctrl-0 = <&qup_i2c7_default>; 1478 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1479 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1480 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1481 dma-names = "tx", "rx"; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 status = "disabled"; 1485 }; 1486 1487 spi7: spi@99c000 { 1488 compatible = "qcom,geni-spi"; 1489 reg = <0 0x0099c000 0 0x4000>; 1490 clock-names = "se"; 1491 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1492 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1493 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1494 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1495 dma-names = "tx", "rx"; 1496 power-domains = <&rpmhpd SM8250_CX>; 1497 operating-points-v2 = <&qup_opp_table>; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 status = "disabled"; 1501 }; 1502 }; 1503 1504 gpi_dma1: dma-controller@a00000 { 1505 compatible = "qcom,sm8250-gpi-dma"; 1506 reg = <0 0x00a00000 0 0x70000>; 1507 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1517 dma-channels = <10>; 1518 dma-channel-mask = <0x3f>; 1519 iommus = <&apps_smmu 0x56 0x0>; 1520 #dma-cells = <3>; 1521 status = "disabled"; 1522 }; 1523 1524 qupv3_id_1: geniqup@ac0000 { 1525 compatible = "qcom,geni-se-qup"; 1526 reg = <0x0 0x00ac0000 0x0 0x6000>; 1527 clock-names = "m-ahb", "s-ahb"; 1528 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1529 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1530 #address-cells = <2>; 1531 #size-cells = <2>; 1532 iommus = <&apps_smmu 0x43 0x0>; 1533 ranges; 1534 status = "disabled"; 1535 1536 i2c8: i2c@a80000 { 1537 compatible = "qcom,geni-i2c"; 1538 reg = <0 0x00a80000 0 0x4000>; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&qup_i2c8_default>; 1543 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1544 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1545 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1546 dma-names = "tx", "rx"; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 status = "disabled"; 1550 }; 1551 1552 spi8: spi@a80000 { 1553 compatible = "qcom,geni-spi"; 1554 reg = <0 0x00a80000 0 0x4000>; 1555 clock-names = "se"; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1557 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1558 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1559 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1560 dma-names = "tx", "rx"; 1561 power-domains = <&rpmhpd SM8250_CX>; 1562 operating-points-v2 = <&qup_opp_table>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 status = "disabled"; 1566 }; 1567 1568 i2c9: i2c@a84000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0 0x00a84000 0 0x4000>; 1571 clock-names = "se"; 1572 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c9_default>; 1575 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1576 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1577 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1578 dma-names = "tx", "rx"; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 status = "disabled"; 1582 }; 1583 1584 spi9: spi@a84000 { 1585 compatible = "qcom,geni-spi"; 1586 reg = <0 0x00a84000 0 0x4000>; 1587 clock-names = "se"; 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1589 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1590 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1591 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1592 dma-names = "tx", "rx"; 1593 power-domains = <&rpmhpd SM8250_CX>; 1594 operating-points-v2 = <&qup_opp_table>; 1595 #address-cells = <1>; 1596 #size-cells = <0>; 1597 status = "disabled"; 1598 }; 1599 1600 i2c10: i2c@a88000 { 1601 compatible = "qcom,geni-i2c"; 1602 reg = <0 0x00a88000 0 0x4000>; 1603 clock-names = "se"; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1605 pinctrl-names = "default"; 1606 pinctrl-0 = <&qup_i2c10_default>; 1607 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1608 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1609 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1610 dma-names = "tx", "rx"; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 spi10: spi@a88000 { 1617 compatible = "qcom,geni-spi"; 1618 reg = <0 0x00a88000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1621 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1622 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1623 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1624 dma-names = "tx", "rx"; 1625 power-domains = <&rpmhpd SM8250_CX>; 1626 operating-points-v2 = <&qup_opp_table>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c11: i2c@a8c000 { 1633 compatible = "qcom,geni-i2c"; 1634 reg = <0 0x00a8c000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_i2c11_default>; 1639 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1640 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1641 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1642 dma-names = "tx", "rx"; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 spi11: spi@a8c000 { 1649 compatible = "qcom,geni-spi"; 1650 reg = <0 0x00a8c000 0 0x4000>; 1651 clock-names = "se"; 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1653 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1654 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1655 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1656 dma-names = "tx", "rx"; 1657 power-domains = <&rpmhpd SM8250_CX>; 1658 operating-points-v2 = <&qup_opp_table>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 status = "disabled"; 1662 }; 1663 1664 i2c12: i2c@a90000 { 1665 compatible = "qcom,geni-i2c"; 1666 reg = <0 0x00a90000 0 0x4000>; 1667 clock-names = "se"; 1668 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1669 pinctrl-names = "default"; 1670 pinctrl-0 = <&qup_i2c12_default>; 1671 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1672 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1673 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1674 dma-names = "tx", "rx"; 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 status = "disabled"; 1678 }; 1679 1680 spi12: spi@a90000 { 1681 compatible = "qcom,geni-spi"; 1682 reg = <0 0x00a90000 0 0x4000>; 1683 clock-names = "se"; 1684 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1685 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1686 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1687 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1688 dma-names = "tx", "rx"; 1689 power-domains = <&rpmhpd SM8250_CX>; 1690 operating-points-v2 = <&qup_opp_table>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 uart12: serial@a90000 { 1697 compatible = "qcom,geni-debug-uart"; 1698 reg = <0x0 0x00a90000 0x0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_uart12_default>; 1703 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1704 power-domains = <&rpmhpd SM8250_CX>; 1705 operating-points-v2 = <&qup_opp_table>; 1706 status = "disabled"; 1707 }; 1708 1709 i2c13: i2c@a94000 { 1710 compatible = "qcom,geni-i2c"; 1711 reg = <0 0x00a94000 0 0x4000>; 1712 clock-names = "se"; 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1714 pinctrl-names = "default"; 1715 pinctrl-0 = <&qup_i2c13_default>; 1716 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1717 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1718 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1719 dma-names = "tx", "rx"; 1720 #address-cells = <1>; 1721 #size-cells = <0>; 1722 status = "disabled"; 1723 }; 1724 1725 spi13: spi@a94000 { 1726 compatible = "qcom,geni-spi"; 1727 reg = <0 0x00a94000 0 0x4000>; 1728 clock-names = "se"; 1729 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1730 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1731 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1732 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1733 dma-names = "tx", "rx"; 1734 power-domains = <&rpmhpd SM8250_CX>; 1735 operating-points-v2 = <&qup_opp_table>; 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 status = "disabled"; 1739 }; 1740 }; 1741 1742 config_noc: interconnect@1500000 { 1743 compatible = "qcom,sm8250-config-noc"; 1744 reg = <0 0x01500000 0 0xa580>; 1745 #interconnect-cells = <1>; 1746 qcom,bcm-voters = <&apps_bcm_voter>; 1747 }; 1748 1749 system_noc: interconnect@1620000 { 1750 compatible = "qcom,sm8250-system-noc"; 1751 reg = <0 0x01620000 0 0x1c200>; 1752 #interconnect-cells = <1>; 1753 qcom,bcm-voters = <&apps_bcm_voter>; 1754 }; 1755 1756 mc_virt: interconnect@163d000 { 1757 compatible = "qcom,sm8250-mc-virt"; 1758 reg = <0 0x0163d000 0 0x1000>; 1759 #interconnect-cells = <1>; 1760 qcom,bcm-voters = <&apps_bcm_voter>; 1761 }; 1762 1763 aggre1_noc: interconnect@16e0000 { 1764 compatible = "qcom,sm8250-aggre1-noc"; 1765 reg = <0 0x016e0000 0 0x1f180>; 1766 #interconnect-cells = <1>; 1767 qcom,bcm-voters = <&apps_bcm_voter>; 1768 }; 1769 1770 aggre2_noc: interconnect@1700000 { 1771 compatible = "qcom,sm8250-aggre2-noc"; 1772 reg = <0 0x01700000 0 0x33000>; 1773 #interconnect-cells = <1>; 1774 qcom,bcm-voters = <&apps_bcm_voter>; 1775 }; 1776 1777 compute_noc: interconnect@1733000 { 1778 compatible = "qcom,sm8250-compute-noc"; 1779 reg = <0 0x01733000 0 0xa180>; 1780 #interconnect-cells = <1>; 1781 qcom,bcm-voters = <&apps_bcm_voter>; 1782 }; 1783 1784 mmss_noc: interconnect@1740000 { 1785 compatible = "qcom,sm8250-mmss-noc"; 1786 reg = <0 0x01740000 0 0x1f080>; 1787 #interconnect-cells = <1>; 1788 qcom,bcm-voters = <&apps_bcm_voter>; 1789 }; 1790 1791 pcie0: pci@1c00000 { 1792 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1793 reg = <0 0x01c00000 0 0x3000>, 1794 <0 0x60000000 0 0xf1d>, 1795 <0 0x60000f20 0 0xa8>, 1796 <0 0x60001000 0 0x1000>, 1797 <0 0x60100000 0 0x100000>; 1798 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1799 device_type = "pci"; 1800 linux,pci-domain = <0>; 1801 bus-range = <0x00 0xff>; 1802 num-lanes = <1>; 1803 1804 #address-cells = <3>; 1805 #size-cells = <2>; 1806 1807 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1808 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1809 1810 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1811 interrupt-names = "msi"; 1812 #interrupt-cells = <1>; 1813 interrupt-map-mask = <0 0 0 0x7>; 1814 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1815 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1816 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1817 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1818 1819 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1820 <&gcc GCC_PCIE_0_AUX_CLK>, 1821 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1822 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1823 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1824 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1825 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1826 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1827 clock-names = "pipe", 1828 "aux", 1829 "cfg", 1830 "bus_master", 1831 "bus_slave", 1832 "slave_q2a", 1833 "tbu", 1834 "ddrss_sf_tbu"; 1835 1836 iommus = <&apps_smmu 0x1c00 0x7f>; 1837 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1838 <0x100 &apps_smmu 0x1c01 0x1>; 1839 1840 resets = <&gcc GCC_PCIE_0_BCR>; 1841 reset-names = "pci"; 1842 1843 power-domains = <&gcc PCIE_0_GDSC>; 1844 1845 phys = <&pcie0_lane>; 1846 phy-names = "pciephy"; 1847 1848 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1849 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1850 1851 pinctrl-names = "default"; 1852 pinctrl-0 = <&pcie0_default_state>; 1853 1854 status = "disabled"; 1855 }; 1856 1857 pcie0_phy: phy@1c06000 { 1858 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1859 reg = <0 0x01c06000 0 0x1c0>; 1860 #address-cells = <2>; 1861 #size-cells = <2>; 1862 ranges; 1863 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1864 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1865 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1866 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1867 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1868 1869 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1870 reset-names = "phy"; 1871 1872 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1873 assigned-clock-rates = <100000000>; 1874 1875 status = "disabled"; 1876 1877 pcie0_lane: phy@1c06200 { 1878 reg = <0 0x1c06200 0 0x170>, /* tx */ 1879 <0 0x1c06400 0 0x200>, /* rx */ 1880 <0 0x1c06800 0 0x1f0>, /* pcs */ 1881 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1882 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1883 clock-names = "pipe0"; 1884 1885 #phy-cells = <0>; 1886 clock-output-names = "pcie_0_pipe_clk"; 1887 }; 1888 }; 1889 1890 pcie1: pci@1c08000 { 1891 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1892 reg = <0 0x01c08000 0 0x3000>, 1893 <0 0x40000000 0 0xf1d>, 1894 <0 0x40000f20 0 0xa8>, 1895 <0 0x40001000 0 0x1000>, 1896 <0 0x40100000 0 0x100000>; 1897 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1898 device_type = "pci"; 1899 linux,pci-domain = <1>; 1900 bus-range = <0x00 0xff>; 1901 num-lanes = <2>; 1902 1903 #address-cells = <3>; 1904 #size-cells = <2>; 1905 1906 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1907 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1908 1909 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1910 interrupt-names = "msi"; 1911 #interrupt-cells = <1>; 1912 interrupt-map-mask = <0 0 0 0x7>; 1913 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1914 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1915 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1916 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1917 1918 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1919 <&gcc GCC_PCIE_1_AUX_CLK>, 1920 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1921 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1922 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1923 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1924 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1925 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1926 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1927 clock-names = "pipe", 1928 "aux", 1929 "cfg", 1930 "bus_master", 1931 "bus_slave", 1932 "slave_q2a", 1933 "ref", 1934 "tbu", 1935 "ddrss_sf_tbu"; 1936 1937 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1938 assigned-clock-rates = <19200000>; 1939 1940 iommus = <&apps_smmu 0x1c80 0x7f>; 1941 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1942 <0x100 &apps_smmu 0x1c81 0x1>; 1943 1944 resets = <&gcc GCC_PCIE_1_BCR>; 1945 reset-names = "pci"; 1946 1947 power-domains = <&gcc PCIE_1_GDSC>; 1948 1949 phys = <&pcie1_lane>; 1950 phy-names = "pciephy"; 1951 1952 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 1953 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1954 1955 pinctrl-names = "default"; 1956 pinctrl-0 = <&pcie1_default_state>; 1957 1958 status = "disabled"; 1959 }; 1960 1961 pcie1_phy: phy@1c0e000 { 1962 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1963 reg = <0 0x01c0e000 0 0x1c0>; 1964 #address-cells = <2>; 1965 #size-cells = <2>; 1966 ranges; 1967 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1968 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1969 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1970 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1971 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1972 1973 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1974 reset-names = "phy"; 1975 1976 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1977 assigned-clock-rates = <100000000>; 1978 1979 status = "disabled"; 1980 1981 pcie1_lane: phy@1c0e200 { 1982 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1983 <0 0x1c0e400 0 0x200>, /* rx0 */ 1984 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1985 <0 0x1c0e600 0 0x170>, /* tx1 */ 1986 <0 0x1c0e800 0 0x200>, /* rx1 */ 1987 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1988 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1989 clock-names = "pipe0"; 1990 1991 #phy-cells = <0>; 1992 clock-output-names = "pcie_1_pipe_clk"; 1993 }; 1994 }; 1995 1996 pcie2: pci@1c10000 { 1997 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1998 reg = <0 0x01c10000 0 0x3000>, 1999 <0 0x64000000 0 0xf1d>, 2000 <0 0x64000f20 0 0xa8>, 2001 <0 0x64001000 0 0x1000>, 2002 <0 0x64100000 0 0x100000>; 2003 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2004 device_type = "pci"; 2005 linux,pci-domain = <2>; 2006 bus-range = <0x00 0xff>; 2007 num-lanes = <2>; 2008 2009 #address-cells = <3>; 2010 #size-cells = <2>; 2011 2012 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 2013 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2014 2015 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2016 interrupt-names = "msi"; 2017 #interrupt-cells = <1>; 2018 interrupt-map-mask = <0 0 0 0x7>; 2019 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2020 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2021 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2022 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2023 2024 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2025 <&gcc GCC_PCIE_2_AUX_CLK>, 2026 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2027 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2028 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2029 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2030 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2031 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2032 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2033 clock-names = "pipe", 2034 "aux", 2035 "cfg", 2036 "bus_master", 2037 "bus_slave", 2038 "slave_q2a", 2039 "ref", 2040 "tbu", 2041 "ddrss_sf_tbu"; 2042 2043 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2044 assigned-clock-rates = <19200000>; 2045 2046 iommus = <&apps_smmu 0x1d00 0x7f>; 2047 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2048 <0x100 &apps_smmu 0x1d01 0x1>; 2049 2050 resets = <&gcc GCC_PCIE_2_BCR>; 2051 reset-names = "pci"; 2052 2053 power-domains = <&gcc PCIE_2_GDSC>; 2054 2055 phys = <&pcie2_lane>; 2056 phy-names = "pciephy"; 2057 2058 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2059 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2060 2061 pinctrl-names = "default"; 2062 pinctrl-0 = <&pcie2_default_state>; 2063 2064 status = "disabled"; 2065 }; 2066 2067 pcie2_phy: phy@1c16000 { 2068 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2069 reg = <0 0x1c16000 0 0x1c0>; 2070 #address-cells = <2>; 2071 #size-cells = <2>; 2072 ranges; 2073 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2074 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2075 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2076 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2077 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2078 2079 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2080 reset-names = "phy"; 2081 2082 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2083 assigned-clock-rates = <100000000>; 2084 2085 status = "disabled"; 2086 2087 pcie2_lane: phy@1c16200 { 2088 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 2089 <0 0x1c16400 0 0x200>, /* rx0 */ 2090 <0 0x1c16a00 0 0x1f0>, /* pcs */ 2091 <0 0x1c16600 0 0x170>, /* tx1 */ 2092 <0 0x1c16800 0 0x200>, /* rx1 */ 2093 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2094 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2095 clock-names = "pipe0"; 2096 2097 #phy-cells = <0>; 2098 clock-output-names = "pcie_2_pipe_clk"; 2099 }; 2100 }; 2101 2102 ufs_mem_hc: ufshc@1d84000 { 2103 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2104 "jedec,ufs-2.0"; 2105 reg = <0 0x01d84000 0 0x3000>; 2106 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2107 phys = <&ufs_mem_phy_lanes>; 2108 phy-names = "ufsphy"; 2109 lanes-per-direction = <2>; 2110 #reset-cells = <1>; 2111 resets = <&gcc GCC_UFS_PHY_BCR>; 2112 reset-names = "rst"; 2113 2114 power-domains = <&gcc UFS_PHY_GDSC>; 2115 2116 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2117 2118 clock-names = 2119 "core_clk", 2120 "bus_aggr_clk", 2121 "iface_clk", 2122 "core_clk_unipro", 2123 "ref_clk", 2124 "tx_lane0_sync_clk", 2125 "rx_lane0_sync_clk", 2126 "rx_lane1_sync_clk"; 2127 clocks = 2128 <&gcc GCC_UFS_PHY_AXI_CLK>, 2129 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2130 <&gcc GCC_UFS_PHY_AHB_CLK>, 2131 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2132 <&rpmhcc RPMH_CXO_CLK>, 2133 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2134 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2135 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2136 freq-table-hz = 2137 <37500000 300000000>, 2138 <0 0>, 2139 <0 0>, 2140 <37500000 300000000>, 2141 <0 0>, 2142 <0 0>, 2143 <0 0>, 2144 <0 0>; 2145 2146 status = "disabled"; 2147 }; 2148 2149 ufs_mem_phy: phy@1d87000 { 2150 compatible = "qcom,sm8250-qmp-ufs-phy"; 2151 reg = <0 0x01d87000 0 0x1c0>; 2152 #address-cells = <2>; 2153 #size-cells = <2>; 2154 ranges; 2155 clock-names = "ref", 2156 "ref_aux"; 2157 clocks = <&rpmhcc RPMH_CXO_CLK>, 2158 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2159 2160 resets = <&ufs_mem_hc 0>; 2161 reset-names = "ufsphy"; 2162 status = "disabled"; 2163 2164 ufs_mem_phy_lanes: phy@1d87400 { 2165 reg = <0 0x01d87400 0 0x108>, 2166 <0 0x01d87600 0 0x1e0>, 2167 <0 0x01d87c00 0 0x1dc>, 2168 <0 0x01d87800 0 0x108>, 2169 <0 0x01d87a00 0 0x1e0>; 2170 #phy-cells = <0>; 2171 }; 2172 }; 2173 2174 ipa_virt: interconnect@1e00000 { 2175 compatible = "qcom,sm8250-ipa-virt"; 2176 reg = <0 0x01e00000 0 0x1000>; 2177 #interconnect-cells = <1>; 2178 qcom,bcm-voters = <&apps_bcm_voter>; 2179 }; 2180 2181 tcsr_mutex: hwlock@1f40000 { 2182 compatible = "qcom,tcsr-mutex"; 2183 reg = <0x0 0x01f40000 0x0 0x40000>; 2184 #hwlock-cells = <1>; 2185 }; 2186 2187 wsamacro: codec@3240000 { 2188 compatible = "qcom,sm8250-lpass-wsa-macro"; 2189 reg = <0 0x03240000 0 0x1000>; 2190 clocks = <&audiocc 1>, 2191 <&audiocc 0>, 2192 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2193 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2194 <&aoncc 0>, 2195 <&vamacro>; 2196 2197 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2198 2199 #clock-cells = <0>; 2200 clock-frequency = <9600000>; 2201 clock-output-names = "mclk"; 2202 #sound-dai-cells = <1>; 2203 2204 pinctrl-names = "default"; 2205 pinctrl-0 = <&wsa_swr_active>; 2206 }; 2207 2208 swr0: soundwire-controller@3250000 { 2209 reg = <0 0x03250000 0 0x2000>; 2210 compatible = "qcom,soundwire-v1.5.1"; 2211 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2212 clocks = <&wsamacro>; 2213 clock-names = "iface"; 2214 2215 qcom,din-ports = <2>; 2216 qcom,dout-ports = <6>; 2217 2218 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2219 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2220 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2221 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2222 2223 #sound-dai-cells = <1>; 2224 #address-cells = <2>; 2225 #size-cells = <0>; 2226 }; 2227 2228 audiocc: clock-controller@3300000 { 2229 compatible = "qcom,sm8250-lpass-audiocc"; 2230 reg = <0 0x03300000 0 0x30000>; 2231 #clock-cells = <1>; 2232 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2233 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2234 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2235 clock-names = "core", "audio", "bus"; 2236 }; 2237 2238 vamacro: codec@3370000 { 2239 compatible = "qcom,sm8250-lpass-va-macro"; 2240 reg = <0 0x03370000 0 0x1000>; 2241 clocks = <&aoncc 0>, 2242 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2243 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2244 2245 clock-names = "mclk", "macro", "dcodec"; 2246 2247 #clock-cells = <0>; 2248 clock-frequency = <9600000>; 2249 clock-output-names = "fsgen"; 2250 #sound-dai-cells = <1>; 2251 }; 2252 2253 rxmacro: rxmacro@3200000 { 2254 pinctrl-names = "default"; 2255 pinctrl-0 = <&rx_swr_active>; 2256 compatible = "qcom,sm8250-lpass-rx-macro"; 2257 reg = <0 0x3200000 0 0x1000>; 2258 status = "disabled"; 2259 2260 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2261 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2262 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2263 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2264 <&vamacro>; 2265 2266 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2267 2268 #clock-cells = <0>; 2269 clock-frequency = <9600000>; 2270 clock-output-names = "mclk"; 2271 #sound-dai-cells = <1>; 2272 }; 2273 2274 swr1: soundwire-controller@3210000 { 2275 reg = <0 0x3210000 0 0x2000>; 2276 compatible = "qcom,soundwire-v1.5.1"; 2277 status = "disabled"; 2278 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&rxmacro>; 2280 clock-names = "iface"; 2281 label = "RX"; 2282 qcom,din-ports = <0>; 2283 qcom,dout-ports = <5>; 2284 2285 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; 2286 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2287 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2288 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; 2289 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; 2290 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; 2291 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; 2292 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2293 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; 2294 2295 #sound-dai-cells = <1>; 2296 #address-cells = <2>; 2297 #size-cells = <0>; 2298 }; 2299 2300 txmacro: txmacro@3220000 { 2301 pinctrl-names = "default"; 2302 pinctrl-0 = <&tx_swr_active>; 2303 compatible = "qcom,sm8250-lpass-tx-macro"; 2304 reg = <0 0x3220000 0 0x1000>; 2305 status = "disabled"; 2306 2307 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2308 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2309 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2310 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2311 <&vamacro>; 2312 2313 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2314 2315 #clock-cells = <0>; 2316 clock-frequency = <9600000>; 2317 clock-output-names = "mclk"; 2318 #address-cells = <2>; 2319 #size-cells = <2>; 2320 #sound-dai-cells = <1>; 2321 }; 2322 2323 /* tx macro */ 2324 swr2: soundwire-controller@3230000 { 2325 reg = <0 0x3230000 0 0x2000>; 2326 compatible = "qcom,soundwire-v1.5.1"; 2327 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2328 interrupt-names = "core"; 2329 status = "disabled"; 2330 2331 clocks = <&txmacro>; 2332 clock-names = "iface"; 2333 label = "TX"; 2334 2335 qcom,din-ports = <5>; 2336 qcom,dout-ports = <0>; 2337 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; 2338 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; 2339 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; 2340 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2341 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2342 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2343 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2344 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; 2345 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; 2346 qcom,port-offset = <1>; 2347 #sound-dai-cells = <1>; 2348 #address-cells = <2>; 2349 #size-cells = <0>; 2350 }; 2351 2352 aoncc: clock-controller@3380000 { 2353 compatible = "qcom,sm8250-lpass-aoncc"; 2354 reg = <0 0x03380000 0 0x40000>; 2355 #clock-cells = <1>; 2356 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2357 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2358 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2359 clock-names = "core", "audio", "bus"; 2360 }; 2361 2362 lpass_tlmm: pinctrl@33c0000{ 2363 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2364 reg = <0 0x033c0000 0x0 0x20000>, 2365 <0 0x03550000 0x0 0x10000>; 2366 gpio-controller; 2367 #gpio-cells = <2>; 2368 gpio-ranges = <&lpass_tlmm 0 0 14>; 2369 2370 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2371 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2372 clock-names = "core", "audio"; 2373 2374 wsa_swr_active: wsa-swr-active-pins { 2375 clk { 2376 pins = "gpio10"; 2377 function = "wsa_swr_clk"; 2378 drive-strength = <2>; 2379 slew-rate = <1>; 2380 bias-disable; 2381 }; 2382 2383 data { 2384 pins = "gpio11"; 2385 function = "wsa_swr_data"; 2386 drive-strength = <2>; 2387 slew-rate = <1>; 2388 bias-bus-hold; 2389 2390 }; 2391 }; 2392 2393 wsa_swr_sleep: wsa-swr-sleep-pins { 2394 clk { 2395 pins = "gpio10"; 2396 function = "wsa_swr_clk"; 2397 drive-strength = <2>; 2398 input-enable; 2399 bias-pull-down; 2400 }; 2401 2402 data { 2403 pins = "gpio11"; 2404 function = "wsa_swr_data"; 2405 drive-strength = <2>; 2406 input-enable; 2407 bias-pull-down; 2408 2409 }; 2410 }; 2411 2412 dmic01_active: dmic01-active-pins { 2413 clk { 2414 pins = "gpio6"; 2415 function = "dmic1_clk"; 2416 drive-strength = <8>; 2417 output-high; 2418 }; 2419 data { 2420 pins = "gpio7"; 2421 function = "dmic1_data"; 2422 drive-strength = <8>; 2423 input-enable; 2424 }; 2425 }; 2426 2427 dmic01_sleep: dmic01-sleep-pins { 2428 clk { 2429 pins = "gpio6"; 2430 function = "dmic1_clk"; 2431 drive-strength = <2>; 2432 bias-disable; 2433 output-low; 2434 }; 2435 2436 data { 2437 pins = "gpio7"; 2438 function = "dmic1_data"; 2439 drive-strength = <2>; 2440 pull-down; 2441 input-enable; 2442 }; 2443 }; 2444 2445 rx_swr_active: rx_swr-active-pins { 2446 clk { 2447 pins = "gpio3"; 2448 function = "swr_rx_clk"; 2449 drive-strength = <2>; 2450 slew-rate = <1>; 2451 bias-disable; 2452 }; 2453 2454 data { 2455 pins = "gpio4", "gpio5"; 2456 function = "swr_rx_data"; 2457 drive-strength = <2>; 2458 slew-rate = <1>; 2459 bias-bus-hold; 2460 }; 2461 }; 2462 2463 tx_swr_active: tx_swr-active-pins { 2464 clk { 2465 pins = "gpio0"; 2466 function = "swr_tx_clk"; 2467 drive-strength = <2>; 2468 slew-rate = <1>; 2469 bias-disable; 2470 }; 2471 2472 data { 2473 pins = "gpio1", "gpio2"; 2474 function = "swr_tx_data"; 2475 drive-strength = <2>; 2476 slew-rate = <1>; 2477 bias-bus-hold; 2478 }; 2479 }; 2480 2481 tx_swr_sleep: tx_swr-sleep-pins { 2482 clk { 2483 pins = "gpio0"; 2484 function = "swr_tx_clk"; 2485 drive-strength = <2>; 2486 input-enable; 2487 bias-pull-down; 2488 }; 2489 2490 data1 { 2491 pins = "gpio1"; 2492 function = "swr_tx_data"; 2493 drive-strength = <2>; 2494 input-enable; 2495 bias-bus-hold; 2496 }; 2497 2498 data2 { 2499 pins = "gpio2"; 2500 function = "swr_tx_data"; 2501 drive-strength = <2>; 2502 input-enable; 2503 bias-pull-down; 2504 }; 2505 }; 2506 }; 2507 2508 gpu: gpu@3d00000 { 2509 compatible = "qcom,adreno-650.2", 2510 "qcom,adreno"; 2511 2512 reg = <0 0x03d00000 0 0x40000>; 2513 reg-names = "kgsl_3d0_reg_memory"; 2514 2515 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2516 2517 iommus = <&adreno_smmu 0 0x401>; 2518 2519 operating-points-v2 = <&gpu_opp_table>; 2520 2521 qcom,gmu = <&gmu>; 2522 2523 status = "disabled"; 2524 2525 zap-shader { 2526 memory-region = <&gpu_mem>; 2527 }; 2528 2529 /* note: downstream checks gpu binning for 670 Mhz */ 2530 gpu_opp_table: opp-table { 2531 compatible = "operating-points-v2"; 2532 2533 opp-670000000 { 2534 opp-hz = /bits/ 64 <670000000>; 2535 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2536 }; 2537 2538 opp-587000000 { 2539 opp-hz = /bits/ 64 <587000000>; 2540 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2541 }; 2542 2543 opp-525000000 { 2544 opp-hz = /bits/ 64 <525000000>; 2545 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2546 }; 2547 2548 opp-490000000 { 2549 opp-hz = /bits/ 64 <490000000>; 2550 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2551 }; 2552 2553 opp-441600000 { 2554 opp-hz = /bits/ 64 <441600000>; 2555 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2556 }; 2557 2558 opp-400000000 { 2559 opp-hz = /bits/ 64 <400000000>; 2560 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2561 }; 2562 2563 opp-305000000 { 2564 opp-hz = /bits/ 64 <305000000>; 2565 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2566 }; 2567 }; 2568 }; 2569 2570 gmu: gmu@3d6a000 { 2571 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2572 2573 reg = <0 0x03d6a000 0 0x30000>, 2574 <0 0x3de0000 0 0x10000>, 2575 <0 0xb290000 0 0x10000>, 2576 <0 0xb490000 0 0x10000>; 2577 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2578 2579 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2581 interrupt-names = "hfi", "gmu"; 2582 2583 clocks = <&gpucc GPU_CC_AHB_CLK>, 2584 <&gpucc GPU_CC_CX_GMU_CLK>, 2585 <&gpucc GPU_CC_CXO_CLK>, 2586 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2587 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2588 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2589 2590 power-domains = <&gpucc GPU_CX_GDSC>, 2591 <&gpucc GPU_GX_GDSC>; 2592 power-domain-names = "cx", "gx"; 2593 2594 iommus = <&adreno_smmu 5 0x400>; 2595 2596 operating-points-v2 = <&gmu_opp_table>; 2597 2598 status = "disabled"; 2599 2600 gmu_opp_table: opp-table { 2601 compatible = "operating-points-v2"; 2602 2603 opp-200000000 { 2604 opp-hz = /bits/ 64 <200000000>; 2605 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2606 }; 2607 }; 2608 }; 2609 2610 gpucc: clock-controller@3d90000 { 2611 compatible = "qcom,sm8250-gpucc"; 2612 reg = <0 0x03d90000 0 0x9000>; 2613 clocks = <&rpmhcc RPMH_CXO_CLK>, 2614 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2615 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2616 clock-names = "bi_tcxo", 2617 "gcc_gpu_gpll0_clk_src", 2618 "gcc_gpu_gpll0_div_clk_src"; 2619 #clock-cells = <1>; 2620 #reset-cells = <1>; 2621 #power-domain-cells = <1>; 2622 }; 2623 2624 adreno_smmu: iommu@3da0000 { 2625 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 2626 reg = <0 0x03da0000 0 0x10000>; 2627 #iommu-cells = <2>; 2628 #global-interrupts = <2>; 2629 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2630 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2631 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2632 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2633 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2634 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2635 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2636 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2637 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2638 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2639 clocks = <&gpucc GPU_CC_AHB_CLK>, 2640 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2641 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2642 clock-names = "ahb", "bus", "iface"; 2643 2644 power-domains = <&gpucc GPU_CX_GDSC>; 2645 }; 2646 2647 slpi: remoteproc@5c00000 { 2648 compatible = "qcom,sm8250-slpi-pas"; 2649 reg = <0 0x05c00000 0 0x4000>; 2650 2651 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2652 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2653 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2654 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2655 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2656 interrupt-names = "wdog", "fatal", "ready", 2657 "handover", "stop-ack"; 2658 2659 clocks = <&rpmhcc RPMH_CXO_CLK>; 2660 clock-names = "xo"; 2661 2662 power-domains = <&rpmhpd SM8250_LCX>, 2663 <&rpmhpd SM8250_LMX>; 2664 power-domain-names = "lcx", "lmx"; 2665 2666 memory-region = <&slpi_mem>; 2667 2668 qcom,qmp = <&aoss_qmp>; 2669 2670 qcom,smem-states = <&smp2p_slpi_out 0>; 2671 qcom,smem-state-names = "stop"; 2672 2673 status = "disabled"; 2674 2675 glink-edge { 2676 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2677 IPCC_MPROC_SIGNAL_GLINK_QMP 2678 IRQ_TYPE_EDGE_RISING>; 2679 mboxes = <&ipcc IPCC_CLIENT_SLPI 2680 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2681 2682 label = "slpi"; 2683 qcom,remote-pid = <3>; 2684 2685 fastrpc { 2686 compatible = "qcom,fastrpc"; 2687 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2688 label = "sdsp"; 2689 qcom,non-secure-domain; 2690 #address-cells = <1>; 2691 #size-cells = <0>; 2692 2693 compute-cb@1 { 2694 compatible = "qcom,fastrpc-compute-cb"; 2695 reg = <1>; 2696 iommus = <&apps_smmu 0x0541 0x0>; 2697 }; 2698 2699 compute-cb@2 { 2700 compatible = "qcom,fastrpc-compute-cb"; 2701 reg = <2>; 2702 iommus = <&apps_smmu 0x0542 0x0>; 2703 }; 2704 2705 compute-cb@3 { 2706 compatible = "qcom,fastrpc-compute-cb"; 2707 reg = <3>; 2708 iommus = <&apps_smmu 0x0543 0x0>; 2709 /* note: shared-cb = <4> in downstream */ 2710 }; 2711 }; 2712 }; 2713 }; 2714 2715 cdsp: remoteproc@8300000 { 2716 compatible = "qcom,sm8250-cdsp-pas"; 2717 reg = <0 0x08300000 0 0x10000>; 2718 2719 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2720 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2721 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2722 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2723 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2724 interrupt-names = "wdog", "fatal", "ready", 2725 "handover", "stop-ack"; 2726 2727 clocks = <&rpmhcc RPMH_CXO_CLK>; 2728 clock-names = "xo"; 2729 2730 power-domains = <&rpmhpd SM8250_CX>; 2731 2732 memory-region = <&cdsp_mem>; 2733 2734 qcom,qmp = <&aoss_qmp>; 2735 2736 qcom,smem-states = <&smp2p_cdsp_out 0>; 2737 qcom,smem-state-names = "stop"; 2738 2739 status = "disabled"; 2740 2741 glink-edge { 2742 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2743 IPCC_MPROC_SIGNAL_GLINK_QMP 2744 IRQ_TYPE_EDGE_RISING>; 2745 mboxes = <&ipcc IPCC_CLIENT_CDSP 2746 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2747 2748 label = "cdsp"; 2749 qcom,remote-pid = <5>; 2750 2751 fastrpc { 2752 compatible = "qcom,fastrpc"; 2753 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2754 label = "cdsp"; 2755 qcom,non-secure-domain; 2756 #address-cells = <1>; 2757 #size-cells = <0>; 2758 2759 compute-cb@1 { 2760 compatible = "qcom,fastrpc-compute-cb"; 2761 reg = <1>; 2762 iommus = <&apps_smmu 0x1001 0x0460>; 2763 }; 2764 2765 compute-cb@2 { 2766 compatible = "qcom,fastrpc-compute-cb"; 2767 reg = <2>; 2768 iommus = <&apps_smmu 0x1002 0x0460>; 2769 }; 2770 2771 compute-cb@3 { 2772 compatible = "qcom,fastrpc-compute-cb"; 2773 reg = <3>; 2774 iommus = <&apps_smmu 0x1003 0x0460>; 2775 }; 2776 2777 compute-cb@4 { 2778 compatible = "qcom,fastrpc-compute-cb"; 2779 reg = <4>; 2780 iommus = <&apps_smmu 0x1004 0x0460>; 2781 }; 2782 2783 compute-cb@5 { 2784 compatible = "qcom,fastrpc-compute-cb"; 2785 reg = <5>; 2786 iommus = <&apps_smmu 0x1005 0x0460>; 2787 }; 2788 2789 compute-cb@6 { 2790 compatible = "qcom,fastrpc-compute-cb"; 2791 reg = <6>; 2792 iommus = <&apps_smmu 0x1006 0x0460>; 2793 }; 2794 2795 compute-cb@7 { 2796 compatible = "qcom,fastrpc-compute-cb"; 2797 reg = <7>; 2798 iommus = <&apps_smmu 0x1007 0x0460>; 2799 }; 2800 2801 compute-cb@8 { 2802 compatible = "qcom,fastrpc-compute-cb"; 2803 reg = <8>; 2804 iommus = <&apps_smmu 0x1008 0x0460>; 2805 }; 2806 2807 /* note: secure cb9 in downstream */ 2808 }; 2809 }; 2810 }; 2811 2812 sound: sound { 2813 }; 2814 2815 usb_1_hsphy: phy@88e3000 { 2816 compatible = "qcom,sm8250-usb-hs-phy", 2817 "qcom,usb-snps-hs-7nm-phy"; 2818 reg = <0 0x088e3000 0 0x400>; 2819 status = "disabled"; 2820 #phy-cells = <0>; 2821 2822 clocks = <&rpmhcc RPMH_CXO_CLK>; 2823 clock-names = "ref"; 2824 2825 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2826 }; 2827 2828 usb_2_hsphy: phy@88e4000 { 2829 compatible = "qcom,sm8250-usb-hs-phy", 2830 "qcom,usb-snps-hs-7nm-phy"; 2831 reg = <0 0x088e4000 0 0x400>; 2832 status = "disabled"; 2833 #phy-cells = <0>; 2834 2835 clocks = <&rpmhcc RPMH_CXO_CLK>; 2836 clock-names = "ref"; 2837 2838 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2839 }; 2840 2841 usb_1_qmpphy: phy@88e9000 { 2842 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2843 reg = <0 0x088e9000 0 0x200>, 2844 <0 0x088e8000 0 0x40>, 2845 <0 0x088ea000 0 0x200>; 2846 status = "disabled"; 2847 #address-cells = <2>; 2848 #size-cells = <2>; 2849 ranges; 2850 2851 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2852 <&rpmhcc RPMH_CXO_CLK>, 2853 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2854 clock-names = "aux", "ref_clk_src", "com_aux"; 2855 2856 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2857 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2858 reset-names = "phy", "common"; 2859 2860 usb_1_ssphy: usb3-phy@88e9200 { 2861 reg = <0 0x088e9200 0 0x200>, 2862 <0 0x088e9400 0 0x200>, 2863 <0 0x088e9c00 0 0x400>, 2864 <0 0x088e9600 0 0x200>, 2865 <0 0x088e9800 0 0x200>, 2866 <0 0x088e9a00 0 0x100>; 2867 #clock-cells = <0>; 2868 #phy-cells = <0>; 2869 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2870 clock-names = "pipe0"; 2871 clock-output-names = "usb3_phy_pipe_clk_src"; 2872 }; 2873 2874 dp_phy: dp-phy@88ea200 { 2875 reg = <0 0x088ea200 0 0x200>, 2876 <0 0x088ea400 0 0x200>, 2877 <0 0x088eac00 0 0x400>, 2878 <0 0x088ea600 0 0x200>, 2879 <0 0x088ea800 0 0x200>, 2880 <0 0x088eaa00 0 0x100>; 2881 #phy-cells = <0>; 2882 #clock-cells = <1>; 2883 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2884 clock-names = "pipe0"; 2885 clock-output-names = "usb3_phy_pipe_clk_src"; 2886 }; 2887 }; 2888 2889 usb_2_qmpphy: phy@88eb000 { 2890 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2891 reg = <0 0x088eb000 0 0x200>; 2892 status = "disabled"; 2893 #address-cells = <2>; 2894 #size-cells = <2>; 2895 ranges; 2896 2897 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2898 <&rpmhcc RPMH_CXO_CLK>, 2899 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2900 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2901 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2902 2903 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2904 <&gcc GCC_USB3_PHY_SEC_BCR>; 2905 reset-names = "phy", "common"; 2906 2907 usb_2_ssphy: phy@88eb200 { 2908 reg = <0 0x088eb200 0 0x200>, 2909 <0 0x088eb400 0 0x200>, 2910 <0 0x088eb800 0 0x800>; 2911 #clock-cells = <0>; 2912 #phy-cells = <0>; 2913 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2914 clock-names = "pipe0"; 2915 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2916 }; 2917 }; 2918 2919 sdhc_2: sdhci@8804000 { 2920 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2921 reg = <0 0x08804000 0 0x1000>; 2922 2923 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2924 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2925 interrupt-names = "hc_irq", "pwr_irq"; 2926 2927 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2928 <&gcc GCC_SDCC2_APPS_CLK>, 2929 <&rpmhcc RPMH_CXO_CLK>; 2930 clock-names = "iface", "core", "xo"; 2931 iommus = <&apps_smmu 0x4a0 0x0>; 2932 qcom,dll-config = <0x0007642c>; 2933 qcom,ddr-config = <0x80040868>; 2934 power-domains = <&rpmhpd SM8250_CX>; 2935 operating-points-v2 = <&sdhc2_opp_table>; 2936 2937 status = "disabled"; 2938 2939 sdhc2_opp_table: sdhc2-opp-table { 2940 compatible = "operating-points-v2"; 2941 2942 opp-19200000 { 2943 opp-hz = /bits/ 64 <19200000>; 2944 required-opps = <&rpmhpd_opp_min_svs>; 2945 }; 2946 2947 opp-50000000 { 2948 opp-hz = /bits/ 64 <50000000>; 2949 required-opps = <&rpmhpd_opp_low_svs>; 2950 }; 2951 2952 opp-100000000 { 2953 opp-hz = /bits/ 64 <100000000>; 2954 required-opps = <&rpmhpd_opp_svs>; 2955 }; 2956 2957 opp-202000000 { 2958 opp-hz = /bits/ 64 <202000000>; 2959 required-opps = <&rpmhpd_opp_svs_l1>; 2960 }; 2961 }; 2962 }; 2963 2964 dc_noc: interconnect@90c0000 { 2965 compatible = "qcom,sm8250-dc-noc"; 2966 reg = <0 0x090c0000 0 0x4200>; 2967 #interconnect-cells = <1>; 2968 qcom,bcm-voters = <&apps_bcm_voter>; 2969 }; 2970 2971 gem_noc: interconnect@9100000 { 2972 compatible = "qcom,sm8250-gem-noc"; 2973 reg = <0 0x09100000 0 0xb4000>; 2974 #interconnect-cells = <1>; 2975 qcom,bcm-voters = <&apps_bcm_voter>; 2976 }; 2977 2978 npu_noc: interconnect@9990000 { 2979 compatible = "qcom,sm8250-npu-noc"; 2980 reg = <0 0x09990000 0 0x1600>; 2981 #interconnect-cells = <1>; 2982 qcom,bcm-voters = <&apps_bcm_voter>; 2983 }; 2984 2985 usb_1: usb@a6f8800 { 2986 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2987 reg = <0 0x0a6f8800 0 0x400>; 2988 status = "disabled"; 2989 #address-cells = <2>; 2990 #size-cells = <2>; 2991 ranges; 2992 dma-ranges; 2993 2994 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2995 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2996 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2997 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2998 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2999 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3000 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3001 "sleep", "xo"; 3002 3003 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3004 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3005 assigned-clock-rates = <19200000>, <200000000>; 3006 3007 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3008 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3009 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3010 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3011 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3012 "dm_hs_phy_irq", "ss_phy_irq"; 3013 3014 power-domains = <&gcc USB30_PRIM_GDSC>; 3015 3016 resets = <&gcc GCC_USB30_PRIM_BCR>; 3017 3018 usb_1_dwc3: usb@a600000 { 3019 compatible = "snps,dwc3"; 3020 reg = <0 0x0a600000 0 0xcd00>; 3021 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3022 iommus = <&apps_smmu 0x0 0x0>; 3023 snps,dis_u2_susphy_quirk; 3024 snps,dis_enblslpm_quirk; 3025 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3026 phy-names = "usb2-phy", "usb3-phy"; 3027 }; 3028 }; 3029 3030 system-cache-controller@9200000 { 3031 compatible = "qcom,sm8250-llcc"; 3032 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 3033 reg-names = "llcc_base", "llcc_broadcast_base"; 3034 }; 3035 3036 usb_2: usb@a8f8800 { 3037 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3038 reg = <0 0x0a8f8800 0 0x400>; 3039 status = "disabled"; 3040 #address-cells = <2>; 3041 #size-cells = <2>; 3042 ranges; 3043 dma-ranges; 3044 3045 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3046 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3047 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3048 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3049 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3050 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3051 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3052 "sleep", "xo"; 3053 3054 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3055 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3056 assigned-clock-rates = <19200000>, <200000000>; 3057 3058 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3059 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3060 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3061 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 3062 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 3063 "dm_hs_phy_irq", "ss_phy_irq"; 3064 3065 power-domains = <&gcc USB30_SEC_GDSC>; 3066 3067 resets = <&gcc GCC_USB30_SEC_BCR>; 3068 3069 usb_2_dwc3: usb@a800000 { 3070 compatible = "snps,dwc3"; 3071 reg = <0 0x0a800000 0 0xcd00>; 3072 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3073 iommus = <&apps_smmu 0x20 0>; 3074 snps,dis_u2_susphy_quirk; 3075 snps,dis_enblslpm_quirk; 3076 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3077 phy-names = "usb2-phy", "usb3-phy"; 3078 }; 3079 }; 3080 3081 venus: video-codec@aa00000 { 3082 compatible = "qcom,sm8250-venus"; 3083 reg = <0 0x0aa00000 0 0x100000>; 3084 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3085 power-domains = <&videocc MVS0C_GDSC>, 3086 <&videocc MVS0_GDSC>, 3087 <&rpmhpd SM8250_MX>; 3088 power-domain-names = "venus", "vcodec0", "mx"; 3089 operating-points-v2 = <&venus_opp_table>; 3090 3091 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3092 <&videocc VIDEO_CC_MVS0C_CLK>, 3093 <&videocc VIDEO_CC_MVS0_CLK>; 3094 clock-names = "iface", "core", "vcodec0_core"; 3095 3096 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3097 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3098 interconnect-names = "cpu-cfg", "video-mem"; 3099 3100 iommus = <&apps_smmu 0x2100 0x0400>; 3101 memory-region = <&video_mem>; 3102 3103 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3104 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3105 reset-names = "bus", "core"; 3106 3107 status = "disabled"; 3108 3109 video-decoder { 3110 compatible = "venus-decoder"; 3111 }; 3112 3113 video-encoder { 3114 compatible = "venus-encoder"; 3115 }; 3116 3117 venus_opp_table: venus-opp-table { 3118 compatible = "operating-points-v2"; 3119 3120 opp-720000000 { 3121 opp-hz = /bits/ 64 <720000000>; 3122 required-opps = <&rpmhpd_opp_low_svs>; 3123 }; 3124 3125 opp-1014000000 { 3126 opp-hz = /bits/ 64 <1014000000>; 3127 required-opps = <&rpmhpd_opp_svs>; 3128 }; 3129 3130 opp-1098000000 { 3131 opp-hz = /bits/ 64 <1098000000>; 3132 required-opps = <&rpmhpd_opp_svs_l1>; 3133 }; 3134 3135 opp-1332000000 { 3136 opp-hz = /bits/ 64 <1332000000>; 3137 required-opps = <&rpmhpd_opp_nom>; 3138 }; 3139 }; 3140 }; 3141 3142 videocc: clock-controller@abf0000 { 3143 compatible = "qcom,sm8250-videocc"; 3144 reg = <0 0x0abf0000 0 0x10000>; 3145 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3146 <&rpmhcc RPMH_CXO_CLK>, 3147 <&rpmhcc RPMH_CXO_CLK_A>; 3148 power-domains = <&rpmhpd SM8250_MMCX>; 3149 required-opps = <&rpmhpd_opp_low_svs>; 3150 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3151 #clock-cells = <1>; 3152 #reset-cells = <1>; 3153 #power-domain-cells = <1>; 3154 }; 3155 3156 mdss: mdss@ae00000 { 3157 compatible = "qcom,sm8250-mdss"; 3158 reg = <0 0x0ae00000 0 0x1000>; 3159 reg-names = "mdss"; 3160 3161 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3162 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3163 interconnect-names = "mdp0-mem", "mdp1-mem"; 3164 3165 power-domains = <&dispcc MDSS_GDSC>; 3166 3167 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3168 <&gcc GCC_DISP_HF_AXI_CLK>, 3169 <&gcc GCC_DISP_SF_AXI_CLK>, 3170 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3171 clock-names = "iface", "bus", "nrt_bus", "core"; 3172 3173 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3174 assigned-clock-rates = <460000000>; 3175 3176 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3177 interrupt-controller; 3178 #interrupt-cells = <1>; 3179 3180 iommus = <&apps_smmu 0x820 0x402>; 3181 3182 status = "disabled"; 3183 3184 #address-cells = <2>; 3185 #size-cells = <2>; 3186 ranges; 3187 3188 mdss_mdp: mdp@ae01000 { 3189 compatible = "qcom,sm8250-dpu"; 3190 reg = <0 0x0ae01000 0 0x8f000>, 3191 <0 0x0aeb0000 0 0x2008>; 3192 reg-names = "mdp", "vbif"; 3193 3194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3195 <&gcc GCC_DISP_HF_AXI_CLK>, 3196 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3197 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3198 clock-names = "iface", "bus", "core", "vsync"; 3199 3200 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3201 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3202 assigned-clock-rates = <460000000>, 3203 <19200000>; 3204 3205 operating-points-v2 = <&mdp_opp_table>; 3206 power-domains = <&rpmhpd SM8250_MMCX>; 3207 3208 interrupt-parent = <&mdss>; 3209 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 3210 3211 ports { 3212 #address-cells = <1>; 3213 #size-cells = <0>; 3214 3215 port@0 { 3216 reg = <0>; 3217 dpu_intf1_out: endpoint { 3218 remote-endpoint = <&dsi0_in>; 3219 }; 3220 }; 3221 3222 port@1 { 3223 reg = <1>; 3224 dpu_intf2_out: endpoint { 3225 remote-endpoint = <&dsi1_in>; 3226 }; 3227 }; 3228 }; 3229 3230 mdp_opp_table: mdp-opp-table { 3231 compatible = "operating-points-v2"; 3232 3233 opp-200000000 { 3234 opp-hz = /bits/ 64 <200000000>; 3235 required-opps = <&rpmhpd_opp_low_svs>; 3236 }; 3237 3238 opp-300000000 { 3239 opp-hz = /bits/ 64 <300000000>; 3240 required-opps = <&rpmhpd_opp_svs>; 3241 }; 3242 3243 opp-345000000 { 3244 opp-hz = /bits/ 64 <345000000>; 3245 required-opps = <&rpmhpd_opp_svs_l1>; 3246 }; 3247 3248 opp-460000000 { 3249 opp-hz = /bits/ 64 <460000000>; 3250 required-opps = <&rpmhpd_opp_nom>; 3251 }; 3252 }; 3253 }; 3254 3255 dsi0: dsi@ae94000 { 3256 compatible = "qcom,mdss-dsi-ctrl"; 3257 reg = <0 0x0ae94000 0 0x400>; 3258 reg-names = "dsi_ctrl"; 3259 3260 interrupt-parent = <&mdss>; 3261 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 3262 3263 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3264 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3265 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3266 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3267 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3268 <&gcc GCC_DISP_HF_AXI_CLK>; 3269 clock-names = "byte", 3270 "byte_intf", 3271 "pixel", 3272 "core", 3273 "iface", 3274 "bus"; 3275 3276 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3277 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 3278 3279 operating-points-v2 = <&dsi_opp_table>; 3280 power-domains = <&rpmhpd SM8250_MMCX>; 3281 3282 phys = <&dsi0_phy>; 3283 phy-names = "dsi"; 3284 3285 status = "disabled"; 3286 3287 #address-cells = <1>; 3288 #size-cells = <0>; 3289 3290 ports { 3291 #address-cells = <1>; 3292 #size-cells = <0>; 3293 3294 port@0 { 3295 reg = <0>; 3296 dsi0_in: endpoint { 3297 remote-endpoint = <&dpu_intf1_out>; 3298 }; 3299 }; 3300 3301 port@1 { 3302 reg = <1>; 3303 dsi0_out: endpoint { 3304 }; 3305 }; 3306 }; 3307 }; 3308 3309 dsi0_phy: dsi-phy@ae94400 { 3310 compatible = "qcom,dsi-phy-7nm"; 3311 reg = <0 0x0ae94400 0 0x200>, 3312 <0 0x0ae94600 0 0x280>, 3313 <0 0x0ae94900 0 0x260>; 3314 reg-names = "dsi_phy", 3315 "dsi_phy_lane", 3316 "dsi_pll"; 3317 3318 #clock-cells = <1>; 3319 #phy-cells = <0>; 3320 3321 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3322 <&rpmhcc RPMH_CXO_CLK>; 3323 clock-names = "iface", "ref"; 3324 3325 status = "disabled"; 3326 }; 3327 3328 dsi1: dsi@ae96000 { 3329 compatible = "qcom,mdss-dsi-ctrl"; 3330 reg = <0 0x0ae96000 0 0x400>; 3331 reg-names = "dsi_ctrl"; 3332 3333 interrupt-parent = <&mdss>; 3334 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 3335 3336 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3337 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3338 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3339 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3340 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3341 <&gcc GCC_DISP_HF_AXI_CLK>; 3342 clock-names = "byte", 3343 "byte_intf", 3344 "pixel", 3345 "core", 3346 "iface", 3347 "bus"; 3348 3349 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3350 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 3351 3352 operating-points-v2 = <&dsi_opp_table>; 3353 power-domains = <&rpmhpd SM8250_MMCX>; 3354 3355 phys = <&dsi1_phy>; 3356 phy-names = "dsi"; 3357 3358 status = "disabled"; 3359 3360 #address-cells = <1>; 3361 #size-cells = <0>; 3362 3363 ports { 3364 #address-cells = <1>; 3365 #size-cells = <0>; 3366 3367 port@0 { 3368 reg = <0>; 3369 dsi1_in: endpoint { 3370 remote-endpoint = <&dpu_intf2_out>; 3371 }; 3372 }; 3373 3374 port@1 { 3375 reg = <1>; 3376 dsi1_out: endpoint { 3377 }; 3378 }; 3379 }; 3380 }; 3381 3382 dsi1_phy: dsi-phy@ae96400 { 3383 compatible = "qcom,dsi-phy-7nm"; 3384 reg = <0 0x0ae96400 0 0x200>, 3385 <0 0x0ae96600 0 0x280>, 3386 <0 0x0ae96900 0 0x260>; 3387 reg-names = "dsi_phy", 3388 "dsi_phy_lane", 3389 "dsi_pll"; 3390 3391 #clock-cells = <1>; 3392 #phy-cells = <0>; 3393 3394 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3395 <&rpmhcc RPMH_CXO_CLK>; 3396 clock-names = "iface", "ref"; 3397 3398 status = "disabled"; 3399 3400 dsi_opp_table: dsi-opp-table { 3401 compatible = "operating-points-v2"; 3402 3403 opp-187500000 { 3404 opp-hz = /bits/ 64 <187500000>; 3405 required-opps = <&rpmhpd_opp_low_svs>; 3406 }; 3407 3408 opp-300000000 { 3409 opp-hz = /bits/ 64 <300000000>; 3410 required-opps = <&rpmhpd_opp_svs>; 3411 }; 3412 3413 opp-358000000 { 3414 opp-hz = /bits/ 64 <358000000>; 3415 required-opps = <&rpmhpd_opp_svs_l1>; 3416 }; 3417 }; 3418 }; 3419 }; 3420 3421 dispcc: clock-controller@af00000 { 3422 compatible = "qcom,sm8250-dispcc"; 3423 reg = <0 0x0af00000 0 0x10000>; 3424 power-domains = <&rpmhpd SM8250_MMCX>; 3425 required-opps = <&rpmhpd_opp_low_svs>; 3426 clocks = <&rpmhcc RPMH_CXO_CLK>, 3427 <&dsi0_phy 0>, 3428 <&dsi0_phy 1>, 3429 <&dsi1_phy 0>, 3430 <&dsi1_phy 1>, 3431 <&dp_phy 0>, 3432 <&dp_phy 1>; 3433 clock-names = "bi_tcxo", 3434 "dsi0_phy_pll_out_byteclk", 3435 "dsi0_phy_pll_out_dsiclk", 3436 "dsi1_phy_pll_out_byteclk", 3437 "dsi1_phy_pll_out_dsiclk", 3438 "dp_phy_pll_link_clk", 3439 "dp_phy_pll_vco_div_clk"; 3440 #clock-cells = <1>; 3441 #reset-cells = <1>; 3442 #power-domain-cells = <1>; 3443 }; 3444 3445 pdc: interrupt-controller@b220000 { 3446 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 3447 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3448 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3449 <125 63 1>, <126 716 12>; 3450 #interrupt-cells = <2>; 3451 interrupt-parent = <&intc>; 3452 interrupt-controller; 3453 }; 3454 3455 tsens0: thermal-sensor@c263000 { 3456 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3457 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3458 <0 0x0c222000 0 0x1ff>; /* SROT */ 3459 #qcom,sensors = <16>; 3460 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3462 interrupt-names = "uplow", "critical"; 3463 #thermal-sensor-cells = <1>; 3464 }; 3465 3466 tsens1: thermal-sensor@c265000 { 3467 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 3468 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3469 <0 0x0c223000 0 0x1ff>; /* SROT */ 3470 #qcom,sensors = <9>; 3471 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3473 interrupt-names = "uplow", "critical"; 3474 #thermal-sensor-cells = <1>; 3475 }; 3476 3477 aoss_qmp: power-controller@c300000 { 3478 compatible = "qcom,sm8250-aoss-qmp"; 3479 reg = <0 0x0c300000 0 0x400>; 3480 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3481 IPCC_MPROC_SIGNAL_GLINK_QMP 3482 IRQ_TYPE_EDGE_RISING>; 3483 mboxes = <&ipcc IPCC_CLIENT_AOP 3484 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3485 3486 #clock-cells = <0>; 3487 }; 3488 3489 sram@c3f0000 { 3490 compatible = "qcom,rpmh-stats"; 3491 reg = <0 0x0c3f0000 0 0x400>; 3492 }; 3493 3494 spmi_bus: spmi@c440000 { 3495 compatible = "qcom,spmi-pmic-arb"; 3496 reg = <0x0 0x0c440000 0x0 0x0001100>, 3497 <0x0 0x0c600000 0x0 0x2000000>, 3498 <0x0 0x0e600000 0x0 0x0100000>, 3499 <0x0 0x0e700000 0x0 0x00a0000>, 3500 <0x0 0x0c40a000 0x0 0x0026000>; 3501 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3502 interrupt-names = "periph_irq"; 3503 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3504 qcom,ee = <0>; 3505 qcom,channel = <0>; 3506 #address-cells = <2>; 3507 #size-cells = <0>; 3508 interrupt-controller; 3509 #interrupt-cells = <4>; 3510 }; 3511 3512 tlmm: pinctrl@f100000 { 3513 compatible = "qcom,sm8250-pinctrl"; 3514 reg = <0 0x0f100000 0 0x300000>, 3515 <0 0x0f500000 0 0x300000>, 3516 <0 0x0f900000 0 0x300000>; 3517 reg-names = "west", "south", "north"; 3518 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3519 gpio-controller; 3520 #gpio-cells = <2>; 3521 interrupt-controller; 3522 #interrupt-cells = <2>; 3523 gpio-ranges = <&tlmm 0 0 181>; 3524 wakeup-parent = <&pdc>; 3525 3526 pri_mi2s_active: pri-mi2s-active { 3527 sclk { 3528 pins = "gpio138"; 3529 function = "mi2s0_sck"; 3530 drive-strength = <8>; 3531 bias-disable; 3532 }; 3533 3534 ws { 3535 pins = "gpio141"; 3536 function = "mi2s0_ws"; 3537 drive-strength = <8>; 3538 output-high; 3539 }; 3540 3541 data0 { 3542 pins = "gpio139"; 3543 function = "mi2s0_data0"; 3544 drive-strength = <8>; 3545 bias-disable; 3546 output-high; 3547 }; 3548 3549 data1 { 3550 pins = "gpio140"; 3551 function = "mi2s0_data1"; 3552 drive-strength = <8>; 3553 output-high; 3554 }; 3555 }; 3556 3557 qup_i2c0_default: qup-i2c0-default { 3558 mux { 3559 pins = "gpio28", "gpio29"; 3560 function = "qup0"; 3561 }; 3562 3563 config { 3564 pins = "gpio28", "gpio29"; 3565 drive-strength = <2>; 3566 bias-disable; 3567 }; 3568 }; 3569 3570 qup_i2c1_default: qup-i2c1-default { 3571 pinmux { 3572 pins = "gpio4", "gpio5"; 3573 function = "qup1"; 3574 }; 3575 3576 config { 3577 pins = "gpio4", "gpio5"; 3578 drive-strength = <2>; 3579 bias-disable; 3580 }; 3581 }; 3582 3583 qup_i2c2_default: qup-i2c2-default { 3584 mux { 3585 pins = "gpio115", "gpio116"; 3586 function = "qup2"; 3587 }; 3588 3589 config { 3590 pins = "gpio115", "gpio116"; 3591 drive-strength = <2>; 3592 bias-disable; 3593 }; 3594 }; 3595 3596 qup_i2c3_default: qup-i2c3-default { 3597 mux { 3598 pins = "gpio119", "gpio120"; 3599 function = "qup3"; 3600 }; 3601 3602 config { 3603 pins = "gpio119", "gpio120"; 3604 drive-strength = <2>; 3605 bias-disable; 3606 }; 3607 }; 3608 3609 qup_i2c4_default: qup-i2c4-default { 3610 mux { 3611 pins = "gpio8", "gpio9"; 3612 function = "qup4"; 3613 }; 3614 3615 config { 3616 pins = "gpio8", "gpio9"; 3617 drive-strength = <2>; 3618 bias-disable; 3619 }; 3620 }; 3621 3622 qup_i2c5_default: qup-i2c5-default { 3623 mux { 3624 pins = "gpio12", "gpio13"; 3625 function = "qup5"; 3626 }; 3627 3628 config { 3629 pins = "gpio12", "gpio13"; 3630 drive-strength = <2>; 3631 bias-disable; 3632 }; 3633 }; 3634 3635 qup_i2c6_default: qup-i2c6-default { 3636 mux { 3637 pins = "gpio16", "gpio17"; 3638 function = "qup6"; 3639 }; 3640 3641 config { 3642 pins = "gpio16", "gpio17"; 3643 drive-strength = <2>; 3644 bias-disable; 3645 }; 3646 }; 3647 3648 qup_i2c7_default: qup-i2c7-default { 3649 mux { 3650 pins = "gpio20", "gpio21"; 3651 function = "qup7"; 3652 }; 3653 3654 config { 3655 pins = "gpio20", "gpio21"; 3656 drive-strength = <2>; 3657 bias-disable; 3658 }; 3659 }; 3660 3661 qup_i2c8_default: qup-i2c8-default { 3662 mux { 3663 pins = "gpio24", "gpio25"; 3664 function = "qup8"; 3665 }; 3666 3667 config { 3668 pins = "gpio24", "gpio25"; 3669 drive-strength = <2>; 3670 bias-disable; 3671 }; 3672 }; 3673 3674 qup_i2c9_default: qup-i2c9-default { 3675 mux { 3676 pins = "gpio125", "gpio126"; 3677 function = "qup9"; 3678 }; 3679 3680 config { 3681 pins = "gpio125", "gpio126"; 3682 drive-strength = <2>; 3683 bias-disable; 3684 }; 3685 }; 3686 3687 qup_i2c10_default: qup-i2c10-default { 3688 mux { 3689 pins = "gpio129", "gpio130"; 3690 function = "qup10"; 3691 }; 3692 3693 config { 3694 pins = "gpio129", "gpio130"; 3695 drive-strength = <2>; 3696 bias-disable; 3697 }; 3698 }; 3699 3700 qup_i2c11_default: qup-i2c11-default { 3701 mux { 3702 pins = "gpio60", "gpio61"; 3703 function = "qup11"; 3704 }; 3705 3706 config { 3707 pins = "gpio60", "gpio61"; 3708 drive-strength = <2>; 3709 bias-disable; 3710 }; 3711 }; 3712 3713 qup_i2c12_default: qup-i2c12-default { 3714 mux { 3715 pins = "gpio32", "gpio33"; 3716 function = "qup12"; 3717 }; 3718 3719 config { 3720 pins = "gpio32", "gpio33"; 3721 drive-strength = <2>; 3722 bias-disable; 3723 }; 3724 }; 3725 3726 qup_i2c13_default: qup-i2c13-default { 3727 mux { 3728 pins = "gpio36", "gpio37"; 3729 function = "qup13"; 3730 }; 3731 3732 config { 3733 pins = "gpio36", "gpio37"; 3734 drive-strength = <2>; 3735 bias-disable; 3736 }; 3737 }; 3738 3739 qup_i2c14_default: qup-i2c14-default { 3740 mux { 3741 pins = "gpio40", "gpio41"; 3742 function = "qup14"; 3743 }; 3744 3745 config { 3746 pins = "gpio40", "gpio41"; 3747 drive-strength = <2>; 3748 bias-disable; 3749 }; 3750 }; 3751 3752 qup_i2c15_default: qup-i2c15-default { 3753 mux { 3754 pins = "gpio44", "gpio45"; 3755 function = "qup15"; 3756 }; 3757 3758 config { 3759 pins = "gpio44", "gpio45"; 3760 drive-strength = <2>; 3761 bias-disable; 3762 }; 3763 }; 3764 3765 qup_i2c16_default: qup-i2c16-default { 3766 mux { 3767 pins = "gpio48", "gpio49"; 3768 function = "qup16"; 3769 }; 3770 3771 config { 3772 pins = "gpio48", "gpio49"; 3773 drive-strength = <2>; 3774 bias-disable; 3775 }; 3776 }; 3777 3778 qup_i2c17_default: qup-i2c17-default { 3779 mux { 3780 pins = "gpio52", "gpio53"; 3781 function = "qup17"; 3782 }; 3783 3784 config { 3785 pins = "gpio52", "gpio53"; 3786 drive-strength = <2>; 3787 bias-disable; 3788 }; 3789 }; 3790 3791 qup_i2c18_default: qup-i2c18-default { 3792 mux { 3793 pins = "gpio56", "gpio57"; 3794 function = "qup18"; 3795 }; 3796 3797 config { 3798 pins = "gpio56", "gpio57"; 3799 drive-strength = <2>; 3800 bias-disable; 3801 }; 3802 }; 3803 3804 qup_i2c19_default: qup-i2c19-default { 3805 mux { 3806 pins = "gpio0", "gpio1"; 3807 function = "qup19"; 3808 }; 3809 3810 config { 3811 pins = "gpio0", "gpio1"; 3812 drive-strength = <2>; 3813 bias-disable; 3814 }; 3815 }; 3816 3817 qup_spi0_cs: qup-spi0-cs { 3818 pins = "gpio31"; 3819 function = "qup0"; 3820 }; 3821 3822 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3823 pins = "gpio31"; 3824 function = "gpio"; 3825 }; 3826 3827 qup_spi0_data_clk: qup-spi0-data-clk { 3828 pins = "gpio28", "gpio29", 3829 "gpio30"; 3830 function = "qup0"; 3831 }; 3832 3833 qup_spi1_cs: qup-spi1-cs { 3834 pins = "gpio7"; 3835 function = "qup1"; 3836 }; 3837 3838 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3839 pins = "gpio7"; 3840 function = "gpio"; 3841 }; 3842 3843 qup_spi1_data_clk: qup-spi1-data-clk { 3844 pins = "gpio4", "gpio5", 3845 "gpio6"; 3846 function = "qup1"; 3847 }; 3848 3849 qup_spi2_cs: qup-spi2-cs { 3850 pins = "gpio118"; 3851 function = "qup2"; 3852 }; 3853 3854 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3855 pins = "gpio118"; 3856 function = "gpio"; 3857 }; 3858 3859 qup_spi2_data_clk: qup-spi2-data-clk { 3860 pins = "gpio115", "gpio116", 3861 "gpio117"; 3862 function = "qup2"; 3863 }; 3864 3865 qup_spi3_cs: qup-spi3-cs { 3866 pins = "gpio122"; 3867 function = "qup3"; 3868 }; 3869 3870 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3871 pins = "gpio122"; 3872 function = "gpio"; 3873 }; 3874 3875 qup_spi3_data_clk: qup-spi3-data-clk { 3876 pins = "gpio119", "gpio120", 3877 "gpio121"; 3878 function = "qup3"; 3879 }; 3880 3881 qup_spi4_cs: qup-spi4-cs { 3882 pins = "gpio11"; 3883 function = "qup4"; 3884 }; 3885 3886 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3887 pins = "gpio11"; 3888 function = "gpio"; 3889 }; 3890 3891 qup_spi4_data_clk: qup-spi4-data-clk { 3892 pins = "gpio8", "gpio9", 3893 "gpio10"; 3894 function = "qup4"; 3895 }; 3896 3897 qup_spi5_cs: qup-spi5-cs { 3898 pins = "gpio15"; 3899 function = "qup5"; 3900 }; 3901 3902 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3903 pins = "gpio15"; 3904 function = "gpio"; 3905 }; 3906 3907 qup_spi5_data_clk: qup-spi5-data-clk { 3908 pins = "gpio12", "gpio13", 3909 "gpio14"; 3910 function = "qup5"; 3911 }; 3912 3913 qup_spi6_cs: qup-spi6-cs { 3914 pins = "gpio19"; 3915 function = "qup6"; 3916 }; 3917 3918 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3919 pins = "gpio19"; 3920 function = "gpio"; 3921 }; 3922 3923 qup_spi6_data_clk: qup-spi6-data-clk { 3924 pins = "gpio16", "gpio17", 3925 "gpio18"; 3926 function = "qup6"; 3927 }; 3928 3929 qup_spi7_cs: qup-spi7-cs { 3930 pins = "gpio23"; 3931 function = "qup7"; 3932 }; 3933 3934 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3935 pins = "gpio23"; 3936 function = "gpio"; 3937 }; 3938 3939 qup_spi7_data_clk: qup-spi7-data-clk { 3940 pins = "gpio20", "gpio21", 3941 "gpio22"; 3942 function = "qup7"; 3943 }; 3944 3945 qup_spi8_cs: qup-spi8-cs { 3946 pins = "gpio27"; 3947 function = "qup8"; 3948 }; 3949 3950 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3951 pins = "gpio27"; 3952 function = "gpio"; 3953 }; 3954 3955 qup_spi8_data_clk: qup-spi8-data-clk { 3956 pins = "gpio24", "gpio25", 3957 "gpio26"; 3958 function = "qup8"; 3959 }; 3960 3961 qup_spi9_cs: qup-spi9-cs { 3962 pins = "gpio128"; 3963 function = "qup9"; 3964 }; 3965 3966 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3967 pins = "gpio128"; 3968 function = "gpio"; 3969 }; 3970 3971 qup_spi9_data_clk: qup-spi9-data-clk { 3972 pins = "gpio125", "gpio126", 3973 "gpio127"; 3974 function = "qup9"; 3975 }; 3976 3977 qup_spi10_cs: qup-spi10-cs { 3978 pins = "gpio132"; 3979 function = "qup10"; 3980 }; 3981 3982 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3983 pins = "gpio132"; 3984 function = "gpio"; 3985 }; 3986 3987 qup_spi10_data_clk: qup-spi10-data-clk { 3988 pins = "gpio129", "gpio130", 3989 "gpio131"; 3990 function = "qup10"; 3991 }; 3992 3993 qup_spi11_cs: qup-spi11-cs { 3994 pins = "gpio63"; 3995 function = "qup11"; 3996 }; 3997 3998 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3999 pins = "gpio63"; 4000 function = "gpio"; 4001 }; 4002 4003 qup_spi11_data_clk: qup-spi11-data-clk { 4004 pins = "gpio60", "gpio61", 4005 "gpio62"; 4006 function = "qup11"; 4007 }; 4008 4009 qup_spi12_cs: qup-spi12-cs { 4010 pins = "gpio35"; 4011 function = "qup12"; 4012 }; 4013 4014 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 4015 pins = "gpio35"; 4016 function = "gpio"; 4017 }; 4018 4019 qup_spi12_data_clk: qup-spi12-data-clk { 4020 pins = "gpio32", "gpio33", 4021 "gpio34"; 4022 function = "qup12"; 4023 }; 4024 4025 qup_spi13_cs: qup-spi13-cs { 4026 pins = "gpio39"; 4027 function = "qup13"; 4028 }; 4029 4030 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 4031 pins = "gpio39"; 4032 function = "gpio"; 4033 }; 4034 4035 qup_spi13_data_clk: qup-spi13-data-clk { 4036 pins = "gpio36", "gpio37", 4037 "gpio38"; 4038 function = "qup13"; 4039 }; 4040 4041 qup_spi14_cs: qup-spi14-cs { 4042 pins = "gpio43"; 4043 function = "qup14"; 4044 }; 4045 4046 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 4047 pins = "gpio43"; 4048 function = "gpio"; 4049 }; 4050 4051 qup_spi14_data_clk: qup-spi14-data-clk { 4052 pins = "gpio40", "gpio41", 4053 "gpio42"; 4054 function = "qup14"; 4055 }; 4056 4057 qup_spi15_cs: qup-spi15-cs { 4058 pins = "gpio47"; 4059 function = "qup15"; 4060 }; 4061 4062 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 4063 pins = "gpio47"; 4064 function = "gpio"; 4065 }; 4066 4067 qup_spi15_data_clk: qup-spi15-data-clk { 4068 pins = "gpio44", "gpio45", 4069 "gpio46"; 4070 function = "qup15"; 4071 }; 4072 4073 qup_spi16_cs: qup-spi16-cs { 4074 pins = "gpio51"; 4075 function = "qup16"; 4076 }; 4077 4078 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 4079 pins = "gpio51"; 4080 function = "gpio"; 4081 }; 4082 4083 qup_spi16_data_clk: qup-spi16-data-clk { 4084 pins = "gpio48", "gpio49", 4085 "gpio50"; 4086 function = "qup16"; 4087 }; 4088 4089 qup_spi17_cs: qup-spi17-cs { 4090 pins = "gpio55"; 4091 function = "qup17"; 4092 }; 4093 4094 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 4095 pins = "gpio55"; 4096 function = "gpio"; 4097 }; 4098 4099 qup_spi17_data_clk: qup-spi17-data-clk { 4100 pins = "gpio52", "gpio53", 4101 "gpio54"; 4102 function = "qup17"; 4103 }; 4104 4105 qup_spi18_cs: qup-spi18-cs { 4106 pins = "gpio59"; 4107 function = "qup18"; 4108 }; 4109 4110 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 4111 pins = "gpio59"; 4112 function = "gpio"; 4113 }; 4114 4115 qup_spi18_data_clk: qup-spi18-data-clk { 4116 pins = "gpio56", "gpio57", 4117 "gpio58"; 4118 function = "qup18"; 4119 }; 4120 4121 qup_spi19_cs: qup-spi19-cs { 4122 pins = "gpio3"; 4123 function = "qup19"; 4124 }; 4125 4126 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 4127 pins = "gpio3"; 4128 function = "gpio"; 4129 }; 4130 4131 qup_spi19_data_clk: qup-spi19-data-clk { 4132 pins = "gpio0", "gpio1", 4133 "gpio2"; 4134 function = "qup19"; 4135 }; 4136 4137 qup_uart2_default: qup-uart2-default { 4138 mux { 4139 pins = "gpio117", "gpio118"; 4140 function = "qup2"; 4141 }; 4142 }; 4143 4144 qup_uart6_default: qup-uart6-default { 4145 mux { 4146 pins = "gpio16", "gpio17", 4147 "gpio18", "gpio19"; 4148 function = "qup6"; 4149 }; 4150 }; 4151 4152 qup_uart12_default: qup-uart12-default { 4153 mux { 4154 pins = "gpio34", "gpio35"; 4155 function = "qup12"; 4156 }; 4157 }; 4158 4159 qup_uart17_default: qup-uart17-default { 4160 mux { 4161 pins = "gpio52", "gpio53", 4162 "gpio54", "gpio55"; 4163 function = "qup17"; 4164 }; 4165 }; 4166 4167 qup_uart18_default: qup-uart18-default { 4168 mux { 4169 pins = "gpio58", "gpio59"; 4170 function = "qup18"; 4171 }; 4172 }; 4173 4174 tert_mi2s_active: tert-mi2s-active { 4175 sck { 4176 pins = "gpio133"; 4177 function = "mi2s2_sck"; 4178 drive-strength = <8>; 4179 bias-disable; 4180 }; 4181 4182 data0 { 4183 pins = "gpio134"; 4184 function = "mi2s2_data0"; 4185 drive-strength = <8>; 4186 bias-disable; 4187 output-high; 4188 }; 4189 4190 ws { 4191 pins = "gpio135"; 4192 function = "mi2s2_ws"; 4193 drive-strength = <8>; 4194 output-high; 4195 }; 4196 }; 4197 4198 sdc2_sleep_state: sdc2-sleep { 4199 clk { 4200 pins = "sdc2_clk"; 4201 drive-strength = <2>; 4202 bias-disable; 4203 }; 4204 4205 cmd { 4206 pins = "sdc2_cmd"; 4207 drive-strength = <2>; 4208 bias-pull-up; 4209 }; 4210 4211 data { 4212 pins = "sdc2_data"; 4213 drive-strength = <2>; 4214 bias-pull-up; 4215 }; 4216 }; 4217 4218 pcie0_default_state: pcie0-default { 4219 perst { 4220 pins = "gpio79"; 4221 function = "gpio"; 4222 drive-strength = <2>; 4223 bias-pull-down; 4224 }; 4225 4226 clkreq { 4227 pins = "gpio80"; 4228 function = "pci_e0"; 4229 drive-strength = <2>; 4230 bias-pull-up; 4231 }; 4232 4233 wake { 4234 pins = "gpio81"; 4235 function = "gpio"; 4236 drive-strength = <2>; 4237 bias-pull-up; 4238 }; 4239 }; 4240 4241 pcie1_default_state: pcie1-default { 4242 perst { 4243 pins = "gpio82"; 4244 function = "gpio"; 4245 drive-strength = <2>; 4246 bias-pull-down; 4247 }; 4248 4249 clkreq { 4250 pins = "gpio83"; 4251 function = "pci_e1"; 4252 drive-strength = <2>; 4253 bias-pull-up; 4254 }; 4255 4256 wake { 4257 pins = "gpio84"; 4258 function = "gpio"; 4259 drive-strength = <2>; 4260 bias-pull-up; 4261 }; 4262 }; 4263 4264 pcie2_default_state: pcie2-default { 4265 perst { 4266 pins = "gpio85"; 4267 function = "gpio"; 4268 drive-strength = <2>; 4269 bias-pull-down; 4270 }; 4271 4272 clkreq { 4273 pins = "gpio86"; 4274 function = "pci_e2"; 4275 drive-strength = <2>; 4276 bias-pull-up; 4277 }; 4278 4279 wake { 4280 pins = "gpio87"; 4281 function = "gpio"; 4282 drive-strength = <2>; 4283 bias-pull-up; 4284 }; 4285 }; 4286 }; 4287 4288 apps_smmu: iommu@15000000 { 4289 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 4290 reg = <0 0x15000000 0 0x100000>; 4291 #iommu-cells = <2>; 4292 #global-interrupts = <2>; 4293 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4370 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4383 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4384 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4387 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4388 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 4391 }; 4392 4393 adsp: remoteproc@17300000 { 4394 compatible = "qcom,sm8250-adsp-pas"; 4395 reg = <0 0x17300000 0 0x100>; 4396 4397 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 4398 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4399 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4400 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4401 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4402 interrupt-names = "wdog", "fatal", "ready", 4403 "handover", "stop-ack"; 4404 4405 clocks = <&rpmhcc RPMH_CXO_CLK>; 4406 clock-names = "xo"; 4407 4408 power-domains = <&rpmhpd SM8250_LCX>, 4409 <&rpmhpd SM8250_LMX>; 4410 power-domain-names = "lcx", "lmx"; 4411 4412 memory-region = <&adsp_mem>; 4413 4414 qcom,qmp = <&aoss_qmp>; 4415 4416 qcom,smem-states = <&smp2p_adsp_out 0>; 4417 qcom,smem-state-names = "stop"; 4418 4419 status = "disabled"; 4420 4421 glink-edge { 4422 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4423 IPCC_MPROC_SIGNAL_GLINK_QMP 4424 IRQ_TYPE_EDGE_RISING>; 4425 mboxes = <&ipcc IPCC_CLIENT_LPASS 4426 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4427 4428 label = "lpass"; 4429 qcom,remote-pid = <2>; 4430 4431 apr { 4432 compatible = "qcom,apr-v2"; 4433 qcom,glink-channels = "apr_audio_svc"; 4434 qcom,domain = <APR_DOMAIN_ADSP>; 4435 #address-cells = <1>; 4436 #size-cells = <0>; 4437 4438 apr-service@3 { 4439 reg = <APR_SVC_ADSP_CORE>; 4440 compatible = "qcom,q6core"; 4441 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4442 }; 4443 4444 q6afe: apr-service@4 { 4445 compatible = "qcom,q6afe"; 4446 reg = <APR_SVC_AFE>; 4447 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4448 q6afedai: dais { 4449 compatible = "qcom,q6afe-dais"; 4450 #address-cells = <1>; 4451 #size-cells = <0>; 4452 #sound-dai-cells = <1>; 4453 }; 4454 4455 q6afecc: cc { 4456 compatible = "qcom,q6afe-clocks"; 4457 #clock-cells = <2>; 4458 }; 4459 }; 4460 4461 q6asm: apr-service@7 { 4462 compatible = "qcom,q6asm"; 4463 reg = <APR_SVC_ASM>; 4464 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4465 q6asmdai: dais { 4466 compatible = "qcom,q6asm-dais"; 4467 #address-cells = <1>; 4468 #size-cells = <0>; 4469 #sound-dai-cells = <1>; 4470 iommus = <&apps_smmu 0x1801 0x0>; 4471 }; 4472 }; 4473 4474 q6adm: apr-service@8 { 4475 compatible = "qcom,q6adm"; 4476 reg = <APR_SVC_ADM>; 4477 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4478 q6routing: routing { 4479 compatible = "qcom,q6adm-routing"; 4480 #sound-dai-cells = <0>; 4481 }; 4482 }; 4483 }; 4484 4485 fastrpc { 4486 compatible = "qcom,fastrpc"; 4487 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4488 label = "adsp"; 4489 qcom,non-secure-domain; 4490 #address-cells = <1>; 4491 #size-cells = <0>; 4492 4493 compute-cb@3 { 4494 compatible = "qcom,fastrpc-compute-cb"; 4495 reg = <3>; 4496 iommus = <&apps_smmu 0x1803 0x0>; 4497 }; 4498 4499 compute-cb@4 { 4500 compatible = "qcom,fastrpc-compute-cb"; 4501 reg = <4>; 4502 iommus = <&apps_smmu 0x1804 0x0>; 4503 }; 4504 4505 compute-cb@5 { 4506 compatible = "qcom,fastrpc-compute-cb"; 4507 reg = <5>; 4508 iommus = <&apps_smmu 0x1805 0x0>; 4509 }; 4510 }; 4511 }; 4512 }; 4513 4514 intc: interrupt-controller@17a00000 { 4515 compatible = "arm,gic-v3"; 4516 #interrupt-cells = <3>; 4517 interrupt-controller; 4518 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4519 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4520 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4521 }; 4522 4523 watchdog@17c10000 { 4524 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 4525 reg = <0 0x17c10000 0 0x1000>; 4526 clocks = <&sleep_clk>; 4527 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4528 }; 4529 4530 timer@17c20000 { 4531 #address-cells = <2>; 4532 #size-cells = <2>; 4533 ranges; 4534 compatible = "arm,armv7-timer-mem"; 4535 reg = <0x0 0x17c20000 0x0 0x1000>; 4536 clock-frequency = <19200000>; 4537 4538 frame@17c21000 { 4539 frame-number = <0>; 4540 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4541 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4542 reg = <0x0 0x17c21000 0x0 0x1000>, 4543 <0x0 0x17c22000 0x0 0x1000>; 4544 }; 4545 4546 frame@17c23000 { 4547 frame-number = <1>; 4548 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4549 reg = <0x0 0x17c23000 0x0 0x1000>; 4550 status = "disabled"; 4551 }; 4552 4553 frame@17c25000 { 4554 frame-number = <2>; 4555 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4556 reg = <0x0 0x17c25000 0x0 0x1000>; 4557 status = "disabled"; 4558 }; 4559 4560 frame@17c27000 { 4561 frame-number = <3>; 4562 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4563 reg = <0x0 0x17c27000 0x0 0x1000>; 4564 status = "disabled"; 4565 }; 4566 4567 frame@17c29000 { 4568 frame-number = <4>; 4569 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4570 reg = <0x0 0x17c29000 0x0 0x1000>; 4571 status = "disabled"; 4572 }; 4573 4574 frame@17c2b000 { 4575 frame-number = <5>; 4576 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4577 reg = <0x0 0x17c2b000 0x0 0x1000>; 4578 status = "disabled"; 4579 }; 4580 4581 frame@17c2d000 { 4582 frame-number = <6>; 4583 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4584 reg = <0x0 0x17c2d000 0x0 0x1000>; 4585 status = "disabled"; 4586 }; 4587 }; 4588 4589 apps_rsc: rsc@18200000 { 4590 label = "apps_rsc"; 4591 compatible = "qcom,rpmh-rsc"; 4592 reg = <0x0 0x18200000 0x0 0x10000>, 4593 <0x0 0x18210000 0x0 0x10000>, 4594 <0x0 0x18220000 0x0 0x10000>; 4595 reg-names = "drv-0", "drv-1", "drv-2"; 4596 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4598 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4599 qcom,tcs-offset = <0xd00>; 4600 qcom,drv-id = <2>; 4601 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4602 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4603 4604 rpmhcc: clock-controller { 4605 compatible = "qcom,sm8250-rpmh-clk"; 4606 #clock-cells = <1>; 4607 clock-names = "xo"; 4608 clocks = <&xo_board>; 4609 }; 4610 4611 rpmhpd: power-controller { 4612 compatible = "qcom,sm8250-rpmhpd"; 4613 #power-domain-cells = <1>; 4614 operating-points-v2 = <&rpmhpd_opp_table>; 4615 4616 rpmhpd_opp_table: opp-table { 4617 compatible = "operating-points-v2"; 4618 4619 rpmhpd_opp_ret: opp1 { 4620 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4621 }; 4622 4623 rpmhpd_opp_min_svs: opp2 { 4624 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4625 }; 4626 4627 rpmhpd_opp_low_svs: opp3 { 4628 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4629 }; 4630 4631 rpmhpd_opp_svs: opp4 { 4632 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4633 }; 4634 4635 rpmhpd_opp_svs_l1: opp5 { 4636 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4637 }; 4638 4639 rpmhpd_opp_nom: opp6 { 4640 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4641 }; 4642 4643 rpmhpd_opp_nom_l1: opp7 { 4644 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4645 }; 4646 4647 rpmhpd_opp_nom_l2: opp8 { 4648 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4649 }; 4650 4651 rpmhpd_opp_turbo: opp9 { 4652 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4653 }; 4654 4655 rpmhpd_opp_turbo_l1: opp10 { 4656 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4657 }; 4658 }; 4659 }; 4660 4661 apps_bcm_voter: bcm_voter { 4662 compatible = "qcom,bcm-voter"; 4663 }; 4664 }; 4665 4666 epss_l3: interconnect@18590000 { 4667 compatible = "qcom,sm8250-epss-l3"; 4668 reg = <0 0x18590000 0 0x1000>; 4669 4670 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4671 clock-names = "xo", "alternate"; 4672 4673 #interconnect-cells = <1>; 4674 }; 4675 4676 cpufreq_hw: cpufreq@18591000 { 4677 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 4678 reg = <0 0x18591000 0 0x1000>, 4679 <0 0x18592000 0 0x1000>, 4680 <0 0x18593000 0 0x1000>; 4681 reg-names = "freq-domain0", "freq-domain1", 4682 "freq-domain2"; 4683 4684 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4685 clock-names = "xo", "alternate"; 4686 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4687 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4688 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4689 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4690 #freq-domain-cells = <1>; 4691 }; 4692 }; 4693 4694 timer { 4695 compatible = "arm,armv8-timer"; 4696 interrupts = <GIC_PPI 13 4697 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4698 <GIC_PPI 14 4699 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4700 <GIC_PPI 11 4701 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4702 <GIC_PPI 10 4703 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4704 }; 4705 4706 thermal-zones { 4707 cpu0-thermal { 4708 polling-delay-passive = <250>; 4709 polling-delay = <1000>; 4710 4711 thermal-sensors = <&tsens0 1>; 4712 4713 trips { 4714 cpu0_alert0: trip-point0 { 4715 temperature = <90000>; 4716 hysteresis = <2000>; 4717 type = "passive"; 4718 }; 4719 4720 cpu0_alert1: trip-point1 { 4721 temperature = <95000>; 4722 hysteresis = <2000>; 4723 type = "passive"; 4724 }; 4725 4726 cpu0_crit: cpu_crit { 4727 temperature = <110000>; 4728 hysteresis = <1000>; 4729 type = "critical"; 4730 }; 4731 }; 4732 4733 cooling-maps { 4734 map0 { 4735 trip = <&cpu0_alert0>; 4736 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4737 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4738 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4739 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4740 }; 4741 map1 { 4742 trip = <&cpu0_alert1>; 4743 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4744 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4745 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4746 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4747 }; 4748 }; 4749 }; 4750 4751 cpu1-thermal { 4752 polling-delay-passive = <250>; 4753 polling-delay = <1000>; 4754 4755 thermal-sensors = <&tsens0 2>; 4756 4757 trips { 4758 cpu1_alert0: trip-point0 { 4759 temperature = <90000>; 4760 hysteresis = <2000>; 4761 type = "passive"; 4762 }; 4763 4764 cpu1_alert1: trip-point1 { 4765 temperature = <95000>; 4766 hysteresis = <2000>; 4767 type = "passive"; 4768 }; 4769 4770 cpu1_crit: cpu_crit { 4771 temperature = <110000>; 4772 hysteresis = <1000>; 4773 type = "critical"; 4774 }; 4775 }; 4776 4777 cooling-maps { 4778 map0 { 4779 trip = <&cpu1_alert0>; 4780 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4781 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4782 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4783 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4784 }; 4785 map1 { 4786 trip = <&cpu1_alert1>; 4787 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4788 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4789 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4790 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4791 }; 4792 }; 4793 }; 4794 4795 cpu2-thermal { 4796 polling-delay-passive = <250>; 4797 polling-delay = <1000>; 4798 4799 thermal-sensors = <&tsens0 3>; 4800 4801 trips { 4802 cpu2_alert0: trip-point0 { 4803 temperature = <90000>; 4804 hysteresis = <2000>; 4805 type = "passive"; 4806 }; 4807 4808 cpu2_alert1: trip-point1 { 4809 temperature = <95000>; 4810 hysteresis = <2000>; 4811 type = "passive"; 4812 }; 4813 4814 cpu2_crit: cpu_crit { 4815 temperature = <110000>; 4816 hysteresis = <1000>; 4817 type = "critical"; 4818 }; 4819 }; 4820 4821 cooling-maps { 4822 map0 { 4823 trip = <&cpu2_alert0>; 4824 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4825 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4826 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4827 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4828 }; 4829 map1 { 4830 trip = <&cpu2_alert1>; 4831 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4832 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4833 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4834 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4835 }; 4836 }; 4837 }; 4838 4839 cpu3-thermal { 4840 polling-delay-passive = <250>; 4841 polling-delay = <1000>; 4842 4843 thermal-sensors = <&tsens0 4>; 4844 4845 trips { 4846 cpu3_alert0: trip-point0 { 4847 temperature = <90000>; 4848 hysteresis = <2000>; 4849 type = "passive"; 4850 }; 4851 4852 cpu3_alert1: trip-point1 { 4853 temperature = <95000>; 4854 hysteresis = <2000>; 4855 type = "passive"; 4856 }; 4857 4858 cpu3_crit: cpu_crit { 4859 temperature = <110000>; 4860 hysteresis = <1000>; 4861 type = "critical"; 4862 }; 4863 }; 4864 4865 cooling-maps { 4866 map0 { 4867 trip = <&cpu3_alert0>; 4868 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4869 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4870 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4871 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4872 }; 4873 map1 { 4874 trip = <&cpu3_alert1>; 4875 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4876 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4877 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4878 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4879 }; 4880 }; 4881 }; 4882 4883 cpu4-top-thermal { 4884 polling-delay-passive = <250>; 4885 polling-delay = <1000>; 4886 4887 thermal-sensors = <&tsens0 7>; 4888 4889 trips { 4890 cpu4_top_alert0: trip-point0 { 4891 temperature = <90000>; 4892 hysteresis = <2000>; 4893 type = "passive"; 4894 }; 4895 4896 cpu4_top_alert1: trip-point1 { 4897 temperature = <95000>; 4898 hysteresis = <2000>; 4899 type = "passive"; 4900 }; 4901 4902 cpu4_top_crit: cpu_crit { 4903 temperature = <110000>; 4904 hysteresis = <1000>; 4905 type = "critical"; 4906 }; 4907 }; 4908 4909 cooling-maps { 4910 map0 { 4911 trip = <&cpu4_top_alert0>; 4912 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4913 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4914 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4915 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4916 }; 4917 map1 { 4918 trip = <&cpu4_top_alert1>; 4919 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4920 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4921 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4922 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4923 }; 4924 }; 4925 }; 4926 4927 cpu5-top-thermal { 4928 polling-delay-passive = <250>; 4929 polling-delay = <1000>; 4930 4931 thermal-sensors = <&tsens0 8>; 4932 4933 trips { 4934 cpu5_top_alert0: trip-point0 { 4935 temperature = <90000>; 4936 hysteresis = <2000>; 4937 type = "passive"; 4938 }; 4939 4940 cpu5_top_alert1: trip-point1 { 4941 temperature = <95000>; 4942 hysteresis = <2000>; 4943 type = "passive"; 4944 }; 4945 4946 cpu5_top_crit: cpu_crit { 4947 temperature = <110000>; 4948 hysteresis = <1000>; 4949 type = "critical"; 4950 }; 4951 }; 4952 4953 cooling-maps { 4954 map0 { 4955 trip = <&cpu5_top_alert0>; 4956 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4957 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4958 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4959 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4960 }; 4961 map1 { 4962 trip = <&cpu5_top_alert1>; 4963 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4964 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4965 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4966 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4967 }; 4968 }; 4969 }; 4970 4971 cpu6-top-thermal { 4972 polling-delay-passive = <250>; 4973 polling-delay = <1000>; 4974 4975 thermal-sensors = <&tsens0 9>; 4976 4977 trips { 4978 cpu6_top_alert0: trip-point0 { 4979 temperature = <90000>; 4980 hysteresis = <2000>; 4981 type = "passive"; 4982 }; 4983 4984 cpu6_top_alert1: trip-point1 { 4985 temperature = <95000>; 4986 hysteresis = <2000>; 4987 type = "passive"; 4988 }; 4989 4990 cpu6_top_crit: cpu_crit { 4991 temperature = <110000>; 4992 hysteresis = <1000>; 4993 type = "critical"; 4994 }; 4995 }; 4996 4997 cooling-maps { 4998 map0 { 4999 trip = <&cpu6_top_alert0>; 5000 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5001 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5002 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5003 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5004 }; 5005 map1 { 5006 trip = <&cpu6_top_alert1>; 5007 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5008 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5009 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5010 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5011 }; 5012 }; 5013 }; 5014 5015 cpu7-top-thermal { 5016 polling-delay-passive = <250>; 5017 polling-delay = <1000>; 5018 5019 thermal-sensors = <&tsens0 10>; 5020 5021 trips { 5022 cpu7_top_alert0: trip-point0 { 5023 temperature = <90000>; 5024 hysteresis = <2000>; 5025 type = "passive"; 5026 }; 5027 5028 cpu7_top_alert1: trip-point1 { 5029 temperature = <95000>; 5030 hysteresis = <2000>; 5031 type = "passive"; 5032 }; 5033 5034 cpu7_top_crit: cpu_crit { 5035 temperature = <110000>; 5036 hysteresis = <1000>; 5037 type = "critical"; 5038 }; 5039 }; 5040 5041 cooling-maps { 5042 map0 { 5043 trip = <&cpu7_top_alert0>; 5044 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5045 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5046 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5047 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5048 }; 5049 map1 { 5050 trip = <&cpu7_top_alert1>; 5051 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5052 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5053 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5054 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5055 }; 5056 }; 5057 }; 5058 5059 cpu4-bottom-thermal { 5060 polling-delay-passive = <250>; 5061 polling-delay = <1000>; 5062 5063 thermal-sensors = <&tsens0 11>; 5064 5065 trips { 5066 cpu4_bottom_alert0: trip-point0 { 5067 temperature = <90000>; 5068 hysteresis = <2000>; 5069 type = "passive"; 5070 }; 5071 5072 cpu4_bottom_alert1: trip-point1 { 5073 temperature = <95000>; 5074 hysteresis = <2000>; 5075 type = "passive"; 5076 }; 5077 5078 cpu4_bottom_crit: cpu_crit { 5079 temperature = <110000>; 5080 hysteresis = <1000>; 5081 type = "critical"; 5082 }; 5083 }; 5084 5085 cooling-maps { 5086 map0 { 5087 trip = <&cpu4_bottom_alert0>; 5088 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5089 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5090 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5091 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5092 }; 5093 map1 { 5094 trip = <&cpu4_bottom_alert1>; 5095 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5096 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5097 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5098 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5099 }; 5100 }; 5101 }; 5102 5103 cpu5-bottom-thermal { 5104 polling-delay-passive = <250>; 5105 polling-delay = <1000>; 5106 5107 thermal-sensors = <&tsens0 12>; 5108 5109 trips { 5110 cpu5_bottom_alert0: trip-point0 { 5111 temperature = <90000>; 5112 hysteresis = <2000>; 5113 type = "passive"; 5114 }; 5115 5116 cpu5_bottom_alert1: trip-point1 { 5117 temperature = <95000>; 5118 hysteresis = <2000>; 5119 type = "passive"; 5120 }; 5121 5122 cpu5_bottom_crit: cpu_crit { 5123 temperature = <110000>; 5124 hysteresis = <1000>; 5125 type = "critical"; 5126 }; 5127 }; 5128 5129 cooling-maps { 5130 map0 { 5131 trip = <&cpu5_bottom_alert0>; 5132 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5133 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5134 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5135 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5136 }; 5137 map1 { 5138 trip = <&cpu5_bottom_alert1>; 5139 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5140 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5141 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5142 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5143 }; 5144 }; 5145 }; 5146 5147 cpu6-bottom-thermal { 5148 polling-delay-passive = <250>; 5149 polling-delay = <1000>; 5150 5151 thermal-sensors = <&tsens0 13>; 5152 5153 trips { 5154 cpu6_bottom_alert0: trip-point0 { 5155 temperature = <90000>; 5156 hysteresis = <2000>; 5157 type = "passive"; 5158 }; 5159 5160 cpu6_bottom_alert1: trip-point1 { 5161 temperature = <95000>; 5162 hysteresis = <2000>; 5163 type = "passive"; 5164 }; 5165 5166 cpu6_bottom_crit: cpu_crit { 5167 temperature = <110000>; 5168 hysteresis = <1000>; 5169 type = "critical"; 5170 }; 5171 }; 5172 5173 cooling-maps { 5174 map0 { 5175 trip = <&cpu6_bottom_alert0>; 5176 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5177 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5178 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5179 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5180 }; 5181 map1 { 5182 trip = <&cpu6_bottom_alert1>; 5183 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5184 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5185 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5186 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5187 }; 5188 }; 5189 }; 5190 5191 cpu7-bottom-thermal { 5192 polling-delay-passive = <250>; 5193 polling-delay = <1000>; 5194 5195 thermal-sensors = <&tsens0 14>; 5196 5197 trips { 5198 cpu7_bottom_alert0: trip-point0 { 5199 temperature = <90000>; 5200 hysteresis = <2000>; 5201 type = "passive"; 5202 }; 5203 5204 cpu7_bottom_alert1: trip-point1 { 5205 temperature = <95000>; 5206 hysteresis = <2000>; 5207 type = "passive"; 5208 }; 5209 5210 cpu7_bottom_crit: cpu_crit { 5211 temperature = <110000>; 5212 hysteresis = <1000>; 5213 type = "critical"; 5214 }; 5215 }; 5216 5217 cooling-maps { 5218 map0 { 5219 trip = <&cpu7_bottom_alert0>; 5220 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5221 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5222 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5223 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5224 }; 5225 map1 { 5226 trip = <&cpu7_bottom_alert1>; 5227 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5228 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5229 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5230 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5231 }; 5232 }; 5233 }; 5234 5235 aoss0-thermal { 5236 polling-delay-passive = <250>; 5237 polling-delay = <1000>; 5238 5239 thermal-sensors = <&tsens0 0>; 5240 5241 trips { 5242 aoss0_alert0: trip-point0 { 5243 temperature = <90000>; 5244 hysteresis = <2000>; 5245 type = "hot"; 5246 }; 5247 }; 5248 }; 5249 5250 cluster0-thermal { 5251 polling-delay-passive = <250>; 5252 polling-delay = <1000>; 5253 5254 thermal-sensors = <&tsens0 5>; 5255 5256 trips { 5257 cluster0_alert0: trip-point0 { 5258 temperature = <90000>; 5259 hysteresis = <2000>; 5260 type = "hot"; 5261 }; 5262 cluster0_crit: cluster0_crit { 5263 temperature = <110000>; 5264 hysteresis = <2000>; 5265 type = "critical"; 5266 }; 5267 }; 5268 }; 5269 5270 cluster1-thermal { 5271 polling-delay-passive = <250>; 5272 polling-delay = <1000>; 5273 5274 thermal-sensors = <&tsens0 6>; 5275 5276 trips { 5277 cluster1_alert0: trip-point0 { 5278 temperature = <90000>; 5279 hysteresis = <2000>; 5280 type = "hot"; 5281 }; 5282 cluster1_crit: cluster1_crit { 5283 temperature = <110000>; 5284 hysteresis = <2000>; 5285 type = "critical"; 5286 }; 5287 }; 5288 }; 5289 5290 gpu-top-thermal { 5291 polling-delay-passive = <250>; 5292 polling-delay = <1000>; 5293 5294 thermal-sensors = <&tsens0 15>; 5295 5296 trips { 5297 gpu1_alert0: trip-point0 { 5298 temperature = <90000>; 5299 hysteresis = <2000>; 5300 type = "hot"; 5301 }; 5302 }; 5303 }; 5304 5305 aoss1-thermal { 5306 polling-delay-passive = <250>; 5307 polling-delay = <1000>; 5308 5309 thermal-sensors = <&tsens1 0>; 5310 5311 trips { 5312 aoss1_alert0: trip-point0 { 5313 temperature = <90000>; 5314 hysteresis = <2000>; 5315 type = "hot"; 5316 }; 5317 }; 5318 }; 5319 5320 wlan-thermal { 5321 polling-delay-passive = <250>; 5322 polling-delay = <1000>; 5323 5324 thermal-sensors = <&tsens1 1>; 5325 5326 trips { 5327 wlan_alert0: trip-point0 { 5328 temperature = <90000>; 5329 hysteresis = <2000>; 5330 type = "hot"; 5331 }; 5332 }; 5333 }; 5334 5335 video-thermal { 5336 polling-delay-passive = <250>; 5337 polling-delay = <1000>; 5338 5339 thermal-sensors = <&tsens1 2>; 5340 5341 trips { 5342 video_alert0: trip-point0 { 5343 temperature = <90000>; 5344 hysteresis = <2000>; 5345 type = "hot"; 5346 }; 5347 }; 5348 }; 5349 5350 mem-thermal { 5351 polling-delay-passive = <250>; 5352 polling-delay = <1000>; 5353 5354 thermal-sensors = <&tsens1 3>; 5355 5356 trips { 5357 mem_alert0: trip-point0 { 5358 temperature = <90000>; 5359 hysteresis = <2000>; 5360 type = "hot"; 5361 }; 5362 }; 5363 }; 5364 5365 q6-hvx-thermal { 5366 polling-delay-passive = <250>; 5367 polling-delay = <1000>; 5368 5369 thermal-sensors = <&tsens1 4>; 5370 5371 trips { 5372 q6_hvx_alert0: trip-point0 { 5373 temperature = <90000>; 5374 hysteresis = <2000>; 5375 type = "hot"; 5376 }; 5377 }; 5378 }; 5379 5380 camera-thermal { 5381 polling-delay-passive = <250>; 5382 polling-delay = <1000>; 5383 5384 thermal-sensors = <&tsens1 5>; 5385 5386 trips { 5387 camera_alert0: trip-point0 { 5388 temperature = <90000>; 5389 hysteresis = <2000>; 5390 type = "hot"; 5391 }; 5392 }; 5393 }; 5394 5395 compute-thermal { 5396 polling-delay-passive = <250>; 5397 polling-delay = <1000>; 5398 5399 thermal-sensors = <&tsens1 6>; 5400 5401 trips { 5402 compute_alert0: trip-point0 { 5403 temperature = <90000>; 5404 hysteresis = <2000>; 5405 type = "hot"; 5406 }; 5407 }; 5408 }; 5409 5410 npu-thermal { 5411 polling-delay-passive = <250>; 5412 polling-delay = <1000>; 5413 5414 thermal-sensors = <&tsens1 7>; 5415 5416 trips { 5417 npu_alert0: trip-point0 { 5418 temperature = <90000>; 5419 hysteresis = <2000>; 5420 type = "hot"; 5421 }; 5422 }; 5423 }; 5424 5425 gpu-bottom-thermal { 5426 polling-delay-passive = <250>; 5427 polling-delay = <1000>; 5428 5429 thermal-sensors = <&tsens1 8>; 5430 5431 trips { 5432 gpu2_alert0: trip-point0 { 5433 temperature = <90000>; 5434 hysteresis = <2000>; 5435 type = "hot"; 5436 }; 5437 }; 5438 }; 5439 }; 5440}; 5441