1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interconnect/qcom,sm8250.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-aoss-qmp.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,apr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6afe.h> 19#include <dt-bindings/thermal/thermal.h> 20#include <dt-bindings/clock/qcom,videocc-sm8250.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 aliases { 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 i2c3 = &i2c3; 33 i2c4 = &i2c4; 34 i2c5 = &i2c5; 35 i2c6 = &i2c6; 36 i2c7 = &i2c7; 37 i2c8 = &i2c8; 38 i2c9 = &i2c9; 39 i2c10 = &i2c10; 40 i2c11 = &i2c11; 41 i2c12 = &i2c12; 42 i2c13 = &i2c13; 43 i2c14 = &i2c14; 44 i2c15 = &i2c15; 45 i2c16 = &i2c16; 46 i2c17 = &i2c17; 47 i2c18 = &i2c18; 48 i2c19 = &i2c19; 49 spi0 = &spi0; 50 spi1 = &spi1; 51 spi2 = &spi2; 52 spi3 = &spi3; 53 spi4 = &spi4; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi7 = &spi7; 57 spi8 = &spi8; 58 spi9 = &spi9; 59 spi10 = &spi10; 60 spi11 = &spi11; 61 spi12 = &spi12; 62 spi13 = &spi13; 63 spi14 = &spi14; 64 spi15 = &spi15; 65 spi16 = &spi16; 66 spi17 = &spi17; 67 spi18 = &spi18; 68 spi19 = &spi19; 69 }; 70 71 chosen { }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <38400000>; 78 clock-output-names = "xo_board"; 79 }; 80 81 sleep_clk: sleep-clk { 82 compatible = "fixed-clock"; 83 clock-frequency = <32768>; 84 #clock-cells = <0>; 85 }; 86 }; 87 88 cpus { 89 #address-cells = <2>; 90 #size-cells = <0>; 91 92 CPU0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo485"; 95 reg = <0x0 0x0>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <448>; 98 dynamic-power-coefficient = <205>; 99 next-level-cache = <&L2_0>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 #cooling-cells = <2>; 102 L2_0: l2-cache { 103 compatible = "cache"; 104 next-level-cache = <&L3_0>; 105 L3_0: l3-cache { 106 compatible = "cache"; 107 }; 108 }; 109 }; 110 111 CPU1: cpu@100 { 112 device_type = "cpu"; 113 compatible = "qcom,kryo485"; 114 reg = <0x0 0x100>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <448>; 117 dynamic-power-coefficient = <205>; 118 next-level-cache = <&L2_100>; 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 #cooling-cells = <2>; 121 L2_100: l2-cache { 122 compatible = "cache"; 123 next-level-cache = <&L3_0>; 124 }; 125 }; 126 127 CPU2: cpu@200 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo485"; 130 reg = <0x0 0x200>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <448>; 133 dynamic-power-coefficient = <205>; 134 next-level-cache = <&L2_200>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 #cooling-cells = <2>; 137 L2_200: l2-cache { 138 compatible = "cache"; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU3: cpu@300 { 144 device_type = "cpu"; 145 compatible = "qcom,kryo485"; 146 reg = <0x0 0x300>; 147 enable-method = "psci"; 148 capacity-dmips-mhz = <448>; 149 dynamic-power-coefficient = <205>; 150 next-level-cache = <&L2_300>; 151 qcom,freq-domain = <&cpufreq_hw 0>; 152 #cooling-cells = <2>; 153 L2_300: l2-cache { 154 compatible = "cache"; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU4: cpu@400 { 160 device_type = "cpu"; 161 compatible = "qcom,kryo485"; 162 reg = <0x0 0x400>; 163 enable-method = "psci"; 164 capacity-dmips-mhz = <1024>; 165 dynamic-power-coefficient = <379>; 166 next-level-cache = <&L2_400>; 167 qcom,freq-domain = <&cpufreq_hw 1>; 168 #cooling-cells = <2>; 169 L2_400: l2-cache { 170 compatible = "cache"; 171 next-level-cache = <&L3_0>; 172 }; 173 }; 174 175 CPU5: cpu@500 { 176 device_type = "cpu"; 177 compatible = "qcom,kryo485"; 178 reg = <0x0 0x500>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 dynamic-power-coefficient = <379>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 #cooling-cells = <2>; 185 L2_500: l2-cache { 186 compatible = "cache"; 187 next-level-cache = <&L3_0>; 188 }; 189 190 }; 191 192 CPU6: cpu@600 { 193 device_type = "cpu"; 194 compatible = "qcom,kryo485"; 195 reg = <0x0 0x600>; 196 enable-method = "psci"; 197 capacity-dmips-mhz = <1024>; 198 dynamic-power-coefficient = <379>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 #cooling-cells = <2>; 202 L2_600: l2-cache { 203 compatible = "cache"; 204 next-level-cache = <&L3_0>; 205 }; 206 }; 207 208 CPU7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "qcom,kryo485"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 capacity-dmips-mhz = <1024>; 214 dynamic-power-coefficient = <444>; 215 next-level-cache = <&L2_700>; 216 qcom,freq-domain = <&cpufreq_hw 2>; 217 #cooling-cells = <2>; 218 L2_700: l2-cache { 219 compatible = "cache"; 220 next-level-cache = <&L3_0>; 221 }; 222 }; 223 224 cpu-map { 225 cluster0 { 226 core0 { 227 cpu = <&CPU0>; 228 }; 229 230 core1 { 231 cpu = <&CPU1>; 232 }; 233 234 core2 { 235 cpu = <&CPU2>; 236 }; 237 238 core3 { 239 cpu = <&CPU3>; 240 }; 241 242 core4 { 243 cpu = <&CPU4>; 244 }; 245 246 core5 { 247 cpu = <&CPU5>; 248 }; 249 250 core6 { 251 cpu = <&CPU6>; 252 }; 253 254 core7 { 255 cpu = <&CPU7>; 256 }; 257 }; 258 }; 259 }; 260 261 firmware { 262 scm: scm { 263 compatible = "qcom,scm"; 264 #reset-cells = <1>; 265 }; 266 }; 267 268 memory@80000000 { 269 device_type = "memory"; 270 /* We expect the bootloader to fill in the size */ 271 reg = <0x0 0x80000000 0x0 0x0>; 272 }; 273 274 mmcx_reg: mmcx-reg { 275 compatible = "regulator-fixed-domain"; 276 power-domains = <&rpmhpd SM8250_MMCX>; 277 required-opps = <&rpmhpd_opp_low_svs>; 278 regulator-name = "MMCX"; 279 }; 280 281 pmu { 282 compatible = "arm,armv8-pmuv3"; 283 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 284 }; 285 286 psci { 287 compatible = "arm,psci-1.0"; 288 method = "smc"; 289 }; 290 291 reserved-memory { 292 #address-cells = <2>; 293 #size-cells = <2>; 294 ranges; 295 296 hyp_mem: memory@80000000 { 297 reg = <0x0 0x80000000 0x0 0x600000>; 298 no-map; 299 }; 300 301 xbl_aop_mem: memory@80700000 { 302 reg = <0x0 0x80700000 0x0 0x160000>; 303 no-map; 304 }; 305 306 cmd_db: memory@80860000 { 307 compatible = "qcom,cmd-db"; 308 reg = <0x0 0x80860000 0x0 0x20000>; 309 no-map; 310 }; 311 312 smem_mem: memory@80900000 { 313 reg = <0x0 0x80900000 0x0 0x200000>; 314 no-map; 315 }; 316 317 removed_mem: memory@80b00000 { 318 reg = <0x0 0x80b00000 0x0 0x5300000>; 319 no-map; 320 }; 321 322 camera_mem: memory@86200000 { 323 reg = <0x0 0x86200000 0x0 0x500000>; 324 no-map; 325 }; 326 327 wlan_mem: memory@86700000 { 328 reg = <0x0 0x86700000 0x0 0x100000>; 329 no-map; 330 }; 331 332 ipa_fw_mem: memory@86800000 { 333 reg = <0x0 0x86800000 0x0 0x10000>; 334 no-map; 335 }; 336 337 ipa_gsi_mem: memory@86810000 { 338 reg = <0x0 0x86810000 0x0 0xa000>; 339 no-map; 340 }; 341 342 gpu_mem: memory@8681a000 { 343 reg = <0x0 0x8681a000 0x0 0x2000>; 344 no-map; 345 }; 346 347 npu_mem: memory@86900000 { 348 reg = <0x0 0x86900000 0x0 0x500000>; 349 no-map; 350 }; 351 352 video_mem: memory@86e00000 { 353 reg = <0x0 0x86e00000 0x0 0x500000>; 354 no-map; 355 }; 356 357 cvp_mem: memory@87300000 { 358 reg = <0x0 0x87300000 0x0 0x500000>; 359 no-map; 360 }; 361 362 cdsp_mem: memory@87800000 { 363 reg = <0x0 0x87800000 0x0 0x1400000>; 364 no-map; 365 }; 366 367 slpi_mem: memory@88c00000 { 368 reg = <0x0 0x88c00000 0x0 0x1500000>; 369 no-map; 370 }; 371 372 adsp_mem: memory@8a100000 { 373 reg = <0x0 0x8a100000 0x0 0x1d00000>; 374 no-map; 375 }; 376 377 spss_mem: memory@8be00000 { 378 reg = <0x0 0x8be00000 0x0 0x100000>; 379 no-map; 380 }; 381 382 cdsp_secure_heap: memory@8bf00000 { 383 reg = <0x0 0x8bf00000 0x0 0x4600000>; 384 no-map; 385 }; 386 }; 387 388 smem { 389 compatible = "qcom,smem"; 390 memory-region = <&smem_mem>; 391 hwlocks = <&tcsr_mutex 3>; 392 }; 393 394 smp2p-adsp { 395 compatible = "qcom,smp2p"; 396 qcom,smem = <443>, <429>; 397 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 398 IPCC_MPROC_SIGNAL_SMP2P 399 IRQ_TYPE_EDGE_RISING>; 400 mboxes = <&ipcc IPCC_CLIENT_LPASS 401 IPCC_MPROC_SIGNAL_SMP2P>; 402 403 qcom,local-pid = <0>; 404 qcom,remote-pid = <2>; 405 406 smp2p_adsp_out: master-kernel { 407 qcom,entry-name = "master-kernel"; 408 #qcom,smem-state-cells = <1>; 409 }; 410 411 smp2p_adsp_in: slave-kernel { 412 qcom,entry-name = "slave-kernel"; 413 interrupt-controller; 414 #interrupt-cells = <2>; 415 }; 416 }; 417 418 smp2p-cdsp { 419 compatible = "qcom,smp2p"; 420 qcom,smem = <94>, <432>; 421 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 422 IPCC_MPROC_SIGNAL_SMP2P 423 IRQ_TYPE_EDGE_RISING>; 424 mboxes = <&ipcc IPCC_CLIENT_CDSP 425 IPCC_MPROC_SIGNAL_SMP2P>; 426 427 qcom,local-pid = <0>; 428 qcom,remote-pid = <5>; 429 430 smp2p_cdsp_out: master-kernel { 431 qcom,entry-name = "master-kernel"; 432 #qcom,smem-state-cells = <1>; 433 }; 434 435 smp2p_cdsp_in: slave-kernel { 436 qcom,entry-name = "slave-kernel"; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 }; 440 }; 441 442 smp2p-slpi { 443 compatible = "qcom,smp2p"; 444 qcom,smem = <481>, <430>; 445 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 446 IPCC_MPROC_SIGNAL_SMP2P 447 IRQ_TYPE_EDGE_RISING>; 448 mboxes = <&ipcc IPCC_CLIENT_SLPI 449 IPCC_MPROC_SIGNAL_SMP2P>; 450 451 qcom,local-pid = <0>; 452 qcom,remote-pid = <3>; 453 454 smp2p_slpi_out: master-kernel { 455 qcom,entry-name = "master-kernel"; 456 #qcom,smem-state-cells = <1>; 457 }; 458 459 smp2p_slpi_in: slave-kernel { 460 qcom,entry-name = "slave-kernel"; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 }; 464 }; 465 466 soc: soc@0 { 467 #address-cells = <2>; 468 #size-cells = <2>; 469 ranges = <0 0 0 0 0x10 0>; 470 dma-ranges = <0 0 0 0 0x10 0>; 471 compatible = "simple-bus"; 472 473 gcc: clock-controller@100000 { 474 compatible = "qcom,gcc-sm8250"; 475 reg = <0x0 0x00100000 0x0 0x1f0000>; 476 #clock-cells = <1>; 477 #reset-cells = <1>; 478 #power-domain-cells = <1>; 479 clock-names = "bi_tcxo", 480 "bi_tcxo_ao", 481 "sleep_clk"; 482 clocks = <&rpmhcc RPMH_CXO_CLK>, 483 <&rpmhcc RPMH_CXO_CLK_A>, 484 <&sleep_clk>; 485 }; 486 487 ipcc: mailbox@408000 { 488 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 489 reg = <0 0x00408000 0 0x1000>; 490 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 491 interrupt-controller; 492 #interrupt-cells = <3>; 493 #mbox-cells = <2>; 494 }; 495 496 rng: rng@793000 { 497 compatible = "qcom,prng-ee"; 498 reg = <0 0x00793000 0 0x1000>; 499 clocks = <&gcc GCC_PRNG_AHB_CLK>; 500 clock-names = "core"; 501 }; 502 503 qup_opp_table: qup-opp-table { 504 compatible = "operating-points-v2"; 505 506 opp-50000000 { 507 opp-hz = /bits/ 64 <50000000>; 508 required-opps = <&rpmhpd_opp_min_svs>; 509 }; 510 511 opp-75000000 { 512 opp-hz = /bits/ 64 <75000000>; 513 required-opps = <&rpmhpd_opp_low_svs>; 514 }; 515 516 opp-120000000 { 517 opp-hz = /bits/ 64 <120000000>; 518 required-opps = <&rpmhpd_opp_svs>; 519 }; 520 }; 521 522 qupv3_id_2: geniqup@8c0000 { 523 compatible = "qcom,geni-se-qup"; 524 reg = <0x0 0x008c0000 0x0 0x6000>; 525 clock-names = "m-ahb", "s-ahb"; 526 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 527 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 528 #address-cells = <2>; 529 #size-cells = <2>; 530 iommus = <&apps_smmu 0x63 0x0>; 531 ranges; 532 status = "disabled"; 533 534 i2c14: i2c@880000 { 535 compatible = "qcom,geni-i2c"; 536 reg = <0 0x00880000 0 0x4000>; 537 clock-names = "se"; 538 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&qup_i2c14_default>; 541 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 status = "disabled"; 545 }; 546 547 spi14: spi@880000 { 548 compatible = "qcom,geni-spi"; 549 reg = <0 0x00880000 0 0x4000>; 550 clock-names = "se"; 551 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 552 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 power-domains = <&rpmhpd SM8250_CX>; 556 operating-points-v2 = <&qup_opp_table>; 557 status = "disabled"; 558 }; 559 560 i2c15: i2c@884000 { 561 compatible = "qcom,geni-i2c"; 562 reg = <0 0x00884000 0 0x4000>; 563 clock-names = "se"; 564 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&qup_i2c15_default>; 567 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 spi15: spi@884000 { 574 compatible = "qcom,geni-spi"; 575 reg = <0 0x00884000 0 0x4000>; 576 clock-names = "se"; 577 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 578 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 power-domains = <&rpmhpd SM8250_CX>; 582 operating-points-v2 = <&qup_opp_table>; 583 status = "disabled"; 584 }; 585 586 i2c16: i2c@888000 { 587 compatible = "qcom,geni-i2c"; 588 reg = <0 0x00888000 0 0x4000>; 589 clock-names = "se"; 590 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&qup_i2c16_default>; 593 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 status = "disabled"; 597 }; 598 599 spi16: spi@888000 { 600 compatible = "qcom,geni-spi"; 601 reg = <0 0x00888000 0 0x4000>; 602 clock-names = "se"; 603 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 604 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 power-domains = <&rpmhpd SM8250_CX>; 608 operating-points-v2 = <&qup_opp_table>; 609 status = "disabled"; 610 }; 611 612 i2c17: i2c@88c000 { 613 compatible = "qcom,geni-i2c"; 614 reg = <0 0x0088c000 0 0x4000>; 615 clock-names = "se"; 616 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&qup_i2c17_default>; 619 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 status = "disabled"; 623 }; 624 625 spi17: spi@88c000 { 626 compatible = "qcom,geni-spi"; 627 reg = <0 0x0088c000 0 0x4000>; 628 clock-names = "se"; 629 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 630 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 power-domains = <&rpmhpd SM8250_CX>; 634 operating-points-v2 = <&qup_opp_table>; 635 status = "disabled"; 636 }; 637 638 uart17: serial@88c000 { 639 compatible = "qcom,geni-uart"; 640 reg = <0 0x0088c000 0 0x4000>; 641 clock-names = "se"; 642 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&qup_uart17_default>; 645 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 646 power-domains = <&rpmhpd SM8250_CX>; 647 operating-points-v2 = <&qup_opp_table>; 648 status = "disabled"; 649 }; 650 651 i2c18: i2c@890000 { 652 compatible = "qcom,geni-i2c"; 653 reg = <0 0x00890000 0 0x4000>; 654 clock-names = "se"; 655 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&qup_i2c18_default>; 658 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 status = "disabled"; 662 }; 663 664 spi18: spi@890000 { 665 compatible = "qcom,geni-spi"; 666 reg = <0 0x00890000 0 0x4000>; 667 clock-names = "se"; 668 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 669 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 power-domains = <&rpmhpd SM8250_CX>; 673 operating-points-v2 = <&qup_opp_table>; 674 status = "disabled"; 675 }; 676 677 uart18: serial@890000 { 678 compatible = "qcom,geni-uart"; 679 reg = <0 0x00890000 0 0x4000>; 680 clock-names = "se"; 681 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 682 pinctrl-names = "default"; 683 pinctrl-0 = <&qup_uart18_default>; 684 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 685 power-domains = <&rpmhpd SM8250_CX>; 686 operating-points-v2 = <&qup_opp_table>; 687 status = "disabled"; 688 }; 689 690 i2c19: i2c@894000 { 691 compatible = "qcom,geni-i2c"; 692 reg = <0 0x00894000 0 0x4000>; 693 clock-names = "se"; 694 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&qup_i2c19_default>; 697 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 spi19: spi@894000 { 704 compatible = "qcom,geni-spi"; 705 reg = <0 0x00894000 0 0x4000>; 706 clock-names = "se"; 707 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 708 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 power-domains = <&rpmhpd SM8250_CX>; 712 operating-points-v2 = <&qup_opp_table>; 713 status = "disabled"; 714 }; 715 }; 716 717 qupv3_id_0: geniqup@9c0000 { 718 compatible = "qcom,geni-se-qup"; 719 reg = <0x0 0x009c0000 0x0 0x6000>; 720 clock-names = "m-ahb", "s-ahb"; 721 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 722 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 723 #address-cells = <2>; 724 #size-cells = <2>; 725 iommus = <&apps_smmu 0x5a3 0x0>; 726 ranges; 727 status = "disabled"; 728 729 i2c0: i2c@980000 { 730 compatible = "qcom,geni-i2c"; 731 reg = <0 0x00980000 0 0x4000>; 732 clock-names = "se"; 733 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&qup_i2c0_default>; 736 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 status = "disabled"; 740 }; 741 742 spi0: spi@980000 { 743 compatible = "qcom,geni-spi"; 744 reg = <0 0x00980000 0 0x4000>; 745 clock-names = "se"; 746 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 747 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 power-domains = <&rpmhpd SM8250_CX>; 751 operating-points-v2 = <&qup_opp_table>; 752 status = "disabled"; 753 }; 754 755 i2c1: i2c@984000 { 756 compatible = "qcom,geni-i2c"; 757 reg = <0 0x00984000 0 0x4000>; 758 clock-names = "se"; 759 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&qup_i2c1_default>; 762 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 status = "disabled"; 766 }; 767 768 spi1: spi@984000 { 769 compatible = "qcom,geni-spi"; 770 reg = <0 0x00984000 0 0x4000>; 771 clock-names = "se"; 772 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 773 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 power-domains = <&rpmhpd SM8250_CX>; 777 operating-points-v2 = <&qup_opp_table>; 778 status = "disabled"; 779 }; 780 781 i2c2: i2c@988000 { 782 compatible = "qcom,geni-i2c"; 783 reg = <0 0x00988000 0 0x4000>; 784 clock-names = "se"; 785 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&qup_i2c2_default>; 788 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 794 spi2: spi@988000 { 795 compatible = "qcom,geni-spi"; 796 reg = <0 0x00988000 0 0x4000>; 797 clock-names = "se"; 798 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 799 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 power-domains = <&rpmhpd SM8250_CX>; 803 operating-points-v2 = <&qup_opp_table>; 804 status = "disabled"; 805 }; 806 807 uart2: serial@988000 { 808 compatible = "qcom,geni-debug-uart"; 809 reg = <0 0x00988000 0 0x4000>; 810 clock-names = "se"; 811 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&qup_uart2_default>; 814 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 815 power-domains = <&rpmhpd SM8250_CX>; 816 operating-points-v2 = <&qup_opp_table>; 817 status = "disabled"; 818 }; 819 820 i2c3: i2c@98c000 { 821 compatible = "qcom,geni-i2c"; 822 reg = <0 0x0098c000 0 0x4000>; 823 clock-names = "se"; 824 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 825 pinctrl-names = "default"; 826 pinctrl-0 = <&qup_i2c3_default>; 827 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 status = "disabled"; 831 }; 832 833 spi3: spi@98c000 { 834 compatible = "qcom,geni-spi"; 835 reg = <0 0x0098c000 0 0x4000>; 836 clock-names = "se"; 837 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 838 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 power-domains = <&rpmhpd SM8250_CX>; 842 operating-points-v2 = <&qup_opp_table>; 843 status = "disabled"; 844 }; 845 846 i2c4: i2c@990000 { 847 compatible = "qcom,geni-i2c"; 848 reg = <0 0x00990000 0 0x4000>; 849 clock-names = "se"; 850 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&qup_i2c4_default>; 853 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 status = "disabled"; 857 }; 858 859 spi4: spi@990000 { 860 compatible = "qcom,geni-spi"; 861 reg = <0 0x00990000 0 0x4000>; 862 clock-names = "se"; 863 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 864 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 power-domains = <&rpmhpd SM8250_CX>; 868 operating-points-v2 = <&qup_opp_table>; 869 status = "disabled"; 870 }; 871 872 i2c5: i2c@994000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0 0x00994000 0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&qup_i2c5_default>; 879 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 status = "disabled"; 883 }; 884 885 spi5: spi@994000 { 886 compatible = "qcom,geni-spi"; 887 reg = <0 0x00994000 0 0x4000>; 888 clock-names = "se"; 889 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 890 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 power-domains = <&rpmhpd SM8250_CX>; 894 operating-points-v2 = <&qup_opp_table>; 895 status = "disabled"; 896 }; 897 898 i2c6: i2c@998000 { 899 compatible = "qcom,geni-i2c"; 900 reg = <0 0x00998000 0 0x4000>; 901 clock-names = "se"; 902 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 903 pinctrl-names = "default"; 904 pinctrl-0 = <&qup_i2c6_default>; 905 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 status = "disabled"; 909 }; 910 911 spi6: spi@998000 { 912 compatible = "qcom,geni-spi"; 913 reg = <0 0x00998000 0 0x4000>; 914 clock-names = "se"; 915 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 916 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 power-domains = <&rpmhpd SM8250_CX>; 920 operating-points-v2 = <&qup_opp_table>; 921 status = "disabled"; 922 }; 923 924 uart6: serial@998000 { 925 compatible = "qcom,geni-uart"; 926 reg = <0 0x00998000 0 0x4000>; 927 clock-names = "se"; 928 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 929 pinctrl-names = "default"; 930 pinctrl-0 = <&qup_uart6_default>; 931 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 932 power-domains = <&rpmhpd SM8250_CX>; 933 operating-points-v2 = <&qup_opp_table>; 934 status = "disabled"; 935 }; 936 937 i2c7: i2c@99c000 { 938 compatible = "qcom,geni-i2c"; 939 reg = <0 0x0099c000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_i2c7_default>; 944 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 spi7: spi@99c000 { 951 compatible = "qcom,geni-spi"; 952 reg = <0 0x0099c000 0 0x4000>; 953 clock-names = "se"; 954 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 955 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 power-domains = <&rpmhpd SM8250_CX>; 959 operating-points-v2 = <&qup_opp_table>; 960 status = "disabled"; 961 }; 962 }; 963 964 qupv3_id_1: geniqup@ac0000 { 965 compatible = "qcom,geni-se-qup"; 966 reg = <0x0 0x00ac0000 0x0 0x6000>; 967 clock-names = "m-ahb", "s-ahb"; 968 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 969 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 970 #address-cells = <2>; 971 #size-cells = <2>; 972 iommus = <&apps_smmu 0x43 0x0>; 973 ranges; 974 status = "disabled"; 975 976 i2c8: i2c@a80000 { 977 compatible = "qcom,geni-i2c"; 978 reg = <0 0x00a80000 0 0x4000>; 979 clock-names = "se"; 980 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&qup_i2c8_default>; 983 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 status = "disabled"; 987 }; 988 989 spi8: spi@a80000 { 990 compatible = "qcom,geni-spi"; 991 reg = <0 0x00a80000 0 0x4000>; 992 clock-names = "se"; 993 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 994 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 power-domains = <&rpmhpd SM8250_CX>; 998 operating-points-v2 = <&qup_opp_table>; 999 status = "disabled"; 1000 }; 1001 1002 i2c9: i2c@a84000 { 1003 compatible = "qcom,geni-i2c"; 1004 reg = <0 0x00a84000 0 0x4000>; 1005 clock-names = "se"; 1006 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1007 pinctrl-names = "default"; 1008 pinctrl-0 = <&qup_i2c9_default>; 1009 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 spi9: spi@a84000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0 0x00a84000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1020 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 power-domains = <&rpmhpd SM8250_CX>; 1024 operating-points-v2 = <&qup_opp_table>; 1025 status = "disabled"; 1026 }; 1027 1028 i2c10: i2c@a88000 { 1029 compatible = "qcom,geni-i2c"; 1030 reg = <0 0x00a88000 0 0x4000>; 1031 clock-names = "se"; 1032 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&qup_i2c10_default>; 1035 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 status = "disabled"; 1039 }; 1040 1041 spi10: spi@a88000 { 1042 compatible = "qcom,geni-spi"; 1043 reg = <0 0x00a88000 0 0x4000>; 1044 clock-names = "se"; 1045 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1046 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 power-domains = <&rpmhpd SM8250_CX>; 1050 operating-points-v2 = <&qup_opp_table>; 1051 status = "disabled"; 1052 }; 1053 1054 i2c11: i2c@a8c000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0 0x00a8c000 0 0x4000>; 1057 clock-names = "se"; 1058 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_i2c11_default>; 1061 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 spi11: spi@a8c000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0 0x00a8c000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1072 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 power-domains = <&rpmhpd SM8250_CX>; 1076 operating-points-v2 = <&qup_opp_table>; 1077 status = "disabled"; 1078 }; 1079 1080 i2c12: i2c@a90000 { 1081 compatible = "qcom,geni-i2c"; 1082 reg = <0 0x00a90000 0 0x4000>; 1083 clock-names = "se"; 1084 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&qup_i2c12_default>; 1087 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 status = "disabled"; 1091 }; 1092 1093 spi12: spi@a90000 { 1094 compatible = "qcom,geni-spi"; 1095 reg = <0 0x00a90000 0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1098 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 power-domains = <&rpmhpd SM8250_CX>; 1102 operating-points-v2 = <&qup_opp_table>; 1103 status = "disabled"; 1104 }; 1105 1106 uart12: serial@a90000 { 1107 compatible = "qcom,geni-debug-uart"; 1108 reg = <0x0 0x00a90000 0x0 0x4000>; 1109 clock-names = "se"; 1110 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&qup_uart12_default>; 1113 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1114 power-domains = <&rpmhpd SM8250_CX>; 1115 operating-points-v2 = <&qup_opp_table>; 1116 status = "disabled"; 1117 }; 1118 1119 i2c13: i2c@a94000 { 1120 compatible = "qcom,geni-i2c"; 1121 reg = <0 0x00a94000 0 0x4000>; 1122 clock-names = "se"; 1123 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&qup_i2c13_default>; 1126 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 spi13: spi@a94000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x00a94000 0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1137 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 power-domains = <&rpmhpd SM8250_CX>; 1141 operating-points-v2 = <&qup_opp_table>; 1142 status = "disabled"; 1143 }; 1144 }; 1145 1146 config_noc: interconnect@1500000 { 1147 compatible = "qcom,sm8250-config-noc"; 1148 reg = <0 0x01500000 0 0xa580>; 1149 #interconnect-cells = <1>; 1150 qcom,bcm-voters = <&apps_bcm_voter>; 1151 }; 1152 1153 system_noc: interconnect@1620000 { 1154 compatible = "qcom,sm8250-system-noc"; 1155 reg = <0 0x01620000 0 0x1c200>; 1156 #interconnect-cells = <1>; 1157 qcom,bcm-voters = <&apps_bcm_voter>; 1158 }; 1159 1160 mc_virt: interconnect@163d000 { 1161 compatible = "qcom,sm8250-mc-virt"; 1162 reg = <0 0x0163d000 0 0x1000>; 1163 #interconnect-cells = <1>; 1164 qcom,bcm-voters = <&apps_bcm_voter>; 1165 }; 1166 1167 aggre1_noc: interconnect@16e0000 { 1168 compatible = "qcom,sm8250-aggre1-noc"; 1169 reg = <0 0x016e0000 0 0x1f180>; 1170 #interconnect-cells = <1>; 1171 qcom,bcm-voters = <&apps_bcm_voter>; 1172 }; 1173 1174 aggre2_noc: interconnect@1700000 { 1175 compatible = "qcom,sm8250-aggre2-noc"; 1176 reg = <0 0x01700000 0 0x33000>; 1177 #interconnect-cells = <1>; 1178 qcom,bcm-voters = <&apps_bcm_voter>; 1179 }; 1180 1181 compute_noc: interconnect@1733000 { 1182 compatible = "qcom,sm8250-compute-noc"; 1183 reg = <0 0x01733000 0 0xa180>; 1184 #interconnect-cells = <1>; 1185 qcom,bcm-voters = <&apps_bcm_voter>; 1186 }; 1187 1188 mmss_noc: interconnect@1740000 { 1189 compatible = "qcom,sm8250-mmss-noc"; 1190 reg = <0 0x01740000 0 0x1f080>; 1191 #interconnect-cells = <1>; 1192 qcom,bcm-voters = <&apps_bcm_voter>; 1193 }; 1194 1195 pcie0: pci@1c00000 { 1196 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1197 reg = <0 0x01c00000 0 0x3000>, 1198 <0 0x60000000 0 0xf1d>, 1199 <0 0x60000f20 0 0xa8>, 1200 <0 0x60001000 0 0x1000>, 1201 <0 0x60100000 0 0x100000>; 1202 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1203 device_type = "pci"; 1204 linux,pci-domain = <0>; 1205 bus-range = <0x00 0xff>; 1206 num-lanes = <1>; 1207 1208 #address-cells = <3>; 1209 #size-cells = <2>; 1210 1211 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1212 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1213 1214 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1215 interrupt-names = "msi"; 1216 #interrupt-cells = <1>; 1217 interrupt-map-mask = <0 0 0 0x7>; 1218 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1219 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1220 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1221 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1222 1223 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1224 <&gcc GCC_PCIE_0_AUX_CLK>, 1225 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1226 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1227 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1228 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1229 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1230 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1231 clock-names = "pipe", 1232 "aux", 1233 "cfg", 1234 "bus_master", 1235 "bus_slave", 1236 "slave_q2a", 1237 "tbu", 1238 "ddrss_sf_tbu"; 1239 1240 iommus = <&apps_smmu 0x1c00 0x7f>; 1241 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1242 <0x100 &apps_smmu 0x1c01 0x1>; 1243 1244 resets = <&gcc GCC_PCIE_0_BCR>; 1245 reset-names = "pci"; 1246 1247 power-domains = <&gcc PCIE_0_GDSC>; 1248 1249 phys = <&pcie0_lane>; 1250 phy-names = "pciephy"; 1251 1252 status = "disabled"; 1253 }; 1254 1255 pcie0_phy: phy@1c06000 { 1256 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1257 reg = <0 0x01c06000 0 0x1c0>; 1258 #address-cells = <2>; 1259 #size-cells = <2>; 1260 ranges; 1261 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1262 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1263 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1264 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1265 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1266 1267 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1268 reset-names = "phy"; 1269 1270 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1271 assigned-clock-rates = <100000000>; 1272 1273 status = "disabled"; 1274 1275 pcie0_lane: lanes@1c06200 { 1276 reg = <0 0x1c06200 0 0x170>, /* tx */ 1277 <0 0x1c06400 0 0x200>, /* rx */ 1278 <0 0x1c06800 0 0x1f0>, /* pcs */ 1279 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1280 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1281 clock-names = "pipe0"; 1282 1283 #phy-cells = <0>; 1284 clock-output-names = "pcie_0_pipe_clk"; 1285 }; 1286 }; 1287 1288 pcie1: pci@1c08000 { 1289 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1290 reg = <0 0x01c08000 0 0x3000>, 1291 <0 0x40000000 0 0xf1d>, 1292 <0 0x40000f20 0 0xa8>, 1293 <0 0x40001000 0 0x1000>, 1294 <0 0x40100000 0 0x100000>; 1295 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1296 device_type = "pci"; 1297 linux,pci-domain = <1>; 1298 bus-range = <0x00 0xff>; 1299 num-lanes = <2>; 1300 1301 #address-cells = <3>; 1302 #size-cells = <2>; 1303 1304 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1305 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1306 1307 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>; 1308 interrupt-names = "msi"; 1309 #interrupt-cells = <1>; 1310 interrupt-map-mask = <0 0 0 0x7>; 1311 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1312 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1313 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1314 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1315 1316 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1317 <&gcc GCC_PCIE_1_AUX_CLK>, 1318 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1319 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1320 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1321 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1322 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1323 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1324 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1325 clock-names = "pipe", 1326 "aux", 1327 "cfg", 1328 "bus_master", 1329 "bus_slave", 1330 "slave_q2a", 1331 "ref", 1332 "tbu", 1333 "ddrss_sf_tbu"; 1334 1335 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1336 assigned-clock-rates = <19200000>; 1337 1338 iommus = <&apps_smmu 0x1c80 0x7f>; 1339 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1340 <0x100 &apps_smmu 0x1c81 0x1>; 1341 1342 resets = <&gcc GCC_PCIE_1_BCR>; 1343 reset-names = "pci"; 1344 1345 power-domains = <&gcc PCIE_1_GDSC>; 1346 1347 phys = <&pcie1_lane>; 1348 phy-names = "pciephy"; 1349 1350 status = "disabled"; 1351 }; 1352 1353 pcie1_phy: phy@1c0e000 { 1354 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1355 reg = <0 0x01c0e000 0 0x1c0>; 1356 #address-cells = <2>; 1357 #size-cells = <2>; 1358 ranges; 1359 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1360 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1361 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1362 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1363 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1364 1365 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1366 reset-names = "phy"; 1367 1368 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1369 assigned-clock-rates = <100000000>; 1370 1371 status = "disabled"; 1372 1373 pcie1_lane: lanes@1c0e200 { 1374 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1375 <0 0x1c0e400 0 0x200>, /* rx0 */ 1376 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1377 <0 0x1c0e600 0 0x170>, /* tx1 */ 1378 <0 0x1c0e800 0 0x200>, /* rx1 */ 1379 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1380 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1381 clock-names = "pipe0"; 1382 1383 #phy-cells = <0>; 1384 clock-output-names = "pcie_1_pipe_clk"; 1385 }; 1386 }; 1387 1388 pcie2: pci@1c10000 { 1389 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1390 reg = <0 0x01c10000 0 0x3000>, 1391 <0 0x64000000 0 0xf1d>, 1392 <0 0x64000f20 0 0xa8>, 1393 <0 0x64001000 0 0x1000>, 1394 <0 0x64100000 0 0x100000>; 1395 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1396 device_type = "pci"; 1397 linux,pci-domain = <2>; 1398 bus-range = <0x00 0xff>; 1399 num-lanes = <2>; 1400 1401 #address-cells = <3>; 1402 #size-cells = <2>; 1403 1404 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 1405 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1406 1407 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 1408 interrupt-names = "msi"; 1409 #interrupt-cells = <1>; 1410 interrupt-map-mask = <0 0 0 0x7>; 1411 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1412 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1413 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1414 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1415 1416 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1417 <&gcc GCC_PCIE_2_AUX_CLK>, 1418 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1419 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1420 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1421 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1422 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1423 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1424 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1425 clock-names = "pipe", 1426 "aux", 1427 "cfg", 1428 "bus_master", 1429 "bus_slave", 1430 "slave_q2a", 1431 "ref", 1432 "tbu", 1433 "ddrss_sf_tbu"; 1434 1435 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1436 assigned-clock-rates = <19200000>; 1437 1438 iommus = <&apps_smmu 0x1d00 0x7f>; 1439 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1440 <0x100 &apps_smmu 0x1d01 0x1>; 1441 1442 resets = <&gcc GCC_PCIE_2_BCR>; 1443 reset-names = "pci"; 1444 1445 power-domains = <&gcc PCIE_2_GDSC>; 1446 1447 phys = <&pcie2_lane>; 1448 phy-names = "pciephy"; 1449 1450 status = "disabled"; 1451 }; 1452 1453 pcie2_phy: phy@1c16000 { 1454 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1455 reg = <0 0x1c16000 0 0x1c0>; 1456 #address-cells = <2>; 1457 #size-cells = <2>; 1458 ranges; 1459 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1460 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1461 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1462 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1463 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1464 1465 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1466 reset-names = "phy"; 1467 1468 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1469 assigned-clock-rates = <100000000>; 1470 1471 status = "disabled"; 1472 1473 pcie2_lane: lanes@1c0e200 { 1474 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1475 <0 0x1c16400 0 0x200>, /* rx0 */ 1476 <0 0x1c16a00 0 0x1f0>, /* pcs */ 1477 <0 0x1c16600 0 0x170>, /* tx1 */ 1478 <0 0x1c16800 0 0x200>, /* rx1 */ 1479 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1480 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1481 clock-names = "pipe0"; 1482 1483 #phy-cells = <0>; 1484 clock-output-names = "pcie_2_pipe_clk"; 1485 }; 1486 }; 1487 1488 ufs_mem_hc: ufshc@1d84000 { 1489 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1490 "jedec,ufs-2.0"; 1491 reg = <0 0x01d84000 0 0x3000>; 1492 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1493 phys = <&ufs_mem_phy_lanes>; 1494 phy-names = "ufsphy"; 1495 lanes-per-direction = <2>; 1496 #reset-cells = <1>; 1497 resets = <&gcc GCC_UFS_PHY_BCR>; 1498 reset-names = "rst"; 1499 1500 power-domains = <&gcc UFS_PHY_GDSC>; 1501 1502 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1503 1504 clock-names = 1505 "core_clk", 1506 "bus_aggr_clk", 1507 "iface_clk", 1508 "core_clk_unipro", 1509 "ref_clk", 1510 "tx_lane0_sync_clk", 1511 "rx_lane0_sync_clk", 1512 "rx_lane1_sync_clk"; 1513 clocks = 1514 <&gcc GCC_UFS_PHY_AXI_CLK>, 1515 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1516 <&gcc GCC_UFS_PHY_AHB_CLK>, 1517 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1518 <&rpmhcc RPMH_CXO_CLK>, 1519 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1520 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1521 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1522 freq-table-hz = 1523 <37500000 300000000>, 1524 <0 0>, 1525 <0 0>, 1526 <37500000 300000000>, 1527 <0 0>, 1528 <0 0>, 1529 <0 0>, 1530 <0 0>; 1531 1532 status = "disabled"; 1533 }; 1534 1535 ufs_mem_phy: phy@1d87000 { 1536 compatible = "qcom,sm8250-qmp-ufs-phy"; 1537 reg = <0 0x01d87000 0 0x1c0>; 1538 #address-cells = <2>; 1539 #size-cells = <2>; 1540 ranges; 1541 clock-names = "ref", 1542 "ref_aux"; 1543 clocks = <&rpmhcc RPMH_CXO_CLK>, 1544 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1545 1546 resets = <&ufs_mem_hc 0>; 1547 reset-names = "ufsphy"; 1548 status = "disabled"; 1549 1550 ufs_mem_phy_lanes: lanes@1d87400 { 1551 reg = <0 0x01d87400 0 0x108>, 1552 <0 0x01d87600 0 0x1e0>, 1553 <0 0x01d87c00 0 0x1dc>, 1554 <0 0x01d87800 0 0x108>, 1555 <0 0x01d87a00 0 0x1e0>; 1556 #phy-cells = <0>; 1557 }; 1558 }; 1559 1560 ipa_virt: interconnect@1e00000 { 1561 compatible = "qcom,sm8250-ipa-virt"; 1562 reg = <0 0x01e00000 0 0x1000>; 1563 #interconnect-cells = <1>; 1564 qcom,bcm-voters = <&apps_bcm_voter>; 1565 }; 1566 1567 tcsr_mutex: hwlock@1f40000 { 1568 compatible = "qcom,tcsr-mutex"; 1569 reg = <0x0 0x01f40000 0x0 0x40000>; 1570 #hwlock-cells = <1>; 1571 }; 1572 1573 wsamacro: codec@3240000 { 1574 compatible = "qcom,sm8250-lpass-wsa-macro"; 1575 reg = <0 0x03240000 0 0x1000>; 1576 clocks = <&audiocc 1>, 1577 <&audiocc 0>, 1578 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1579 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1580 <&aoncc 0>, 1581 <&vamacro>; 1582 1583 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1584 1585 #clock-cells = <0>; 1586 clock-frequency = <9600000>; 1587 clock-output-names = "mclk"; 1588 #sound-dai-cells = <1>; 1589 1590 pinctrl-names = "default"; 1591 pinctrl-0 = <&wsa_swr_active>; 1592 }; 1593 1594 swr0: soundwire-controller@3250000 { 1595 reg = <0 0x03250000 0 0x2000>; 1596 compatible = "qcom,soundwire-v1.5.1"; 1597 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1598 clocks = <&wsamacro>; 1599 clock-names = "iface"; 1600 1601 qcom,din-ports = <2>; 1602 qcom,dout-ports = <6>; 1603 1604 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1605 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1606 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1607 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1608 1609 #sound-dai-cells = <1>; 1610 #address-cells = <2>; 1611 #size-cells = <0>; 1612 }; 1613 1614 audiocc: clock-controller@3300000 { 1615 compatible = "qcom,sm8250-lpass-audiocc"; 1616 reg = <0 0x03300000 0 0x30000>; 1617 #clock-cells = <1>; 1618 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1619 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1620 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1621 clock-names = "core", "audio", "bus"; 1622 }; 1623 1624 vamacro: codec@3370000 { 1625 compatible = "qcom,sm8250-lpass-va-macro"; 1626 reg = <0 0x03370000 0 0x1000>; 1627 clocks = <&aoncc 0>, 1628 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1629 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1630 1631 clock-names = "mclk", "macro", "dcodec"; 1632 1633 #clock-cells = <0>; 1634 clock-frequency = <9600000>; 1635 clock-output-names = "fsgen"; 1636 #sound-dai-cells = <1>; 1637 }; 1638 1639 aoncc: clock-controller@3380000 { 1640 compatible = "qcom,sm8250-lpass-aoncc"; 1641 reg = <0 0x03380000 0 0x40000>; 1642 #clock-cells = <1>; 1643 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1644 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1645 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1646 clock-names = "core", "audio", "bus"; 1647 }; 1648 1649 lpass_tlmm: pinctrl@33c0000{ 1650 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 1651 reg = <0 0x033c0000 0x0 0x20000>, 1652 <0 0x03550000 0x0 0x10000>; 1653 gpio-controller; 1654 #gpio-cells = <2>; 1655 gpio-ranges = <&lpass_tlmm 0 0 14>; 1656 1657 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1658 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1659 clock-names = "core", "audio"; 1660 1661 wsa_swr_active: wsa-swr-active-pins { 1662 clk { 1663 pins = "gpio10"; 1664 function = "wsa_swr_clk"; 1665 drive-strength = <2>; 1666 slew-rate = <1>; 1667 bias-disable; 1668 }; 1669 1670 data { 1671 pins = "gpio11"; 1672 function = "wsa_swr_data"; 1673 drive-strength = <2>; 1674 slew-rate = <1>; 1675 bias-bus-hold; 1676 1677 }; 1678 }; 1679 1680 wsa_swr_sleep: wsa-swr-sleep-pins { 1681 clk { 1682 pins = "gpio10"; 1683 function = "wsa_swr_clk"; 1684 drive-strength = <2>; 1685 input-enable; 1686 bias-pull-down; 1687 }; 1688 1689 data { 1690 pins = "gpio11"; 1691 function = "wsa_swr_data"; 1692 drive-strength = <2>; 1693 input-enable; 1694 bias-pull-down; 1695 1696 }; 1697 }; 1698 1699 dmic01_active: dmic01-active-pins { 1700 clk { 1701 pins = "gpio6"; 1702 function = "dmic1_clk"; 1703 drive-strength = <8>; 1704 output-high; 1705 }; 1706 data { 1707 pins = "gpio7"; 1708 function = "dmic1_data"; 1709 drive-strength = <8>; 1710 input-enable; 1711 }; 1712 }; 1713 1714 dmic01_sleep: dmic01-sleep-pins { 1715 clk { 1716 pins = "gpio6"; 1717 function = "dmic1_clk"; 1718 drive-strength = <2>; 1719 bias-disable; 1720 output-low; 1721 }; 1722 1723 data { 1724 pins = "gpio7"; 1725 function = "dmic1_data"; 1726 drive-strength = <2>; 1727 pull-down; 1728 input-enable; 1729 }; 1730 }; 1731 }; 1732 1733 gpu: gpu@3d00000 { 1734 compatible = "qcom,adreno-650.2", 1735 "qcom,adreno"; 1736 #stream-id-cells = <16>; 1737 1738 reg = <0 0x03d00000 0 0x40000>; 1739 reg-names = "kgsl_3d0_reg_memory"; 1740 1741 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1742 1743 iommus = <&adreno_smmu 0 0x401>; 1744 1745 operating-points-v2 = <&gpu_opp_table>; 1746 1747 qcom,gmu = <&gmu>; 1748 1749 zap-shader { 1750 memory-region = <&gpu_mem>; 1751 }; 1752 1753 /* note: downstream checks gpu binning for 670 Mhz */ 1754 gpu_opp_table: opp-table { 1755 compatible = "operating-points-v2"; 1756 1757 opp-670000000 { 1758 opp-hz = /bits/ 64 <670000000>; 1759 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1760 }; 1761 1762 opp-587000000 { 1763 opp-hz = /bits/ 64 <587000000>; 1764 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1765 }; 1766 1767 opp-525000000 { 1768 opp-hz = /bits/ 64 <525000000>; 1769 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1770 }; 1771 1772 opp-490000000 { 1773 opp-hz = /bits/ 64 <490000000>; 1774 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1775 }; 1776 1777 opp-441600000 { 1778 opp-hz = /bits/ 64 <441600000>; 1779 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1780 }; 1781 1782 opp-400000000 { 1783 opp-hz = /bits/ 64 <400000000>; 1784 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1785 }; 1786 1787 opp-305000000 { 1788 opp-hz = /bits/ 64 <305000000>; 1789 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1790 }; 1791 }; 1792 }; 1793 1794 gmu: gmu@3d6a000 { 1795 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 1796 1797 reg = <0 0x03d6a000 0 0x30000>, 1798 <0 0x3de0000 0 0x10000>, 1799 <0 0xb290000 0 0x10000>, 1800 <0 0xb490000 0 0x10000>; 1801 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 1802 1803 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1805 interrupt-names = "hfi", "gmu"; 1806 1807 clocks = <&gpucc GPU_CC_AHB_CLK>, 1808 <&gpucc GPU_CC_CX_GMU_CLK>, 1809 <&gpucc GPU_CC_CXO_CLK>, 1810 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1811 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1812 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 1813 1814 power-domains = <&gpucc GPU_CX_GDSC>, 1815 <&gpucc GPU_GX_GDSC>; 1816 power-domain-names = "cx", "gx"; 1817 1818 iommus = <&adreno_smmu 5 0x400>; 1819 1820 operating-points-v2 = <&gmu_opp_table>; 1821 1822 gmu_opp_table: opp-table { 1823 compatible = "operating-points-v2"; 1824 1825 opp-200000000 { 1826 opp-hz = /bits/ 64 <200000000>; 1827 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1828 }; 1829 }; 1830 }; 1831 1832 gpucc: clock-controller@3d90000 { 1833 compatible = "qcom,sm8250-gpucc"; 1834 reg = <0 0x03d90000 0 0x9000>; 1835 clocks = <&rpmhcc RPMH_CXO_CLK>, 1836 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1837 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1838 clock-names = "bi_tcxo", 1839 "gcc_gpu_gpll0_clk_src", 1840 "gcc_gpu_gpll0_div_clk_src"; 1841 #clock-cells = <1>; 1842 #reset-cells = <1>; 1843 #power-domain-cells = <1>; 1844 }; 1845 1846 adreno_smmu: iommu@3da0000 { 1847 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 1848 reg = <0 0x03da0000 0 0x10000>; 1849 #iommu-cells = <2>; 1850 #global-interrupts = <2>; 1851 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 1861 clocks = <&gpucc GPU_CC_AHB_CLK>, 1862 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1863 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1864 clock-names = "ahb", "bus", "iface"; 1865 1866 power-domains = <&gpucc GPU_CX_GDSC>; 1867 }; 1868 1869 slpi: remoteproc@5c00000 { 1870 compatible = "qcom,sm8250-slpi-pas"; 1871 reg = <0 0x05c00000 0 0x4000>; 1872 1873 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 1874 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 1875 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 1876 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 1877 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 1878 interrupt-names = "wdog", "fatal", "ready", 1879 "handover", "stop-ack"; 1880 1881 clocks = <&rpmhcc RPMH_CXO_CLK>; 1882 clock-names = "xo"; 1883 1884 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 1885 <&rpmhpd SM8250_LCX>, 1886 <&rpmhpd SM8250_LMX>; 1887 power-domain-names = "load_state", "lcx", "lmx"; 1888 1889 memory-region = <&slpi_mem>; 1890 1891 qcom,smem-states = <&smp2p_slpi_out 0>; 1892 qcom,smem-state-names = "stop"; 1893 1894 status = "disabled"; 1895 1896 glink-edge { 1897 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 1898 IPCC_MPROC_SIGNAL_GLINK_QMP 1899 IRQ_TYPE_EDGE_RISING>; 1900 mboxes = <&ipcc IPCC_CLIENT_SLPI 1901 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1902 1903 label = "slpi"; 1904 qcom,remote-pid = <3>; 1905 1906 fastrpc { 1907 compatible = "qcom,fastrpc"; 1908 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1909 label = "sdsp"; 1910 #address-cells = <1>; 1911 #size-cells = <0>; 1912 1913 compute-cb@1 { 1914 compatible = "qcom,fastrpc-compute-cb"; 1915 reg = <1>; 1916 iommus = <&apps_smmu 0x0541 0x0>; 1917 }; 1918 1919 compute-cb@2 { 1920 compatible = "qcom,fastrpc-compute-cb"; 1921 reg = <2>; 1922 iommus = <&apps_smmu 0x0542 0x0>; 1923 }; 1924 1925 compute-cb@3 { 1926 compatible = "qcom,fastrpc-compute-cb"; 1927 reg = <3>; 1928 iommus = <&apps_smmu 0x0543 0x0>; 1929 /* note: shared-cb = <4> in downstream */ 1930 }; 1931 }; 1932 }; 1933 }; 1934 1935 cdsp: remoteproc@8300000 { 1936 compatible = "qcom,sm8250-cdsp-pas"; 1937 reg = <0 0x08300000 0 0x10000>; 1938 1939 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1940 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1941 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1942 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1943 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1944 interrupt-names = "wdog", "fatal", "ready", 1945 "handover", "stop-ack"; 1946 1947 clocks = <&rpmhcc RPMH_CXO_CLK>; 1948 clock-names = "xo"; 1949 1950 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 1951 <&rpmhpd SM8250_CX>; 1952 power-domain-names = "load_state", "cx"; 1953 1954 memory-region = <&cdsp_mem>; 1955 1956 qcom,smem-states = <&smp2p_cdsp_out 0>; 1957 qcom,smem-state-names = "stop"; 1958 1959 status = "disabled"; 1960 1961 glink-edge { 1962 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1963 IPCC_MPROC_SIGNAL_GLINK_QMP 1964 IRQ_TYPE_EDGE_RISING>; 1965 mboxes = <&ipcc IPCC_CLIENT_CDSP 1966 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1967 1968 label = "cdsp"; 1969 qcom,remote-pid = <5>; 1970 1971 fastrpc { 1972 compatible = "qcom,fastrpc"; 1973 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1974 label = "cdsp"; 1975 #address-cells = <1>; 1976 #size-cells = <0>; 1977 1978 compute-cb@1 { 1979 compatible = "qcom,fastrpc-compute-cb"; 1980 reg = <1>; 1981 iommus = <&apps_smmu 0x1001 0x0460>; 1982 }; 1983 1984 compute-cb@2 { 1985 compatible = "qcom,fastrpc-compute-cb"; 1986 reg = <2>; 1987 iommus = <&apps_smmu 0x1002 0x0460>; 1988 }; 1989 1990 compute-cb@3 { 1991 compatible = "qcom,fastrpc-compute-cb"; 1992 reg = <3>; 1993 iommus = <&apps_smmu 0x1003 0x0460>; 1994 }; 1995 1996 compute-cb@4 { 1997 compatible = "qcom,fastrpc-compute-cb"; 1998 reg = <4>; 1999 iommus = <&apps_smmu 0x1004 0x0460>; 2000 }; 2001 2002 compute-cb@5 { 2003 compatible = "qcom,fastrpc-compute-cb"; 2004 reg = <5>; 2005 iommus = <&apps_smmu 0x1005 0x0460>; 2006 }; 2007 2008 compute-cb@6 { 2009 compatible = "qcom,fastrpc-compute-cb"; 2010 reg = <6>; 2011 iommus = <&apps_smmu 0x1006 0x0460>; 2012 }; 2013 2014 compute-cb@7 { 2015 compatible = "qcom,fastrpc-compute-cb"; 2016 reg = <7>; 2017 iommus = <&apps_smmu 0x1007 0x0460>; 2018 }; 2019 2020 compute-cb@8 { 2021 compatible = "qcom,fastrpc-compute-cb"; 2022 reg = <8>; 2023 iommus = <&apps_smmu 0x1008 0x0460>; 2024 }; 2025 2026 /* note: secure cb9 in downstream */ 2027 }; 2028 }; 2029 }; 2030 2031 sound: sound { 2032 }; 2033 2034 usb_1_hsphy: phy@88e3000 { 2035 compatible = "qcom,sm8250-usb-hs-phy", 2036 "qcom,usb-snps-hs-7nm-phy"; 2037 reg = <0 0x088e3000 0 0x400>; 2038 status = "disabled"; 2039 #phy-cells = <0>; 2040 2041 clocks = <&rpmhcc RPMH_CXO_CLK>; 2042 clock-names = "ref"; 2043 2044 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2045 }; 2046 2047 usb_2_hsphy: phy@88e4000 { 2048 compatible = "qcom,sm8250-usb-hs-phy", 2049 "qcom,usb-snps-hs-7nm-phy"; 2050 reg = <0 0x088e4000 0 0x400>; 2051 status = "disabled"; 2052 #phy-cells = <0>; 2053 2054 clocks = <&rpmhcc RPMH_CXO_CLK>; 2055 clock-names = "ref"; 2056 2057 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2058 }; 2059 2060 usb_1_qmpphy: phy@88e9000 { 2061 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2062 reg = <0 0x088e9000 0 0x200>, 2063 <0 0x088e8000 0 0x40>, 2064 <0 0x088ea000 0 0x200>; 2065 status = "disabled"; 2066 #address-cells = <2>; 2067 #size-cells = <2>; 2068 ranges; 2069 2070 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2071 <&rpmhcc RPMH_CXO_CLK>, 2072 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2073 clock-names = "aux", "ref_clk_src", "com_aux"; 2074 2075 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2076 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2077 reset-names = "phy", "common"; 2078 2079 usb_1_ssphy: usb3-phy@88e9200 { 2080 reg = <0 0x088e9200 0 0x200>, 2081 <0 0x088e9400 0 0x200>, 2082 <0 0x088e9c00 0 0x400>, 2083 <0 0x088e9600 0 0x200>, 2084 <0 0x088e9800 0 0x200>, 2085 <0 0x088e9a00 0 0x100>; 2086 #clock-cells = <0>; 2087 #phy-cells = <0>; 2088 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2089 clock-names = "pipe0"; 2090 clock-output-names = "usb3_phy_pipe_clk_src"; 2091 }; 2092 2093 dp_phy: dp-phy@88ea200 { 2094 reg = <0 0x088ea200 0 0x200>, 2095 <0 0x088ea400 0 0x200>, 2096 <0 0x088eac00 0 0x400>, 2097 <0 0x088ea600 0 0x200>, 2098 <0 0x088ea800 0 0x200>, 2099 <0 0x088eaa00 0 0x100>; 2100 #phy-cells = <0>; 2101 #clock-cells = <1>; 2102 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2103 clock-names = "pipe0"; 2104 clock-output-names = "usb3_phy_pipe_clk_src"; 2105 }; 2106 }; 2107 2108 usb_2_qmpphy: phy@88eb000 { 2109 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2110 reg = <0 0x088eb000 0 0x200>; 2111 status = "disabled"; 2112 #address-cells = <2>; 2113 #size-cells = <2>; 2114 ranges; 2115 2116 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2117 <&rpmhcc RPMH_CXO_CLK>, 2118 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2119 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2120 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2121 2122 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2123 <&gcc GCC_USB3_PHY_SEC_BCR>; 2124 reset-names = "phy", "common"; 2125 2126 usb_2_ssphy: lane@88eb200 { 2127 reg = <0 0x088eb200 0 0x200>, 2128 <0 0x088eb400 0 0x200>, 2129 <0 0x088eb800 0 0x800>; 2130 #clock-cells = <0>; 2131 #phy-cells = <0>; 2132 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2133 clock-names = "pipe0"; 2134 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2135 }; 2136 }; 2137 2138 sdhc_2: sdhci@8804000 { 2139 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2140 reg = <0 0x08804000 0 0x1000>; 2141 2142 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2144 interrupt-names = "hc_irq", "pwr_irq"; 2145 2146 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2147 <&gcc GCC_SDCC2_APPS_CLK>, 2148 <&rpmhcc RPMH_CXO_CLK>; 2149 clock-names = "iface", "core", "xo"; 2150 iommus = <&apps_smmu 0x4a0 0x0>; 2151 qcom,dll-config = <0x0007642c>; 2152 qcom,ddr-config = <0x80040868>; 2153 power-domains = <&rpmhpd SM8250_CX>; 2154 operating-points-v2 = <&sdhc2_opp_table>; 2155 2156 status = "disabled"; 2157 2158 sdhc2_opp_table: sdhc2-opp-table { 2159 compatible = "operating-points-v2"; 2160 2161 opp-19200000 { 2162 opp-hz = /bits/ 64 <19200000>; 2163 required-opps = <&rpmhpd_opp_min_svs>; 2164 }; 2165 2166 opp-50000000 { 2167 opp-hz = /bits/ 64 <50000000>; 2168 required-opps = <&rpmhpd_opp_low_svs>; 2169 }; 2170 2171 opp-100000000 { 2172 opp-hz = /bits/ 64 <100000000>; 2173 required-opps = <&rpmhpd_opp_svs>; 2174 }; 2175 2176 opp-202000000 { 2177 opp-hz = /bits/ 64 <202000000>; 2178 required-opps = <&rpmhpd_opp_svs_l1>; 2179 }; 2180 }; 2181 }; 2182 2183 dc_noc: interconnect@90c0000 { 2184 compatible = "qcom,sm8250-dc-noc"; 2185 reg = <0 0x090c0000 0 0x4200>; 2186 #interconnect-cells = <1>; 2187 qcom,bcm-voters = <&apps_bcm_voter>; 2188 }; 2189 2190 gem_noc: interconnect@9100000 { 2191 compatible = "qcom,sm8250-gem-noc"; 2192 reg = <0 0x09100000 0 0xb4000>; 2193 #interconnect-cells = <1>; 2194 qcom,bcm-voters = <&apps_bcm_voter>; 2195 }; 2196 2197 npu_noc: interconnect@9990000 { 2198 compatible = "qcom,sm8250-npu-noc"; 2199 reg = <0 0x09990000 0 0x1600>; 2200 #interconnect-cells = <1>; 2201 qcom,bcm-voters = <&apps_bcm_voter>; 2202 }; 2203 2204 usb_1: usb@a6f8800 { 2205 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2206 reg = <0 0x0a6f8800 0 0x400>; 2207 status = "disabled"; 2208 #address-cells = <2>; 2209 #size-cells = <2>; 2210 ranges; 2211 dma-ranges; 2212 2213 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2214 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2215 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2216 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2217 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2218 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2219 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2220 "sleep", "xo"; 2221 2222 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2223 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2224 assigned-clock-rates = <19200000>, <200000000>; 2225 2226 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2227 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2228 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2229 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2230 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2231 "dm_hs_phy_irq", "ss_phy_irq"; 2232 2233 power-domains = <&gcc USB30_PRIM_GDSC>; 2234 2235 resets = <&gcc GCC_USB30_PRIM_BCR>; 2236 2237 usb_1_dwc3: dwc3@a600000 { 2238 compatible = "snps,dwc3"; 2239 reg = <0 0x0a600000 0 0xcd00>; 2240 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2241 iommus = <&apps_smmu 0x0 0x0>; 2242 snps,dis_u2_susphy_quirk; 2243 snps,dis_enblslpm_quirk; 2244 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2245 phy-names = "usb2-phy", "usb3-phy"; 2246 }; 2247 }; 2248 2249 system-cache-controller@9200000 { 2250 compatible = "qcom,sm8250-llcc"; 2251 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2252 reg-names = "llcc_base", "llcc_broadcast_base"; 2253 }; 2254 2255 usb_2: usb@a8f8800 { 2256 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2257 reg = <0 0x0a8f8800 0 0x400>; 2258 status = "disabled"; 2259 #address-cells = <2>; 2260 #size-cells = <2>; 2261 ranges; 2262 dma-ranges; 2263 2264 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2265 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2266 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2267 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2268 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2269 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2270 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2271 "sleep", "xo"; 2272 2273 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2274 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2275 assigned-clock-rates = <19200000>, <200000000>; 2276 2277 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2278 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2279 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2280 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2281 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2282 "dm_hs_phy_irq", "ss_phy_irq"; 2283 2284 power-domains = <&gcc USB30_SEC_GDSC>; 2285 2286 resets = <&gcc GCC_USB30_SEC_BCR>; 2287 2288 usb_2_dwc3: dwc3@a800000 { 2289 compatible = "snps,dwc3"; 2290 reg = <0 0x0a800000 0 0xcd00>; 2291 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2292 iommus = <&apps_smmu 0x20 0>; 2293 snps,dis_u2_susphy_quirk; 2294 snps,dis_enblslpm_quirk; 2295 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2296 phy-names = "usb2-phy", "usb3-phy"; 2297 }; 2298 }; 2299 2300 venus: video-codec@aa00000 { 2301 compatible = "qcom,sm8250-venus"; 2302 reg = <0 0x0aa00000 0 0x100000>; 2303 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2304 power-domains = <&videocc MVS0C_GDSC>, 2305 <&videocc MVS0_GDSC>, 2306 <&rpmhpd SM8250_MX>; 2307 power-domain-names = "venus", "vcodec0", "mx"; 2308 operating-points-v2 = <&venus_opp_table>; 2309 2310 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2311 <&videocc VIDEO_CC_MVS0C_CLK>, 2312 <&videocc VIDEO_CC_MVS0_CLK>; 2313 clock-names = "iface", "core", "vcodec0_core"; 2314 2315 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 2316 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 2317 interconnect-names = "cpu-cfg", "video-mem"; 2318 2319 iommus = <&apps_smmu 0x2100 0x0400>; 2320 memory-region = <&video_mem>; 2321 2322 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2323 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 2324 reset-names = "bus", "core"; 2325 2326 video-decoder { 2327 compatible = "venus-decoder"; 2328 }; 2329 2330 video-encoder { 2331 compatible = "venus-encoder"; 2332 }; 2333 2334 venus_opp_table: venus-opp-table { 2335 compatible = "operating-points-v2"; 2336 2337 opp-720000000 { 2338 opp-hz = /bits/ 64 <720000000>; 2339 required-opps = <&rpmhpd_opp_low_svs>; 2340 }; 2341 2342 opp-1014000000 { 2343 opp-hz = /bits/ 64 <1014000000>; 2344 required-opps = <&rpmhpd_opp_svs>; 2345 }; 2346 2347 opp-1098000000 { 2348 opp-hz = /bits/ 64 <1098000000>; 2349 required-opps = <&rpmhpd_opp_svs_l1>; 2350 }; 2351 2352 opp-1332000000 { 2353 opp-hz = /bits/ 64 <1332000000>; 2354 required-opps = <&rpmhpd_opp_nom>; 2355 }; 2356 }; 2357 }; 2358 2359 videocc: clock-controller@abf0000 { 2360 compatible = "qcom,sm8250-videocc"; 2361 reg = <0 0x0abf0000 0 0x10000>; 2362 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2363 <&rpmhcc RPMH_CXO_CLK>, 2364 <&rpmhcc RPMH_CXO_CLK_A>; 2365 mmcx-supply = <&mmcx_reg>; 2366 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 2367 #clock-cells = <1>; 2368 #reset-cells = <1>; 2369 #power-domain-cells = <1>; 2370 }; 2371 2372 mdss: mdss@ae00000 { 2373 compatible = "qcom,sdm845-mdss"; 2374 reg = <0 0x0ae00000 0 0x1000>; 2375 reg-names = "mdss"; 2376 2377 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 2378 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 2379 interconnect-names = "mdp0-mem", "mdp1-mem"; 2380 2381 power-domains = <&dispcc MDSS_GDSC>; 2382 2383 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2384 <&gcc GCC_DISP_HF_AXI_CLK>, 2385 <&gcc GCC_DISP_SF_AXI_CLK>, 2386 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2387 clock-names = "iface", "bus", "nrt_bus", "core"; 2388 2389 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2390 assigned-clock-rates = <460000000>; 2391 2392 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2393 interrupt-controller; 2394 #interrupt-cells = <1>; 2395 2396 iommus = <&apps_smmu 0x820 0x402>; 2397 2398 status = "disabled"; 2399 2400 #address-cells = <2>; 2401 #size-cells = <2>; 2402 ranges; 2403 2404 mdss_mdp: mdp@ae01000 { 2405 compatible = "qcom,sdm845-dpu"; 2406 reg = <0 0x0ae01000 0 0x8f000>, 2407 <0 0x0aeb0000 0 0x2008>; 2408 reg-names = "mdp", "vbif"; 2409 2410 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2411 <&gcc GCC_DISP_HF_AXI_CLK>, 2412 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2413 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2414 clock-names = "iface", "bus", "core", "vsync"; 2415 2416 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2417 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2418 assigned-clock-rates = <460000000>, 2419 <19200000>; 2420 2421 operating-points-v2 = <&mdp_opp_table>; 2422 power-domains = <&rpmhpd SM8250_MMCX>; 2423 2424 interrupt-parent = <&mdss>; 2425 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2426 2427 status = "disabled"; 2428 2429 ports { 2430 #address-cells = <1>; 2431 #size-cells = <0>; 2432 2433 port@0 { 2434 reg = <0>; 2435 dpu_intf1_out: endpoint { 2436 remote-endpoint = <&dsi0_in>; 2437 }; 2438 }; 2439 2440 port@1 { 2441 reg = <1>; 2442 dpu_intf2_out: endpoint { 2443 remote-endpoint = <&dsi1_in>; 2444 }; 2445 }; 2446 }; 2447 2448 mdp_opp_table: mdp-opp-table { 2449 compatible = "operating-points-v2"; 2450 2451 opp-200000000 { 2452 opp-hz = /bits/ 64 <200000000>; 2453 required-opps = <&rpmhpd_opp_low_svs>; 2454 }; 2455 2456 opp-300000000 { 2457 opp-hz = /bits/ 64 <300000000>; 2458 required-opps = <&rpmhpd_opp_svs>; 2459 }; 2460 2461 opp-345000000 { 2462 opp-hz = /bits/ 64 <345000000>; 2463 required-opps = <&rpmhpd_opp_svs_l1>; 2464 }; 2465 2466 opp-460000000 { 2467 opp-hz = /bits/ 64 <460000000>; 2468 required-opps = <&rpmhpd_opp_nom>; 2469 }; 2470 }; 2471 }; 2472 2473 dsi0: dsi@ae94000 { 2474 compatible = "qcom,mdss-dsi-ctrl"; 2475 reg = <0 0x0ae94000 0 0x400>; 2476 reg-names = "dsi_ctrl"; 2477 2478 interrupt-parent = <&mdss>; 2479 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2480 2481 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2482 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2483 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2484 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2485 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2486 <&gcc GCC_DISP_HF_AXI_CLK>; 2487 clock-names = "byte", 2488 "byte_intf", 2489 "pixel", 2490 "core", 2491 "iface", 2492 "bus"; 2493 2494 operating-points-v2 = <&dsi_opp_table>; 2495 power-domains = <&rpmhpd SM8250_MMCX>; 2496 2497 phys = <&dsi0_phy>; 2498 phy-names = "dsi"; 2499 2500 status = "disabled"; 2501 2502 ports { 2503 #address-cells = <1>; 2504 #size-cells = <0>; 2505 2506 port@0 { 2507 reg = <0>; 2508 dsi0_in: endpoint { 2509 remote-endpoint = <&dpu_intf1_out>; 2510 }; 2511 }; 2512 2513 port@1 { 2514 reg = <1>; 2515 dsi0_out: endpoint { 2516 }; 2517 }; 2518 }; 2519 }; 2520 2521 dsi0_phy: dsi-phy@ae94400 { 2522 compatible = "qcom,dsi-phy-7nm"; 2523 reg = <0 0x0ae94400 0 0x200>, 2524 <0 0x0ae94600 0 0x280>, 2525 <0 0x0ae94900 0 0x260>; 2526 reg-names = "dsi_phy", 2527 "dsi_phy_lane", 2528 "dsi_pll"; 2529 2530 #clock-cells = <1>; 2531 #phy-cells = <0>; 2532 2533 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2534 <&rpmhcc RPMH_CXO_CLK>; 2535 clock-names = "iface", "ref"; 2536 2537 status = "disabled"; 2538 }; 2539 2540 dsi1: dsi@ae96000 { 2541 compatible = "qcom,mdss-dsi-ctrl"; 2542 reg = <0 0x0ae96000 0 0x400>; 2543 reg-names = "dsi_ctrl"; 2544 2545 interrupt-parent = <&mdss>; 2546 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2547 2548 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2549 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2550 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2551 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2552 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2553 <&gcc GCC_DISP_HF_AXI_CLK>; 2554 clock-names = "byte", 2555 "byte_intf", 2556 "pixel", 2557 "core", 2558 "iface", 2559 "bus"; 2560 2561 operating-points-v2 = <&dsi_opp_table>; 2562 power-domains = <&rpmhpd SM8250_MMCX>; 2563 2564 phys = <&dsi1_phy>; 2565 phy-names = "dsi"; 2566 2567 status = "disabled"; 2568 2569 ports { 2570 #address-cells = <1>; 2571 #size-cells = <0>; 2572 2573 port@0 { 2574 reg = <0>; 2575 dsi1_in: endpoint { 2576 remote-endpoint = <&dpu_intf2_out>; 2577 }; 2578 }; 2579 2580 port@1 { 2581 reg = <1>; 2582 dsi1_out: endpoint { 2583 }; 2584 }; 2585 }; 2586 }; 2587 2588 dsi1_phy: dsi-phy@ae96400 { 2589 compatible = "qcom,dsi-phy-7nm"; 2590 reg = <0 0x0ae96400 0 0x200>, 2591 <0 0x0ae96600 0 0x280>, 2592 <0 0x0ae96900 0 0x260>; 2593 reg-names = "dsi_phy", 2594 "dsi_phy_lane", 2595 "dsi_pll"; 2596 2597 #clock-cells = <1>; 2598 #phy-cells = <0>; 2599 2600 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2601 <&rpmhcc RPMH_CXO_CLK>; 2602 clock-names = "iface", "ref"; 2603 2604 status = "disabled"; 2605 2606 dsi_opp_table: dsi-opp-table { 2607 compatible = "operating-points-v2"; 2608 2609 opp-187500000 { 2610 opp-hz = /bits/ 64 <187500000>; 2611 required-opps = <&rpmhpd_opp_low_svs>; 2612 }; 2613 2614 opp-300000000 { 2615 opp-hz = /bits/ 64 <300000000>; 2616 required-opps = <&rpmhpd_opp_svs>; 2617 }; 2618 2619 opp-358000000 { 2620 opp-hz = /bits/ 64 <358000000>; 2621 required-opps = <&rpmhpd_opp_svs_l1>; 2622 }; 2623 }; 2624 }; 2625 }; 2626 2627 dispcc: clock-controller@af00000 { 2628 compatible = "qcom,sm8250-dispcc"; 2629 reg = <0 0x0af00000 0 0x10000>; 2630 mmcx-supply = <&mmcx_reg>; 2631 clocks = <&rpmhcc RPMH_CXO_CLK>, 2632 <&dsi0_phy 0>, 2633 <&dsi0_phy 1>, 2634 <&dsi1_phy 0>, 2635 <&dsi1_phy 1>, 2636 <&dp_phy 0>, 2637 <&dp_phy 1>; 2638 clock-names = "bi_tcxo", 2639 "dsi0_phy_pll_out_byteclk", 2640 "dsi0_phy_pll_out_dsiclk", 2641 "dsi1_phy_pll_out_byteclk", 2642 "dsi1_phy_pll_out_dsiclk", 2643 "dp_phy_pll_link_clk", 2644 "dp_phy_pll_vco_div_clk"; 2645 #clock-cells = <1>; 2646 #reset-cells = <1>; 2647 #power-domain-cells = <1>; 2648 }; 2649 2650 pdc: interrupt-controller@b220000 { 2651 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 2652 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2653 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2654 <125 63 1>, <126 716 12>; 2655 #interrupt-cells = <2>; 2656 interrupt-parent = <&intc>; 2657 interrupt-controller; 2658 }; 2659 2660 tsens0: thermal-sensor@c263000 { 2661 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2662 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2663 <0 0x0c222000 0 0x1ff>; /* SROT */ 2664 #qcom,sensors = <16>; 2665 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2666 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2667 interrupt-names = "uplow", "critical"; 2668 #thermal-sensor-cells = <1>; 2669 }; 2670 2671 tsens1: thermal-sensor@c265000 { 2672 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2673 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2674 <0 0x0c223000 0 0x1ff>; /* SROT */ 2675 #qcom,sensors = <9>; 2676 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2677 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2678 interrupt-names = "uplow", "critical"; 2679 #thermal-sensor-cells = <1>; 2680 }; 2681 2682 aoss_qmp: power-controller@c300000 { 2683 compatible = "qcom,sm8250-aoss-qmp"; 2684 reg = <0 0x0c300000 0 0x100000>; 2685 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2686 IPCC_MPROC_SIGNAL_GLINK_QMP 2687 IRQ_TYPE_EDGE_RISING>; 2688 mboxes = <&ipcc IPCC_CLIENT_AOP 2689 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2690 2691 #clock-cells = <0>; 2692 #power-domain-cells = <1>; 2693 }; 2694 2695 spmi_bus: spmi@c440000 { 2696 compatible = "qcom,spmi-pmic-arb"; 2697 reg = <0x0 0x0c440000 0x0 0x0001100>, 2698 <0x0 0x0c600000 0x0 0x2000000>, 2699 <0x0 0x0e600000 0x0 0x0100000>, 2700 <0x0 0x0e700000 0x0 0x00a0000>, 2701 <0x0 0x0c40a000 0x0 0x0026000>; 2702 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2703 interrupt-names = "periph_irq"; 2704 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2705 qcom,ee = <0>; 2706 qcom,channel = <0>; 2707 #address-cells = <2>; 2708 #size-cells = <0>; 2709 interrupt-controller; 2710 #interrupt-cells = <4>; 2711 }; 2712 2713 tlmm: pinctrl@f100000 { 2714 compatible = "qcom,sm8250-pinctrl"; 2715 reg = <0 0x0f100000 0 0x300000>, 2716 <0 0x0f500000 0 0x300000>, 2717 <0 0x0f900000 0 0x300000>; 2718 reg-names = "west", "south", "north"; 2719 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2720 gpio-controller; 2721 #gpio-cells = <2>; 2722 interrupt-controller; 2723 #interrupt-cells = <2>; 2724 gpio-ranges = <&tlmm 0 0 181>; 2725 wakeup-parent = <&pdc>; 2726 2727 pri_mi2s_active: pri-mi2s-active { 2728 sclk { 2729 pins = "gpio138"; 2730 function = "mi2s0_sck"; 2731 drive-strength = <8>; 2732 bias-disable; 2733 }; 2734 2735 ws { 2736 pins = "gpio141"; 2737 function = "mi2s0_ws"; 2738 drive-strength = <8>; 2739 output-high; 2740 }; 2741 2742 data0 { 2743 pins = "gpio139"; 2744 function = "mi2s0_data0"; 2745 drive-strength = <8>; 2746 bias-disable; 2747 output-high; 2748 }; 2749 2750 data1 { 2751 pins = "gpio140"; 2752 function = "mi2s0_data1"; 2753 drive-strength = <8>; 2754 output-high; 2755 }; 2756 }; 2757 2758 qup_i2c0_default: qup-i2c0-default { 2759 mux { 2760 pins = "gpio28", "gpio29"; 2761 function = "qup0"; 2762 }; 2763 2764 config { 2765 pins = "gpio28", "gpio29"; 2766 drive-strength = <2>; 2767 bias-disable; 2768 }; 2769 }; 2770 2771 qup_i2c1_default: qup-i2c1-default { 2772 pinmux { 2773 pins = "gpio4", "gpio5"; 2774 function = "qup1"; 2775 }; 2776 2777 config { 2778 pins = "gpio4", "gpio5"; 2779 drive-strength = <2>; 2780 bias-disable; 2781 }; 2782 }; 2783 2784 qup_i2c2_default: qup-i2c2-default { 2785 mux { 2786 pins = "gpio115", "gpio116"; 2787 function = "qup2"; 2788 }; 2789 2790 config { 2791 pins = "gpio115", "gpio116"; 2792 drive-strength = <2>; 2793 bias-disable; 2794 }; 2795 }; 2796 2797 qup_i2c3_default: qup-i2c3-default { 2798 mux { 2799 pins = "gpio119", "gpio120"; 2800 function = "qup3"; 2801 }; 2802 2803 config { 2804 pins = "gpio119", "gpio120"; 2805 drive-strength = <2>; 2806 bias-disable; 2807 }; 2808 }; 2809 2810 qup_i2c4_default: qup-i2c4-default { 2811 mux { 2812 pins = "gpio8", "gpio9"; 2813 function = "qup4"; 2814 }; 2815 2816 config { 2817 pins = "gpio8", "gpio9"; 2818 drive-strength = <2>; 2819 bias-disable; 2820 }; 2821 }; 2822 2823 qup_i2c5_default: qup-i2c5-default { 2824 mux { 2825 pins = "gpio12", "gpio13"; 2826 function = "qup5"; 2827 }; 2828 2829 config { 2830 pins = "gpio12", "gpio13"; 2831 drive-strength = <2>; 2832 bias-disable; 2833 }; 2834 }; 2835 2836 qup_i2c6_default: qup-i2c6-default { 2837 mux { 2838 pins = "gpio16", "gpio17"; 2839 function = "qup6"; 2840 }; 2841 2842 config { 2843 pins = "gpio16", "gpio17"; 2844 drive-strength = <2>; 2845 bias-disable; 2846 }; 2847 }; 2848 2849 qup_i2c7_default: qup-i2c7-default { 2850 mux { 2851 pins = "gpio20", "gpio21"; 2852 function = "qup7"; 2853 }; 2854 2855 config { 2856 pins = "gpio20", "gpio21"; 2857 drive-strength = <2>; 2858 bias-disable; 2859 }; 2860 }; 2861 2862 qup_i2c8_default: qup-i2c8-default { 2863 mux { 2864 pins = "gpio24", "gpio25"; 2865 function = "qup8"; 2866 }; 2867 2868 config { 2869 pins = "gpio24", "gpio25"; 2870 drive-strength = <2>; 2871 bias-disable; 2872 }; 2873 }; 2874 2875 qup_i2c9_default: qup-i2c9-default { 2876 mux { 2877 pins = "gpio125", "gpio126"; 2878 function = "qup9"; 2879 }; 2880 2881 config { 2882 pins = "gpio125", "gpio126"; 2883 drive-strength = <2>; 2884 bias-disable; 2885 }; 2886 }; 2887 2888 qup_i2c10_default: qup-i2c10-default { 2889 mux { 2890 pins = "gpio129", "gpio130"; 2891 function = "qup10"; 2892 }; 2893 2894 config { 2895 pins = "gpio129", "gpio130"; 2896 drive-strength = <2>; 2897 bias-disable; 2898 }; 2899 }; 2900 2901 qup_i2c11_default: qup-i2c11-default { 2902 mux { 2903 pins = "gpio60", "gpio61"; 2904 function = "qup11"; 2905 }; 2906 2907 config { 2908 pins = "gpio60", "gpio61"; 2909 drive-strength = <2>; 2910 bias-disable; 2911 }; 2912 }; 2913 2914 qup_i2c12_default: qup-i2c12-default { 2915 mux { 2916 pins = "gpio32", "gpio33"; 2917 function = "qup12"; 2918 }; 2919 2920 config { 2921 pins = "gpio32", "gpio33"; 2922 drive-strength = <2>; 2923 bias-disable; 2924 }; 2925 }; 2926 2927 qup_i2c13_default: qup-i2c13-default { 2928 mux { 2929 pins = "gpio36", "gpio37"; 2930 function = "qup13"; 2931 }; 2932 2933 config { 2934 pins = "gpio36", "gpio37"; 2935 drive-strength = <2>; 2936 bias-disable; 2937 }; 2938 }; 2939 2940 qup_i2c14_default: qup-i2c14-default { 2941 mux { 2942 pins = "gpio40", "gpio41"; 2943 function = "qup14"; 2944 }; 2945 2946 config { 2947 pins = "gpio40", "gpio41"; 2948 drive-strength = <2>; 2949 bias-disable; 2950 }; 2951 }; 2952 2953 qup_i2c15_default: qup-i2c15-default { 2954 mux { 2955 pins = "gpio44", "gpio45"; 2956 function = "qup15"; 2957 }; 2958 2959 config { 2960 pins = "gpio44", "gpio45"; 2961 drive-strength = <2>; 2962 bias-disable; 2963 }; 2964 }; 2965 2966 qup_i2c16_default: qup-i2c16-default { 2967 mux { 2968 pins = "gpio48", "gpio49"; 2969 function = "qup16"; 2970 }; 2971 2972 config { 2973 pins = "gpio48", "gpio49"; 2974 drive-strength = <2>; 2975 bias-disable; 2976 }; 2977 }; 2978 2979 qup_i2c17_default: qup-i2c17-default { 2980 mux { 2981 pins = "gpio52", "gpio53"; 2982 function = "qup17"; 2983 }; 2984 2985 config { 2986 pins = "gpio52", "gpio53"; 2987 drive-strength = <2>; 2988 bias-disable; 2989 }; 2990 }; 2991 2992 qup_i2c18_default: qup-i2c18-default { 2993 mux { 2994 pins = "gpio56", "gpio57"; 2995 function = "qup18"; 2996 }; 2997 2998 config { 2999 pins = "gpio56", "gpio57"; 3000 drive-strength = <2>; 3001 bias-disable; 3002 }; 3003 }; 3004 3005 qup_i2c19_default: qup-i2c19-default { 3006 mux { 3007 pins = "gpio0", "gpio1"; 3008 function = "qup19"; 3009 }; 3010 3011 config { 3012 pins = "gpio0", "gpio1"; 3013 drive-strength = <2>; 3014 bias-disable; 3015 }; 3016 }; 3017 3018 qup_spi0_cs: qup-spi0-cs { 3019 pins = "gpio31"; 3020 function = "qup0"; 3021 }; 3022 3023 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3024 pins = "gpio31"; 3025 function = "gpio"; 3026 }; 3027 3028 qup_spi0_data_clk: qup-spi0-data-clk { 3029 pins = "gpio28", "gpio29", 3030 "gpio30"; 3031 function = "qup0"; 3032 }; 3033 3034 qup_spi1_cs: qup-spi1-cs { 3035 pins = "gpio7"; 3036 function = "qup1"; 3037 }; 3038 3039 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3040 pins = "gpio7"; 3041 function = "gpio"; 3042 }; 3043 3044 qup_spi1_data_clk: qup-spi1-data-clk { 3045 pins = "gpio4", "gpio5", 3046 "gpio6"; 3047 function = "qup1"; 3048 }; 3049 3050 qup_spi2_cs: qup-spi2-cs { 3051 pins = "gpio118"; 3052 function = "qup2"; 3053 }; 3054 3055 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3056 pins = "gpio118"; 3057 function = "gpio"; 3058 }; 3059 3060 qup_spi2_data_clk: qup-spi2-data-clk { 3061 pins = "gpio115", "gpio116", 3062 "gpio117"; 3063 function = "qup2"; 3064 }; 3065 3066 qup_spi3_cs: qup-spi3-cs { 3067 pins = "gpio122"; 3068 function = "qup3"; 3069 }; 3070 3071 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3072 pins = "gpio122"; 3073 function = "gpio"; 3074 }; 3075 3076 qup_spi3_data_clk: qup-spi3-data-clk { 3077 pins = "gpio119", "gpio120", 3078 "gpio121"; 3079 function = "qup3"; 3080 }; 3081 3082 qup_spi4_cs: qup-spi4-cs { 3083 pins = "gpio11"; 3084 function = "qup4"; 3085 }; 3086 3087 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3088 pins = "gpio11"; 3089 function = "gpio"; 3090 }; 3091 3092 qup_spi4_data_clk: qup-spi4-data-clk { 3093 pins = "gpio8", "gpio9", 3094 "gpio10"; 3095 function = "qup4"; 3096 }; 3097 3098 qup_spi5_cs: qup-spi5-cs { 3099 pins = "gpio15"; 3100 function = "qup5"; 3101 }; 3102 3103 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3104 pins = "gpio15"; 3105 function = "gpio"; 3106 }; 3107 3108 qup_spi5_data_clk: qup-spi5-data-clk { 3109 pins = "gpio12", "gpio13", 3110 "gpio14"; 3111 function = "qup5"; 3112 }; 3113 3114 qup_spi6_cs: qup-spi6-cs { 3115 pins = "gpio19"; 3116 function = "qup6"; 3117 }; 3118 3119 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3120 pins = "gpio19"; 3121 function = "gpio"; 3122 }; 3123 3124 qup_spi6_data_clk: qup-spi6-data-clk { 3125 pins = "gpio16", "gpio17", 3126 "gpio18"; 3127 function = "qup6"; 3128 }; 3129 3130 qup_spi7_cs: qup-spi7-cs { 3131 pins = "gpio23"; 3132 function = "qup7"; 3133 }; 3134 3135 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3136 pins = "gpio23"; 3137 function = "gpio"; 3138 }; 3139 3140 qup_spi7_data_clk: qup-spi7-data-clk { 3141 pins = "gpio20", "gpio21", 3142 "gpio22"; 3143 function = "qup7"; 3144 }; 3145 3146 qup_spi8_cs: qup-spi8-cs { 3147 pins = "gpio27"; 3148 function = "qup8"; 3149 }; 3150 3151 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3152 pins = "gpio27"; 3153 function = "gpio"; 3154 }; 3155 3156 qup_spi8_data_clk: qup-spi8-data-clk { 3157 pins = "gpio24", "gpio25", 3158 "gpio26"; 3159 function = "qup8"; 3160 }; 3161 3162 qup_spi9_cs: qup-spi9-cs { 3163 pins = "gpio128"; 3164 function = "qup9"; 3165 }; 3166 3167 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3168 pins = "gpio128"; 3169 function = "gpio"; 3170 }; 3171 3172 qup_spi9_data_clk: qup-spi9-data-clk { 3173 pins = "gpio125", "gpio126", 3174 "gpio127"; 3175 function = "qup9"; 3176 }; 3177 3178 qup_spi10_cs: qup-spi10-cs { 3179 pins = "gpio132"; 3180 function = "qup10"; 3181 }; 3182 3183 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3184 pins = "gpio132"; 3185 function = "gpio"; 3186 }; 3187 3188 qup_spi10_data_clk: qup-spi10-data-clk { 3189 pins = "gpio129", "gpio130", 3190 "gpio131"; 3191 function = "qup10"; 3192 }; 3193 3194 qup_spi11_cs: qup-spi11-cs { 3195 pins = "gpio63"; 3196 function = "qup11"; 3197 }; 3198 3199 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3200 pins = "gpio63"; 3201 function = "gpio"; 3202 }; 3203 3204 qup_spi11_data_clk: qup-spi11-data-clk { 3205 pins = "gpio60", "gpio61", 3206 "gpio62"; 3207 function = "qup11"; 3208 }; 3209 3210 qup_spi12_cs: qup-spi12-cs { 3211 pins = "gpio35"; 3212 function = "qup12"; 3213 }; 3214 3215 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3216 pins = "gpio35"; 3217 function = "gpio"; 3218 }; 3219 3220 qup_spi12_data_clk: qup-spi12-data-clk { 3221 pins = "gpio32", "gpio33", 3222 "gpio34"; 3223 function = "qup12"; 3224 }; 3225 3226 qup_spi13_cs: qup-spi13-cs { 3227 pins = "gpio39"; 3228 function = "qup13"; 3229 }; 3230 3231 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3232 pins = "gpio39"; 3233 function = "gpio"; 3234 }; 3235 3236 qup_spi13_data_clk: qup-spi13-data-clk { 3237 pins = "gpio36", "gpio37", 3238 "gpio38"; 3239 function = "qup13"; 3240 }; 3241 3242 qup_spi14_cs: qup-spi14-cs { 3243 pins = "gpio43"; 3244 function = "qup14"; 3245 }; 3246 3247 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3248 pins = "gpio43"; 3249 function = "gpio"; 3250 }; 3251 3252 qup_spi14_data_clk: qup-spi14-data-clk { 3253 pins = "gpio40", "gpio41", 3254 "gpio42"; 3255 function = "qup14"; 3256 }; 3257 3258 qup_spi15_cs: qup-spi15-cs { 3259 pins = "gpio47"; 3260 function = "qup15"; 3261 }; 3262 3263 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3264 pins = "gpio47"; 3265 function = "gpio"; 3266 }; 3267 3268 qup_spi15_data_clk: qup-spi15-data-clk { 3269 pins = "gpio44", "gpio45", 3270 "gpio46"; 3271 function = "qup15"; 3272 }; 3273 3274 qup_spi16_cs: qup-spi16-cs { 3275 pins = "gpio51"; 3276 function = "qup16"; 3277 }; 3278 3279 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 3280 pins = "gpio51"; 3281 function = "gpio"; 3282 }; 3283 3284 qup_spi16_data_clk: qup-spi16-data-clk { 3285 pins = "gpio48", "gpio49", 3286 "gpio50"; 3287 function = "qup16"; 3288 }; 3289 3290 qup_spi17_cs: qup-spi17-cs { 3291 pins = "gpio55"; 3292 function = "qup17"; 3293 }; 3294 3295 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 3296 pins = "gpio55"; 3297 function = "gpio"; 3298 }; 3299 3300 qup_spi17_data_clk: qup-spi17-data-clk { 3301 pins = "gpio52", "gpio53", 3302 "gpio54"; 3303 function = "qup17"; 3304 }; 3305 3306 qup_spi18_cs: qup-spi18-cs { 3307 pins = "gpio59"; 3308 function = "qup18"; 3309 }; 3310 3311 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 3312 pins = "gpio59"; 3313 function = "gpio"; 3314 }; 3315 3316 qup_spi18_data_clk: qup-spi18-data-clk { 3317 pins = "gpio56", "gpio57", 3318 "gpio58"; 3319 function = "qup18"; 3320 }; 3321 3322 qup_spi19_cs: qup-spi19-cs { 3323 pins = "gpio3"; 3324 function = "qup19"; 3325 }; 3326 3327 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 3328 pins = "gpio3"; 3329 function = "gpio"; 3330 }; 3331 3332 qup_spi19_data_clk: qup-spi19-data-clk { 3333 pins = "gpio0", "gpio1", 3334 "gpio2"; 3335 function = "qup19"; 3336 }; 3337 3338 qup_uart2_default: qup-uart2-default { 3339 mux { 3340 pins = "gpio117", "gpio118"; 3341 function = "qup2"; 3342 }; 3343 }; 3344 3345 qup_uart6_default: qup-uart6-default { 3346 mux { 3347 pins = "gpio16", "gpio17", 3348 "gpio18", "gpio19"; 3349 function = "qup6"; 3350 }; 3351 }; 3352 3353 qup_uart12_default: qup-uart12-default { 3354 mux { 3355 pins = "gpio34", "gpio35"; 3356 function = "qup12"; 3357 }; 3358 }; 3359 3360 qup_uart17_default: qup-uart17-default { 3361 mux { 3362 pins = "gpio52", "gpio53", 3363 "gpio54", "gpio55"; 3364 function = "qup17"; 3365 }; 3366 }; 3367 3368 qup_uart18_default: qup-uart18-default { 3369 mux { 3370 pins = "gpio58", "gpio59"; 3371 function = "qup18"; 3372 }; 3373 }; 3374 3375 tert_mi2s_active: tert-mi2s-active { 3376 sck { 3377 pins = "gpio133"; 3378 function = "mi2s2_sck"; 3379 drive-strength = <8>; 3380 bias-disable; 3381 }; 3382 3383 data0 { 3384 pins = "gpio134"; 3385 function = "mi2s2_data0"; 3386 drive-strength = <8>; 3387 bias-disable; 3388 output-high; 3389 }; 3390 3391 ws { 3392 pins = "gpio135"; 3393 function = "mi2s2_ws"; 3394 drive-strength = <8>; 3395 output-high; 3396 }; 3397 }; 3398 }; 3399 3400 apps_smmu: iommu@15000000 { 3401 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3402 reg = <0 0x15000000 0 0x100000>; 3403 #iommu-cells = <2>; 3404 #global-interrupts = <2>; 3405 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3503 }; 3504 3505 adsp: remoteproc@17300000 { 3506 compatible = "qcom,sm8250-adsp-pas"; 3507 reg = <0 0x17300000 0 0x100>; 3508 3509 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3510 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3511 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3512 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3513 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3514 interrupt-names = "wdog", "fatal", "ready", 3515 "handover", "stop-ack"; 3516 3517 clocks = <&rpmhcc RPMH_CXO_CLK>; 3518 clock-names = "xo"; 3519 3520 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 3521 <&rpmhpd SM8250_LCX>, 3522 <&rpmhpd SM8250_LMX>; 3523 power-domain-names = "load_state", "lcx", "lmx"; 3524 3525 memory-region = <&adsp_mem>; 3526 3527 qcom,smem-states = <&smp2p_adsp_out 0>; 3528 qcom,smem-state-names = "stop"; 3529 3530 status = "disabled"; 3531 3532 glink-edge { 3533 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3534 IPCC_MPROC_SIGNAL_GLINK_QMP 3535 IRQ_TYPE_EDGE_RISING>; 3536 mboxes = <&ipcc IPCC_CLIENT_LPASS 3537 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3538 3539 label = "lpass"; 3540 qcom,remote-pid = <2>; 3541 3542 apr { 3543 compatible = "qcom,apr-v2"; 3544 qcom,glink-channels = "apr_audio_svc"; 3545 qcom,apr-domain = <APR_DOMAIN_ADSP>; 3546 #address-cells = <1>; 3547 #size-cells = <0>; 3548 3549 apr-service@3 { 3550 reg = <APR_SVC_ADSP_CORE>; 3551 compatible = "qcom,q6core"; 3552 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3553 }; 3554 3555 q6afe: apr-service@4 { 3556 compatible = "qcom,q6afe"; 3557 reg = <APR_SVC_AFE>; 3558 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3559 q6afedai: dais { 3560 compatible = "qcom,q6afe-dais"; 3561 #address-cells = <1>; 3562 #size-cells = <0>; 3563 #sound-dai-cells = <1>; 3564 }; 3565 3566 q6afecc: cc { 3567 compatible = "qcom,q6afe-clocks"; 3568 #clock-cells = <2>; 3569 }; 3570 }; 3571 3572 q6asm: apr-service@7 { 3573 compatible = "qcom,q6asm"; 3574 reg = <APR_SVC_ASM>; 3575 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3576 q6asmdai: dais { 3577 compatible = "qcom,q6asm-dais"; 3578 #address-cells = <1>; 3579 #size-cells = <0>; 3580 #sound-dai-cells = <1>; 3581 iommus = <&apps_smmu 0x1801 0x0>; 3582 }; 3583 }; 3584 3585 q6adm: apr-service@8 { 3586 compatible = "qcom,q6adm"; 3587 reg = <APR_SVC_ADM>; 3588 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3589 q6routing: routing { 3590 compatible = "qcom,q6adm-routing"; 3591 #sound-dai-cells = <0>; 3592 }; 3593 }; 3594 }; 3595 3596 fastrpc { 3597 compatible = "qcom,fastrpc"; 3598 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3599 label = "adsp"; 3600 #address-cells = <1>; 3601 #size-cells = <0>; 3602 3603 compute-cb@3 { 3604 compatible = "qcom,fastrpc-compute-cb"; 3605 reg = <3>; 3606 iommus = <&apps_smmu 0x1803 0x0>; 3607 }; 3608 3609 compute-cb@4 { 3610 compatible = "qcom,fastrpc-compute-cb"; 3611 reg = <4>; 3612 iommus = <&apps_smmu 0x1804 0x0>; 3613 }; 3614 3615 compute-cb@5 { 3616 compatible = "qcom,fastrpc-compute-cb"; 3617 reg = <5>; 3618 iommus = <&apps_smmu 0x1805 0x0>; 3619 }; 3620 }; 3621 }; 3622 }; 3623 3624 intc: interrupt-controller@17a00000 { 3625 compatible = "arm,gic-v3"; 3626 #interrupt-cells = <3>; 3627 interrupt-controller; 3628 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3629 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3630 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3631 }; 3632 3633 watchdog@17c10000 { 3634 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 3635 reg = <0 0x17c10000 0 0x1000>; 3636 clocks = <&sleep_clk>; 3637 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3638 }; 3639 3640 timer@17c20000 { 3641 #address-cells = <2>; 3642 #size-cells = <2>; 3643 ranges; 3644 compatible = "arm,armv7-timer-mem"; 3645 reg = <0x0 0x17c20000 0x0 0x1000>; 3646 clock-frequency = <19200000>; 3647 3648 frame@17c21000 { 3649 frame-number = <0>; 3650 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3652 reg = <0x0 0x17c21000 0x0 0x1000>, 3653 <0x0 0x17c22000 0x0 0x1000>; 3654 }; 3655 3656 frame@17c23000 { 3657 frame-number = <1>; 3658 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3659 reg = <0x0 0x17c23000 0x0 0x1000>; 3660 status = "disabled"; 3661 }; 3662 3663 frame@17c25000 { 3664 frame-number = <2>; 3665 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3666 reg = <0x0 0x17c25000 0x0 0x1000>; 3667 status = "disabled"; 3668 }; 3669 3670 frame@17c27000 { 3671 frame-number = <3>; 3672 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3673 reg = <0x0 0x17c27000 0x0 0x1000>; 3674 status = "disabled"; 3675 }; 3676 3677 frame@17c29000 { 3678 frame-number = <4>; 3679 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3680 reg = <0x0 0x17c29000 0x0 0x1000>; 3681 status = "disabled"; 3682 }; 3683 3684 frame@17c2b000 { 3685 frame-number = <5>; 3686 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3687 reg = <0x0 0x17c2b000 0x0 0x1000>; 3688 status = "disabled"; 3689 }; 3690 3691 frame@17c2d000 { 3692 frame-number = <6>; 3693 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3694 reg = <0x0 0x17c2d000 0x0 0x1000>; 3695 status = "disabled"; 3696 }; 3697 }; 3698 3699 apps_rsc: rsc@18200000 { 3700 label = "apps_rsc"; 3701 compatible = "qcom,rpmh-rsc"; 3702 reg = <0x0 0x18200000 0x0 0x10000>, 3703 <0x0 0x18210000 0x0 0x10000>, 3704 <0x0 0x18220000 0x0 0x10000>; 3705 reg-names = "drv-0", "drv-1", "drv-2"; 3706 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3709 qcom,tcs-offset = <0xd00>; 3710 qcom,drv-id = <2>; 3711 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3712 <WAKE_TCS 3>, <CONTROL_TCS 1>; 3713 3714 rpmhcc: clock-controller { 3715 compatible = "qcom,sm8250-rpmh-clk"; 3716 #clock-cells = <1>; 3717 clock-names = "xo"; 3718 clocks = <&xo_board>; 3719 }; 3720 3721 rpmhpd: power-controller { 3722 compatible = "qcom,sm8250-rpmhpd"; 3723 #power-domain-cells = <1>; 3724 operating-points-v2 = <&rpmhpd_opp_table>; 3725 3726 rpmhpd_opp_table: opp-table { 3727 compatible = "operating-points-v2"; 3728 3729 rpmhpd_opp_ret: opp1 { 3730 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3731 }; 3732 3733 rpmhpd_opp_min_svs: opp2 { 3734 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3735 }; 3736 3737 rpmhpd_opp_low_svs: opp3 { 3738 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3739 }; 3740 3741 rpmhpd_opp_svs: opp4 { 3742 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3743 }; 3744 3745 rpmhpd_opp_svs_l1: opp5 { 3746 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3747 }; 3748 3749 rpmhpd_opp_nom: opp6 { 3750 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3751 }; 3752 3753 rpmhpd_opp_nom_l1: opp7 { 3754 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3755 }; 3756 3757 rpmhpd_opp_nom_l2: opp8 { 3758 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3759 }; 3760 3761 rpmhpd_opp_turbo: opp9 { 3762 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3763 }; 3764 3765 rpmhpd_opp_turbo_l1: opp10 { 3766 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3767 }; 3768 }; 3769 }; 3770 3771 apps_bcm_voter: bcm_voter { 3772 compatible = "qcom,bcm-voter"; 3773 }; 3774 }; 3775 3776 epss_l3: interconnect@18591000 { 3777 compatible = "qcom,sm8250-epss-l3"; 3778 reg = <0 0x18590000 0 0x1000>; 3779 3780 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3781 clock-names = "xo", "alternate"; 3782 3783 #interconnect-cells = <1>; 3784 }; 3785 3786 cpufreq_hw: cpufreq@18591000 { 3787 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 3788 reg = <0 0x18591000 0 0x1000>, 3789 <0 0x18592000 0 0x1000>, 3790 <0 0x18593000 0 0x1000>; 3791 reg-names = "freq-domain0", "freq-domain1", 3792 "freq-domain2"; 3793 3794 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3795 clock-names = "xo", "alternate"; 3796 3797 #freq-domain-cells = <1>; 3798 }; 3799 }; 3800 3801 timer { 3802 compatible = "arm,armv8-timer"; 3803 interrupts = <GIC_PPI 13 3804 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3805 <GIC_PPI 14 3806 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3807 <GIC_PPI 11 3808 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3809 <GIC_PPI 10 3810 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3811 }; 3812 3813 thermal-zones { 3814 cpu0-thermal { 3815 polling-delay-passive = <250>; 3816 polling-delay = <1000>; 3817 3818 thermal-sensors = <&tsens0 1>; 3819 3820 trips { 3821 cpu0_alert0: trip-point0 { 3822 temperature = <90000>; 3823 hysteresis = <2000>; 3824 type = "passive"; 3825 }; 3826 3827 cpu0_alert1: trip-point1 { 3828 temperature = <95000>; 3829 hysteresis = <2000>; 3830 type = "passive"; 3831 }; 3832 3833 cpu0_crit: cpu_crit { 3834 temperature = <110000>; 3835 hysteresis = <1000>; 3836 type = "critical"; 3837 }; 3838 }; 3839 3840 cooling-maps { 3841 map0 { 3842 trip = <&cpu0_alert0>; 3843 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3845 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3846 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3847 }; 3848 map1 { 3849 trip = <&cpu0_alert1>; 3850 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3852 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3853 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3854 }; 3855 }; 3856 }; 3857 3858 cpu1-thermal { 3859 polling-delay-passive = <250>; 3860 polling-delay = <1000>; 3861 3862 thermal-sensors = <&tsens0 2>; 3863 3864 trips { 3865 cpu1_alert0: trip-point0 { 3866 temperature = <90000>; 3867 hysteresis = <2000>; 3868 type = "passive"; 3869 }; 3870 3871 cpu1_alert1: trip-point1 { 3872 temperature = <95000>; 3873 hysteresis = <2000>; 3874 type = "passive"; 3875 }; 3876 3877 cpu1_crit: cpu_crit { 3878 temperature = <110000>; 3879 hysteresis = <1000>; 3880 type = "critical"; 3881 }; 3882 }; 3883 3884 cooling-maps { 3885 map0 { 3886 trip = <&cpu1_alert0>; 3887 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3888 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3889 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3890 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3891 }; 3892 map1 { 3893 trip = <&cpu1_alert1>; 3894 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3896 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3897 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3898 }; 3899 }; 3900 }; 3901 3902 cpu2-thermal { 3903 polling-delay-passive = <250>; 3904 polling-delay = <1000>; 3905 3906 thermal-sensors = <&tsens0 3>; 3907 3908 trips { 3909 cpu2_alert0: trip-point0 { 3910 temperature = <90000>; 3911 hysteresis = <2000>; 3912 type = "passive"; 3913 }; 3914 3915 cpu2_alert1: trip-point1 { 3916 temperature = <95000>; 3917 hysteresis = <2000>; 3918 type = "passive"; 3919 }; 3920 3921 cpu2_crit: cpu_crit { 3922 temperature = <110000>; 3923 hysteresis = <1000>; 3924 type = "critical"; 3925 }; 3926 }; 3927 3928 cooling-maps { 3929 map0 { 3930 trip = <&cpu2_alert0>; 3931 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3933 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3934 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3935 }; 3936 map1 { 3937 trip = <&cpu2_alert1>; 3938 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3940 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3941 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3942 }; 3943 }; 3944 }; 3945 3946 cpu3-thermal { 3947 polling-delay-passive = <250>; 3948 polling-delay = <1000>; 3949 3950 thermal-sensors = <&tsens0 4>; 3951 3952 trips { 3953 cpu3_alert0: trip-point0 { 3954 temperature = <90000>; 3955 hysteresis = <2000>; 3956 type = "passive"; 3957 }; 3958 3959 cpu3_alert1: trip-point1 { 3960 temperature = <95000>; 3961 hysteresis = <2000>; 3962 type = "passive"; 3963 }; 3964 3965 cpu3_crit: cpu_crit { 3966 temperature = <110000>; 3967 hysteresis = <1000>; 3968 type = "critical"; 3969 }; 3970 }; 3971 3972 cooling-maps { 3973 map0 { 3974 trip = <&cpu3_alert0>; 3975 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3976 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3977 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3978 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3979 }; 3980 map1 { 3981 trip = <&cpu3_alert1>; 3982 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3984 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3985 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3986 }; 3987 }; 3988 }; 3989 3990 cpu4-top-thermal { 3991 polling-delay-passive = <250>; 3992 polling-delay = <1000>; 3993 3994 thermal-sensors = <&tsens0 7>; 3995 3996 trips { 3997 cpu4_top_alert0: trip-point0 { 3998 temperature = <90000>; 3999 hysteresis = <2000>; 4000 type = "passive"; 4001 }; 4002 4003 cpu4_top_alert1: trip-point1 { 4004 temperature = <95000>; 4005 hysteresis = <2000>; 4006 type = "passive"; 4007 }; 4008 4009 cpu4_top_crit: cpu_crit { 4010 temperature = <110000>; 4011 hysteresis = <1000>; 4012 type = "critical"; 4013 }; 4014 }; 4015 4016 cooling-maps { 4017 map0 { 4018 trip = <&cpu4_top_alert0>; 4019 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4020 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4021 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4022 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4023 }; 4024 map1 { 4025 trip = <&cpu4_top_alert1>; 4026 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4027 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4028 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4029 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4030 }; 4031 }; 4032 }; 4033 4034 cpu5-top-thermal { 4035 polling-delay-passive = <250>; 4036 polling-delay = <1000>; 4037 4038 thermal-sensors = <&tsens0 8>; 4039 4040 trips { 4041 cpu5_top_alert0: trip-point0 { 4042 temperature = <90000>; 4043 hysteresis = <2000>; 4044 type = "passive"; 4045 }; 4046 4047 cpu5_top_alert1: trip-point1 { 4048 temperature = <95000>; 4049 hysteresis = <2000>; 4050 type = "passive"; 4051 }; 4052 4053 cpu5_top_crit: cpu_crit { 4054 temperature = <110000>; 4055 hysteresis = <1000>; 4056 type = "critical"; 4057 }; 4058 }; 4059 4060 cooling-maps { 4061 map0 { 4062 trip = <&cpu5_top_alert0>; 4063 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4064 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4065 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4066 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4067 }; 4068 map1 { 4069 trip = <&cpu5_top_alert1>; 4070 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4072 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4073 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4074 }; 4075 }; 4076 }; 4077 4078 cpu6-top-thermal { 4079 polling-delay-passive = <250>; 4080 polling-delay = <1000>; 4081 4082 thermal-sensors = <&tsens0 9>; 4083 4084 trips { 4085 cpu6_top_alert0: trip-point0 { 4086 temperature = <90000>; 4087 hysteresis = <2000>; 4088 type = "passive"; 4089 }; 4090 4091 cpu6_top_alert1: trip-point1 { 4092 temperature = <95000>; 4093 hysteresis = <2000>; 4094 type = "passive"; 4095 }; 4096 4097 cpu6_top_crit: cpu_crit { 4098 temperature = <110000>; 4099 hysteresis = <1000>; 4100 type = "critical"; 4101 }; 4102 }; 4103 4104 cooling-maps { 4105 map0 { 4106 trip = <&cpu6_top_alert0>; 4107 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4108 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4109 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4110 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4111 }; 4112 map1 { 4113 trip = <&cpu6_top_alert1>; 4114 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4118 }; 4119 }; 4120 }; 4121 4122 cpu7-top-thermal { 4123 polling-delay-passive = <250>; 4124 polling-delay = <1000>; 4125 4126 thermal-sensors = <&tsens0 10>; 4127 4128 trips { 4129 cpu7_top_alert0: trip-point0 { 4130 temperature = <90000>; 4131 hysteresis = <2000>; 4132 type = "passive"; 4133 }; 4134 4135 cpu7_top_alert1: trip-point1 { 4136 temperature = <95000>; 4137 hysteresis = <2000>; 4138 type = "passive"; 4139 }; 4140 4141 cpu7_top_crit: cpu_crit { 4142 temperature = <110000>; 4143 hysteresis = <1000>; 4144 type = "critical"; 4145 }; 4146 }; 4147 4148 cooling-maps { 4149 map0 { 4150 trip = <&cpu7_top_alert0>; 4151 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4152 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4153 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4154 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4155 }; 4156 map1 { 4157 trip = <&cpu7_top_alert1>; 4158 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4162 }; 4163 }; 4164 }; 4165 4166 cpu4-bottom-thermal { 4167 polling-delay-passive = <250>; 4168 polling-delay = <1000>; 4169 4170 thermal-sensors = <&tsens0 11>; 4171 4172 trips { 4173 cpu4_bottom_alert0: trip-point0 { 4174 temperature = <90000>; 4175 hysteresis = <2000>; 4176 type = "passive"; 4177 }; 4178 4179 cpu4_bottom_alert1: trip-point1 { 4180 temperature = <95000>; 4181 hysteresis = <2000>; 4182 type = "passive"; 4183 }; 4184 4185 cpu4_bottom_crit: cpu_crit { 4186 temperature = <110000>; 4187 hysteresis = <1000>; 4188 type = "critical"; 4189 }; 4190 }; 4191 4192 cooling-maps { 4193 map0 { 4194 trip = <&cpu4_bottom_alert0>; 4195 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4196 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4198 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4199 }; 4200 map1 { 4201 trip = <&cpu4_bottom_alert1>; 4202 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4205 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4206 }; 4207 }; 4208 }; 4209 4210 cpu5-bottom-thermal { 4211 polling-delay-passive = <250>; 4212 polling-delay = <1000>; 4213 4214 thermal-sensors = <&tsens0 12>; 4215 4216 trips { 4217 cpu5_bottom_alert0: trip-point0 { 4218 temperature = <90000>; 4219 hysteresis = <2000>; 4220 type = "passive"; 4221 }; 4222 4223 cpu5_bottom_alert1: trip-point1 { 4224 temperature = <95000>; 4225 hysteresis = <2000>; 4226 type = "passive"; 4227 }; 4228 4229 cpu5_bottom_crit: cpu_crit { 4230 temperature = <110000>; 4231 hysteresis = <1000>; 4232 type = "critical"; 4233 }; 4234 }; 4235 4236 cooling-maps { 4237 map0 { 4238 trip = <&cpu5_bottom_alert0>; 4239 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4242 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4243 }; 4244 map1 { 4245 trip = <&cpu5_bottom_alert1>; 4246 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4248 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4249 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4250 }; 4251 }; 4252 }; 4253 4254 cpu6-bottom-thermal { 4255 polling-delay-passive = <250>; 4256 polling-delay = <1000>; 4257 4258 thermal-sensors = <&tsens0 13>; 4259 4260 trips { 4261 cpu6_bottom_alert0: trip-point0 { 4262 temperature = <90000>; 4263 hysteresis = <2000>; 4264 type = "passive"; 4265 }; 4266 4267 cpu6_bottom_alert1: trip-point1 { 4268 temperature = <95000>; 4269 hysteresis = <2000>; 4270 type = "passive"; 4271 }; 4272 4273 cpu6_bottom_crit: cpu_crit { 4274 temperature = <110000>; 4275 hysteresis = <1000>; 4276 type = "critical"; 4277 }; 4278 }; 4279 4280 cooling-maps { 4281 map0 { 4282 trip = <&cpu6_bottom_alert0>; 4283 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4284 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4286 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4287 }; 4288 map1 { 4289 trip = <&cpu6_bottom_alert1>; 4290 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4291 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4292 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4293 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4294 }; 4295 }; 4296 }; 4297 4298 cpu7-bottom-thermal { 4299 polling-delay-passive = <250>; 4300 polling-delay = <1000>; 4301 4302 thermal-sensors = <&tsens0 14>; 4303 4304 trips { 4305 cpu7_bottom_alert0: trip-point0 { 4306 temperature = <90000>; 4307 hysteresis = <2000>; 4308 type = "passive"; 4309 }; 4310 4311 cpu7_bottom_alert1: trip-point1 { 4312 temperature = <95000>; 4313 hysteresis = <2000>; 4314 type = "passive"; 4315 }; 4316 4317 cpu7_bottom_crit: cpu_crit { 4318 temperature = <110000>; 4319 hysteresis = <1000>; 4320 type = "critical"; 4321 }; 4322 }; 4323 4324 cooling-maps { 4325 map0 { 4326 trip = <&cpu7_bottom_alert0>; 4327 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4328 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4330 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4331 }; 4332 map1 { 4333 trip = <&cpu7_bottom_alert1>; 4334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4336 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4337 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4338 }; 4339 }; 4340 }; 4341 4342 aoss0-thermal { 4343 polling-delay-passive = <250>; 4344 polling-delay = <1000>; 4345 4346 thermal-sensors = <&tsens0 0>; 4347 4348 trips { 4349 aoss0_alert0: trip-point0 { 4350 temperature = <90000>; 4351 hysteresis = <2000>; 4352 type = "hot"; 4353 }; 4354 }; 4355 }; 4356 4357 cluster0-thermal { 4358 polling-delay-passive = <250>; 4359 polling-delay = <1000>; 4360 4361 thermal-sensors = <&tsens0 5>; 4362 4363 trips { 4364 cluster0_alert0: trip-point0 { 4365 temperature = <90000>; 4366 hysteresis = <2000>; 4367 type = "hot"; 4368 }; 4369 cluster0_crit: cluster0_crit { 4370 temperature = <110000>; 4371 hysteresis = <2000>; 4372 type = "critical"; 4373 }; 4374 }; 4375 }; 4376 4377 cluster1-thermal { 4378 polling-delay-passive = <250>; 4379 polling-delay = <1000>; 4380 4381 thermal-sensors = <&tsens0 6>; 4382 4383 trips { 4384 cluster1_alert0: trip-point0 { 4385 temperature = <90000>; 4386 hysteresis = <2000>; 4387 type = "hot"; 4388 }; 4389 cluster1_crit: cluster1_crit { 4390 temperature = <110000>; 4391 hysteresis = <2000>; 4392 type = "critical"; 4393 }; 4394 }; 4395 }; 4396 4397 gpu-thermal-top { 4398 polling-delay-passive = <250>; 4399 polling-delay = <1000>; 4400 4401 thermal-sensors = <&tsens0 15>; 4402 4403 trips { 4404 gpu1_alert0: trip-point0 { 4405 temperature = <90000>; 4406 hysteresis = <2000>; 4407 type = "hot"; 4408 }; 4409 }; 4410 }; 4411 4412 aoss1-thermal { 4413 polling-delay-passive = <250>; 4414 polling-delay = <1000>; 4415 4416 thermal-sensors = <&tsens1 0>; 4417 4418 trips { 4419 aoss1_alert0: trip-point0 { 4420 temperature = <90000>; 4421 hysteresis = <2000>; 4422 type = "hot"; 4423 }; 4424 }; 4425 }; 4426 4427 wlan-thermal { 4428 polling-delay-passive = <250>; 4429 polling-delay = <1000>; 4430 4431 thermal-sensors = <&tsens1 1>; 4432 4433 trips { 4434 wlan_alert0: trip-point0 { 4435 temperature = <90000>; 4436 hysteresis = <2000>; 4437 type = "hot"; 4438 }; 4439 }; 4440 }; 4441 4442 video-thermal { 4443 polling-delay-passive = <250>; 4444 polling-delay = <1000>; 4445 4446 thermal-sensors = <&tsens1 2>; 4447 4448 trips { 4449 video_alert0: trip-point0 { 4450 temperature = <90000>; 4451 hysteresis = <2000>; 4452 type = "hot"; 4453 }; 4454 }; 4455 }; 4456 4457 mem-thermal { 4458 polling-delay-passive = <250>; 4459 polling-delay = <1000>; 4460 4461 thermal-sensors = <&tsens1 3>; 4462 4463 trips { 4464 mem_alert0: trip-point0 { 4465 temperature = <90000>; 4466 hysteresis = <2000>; 4467 type = "hot"; 4468 }; 4469 }; 4470 }; 4471 4472 q6-hvx-thermal { 4473 polling-delay-passive = <250>; 4474 polling-delay = <1000>; 4475 4476 thermal-sensors = <&tsens1 4>; 4477 4478 trips { 4479 q6_hvx_alert0: trip-point0 { 4480 temperature = <90000>; 4481 hysteresis = <2000>; 4482 type = "hot"; 4483 }; 4484 }; 4485 }; 4486 4487 camera-thermal { 4488 polling-delay-passive = <250>; 4489 polling-delay = <1000>; 4490 4491 thermal-sensors = <&tsens1 5>; 4492 4493 trips { 4494 camera_alert0: trip-point0 { 4495 temperature = <90000>; 4496 hysteresis = <2000>; 4497 type = "hot"; 4498 }; 4499 }; 4500 }; 4501 4502 compute-thermal { 4503 polling-delay-passive = <250>; 4504 polling-delay = <1000>; 4505 4506 thermal-sensors = <&tsens1 6>; 4507 4508 trips { 4509 compute_alert0: trip-point0 { 4510 temperature = <90000>; 4511 hysteresis = <2000>; 4512 type = "hot"; 4513 }; 4514 }; 4515 }; 4516 4517 npu-thermal { 4518 polling-delay-passive = <250>; 4519 polling-delay = <1000>; 4520 4521 thermal-sensors = <&tsens1 7>; 4522 4523 trips { 4524 npu_alert0: trip-point0 { 4525 temperature = <90000>; 4526 hysteresis = <2000>; 4527 type = "hot"; 4528 }; 4529 }; 4530 }; 4531 4532 gpu-thermal-bottom { 4533 polling-delay-passive = <250>; 4534 polling-delay = <1000>; 4535 4536 thermal-sensors = <&tsens1 8>; 4537 4538 trips { 4539 gpu2_alert0: trip-point0 { 4540 temperature = <90000>; 4541 hysteresis = <2000>; 4542 type = "hot"; 4543 }; 4544 }; 4545 }; 4546 }; 4547}; 4548