1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8150.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo485"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <488>; 54 dynamic-power-coefficient = <232>; 55 next-level-cache = <&L2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 59 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 #cooling-cells = <2>; 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&L3_0>; 68 L3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 CPU1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo485"; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <488>; 83 dynamic-power-coefficient = <232>; 84 next-level-cache = <&L2_100>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 88 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 89 power-domains = <&CPU_PD1>; 90 power-domain-names = "psci"; 91 #cooling-cells = <2>; 92 L2_100: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&L3_0>; 97 }; 98 }; 99 100 CPU2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "qcom,kryo485"; 103 reg = <0x0 0x200>; 104 clocks = <&cpufreq_hw 0>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <488>; 107 dynamic-power-coefficient = <232>; 108 next-level-cache = <&L2_200>; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 112 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 113 power-domains = <&CPU_PD2>; 114 power-domain-names = "psci"; 115 #cooling-cells = <2>; 116 L2_200: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 cache-unified; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU3: cpu@300 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo485"; 127 reg = <0x0 0x300>; 128 clocks = <&cpufreq_hw 0>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <488>; 131 dynamic-power-coefficient = <232>; 132 next-level-cache = <&L2_300>; 133 qcom,freq-domain = <&cpufreq_hw 0>; 134 operating-points-v2 = <&cpu0_opp_table>; 135 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 136 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 137 power-domains = <&CPU_PD3>; 138 power-domain-names = "psci"; 139 #cooling-cells = <2>; 140 L2_300: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU4: cpu@400 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo485"; 151 reg = <0x0 0x400>; 152 clocks = <&cpufreq_hw 1>; 153 enable-method = "psci"; 154 capacity-dmips-mhz = <1024>; 155 dynamic-power-coefficient = <369>; 156 next-level-cache = <&L2_400>; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 operating-points-v2 = <&cpu4_opp_table>; 159 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 160 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 161 power-domains = <&CPU_PD4>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 L2_400: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU5: cpu@500 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo485"; 175 reg = <0x0 0x500>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <1024>; 179 dynamic-power-coefficient = <369>; 180 next-level-cache = <&L2_500>; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 operating-points-v2 = <&cpu4_opp_table>; 183 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 184 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 185 power-domains = <&CPU_PD5>; 186 power-domain-names = "psci"; 187 #cooling-cells = <2>; 188 L2_500: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 cache-unified; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 CPU6: cpu@600 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo485"; 199 reg = <0x0 0x600>; 200 clocks = <&cpufreq_hw 1>; 201 enable-method = "psci"; 202 capacity-dmips-mhz = <1024>; 203 dynamic-power-coefficient = <369>; 204 next-level-cache = <&L2_600>; 205 qcom,freq-domain = <&cpufreq_hw 1>; 206 operating-points-v2 = <&cpu4_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 power-domains = <&CPU_PD6>; 210 power-domain-names = "psci"; 211 #cooling-cells = <2>; 212 L2_600: l2-cache { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 next-level-cache = <&L3_0>; 217 }; 218 }; 219 220 CPU7: cpu@700 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo485"; 223 reg = <0x0 0x700>; 224 clocks = <&cpufreq_hw 2>; 225 enable-method = "psci"; 226 capacity-dmips-mhz = <1024>; 227 dynamic-power-coefficient = <421>; 228 next-level-cache = <&L2_700>; 229 qcom,freq-domain = <&cpufreq_hw 2>; 230 operating-points-v2 = <&cpu7_opp_table>; 231 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 232 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 233 power-domains = <&CPU_PD7>; 234 power-domain-names = "psci"; 235 #cooling-cells = <2>; 236 L2_700: l2-cache { 237 compatible = "cache"; 238 cache-level = <2>; 239 cache-unified; 240 next-level-cache = <&L3_0>; 241 }; 242 }; 243 244 cpu-map { 245 cluster0 { 246 core0 { 247 cpu = <&CPU0>; 248 }; 249 250 core1 { 251 cpu = <&CPU1>; 252 }; 253 254 core2 { 255 cpu = <&CPU2>; 256 }; 257 258 core3 { 259 cpu = <&CPU3>; 260 }; 261 262 core4 { 263 cpu = <&CPU4>; 264 }; 265 266 core5 { 267 cpu = <&CPU5>; 268 }; 269 270 core6 { 271 cpu = <&CPU6>; 272 }; 273 274 core7 { 275 cpu = <&CPU7>; 276 }; 277 }; 278 }; 279 280 idle-states { 281 entry-method = "psci"; 282 283 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 284 compatible = "arm,idle-state"; 285 idle-state-name = "little-rail-power-collapse"; 286 arm,psci-suspend-param = <0x40000004>; 287 entry-latency-us = <355>; 288 exit-latency-us = <909>; 289 min-residency-us = <3934>; 290 local-timer-stop; 291 }; 292 293 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 294 compatible = "arm,idle-state"; 295 idle-state-name = "big-rail-power-collapse"; 296 arm,psci-suspend-param = <0x40000004>; 297 entry-latency-us = <241>; 298 exit-latency-us = <1461>; 299 min-residency-us = <4488>; 300 local-timer-stop; 301 }; 302 }; 303 304 domain-idle-states { 305 CLUSTER_SLEEP_0: cluster-sleep-0 { 306 compatible = "domain-idle-state"; 307 arm,psci-suspend-param = <0x4100c244>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9987>; 311 }; 312 }; 313 }; 314 315 cpu0_opp_table: opp-table-cpu0 { 316 compatible = "operating-points-v2"; 317 opp-shared; 318 319 cpu0_opp1: opp-300000000 { 320 opp-hz = /bits/ 64 <300000000>; 321 opp-peak-kBps = <800000 9600000>; 322 }; 323 324 cpu0_opp2: opp-403200000 { 325 opp-hz = /bits/ 64 <403200000>; 326 opp-peak-kBps = <800000 9600000>; 327 }; 328 329 cpu0_opp3: opp-499200000 { 330 opp-hz = /bits/ 64 <499200000>; 331 opp-peak-kBps = <800000 12902400>; 332 }; 333 334 cpu0_opp4: opp-576000000 { 335 opp-hz = /bits/ 64 <576000000>; 336 opp-peak-kBps = <800000 12902400>; 337 }; 338 339 cpu0_opp5: opp-672000000 { 340 opp-hz = /bits/ 64 <672000000>; 341 opp-peak-kBps = <800000 15974400>; 342 }; 343 344 cpu0_opp6: opp-768000000 { 345 opp-hz = /bits/ 64 <768000000>; 346 opp-peak-kBps = <1804000 19660800>; 347 }; 348 349 cpu0_opp7: opp-844800000 { 350 opp-hz = /bits/ 64 <844800000>; 351 opp-peak-kBps = <1804000 19660800>; 352 }; 353 354 cpu0_opp8: opp-940800000 { 355 opp-hz = /bits/ 64 <940800000>; 356 opp-peak-kBps = <1804000 22732800>; 357 }; 358 359 cpu0_opp9: opp-1036800000 { 360 opp-hz = /bits/ 64 <1036800000>; 361 opp-peak-kBps = <1804000 22732800>; 362 }; 363 364 cpu0_opp10: opp-1113600000 { 365 opp-hz = /bits/ 64 <1113600000>; 366 opp-peak-kBps = <2188000 25804800>; 367 }; 368 369 cpu0_opp11: opp-1209600000 { 370 opp-hz = /bits/ 64 <1209600000>; 371 opp-peak-kBps = <2188000 31948800>; 372 }; 373 374 cpu0_opp12: opp-1305600000 { 375 opp-hz = /bits/ 64 <1305600000>; 376 opp-peak-kBps = <3072000 31948800>; 377 }; 378 379 cpu0_opp13: opp-1382400000 { 380 opp-hz = /bits/ 64 <1382400000>; 381 opp-peak-kBps = <3072000 31948800>; 382 }; 383 384 cpu0_opp14: opp-1478400000 { 385 opp-hz = /bits/ 64 <1478400000>; 386 opp-peak-kBps = <3072000 31948800>; 387 }; 388 389 cpu0_opp15: opp-1555200000 { 390 opp-hz = /bits/ 64 <1555200000>; 391 opp-peak-kBps = <3072000 40550400>; 392 }; 393 394 cpu0_opp16: opp-1632000000 { 395 opp-hz = /bits/ 64 <1632000000>; 396 opp-peak-kBps = <3072000 40550400>; 397 }; 398 399 cpu0_opp17: opp-1708800000 { 400 opp-hz = /bits/ 64 <1708800000>; 401 opp-peak-kBps = <3072000 43008000>; 402 }; 403 404 cpu0_opp18: opp-1785600000 { 405 opp-hz = /bits/ 64 <1785600000>; 406 opp-peak-kBps = <3072000 43008000>; 407 }; 408 }; 409 410 cpu4_opp_table: opp-table-cpu4 { 411 compatible = "operating-points-v2"; 412 opp-shared; 413 414 cpu4_opp1: opp-710400000 { 415 opp-hz = /bits/ 64 <710400000>; 416 opp-peak-kBps = <1804000 15974400>; 417 }; 418 419 cpu4_opp2: opp-825600000 { 420 opp-hz = /bits/ 64 <825600000>; 421 opp-peak-kBps = <2188000 19660800>; 422 }; 423 424 cpu4_opp3: opp-940800000 { 425 opp-hz = /bits/ 64 <940800000>; 426 opp-peak-kBps = <2188000 22732800>; 427 }; 428 429 cpu4_opp4: opp-1056000000 { 430 opp-hz = /bits/ 64 <1056000000>; 431 opp-peak-kBps = <3072000 25804800>; 432 }; 433 434 cpu4_opp5: opp-1171200000 { 435 opp-hz = /bits/ 64 <1171200000>; 436 opp-peak-kBps = <3072000 31948800>; 437 }; 438 439 cpu4_opp6: opp-1286400000 { 440 opp-hz = /bits/ 64 <1286400000>; 441 opp-peak-kBps = <4068000 31948800>; 442 }; 443 444 cpu4_opp7: opp-1401600000 { 445 opp-hz = /bits/ 64 <1401600000>; 446 opp-peak-kBps = <4068000 31948800>; 447 }; 448 449 cpu4_opp8: opp-1497600000 { 450 opp-hz = /bits/ 64 <1497600000>; 451 opp-peak-kBps = <4068000 40550400>; 452 }; 453 454 cpu4_opp9: opp-1612800000 { 455 opp-hz = /bits/ 64 <1612800000>; 456 opp-peak-kBps = <4068000 40550400>; 457 }; 458 459 cpu4_opp10: opp-1708800000 { 460 opp-hz = /bits/ 64 <1708800000>; 461 opp-peak-kBps = <4068000 43008000>; 462 }; 463 464 cpu4_opp11: opp-1804800000 { 465 opp-hz = /bits/ 64 <1804800000>; 466 opp-peak-kBps = <6220000 43008000>; 467 }; 468 469 cpu4_opp12: opp-1920000000 { 470 opp-hz = /bits/ 64 <1920000000>; 471 opp-peak-kBps = <6220000 49152000>; 472 }; 473 474 cpu4_opp13: opp-2016000000 { 475 opp-hz = /bits/ 64 <2016000000>; 476 opp-peak-kBps = <7216000 49152000>; 477 }; 478 479 cpu4_opp14: opp-2131200000 { 480 opp-hz = /bits/ 64 <2131200000>; 481 opp-peak-kBps = <8368000 49152000>; 482 }; 483 484 cpu4_opp15: opp-2227200000 { 485 opp-hz = /bits/ 64 <2227200000>; 486 opp-peak-kBps = <8368000 51609600>; 487 }; 488 489 cpu4_opp16: opp-2323200000 { 490 opp-hz = /bits/ 64 <2323200000>; 491 opp-peak-kBps = <8368000 51609600>; 492 }; 493 494 cpu4_opp17: opp-2419200000 { 495 opp-hz = /bits/ 64 <2419200000>; 496 opp-peak-kBps = <8368000 51609600>; 497 }; 498 }; 499 500 cpu7_opp_table: opp-table-cpu7 { 501 compatible = "operating-points-v2"; 502 opp-shared; 503 504 cpu7_opp1: opp-825600000 { 505 opp-hz = /bits/ 64 <825600000>; 506 opp-peak-kBps = <2188000 19660800>; 507 }; 508 509 cpu7_opp2: opp-940800000 { 510 opp-hz = /bits/ 64 <940800000>; 511 opp-peak-kBps = <2188000 22732800>; 512 }; 513 514 cpu7_opp3: opp-1056000000 { 515 opp-hz = /bits/ 64 <1056000000>; 516 opp-peak-kBps = <3072000 25804800>; 517 }; 518 519 cpu7_opp4: opp-1171200000 { 520 opp-hz = /bits/ 64 <1171200000>; 521 opp-peak-kBps = <3072000 31948800>; 522 }; 523 524 cpu7_opp5: opp-1286400000 { 525 opp-hz = /bits/ 64 <1286400000>; 526 opp-peak-kBps = <4068000 31948800>; 527 }; 528 529 cpu7_opp6: opp-1401600000 { 530 opp-hz = /bits/ 64 <1401600000>; 531 opp-peak-kBps = <4068000 31948800>; 532 }; 533 534 cpu7_opp7: opp-1497600000 { 535 opp-hz = /bits/ 64 <1497600000>; 536 opp-peak-kBps = <4068000 40550400>; 537 }; 538 539 cpu7_opp8: opp-1612800000 { 540 opp-hz = /bits/ 64 <1612800000>; 541 opp-peak-kBps = <4068000 40550400>; 542 }; 543 544 cpu7_opp9: opp-1708800000 { 545 opp-hz = /bits/ 64 <1708800000>; 546 opp-peak-kBps = <4068000 43008000>; 547 }; 548 549 cpu7_opp10: opp-1804800000 { 550 opp-hz = /bits/ 64 <1804800000>; 551 opp-peak-kBps = <6220000 43008000>; 552 }; 553 554 cpu7_opp11: opp-1920000000 { 555 opp-hz = /bits/ 64 <1920000000>; 556 opp-peak-kBps = <6220000 49152000>; 557 }; 558 559 cpu7_opp12: opp-2016000000 { 560 opp-hz = /bits/ 64 <2016000000>; 561 opp-peak-kBps = <7216000 49152000>; 562 }; 563 564 cpu7_opp13: opp-2131200000 { 565 opp-hz = /bits/ 64 <2131200000>; 566 opp-peak-kBps = <8368000 49152000>; 567 }; 568 569 cpu7_opp14: opp-2227200000 { 570 opp-hz = /bits/ 64 <2227200000>; 571 opp-peak-kBps = <8368000 51609600>; 572 }; 573 574 cpu7_opp15: opp-2323200000 { 575 opp-hz = /bits/ 64 <2323200000>; 576 opp-peak-kBps = <8368000 51609600>; 577 }; 578 579 cpu7_opp16: opp-2419200000 { 580 opp-hz = /bits/ 64 <2419200000>; 581 opp-peak-kBps = <8368000 51609600>; 582 }; 583 584 cpu7_opp17: opp-2534400000 { 585 opp-hz = /bits/ 64 <2534400000>; 586 opp-peak-kBps = <8368000 51609600>; 587 }; 588 589 cpu7_opp18: opp-2649600000 { 590 opp-hz = /bits/ 64 <2649600000>; 591 opp-peak-kBps = <8368000 51609600>; 592 }; 593 594 cpu7_opp19: opp-2745600000 { 595 opp-hz = /bits/ 64 <2745600000>; 596 opp-peak-kBps = <8368000 51609600>; 597 }; 598 599 cpu7_opp20: opp-2841600000 { 600 opp-hz = /bits/ 64 <2841600000>; 601 opp-peak-kBps = <8368000 51609600>; 602 }; 603 }; 604 605 firmware { 606 scm: scm { 607 compatible = "qcom,scm-sm8150", "qcom,scm"; 608 #reset-cells = <1>; 609 }; 610 }; 611 612 memory@80000000 { 613 device_type = "memory"; 614 /* We expect the bootloader to fill in the size */ 615 reg = <0x0 0x80000000 0x0 0x0>; 616 }; 617 618 pmu { 619 compatible = "arm,armv8-pmuv3"; 620 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 621 }; 622 623 psci { 624 compatible = "arm,psci-1.0"; 625 method = "smc"; 626 627 CPU_PD0: power-domain-cpu0 { 628 #power-domain-cells = <0>; 629 power-domains = <&CLUSTER_PD>; 630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 631 }; 632 633 CPU_PD1: power-domain-cpu1 { 634 #power-domain-cells = <0>; 635 power-domains = <&CLUSTER_PD>; 636 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 637 }; 638 639 CPU_PD2: power-domain-cpu2 { 640 #power-domain-cells = <0>; 641 power-domains = <&CLUSTER_PD>; 642 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 643 }; 644 645 CPU_PD3: power-domain-cpu3 { 646 #power-domain-cells = <0>; 647 power-domains = <&CLUSTER_PD>; 648 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 649 }; 650 651 CPU_PD4: power-domain-cpu4 { 652 #power-domain-cells = <0>; 653 power-domains = <&CLUSTER_PD>; 654 domain-idle-states = <&BIG_CPU_SLEEP_0>; 655 }; 656 657 CPU_PD5: power-domain-cpu5 { 658 #power-domain-cells = <0>; 659 power-domains = <&CLUSTER_PD>; 660 domain-idle-states = <&BIG_CPU_SLEEP_0>; 661 }; 662 663 CPU_PD6: power-domain-cpu6 { 664 #power-domain-cells = <0>; 665 power-domains = <&CLUSTER_PD>; 666 domain-idle-states = <&BIG_CPU_SLEEP_0>; 667 }; 668 669 CPU_PD7: power-domain-cpu7 { 670 #power-domain-cells = <0>; 671 power-domains = <&CLUSTER_PD>; 672 domain-idle-states = <&BIG_CPU_SLEEP_0>; 673 }; 674 675 CLUSTER_PD: power-domain-cpu-cluster0 { 676 #power-domain-cells = <0>; 677 domain-idle-states = <&CLUSTER_SLEEP_0>; 678 }; 679 }; 680 681 reserved-memory { 682 #address-cells = <2>; 683 #size-cells = <2>; 684 ranges; 685 686 hyp_mem: memory@85700000 { 687 reg = <0x0 0x85700000 0x0 0x600000>; 688 no-map; 689 }; 690 691 xbl_mem: memory@85d00000 { 692 reg = <0x0 0x85d00000 0x0 0x140000>; 693 no-map; 694 }; 695 696 aop_mem: memory@85f00000 { 697 reg = <0x0 0x85f00000 0x0 0x20000>; 698 no-map; 699 }; 700 701 aop_cmd_db: memory@85f20000 { 702 compatible = "qcom,cmd-db"; 703 reg = <0x0 0x85f20000 0x0 0x20000>; 704 no-map; 705 }; 706 707 smem_mem: memory@86000000 { 708 reg = <0x0 0x86000000 0x0 0x200000>; 709 no-map; 710 }; 711 712 tz_mem: memory@86200000 { 713 reg = <0x0 0x86200000 0x0 0x3900000>; 714 no-map; 715 }; 716 717 rmtfs_mem: memory@89b00000 { 718 compatible = "qcom,rmtfs-mem"; 719 reg = <0x0 0x89b00000 0x0 0x200000>; 720 no-map; 721 722 qcom,client-id = <1>; 723 qcom,vmid = <15>; 724 }; 725 726 camera_mem: memory@8b700000 { 727 reg = <0x0 0x8b700000 0x0 0x500000>; 728 no-map; 729 }; 730 731 wlan_mem: memory@8bc00000 { 732 reg = <0x0 0x8bc00000 0x0 0x180000>; 733 no-map; 734 }; 735 736 npu_mem: memory@8bd80000 { 737 reg = <0x0 0x8bd80000 0x0 0x80000>; 738 no-map; 739 }; 740 741 adsp_mem: memory@8be00000 { 742 reg = <0x0 0x8be00000 0x0 0x1a00000>; 743 no-map; 744 }; 745 746 mpss_mem: memory@8d800000 { 747 reg = <0x0 0x8d800000 0x0 0x9600000>; 748 no-map; 749 }; 750 751 venus_mem: memory@96e00000 { 752 reg = <0x0 0x96e00000 0x0 0x500000>; 753 no-map; 754 }; 755 756 slpi_mem: memory@97300000 { 757 reg = <0x0 0x97300000 0x0 0x1400000>; 758 no-map; 759 }; 760 761 ipa_fw_mem: memory@98700000 { 762 reg = <0x0 0x98700000 0x0 0x10000>; 763 no-map; 764 }; 765 766 ipa_gsi_mem: memory@98710000 { 767 reg = <0x0 0x98710000 0x0 0x5000>; 768 no-map; 769 }; 770 771 gpu_mem: memory@98715000 { 772 reg = <0x0 0x98715000 0x0 0x2000>; 773 no-map; 774 }; 775 776 spss_mem: memory@98800000 { 777 reg = <0x0 0x98800000 0x0 0x100000>; 778 no-map; 779 }; 780 781 cdsp_mem: memory@98900000 { 782 reg = <0x0 0x98900000 0x0 0x1400000>; 783 no-map; 784 }; 785 786 qseecom_mem: memory@9e400000 { 787 reg = <0x0 0x9e400000 0x0 0x1400000>; 788 no-map; 789 }; 790 }; 791 792 smem { 793 compatible = "qcom,smem"; 794 memory-region = <&smem_mem>; 795 hwlocks = <&tcsr_mutex 3>; 796 }; 797 798 smp2p-cdsp { 799 compatible = "qcom,smp2p"; 800 qcom,smem = <94>, <432>; 801 802 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 803 804 mboxes = <&apss_shared 6>; 805 806 qcom,local-pid = <0>; 807 qcom,remote-pid = <5>; 808 809 cdsp_smp2p_out: master-kernel { 810 qcom,entry-name = "master-kernel"; 811 #qcom,smem-state-cells = <1>; 812 }; 813 814 cdsp_smp2p_in: slave-kernel { 815 qcom,entry-name = "slave-kernel"; 816 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 }; 820 }; 821 822 smp2p-lpass { 823 compatible = "qcom,smp2p"; 824 qcom,smem = <443>, <429>; 825 826 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 827 828 mboxes = <&apss_shared 10>; 829 830 qcom,local-pid = <0>; 831 qcom,remote-pid = <2>; 832 833 adsp_smp2p_out: master-kernel { 834 qcom,entry-name = "master-kernel"; 835 #qcom,smem-state-cells = <1>; 836 }; 837 838 adsp_smp2p_in: slave-kernel { 839 qcom,entry-name = "slave-kernel"; 840 841 interrupt-controller; 842 #interrupt-cells = <2>; 843 }; 844 }; 845 846 smp2p-mpss { 847 compatible = "qcom,smp2p"; 848 qcom,smem = <435>, <428>; 849 850 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 851 852 mboxes = <&apss_shared 14>; 853 854 qcom,local-pid = <0>; 855 qcom,remote-pid = <1>; 856 857 modem_smp2p_out: master-kernel { 858 qcom,entry-name = "master-kernel"; 859 #qcom,smem-state-cells = <1>; 860 }; 861 862 modem_smp2p_in: slave-kernel { 863 qcom,entry-name = "slave-kernel"; 864 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 }; 868 }; 869 870 smp2p-slpi { 871 compatible = "qcom,smp2p"; 872 qcom,smem = <481>, <430>; 873 874 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 875 876 mboxes = <&apss_shared 26>; 877 878 qcom,local-pid = <0>; 879 qcom,remote-pid = <3>; 880 881 slpi_smp2p_out: master-kernel { 882 qcom,entry-name = "master-kernel"; 883 #qcom,smem-state-cells = <1>; 884 }; 885 886 slpi_smp2p_in: slave-kernel { 887 qcom,entry-name = "slave-kernel"; 888 889 interrupt-controller; 890 #interrupt-cells = <2>; 891 }; 892 }; 893 894 soc: soc@0 { 895 #address-cells = <2>; 896 #size-cells = <2>; 897 ranges = <0 0 0 0 0x10 0>; 898 dma-ranges = <0 0 0 0 0x10 0>; 899 compatible = "simple-bus"; 900 901 gcc: clock-controller@100000 { 902 compatible = "qcom,gcc-sm8150"; 903 reg = <0x0 0x00100000 0x0 0x1f0000>; 904 #clock-cells = <1>; 905 #reset-cells = <1>; 906 #power-domain-cells = <1>; 907 clock-names = "bi_tcxo", 908 "sleep_clk"; 909 clocks = <&rpmhcc RPMH_CXO_CLK>, 910 <&sleep_clk>; 911 }; 912 913 gpi_dma0: dma-controller@800000 { 914 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 915 reg = <0 0x00800000 0 0x60000>; 916 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 929 dma-channels = <13>; 930 dma-channel-mask = <0xfa>; 931 iommus = <&apps_smmu 0x00d6 0x0>; 932 #dma-cells = <3>; 933 status = "disabled"; 934 }; 935 936 ethernet: ethernet@20000 { 937 compatible = "qcom,sm8150-ethqos"; 938 reg = <0x0 0x00020000 0x0 0x10000>, 939 <0x0 0x00036000 0x0 0x100>; 940 reg-names = "stmmaceth", "rgmii"; 941 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 942 clocks = <&gcc GCC_EMAC_AXI_CLK>, 943 <&gcc GCC_EMAC_SLV_AHB_CLK>, 944 <&gcc GCC_EMAC_PTP_CLK>, 945 <&gcc GCC_EMAC_RGMII_CLK>; 946 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "macirq", "eth_lpi"; 949 950 power-domains = <&gcc EMAC_GDSC>; 951 resets = <&gcc GCC_EMAC_BCR>; 952 953 iommus = <&apps_smmu 0x3c0 0x0>; 954 955 snps,tso; 956 rx-fifo-depth = <4096>; 957 tx-fifo-depth = <4096>; 958 959 status = "disabled"; 960 }; 961 962 qfprom: efuse@784000 { 963 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 964 reg = <0 0x00784000 0 0x8ff>; 965 #address-cells = <1>; 966 #size-cells = <1>; 967 968 gpu_speed_bin: gpu_speed_bin@133 { 969 reg = <0x133 0x1>; 970 bits = <5 3>; 971 }; 972 }; 973 974 qupv3_id_0: geniqup@8c0000 { 975 compatible = "qcom,geni-se-qup"; 976 reg = <0x0 0x008c0000 0x0 0x6000>; 977 clock-names = "m-ahb", "s-ahb"; 978 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 979 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 980 iommus = <&apps_smmu 0xc3 0x0>; 981 #address-cells = <2>; 982 #size-cells = <2>; 983 ranges; 984 status = "disabled"; 985 986 i2c0: i2c@880000 { 987 compatible = "qcom,geni-i2c"; 988 reg = <0 0x00880000 0 0x4000>; 989 clock-names = "se"; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 991 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 992 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 993 dma-names = "tx", "rx"; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_i2c0_default>; 996 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 }; 1001 1002 spi0: spi@880000 { 1003 compatible = "qcom,geni-spi"; 1004 reg = <0 0x00880000 0 0x4000>; 1005 reg-names = "se"; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1008 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1009 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1010 dma-names = "tx", "rx"; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&qup_spi0_default>; 1013 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1014 spi-max-frequency = <50000000>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 i2c1: i2c@884000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0 0x00884000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1025 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1026 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1027 dma-names = "tx", "rx"; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_i2c1_default>; 1030 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 status = "disabled"; 1034 }; 1035 1036 spi1: spi@884000 { 1037 compatible = "qcom,geni-spi"; 1038 reg = <0 0x00884000 0 0x4000>; 1039 reg-names = "se"; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1042 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1043 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1044 dma-names = "tx", "rx"; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_spi1_default>; 1047 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1048 spi-max-frequency = <50000000>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 status = "disabled"; 1052 }; 1053 1054 i2c2: i2c@888000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0 0x00888000 0 0x4000>; 1057 clock-names = "se"; 1058 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1059 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1060 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1061 dma-names = "tx", "rx"; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&qup_i2c2_default>; 1064 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 spi2: spi@888000 { 1071 compatible = "qcom,geni-spi"; 1072 reg = <0 0x00888000 0 0x4000>; 1073 reg-names = "se"; 1074 clock-names = "se"; 1075 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1076 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1077 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1078 dma-names = "tx", "rx"; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_spi2_default>; 1081 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1082 spi-max-frequency = <50000000>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 status = "disabled"; 1086 }; 1087 1088 i2c3: i2c@88c000 { 1089 compatible = "qcom,geni-i2c"; 1090 reg = <0 0x0088c000 0 0x4000>; 1091 clock-names = "se"; 1092 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1093 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1094 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1095 dma-names = "tx", "rx"; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&qup_i2c3_default>; 1098 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 status = "disabled"; 1102 }; 1103 1104 spi3: spi@88c000 { 1105 compatible = "qcom,geni-spi"; 1106 reg = <0 0x0088c000 0 0x4000>; 1107 reg-names = "se"; 1108 clock-names = "se"; 1109 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1110 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1111 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1112 dma-names = "tx", "rx"; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&qup_spi3_default>; 1115 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1116 spi-max-frequency = <50000000>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 status = "disabled"; 1120 }; 1121 1122 i2c4: i2c@890000 { 1123 compatible = "qcom,geni-i2c"; 1124 reg = <0 0x00890000 0 0x4000>; 1125 clock-names = "se"; 1126 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1127 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1128 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1129 dma-names = "tx", "rx"; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&qup_i2c4_default>; 1132 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 status = "disabled"; 1136 }; 1137 1138 spi4: spi@890000 { 1139 compatible = "qcom,geni-spi"; 1140 reg = <0 0x00890000 0 0x4000>; 1141 reg-names = "se"; 1142 clock-names = "se"; 1143 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1144 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1145 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1146 dma-names = "tx", "rx"; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_spi4_default>; 1149 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1150 spi-max-frequency = <50000000>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c5: i2c@894000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x00894000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1161 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1162 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1163 dma-names = "tx", "rx"; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_i2c5_default>; 1166 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 spi5: spi@894000 { 1173 compatible = "qcom,geni-spi"; 1174 reg = <0 0x00894000 0 0x4000>; 1175 reg-names = "se"; 1176 clock-names = "se"; 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1178 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1179 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1180 dma-names = "tx", "rx"; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&qup_spi5_default>; 1183 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1184 spi-max-frequency = <50000000>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 i2c6: i2c@898000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0 0x00898000 0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1195 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1196 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1197 dma-names = "tx", "rx"; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_i2c6_default>; 1200 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 status = "disabled"; 1204 }; 1205 1206 spi6: spi@898000 { 1207 compatible = "qcom,geni-spi"; 1208 reg = <0 0x00898000 0 0x4000>; 1209 reg-names = "se"; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1212 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1213 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1214 dma-names = "tx", "rx"; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&qup_spi6_default>; 1217 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1218 spi-max-frequency = <50000000>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 i2c7: i2c@89c000 { 1225 compatible = "qcom,geni-i2c"; 1226 reg = <0 0x0089c000 0 0x4000>; 1227 clock-names = "se"; 1228 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1229 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1230 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1231 dma-names = "tx", "rx"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_i2c7_default>; 1234 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 status = "disabled"; 1238 }; 1239 1240 spi7: spi@89c000 { 1241 compatible = "qcom,geni-spi"; 1242 reg = <0 0x0089c000 0 0x4000>; 1243 reg-names = "se"; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1246 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1247 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1248 dma-names = "tx", "rx"; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_spi7_default>; 1251 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1252 spi-max-frequency = <50000000>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 status = "disabled"; 1256 }; 1257 }; 1258 1259 gpi_dma1: dma-controller@a00000 { 1260 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1261 reg = <0 0x00a00000 0 0x60000>; 1262 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1275 dma-channels = <13>; 1276 dma-channel-mask = <0xfa>; 1277 iommus = <&apps_smmu 0x0616 0x0>; 1278 #dma-cells = <3>; 1279 status = "disabled"; 1280 }; 1281 1282 qupv3_id_1: geniqup@ac0000 { 1283 compatible = "qcom,geni-se-qup"; 1284 reg = <0x0 0x00ac0000 0x0 0x6000>; 1285 clock-names = "m-ahb", "s-ahb"; 1286 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1287 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1288 iommus = <&apps_smmu 0x603 0x0>; 1289 #address-cells = <2>; 1290 #size-cells = <2>; 1291 ranges; 1292 status = "disabled"; 1293 1294 i2c8: i2c@a80000 { 1295 compatible = "qcom,geni-i2c"; 1296 reg = <0 0x00a80000 0 0x4000>; 1297 clock-names = "se"; 1298 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1299 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1300 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1301 dma-names = "tx", "rx"; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_i2c8_default>; 1304 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 status = "disabled"; 1308 }; 1309 1310 spi8: spi@a80000 { 1311 compatible = "qcom,geni-spi"; 1312 reg = <0 0x00a80000 0 0x4000>; 1313 reg-names = "se"; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1316 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1317 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1318 dma-names = "tx", "rx"; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&qup_spi8_default>; 1321 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1322 spi-max-frequency = <50000000>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 i2c9: i2c@a84000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0 0x00a84000 0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1333 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1334 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1335 dma-names = "tx", "rx"; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_i2c9_default>; 1338 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 status = "disabled"; 1342 }; 1343 1344 spi9: spi@a84000 { 1345 compatible = "qcom,geni-spi"; 1346 reg = <0 0x00a84000 0 0x4000>; 1347 reg-names = "se"; 1348 clock-names = "se"; 1349 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1350 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1351 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1352 dma-names = "tx", "rx"; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_spi9_default>; 1355 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1356 spi-max-frequency = <50000000>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 status = "disabled"; 1360 }; 1361 1362 uart9: serial@a84000 { 1363 compatible = "qcom,geni-uart"; 1364 reg = <0x0 0x00a84000 0x0 0x4000>; 1365 reg-names = "se"; 1366 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1367 clock-names = "se"; 1368 pinctrl-0 = <&qup_uart9_default>; 1369 pinctrl-names = "default"; 1370 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 i2c10: i2c@a88000 { 1377 compatible = "qcom,geni-i2c"; 1378 reg = <0 0x00a88000 0 0x4000>; 1379 clock-names = "se"; 1380 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1381 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1382 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1383 dma-names = "tx", "rx"; 1384 pinctrl-names = "default"; 1385 pinctrl-0 = <&qup_i2c10_default>; 1386 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 status = "disabled"; 1390 }; 1391 1392 spi10: spi@a88000 { 1393 compatible = "qcom,geni-spi"; 1394 reg = <0 0x00a88000 0 0x4000>; 1395 reg-names = "se"; 1396 clock-names = "se"; 1397 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1398 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1399 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1400 dma-names = "tx", "rx"; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_spi10_default>; 1403 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1404 spi-max-frequency = <50000000>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 status = "disabled"; 1408 }; 1409 1410 i2c11: i2c@a8c000 { 1411 compatible = "qcom,geni-i2c"; 1412 reg = <0 0x00a8c000 0 0x4000>; 1413 clock-names = "se"; 1414 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1415 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1416 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1417 dma-names = "tx", "rx"; 1418 pinctrl-names = "default"; 1419 pinctrl-0 = <&qup_i2c11_default>; 1420 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 status = "disabled"; 1424 }; 1425 1426 spi11: spi@a8c000 { 1427 compatible = "qcom,geni-spi"; 1428 reg = <0 0x00a8c000 0 0x4000>; 1429 reg-names = "se"; 1430 clock-names = "se"; 1431 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1432 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1433 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1434 dma-names = "tx", "rx"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_spi11_default>; 1437 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1438 spi-max-frequency = <50000000>; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 status = "disabled"; 1442 }; 1443 1444 uart2: serial@a90000 { 1445 compatible = "qcom,geni-debug-uart"; 1446 reg = <0x0 0x00a90000 0x0 0x4000>; 1447 clock-names = "se"; 1448 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1449 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1450 status = "disabled"; 1451 }; 1452 1453 i2c12: i2c@a90000 { 1454 compatible = "qcom,geni-i2c"; 1455 reg = <0 0x00a90000 0 0x4000>; 1456 clock-names = "se"; 1457 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1458 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1459 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1460 dma-names = "tx", "rx"; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_i2c12_default>; 1463 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 status = "disabled"; 1467 }; 1468 1469 spi12: spi@a90000 { 1470 compatible = "qcom,geni-spi"; 1471 reg = <0 0x00a90000 0 0x4000>; 1472 reg-names = "se"; 1473 clock-names = "se"; 1474 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1475 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1476 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1477 dma-names = "tx", "rx"; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_spi12_default>; 1480 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1481 spi-max-frequency = <50000000>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 status = "disabled"; 1485 }; 1486 1487 i2c16: i2c@94000 { 1488 compatible = "qcom,geni-i2c"; 1489 reg = <0 0x00094000 0 0x4000>; 1490 clock-names = "se"; 1491 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1492 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1493 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1494 dma-names = "tx", "rx"; 1495 pinctrl-names = "default"; 1496 pinctrl-0 = <&qup_i2c16_default>; 1497 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 status = "disabled"; 1501 }; 1502 1503 spi16: spi@a94000 { 1504 compatible = "qcom,geni-spi"; 1505 reg = <0 0x00a94000 0 0x4000>; 1506 reg-names = "se"; 1507 clock-names = "se"; 1508 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1509 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1510 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1511 dma-names = "tx", "rx"; 1512 pinctrl-names = "default"; 1513 pinctrl-0 = <&qup_spi16_default>; 1514 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1515 spi-max-frequency = <50000000>; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 status = "disabled"; 1519 }; 1520 }; 1521 1522 gpi_dma2: dma-controller@c00000 { 1523 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1524 reg = <0 0x00c00000 0 0x60000>; 1525 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1538 dma-channels = <13>; 1539 dma-channel-mask = <0xfa>; 1540 iommus = <&apps_smmu 0x07b6 0x0>; 1541 #dma-cells = <3>; 1542 status = "disabled"; 1543 }; 1544 1545 qupv3_id_2: geniqup@cc0000 { 1546 compatible = "qcom,geni-se-qup"; 1547 reg = <0x0 0x00cc0000 0x0 0x6000>; 1548 1549 clock-names = "m-ahb", "s-ahb"; 1550 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1551 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1552 iommus = <&apps_smmu 0x7a3 0x0>; 1553 #address-cells = <2>; 1554 #size-cells = <2>; 1555 ranges; 1556 status = "disabled"; 1557 1558 i2c17: i2c@c80000 { 1559 compatible = "qcom,geni-i2c"; 1560 reg = <0 0x00c80000 0 0x4000>; 1561 clock-names = "se"; 1562 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1563 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1564 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1565 dma-names = "tx", "rx"; 1566 pinctrl-names = "default"; 1567 pinctrl-0 = <&qup_i2c17_default>; 1568 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 status = "disabled"; 1572 }; 1573 1574 spi17: spi@c80000 { 1575 compatible = "qcom,geni-spi"; 1576 reg = <0 0x00c80000 0 0x4000>; 1577 reg-names = "se"; 1578 clock-names = "se"; 1579 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1580 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1581 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1582 dma-names = "tx", "rx"; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&qup_spi17_default>; 1585 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1586 spi-max-frequency = <50000000>; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 status = "disabled"; 1590 }; 1591 1592 i2c18: i2c@c84000 { 1593 compatible = "qcom,geni-i2c"; 1594 reg = <0 0x00c84000 0 0x4000>; 1595 clock-names = "se"; 1596 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1597 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1598 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1599 dma-names = "tx", "rx"; 1600 pinctrl-names = "default"; 1601 pinctrl-0 = <&qup_i2c18_default>; 1602 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 status = "disabled"; 1606 }; 1607 1608 spi18: spi@c84000 { 1609 compatible = "qcom,geni-spi"; 1610 reg = <0 0x00c84000 0 0x4000>; 1611 reg-names = "se"; 1612 clock-names = "se"; 1613 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1614 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1615 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1616 dma-names = "tx", "rx"; 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&qup_spi18_default>; 1619 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1620 spi-max-frequency = <50000000>; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 status = "disabled"; 1624 }; 1625 1626 i2c19: i2c@c88000 { 1627 compatible = "qcom,geni-i2c"; 1628 reg = <0 0x00c88000 0 0x4000>; 1629 clock-names = "se"; 1630 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1631 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1632 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1633 dma-names = "tx", "rx"; 1634 pinctrl-names = "default"; 1635 pinctrl-0 = <&qup_i2c19_default>; 1636 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 status = "disabled"; 1640 }; 1641 1642 spi19: spi@c88000 { 1643 compatible = "qcom,geni-spi"; 1644 reg = <0 0x00c88000 0 0x4000>; 1645 reg-names = "se"; 1646 clock-names = "se"; 1647 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1648 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1649 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1650 dma-names = "tx", "rx"; 1651 pinctrl-names = "default"; 1652 pinctrl-0 = <&qup_spi19_default>; 1653 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1654 spi-max-frequency = <50000000>; 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 status = "disabled"; 1658 }; 1659 1660 i2c13: i2c@c8c000 { 1661 compatible = "qcom,geni-i2c"; 1662 reg = <0 0x00c8c000 0 0x4000>; 1663 clock-names = "se"; 1664 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1665 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1666 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1667 dma-names = "tx", "rx"; 1668 pinctrl-names = "default"; 1669 pinctrl-0 = <&qup_i2c13_default>; 1670 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 status = "disabled"; 1674 }; 1675 1676 spi13: spi@c8c000 { 1677 compatible = "qcom,geni-spi"; 1678 reg = <0 0x00c8c000 0 0x4000>; 1679 reg-names = "se"; 1680 clock-names = "se"; 1681 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1682 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1683 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1684 dma-names = "tx", "rx"; 1685 pinctrl-names = "default"; 1686 pinctrl-0 = <&qup_spi13_default>; 1687 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1688 spi-max-frequency = <50000000>; 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 status = "disabled"; 1692 }; 1693 1694 i2c14: i2c@c90000 { 1695 compatible = "qcom,geni-i2c"; 1696 reg = <0 0x00c90000 0 0x4000>; 1697 clock-names = "se"; 1698 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1699 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1700 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1701 dma-names = "tx", "rx"; 1702 pinctrl-names = "default"; 1703 pinctrl-0 = <&qup_i2c14_default>; 1704 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 status = "disabled"; 1708 }; 1709 1710 spi14: spi@c90000 { 1711 compatible = "qcom,geni-spi"; 1712 reg = <0 0x00c90000 0 0x4000>; 1713 reg-names = "se"; 1714 clock-names = "se"; 1715 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1716 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1717 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1718 dma-names = "tx", "rx"; 1719 pinctrl-names = "default"; 1720 pinctrl-0 = <&qup_spi14_default>; 1721 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1722 spi-max-frequency = <50000000>; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 status = "disabled"; 1726 }; 1727 1728 i2c15: i2c@c94000 { 1729 compatible = "qcom,geni-i2c"; 1730 reg = <0 0x00c94000 0 0x4000>; 1731 clock-names = "se"; 1732 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1733 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1734 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1735 dma-names = "tx", "rx"; 1736 pinctrl-names = "default"; 1737 pinctrl-0 = <&qup_i2c15_default>; 1738 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 status = "disabled"; 1742 }; 1743 1744 spi15: spi@c94000 { 1745 compatible = "qcom,geni-spi"; 1746 reg = <0 0x00c94000 0 0x4000>; 1747 reg-names = "se"; 1748 clock-names = "se"; 1749 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1750 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1751 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1752 dma-names = "tx", "rx"; 1753 pinctrl-names = "default"; 1754 pinctrl-0 = <&qup_spi15_default>; 1755 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1756 spi-max-frequency = <50000000>; 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 status = "disabled"; 1760 }; 1761 }; 1762 1763 config_noc: interconnect@1500000 { 1764 compatible = "qcom,sm8150-config-noc"; 1765 reg = <0 0x01500000 0 0x7400>; 1766 #interconnect-cells = <1>; 1767 qcom,bcm-voters = <&apps_bcm_voter>; 1768 }; 1769 1770 system_noc: interconnect@1620000 { 1771 compatible = "qcom,sm8150-system-noc"; 1772 reg = <0 0x01620000 0 0x19400>; 1773 #interconnect-cells = <1>; 1774 qcom,bcm-voters = <&apps_bcm_voter>; 1775 }; 1776 1777 mc_virt: interconnect@163a000 { 1778 compatible = "qcom,sm8150-mc-virt"; 1779 reg = <0 0x0163a000 0 0x1000>; 1780 #interconnect-cells = <1>; 1781 qcom,bcm-voters = <&apps_bcm_voter>; 1782 }; 1783 1784 aggre1_noc: interconnect@16e0000 { 1785 compatible = "qcom,sm8150-aggre1-noc"; 1786 reg = <0 0x016e0000 0 0xd080>; 1787 #interconnect-cells = <1>; 1788 qcom,bcm-voters = <&apps_bcm_voter>; 1789 }; 1790 1791 aggre2_noc: interconnect@1700000 { 1792 compatible = "qcom,sm8150-aggre2-noc"; 1793 reg = <0 0x01700000 0 0x20000>; 1794 #interconnect-cells = <1>; 1795 qcom,bcm-voters = <&apps_bcm_voter>; 1796 }; 1797 1798 compute_noc: interconnect@1720000 { 1799 compatible = "qcom,sm8150-compute-noc"; 1800 reg = <0 0x01720000 0 0x7000>; 1801 #interconnect-cells = <1>; 1802 qcom,bcm-voters = <&apps_bcm_voter>; 1803 }; 1804 1805 mmss_noc: interconnect@1740000 { 1806 compatible = "qcom,sm8150-mmss-noc"; 1807 reg = <0 0x01740000 0 0x1c100>; 1808 #interconnect-cells = <1>; 1809 qcom,bcm-voters = <&apps_bcm_voter>; 1810 }; 1811 1812 system-cache-controller@9200000 { 1813 compatible = "qcom,sm8150-llcc"; 1814 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1815 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1816 <0 0x09600000 0 0x50000>; 1817 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1818 "llcc3_base", "llcc_broadcast_base"; 1819 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1820 }; 1821 1822 dma@10a2000 { 1823 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1824 reg = <0x0 0x010a2000 0x0 0x1000>, 1825 <0x0 0x010ad000 0x0 0x3000>; 1826 }; 1827 1828 pcie0: pci@1c00000 { 1829 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1830 reg = <0 0x01c00000 0 0x3000>, 1831 <0 0x60000000 0 0xf1d>, 1832 <0 0x60000f20 0 0xa8>, 1833 <0 0x60001000 0 0x1000>, 1834 <0 0x60100000 0 0x100000>; 1835 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1836 device_type = "pci"; 1837 linux,pci-domain = <0>; 1838 bus-range = <0x00 0xff>; 1839 num-lanes = <1>; 1840 1841 #address-cells = <3>; 1842 #size-cells = <2>; 1843 1844 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1845 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1846 1847 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1848 interrupt-names = "msi"; 1849 #interrupt-cells = <1>; 1850 interrupt-map-mask = <0 0 0 0x7>; 1851 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1852 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1853 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1854 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1855 1856 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1857 <&gcc GCC_PCIE_0_AUX_CLK>, 1858 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1859 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1860 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1861 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1862 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1863 clock-names = "pipe", 1864 "aux", 1865 "cfg", 1866 "bus_master", 1867 "bus_slave", 1868 "slave_q2a", 1869 "tbu"; 1870 1871 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1872 <0x100 &apps_smmu 0x1d81 0x1>; 1873 1874 resets = <&gcc GCC_PCIE_0_BCR>; 1875 reset-names = "pci"; 1876 1877 power-domains = <&gcc PCIE_0_GDSC>; 1878 1879 phys = <&pcie0_lane>; 1880 phy-names = "pciephy"; 1881 1882 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1883 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1884 1885 pinctrl-names = "default"; 1886 pinctrl-0 = <&pcie0_default_state>; 1887 1888 status = "disabled"; 1889 }; 1890 1891 pcie0_phy: phy@1c06000 { 1892 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1893 reg = <0 0x01c06000 0 0x1c0>; 1894 #address-cells = <2>; 1895 #size-cells = <2>; 1896 ranges; 1897 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1898 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1899 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1900 clock-names = "aux", "cfg_ahb", "refgen"; 1901 1902 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1903 reset-names = "phy"; 1904 1905 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1906 assigned-clock-rates = <100000000>; 1907 1908 status = "disabled"; 1909 1910 pcie0_lane: phy@1c06200 { 1911 reg = <0 0x01c06200 0 0x170>, /* tx */ 1912 <0 0x01c06400 0 0x200>, /* rx */ 1913 <0 0x01c06800 0 0x1f0>, /* pcs */ 1914 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1915 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1916 clock-names = "pipe0"; 1917 1918 #phy-cells = <0>; 1919 clock-output-names = "pcie_0_pipe_clk"; 1920 }; 1921 }; 1922 1923 pcie1: pci@1c08000 { 1924 compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; 1925 reg = <0 0x01c08000 0 0x3000>, 1926 <0 0x40000000 0 0xf1d>, 1927 <0 0x40000f20 0 0xa8>, 1928 <0 0x40001000 0 0x1000>, 1929 <0 0x40100000 0 0x100000>; 1930 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1931 device_type = "pci"; 1932 linux,pci-domain = <1>; 1933 bus-range = <0x00 0xff>; 1934 num-lanes = <2>; 1935 1936 #address-cells = <3>; 1937 #size-cells = <2>; 1938 1939 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1940 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1941 1942 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1943 interrupt-names = "msi"; 1944 #interrupt-cells = <1>; 1945 interrupt-map-mask = <0 0 0 0x7>; 1946 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1947 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1948 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1949 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1950 1951 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1952 <&gcc GCC_PCIE_1_AUX_CLK>, 1953 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1954 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1955 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1956 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1957 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1958 clock-names = "pipe", 1959 "aux", 1960 "cfg", 1961 "bus_master", 1962 "bus_slave", 1963 "slave_q2a", 1964 "tbu"; 1965 1966 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1967 assigned-clock-rates = <19200000>; 1968 1969 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1970 <0x100 &apps_smmu 0x1e01 0x1>; 1971 1972 resets = <&gcc GCC_PCIE_1_BCR>; 1973 reset-names = "pci"; 1974 1975 power-domains = <&gcc PCIE_1_GDSC>; 1976 1977 phys = <&pcie1_lane>; 1978 phy-names = "pciephy"; 1979 1980 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1981 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1982 1983 pinctrl-names = "default"; 1984 pinctrl-0 = <&pcie1_default_state>; 1985 1986 status = "disabled"; 1987 }; 1988 1989 pcie1_phy: phy@1c0e000 { 1990 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1991 reg = <0 0x01c0e000 0 0x1c0>; 1992 #address-cells = <2>; 1993 #size-cells = <2>; 1994 ranges; 1995 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1996 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1997 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1998 clock-names = "aux", "cfg_ahb", "refgen"; 1999 2000 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2001 reset-names = "phy"; 2002 2003 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2004 assigned-clock-rates = <100000000>; 2005 2006 status = "disabled"; 2007 2008 pcie1_lane: phy@1c0e200 { 2009 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2010 <0 0x01c0e400 0 0x200>, /* rx0 */ 2011 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2012 <0 0x01c0e600 0 0x170>, /* tx1 */ 2013 <0 0x01c0e800 0 0x200>, /* rx1 */ 2014 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2015 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2016 clock-names = "pipe0"; 2017 2018 #phy-cells = <0>; 2019 clock-output-names = "pcie_1_pipe_clk"; 2020 }; 2021 }; 2022 2023 ufs_mem_hc: ufshc@1d84000 { 2024 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2025 "jedec,ufs-2.0"; 2026 reg = <0 0x01d84000 0 0x2500>, 2027 <0 0x01d90000 0 0x8000>; 2028 reg-names = "std", "ice"; 2029 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2030 phys = <&ufs_mem_phy_lanes>; 2031 phy-names = "ufsphy"; 2032 lanes-per-direction = <2>; 2033 #reset-cells = <1>; 2034 resets = <&gcc GCC_UFS_PHY_BCR>; 2035 reset-names = "rst"; 2036 2037 iommus = <&apps_smmu 0x300 0>; 2038 2039 clock-names = 2040 "core_clk", 2041 "bus_aggr_clk", 2042 "iface_clk", 2043 "core_clk_unipro", 2044 "ref_clk", 2045 "tx_lane0_sync_clk", 2046 "rx_lane0_sync_clk", 2047 "rx_lane1_sync_clk", 2048 "ice_core_clk"; 2049 clocks = 2050 <&gcc GCC_UFS_PHY_AXI_CLK>, 2051 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2052 <&gcc GCC_UFS_PHY_AHB_CLK>, 2053 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2054 <&rpmhcc RPMH_CXO_CLK>, 2055 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2056 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2057 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2058 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2059 freq-table-hz = 2060 <37500000 300000000>, 2061 <0 0>, 2062 <0 0>, 2063 <37500000 300000000>, 2064 <0 0>, 2065 <0 0>, 2066 <0 0>, 2067 <0 0>, 2068 <0 300000000>; 2069 2070 status = "disabled"; 2071 }; 2072 2073 ufs_mem_phy: phy@1d87000 { 2074 compatible = "qcom,sm8150-qmp-ufs-phy"; 2075 reg = <0 0x01d87000 0 0x1c0>; 2076 #address-cells = <2>; 2077 #size-cells = <2>; 2078 ranges; 2079 clock-names = "ref", 2080 "ref_aux"; 2081 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2082 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2083 2084 power-domains = <&gcc UFS_PHY_GDSC>; 2085 2086 resets = <&ufs_mem_hc 0>; 2087 reset-names = "ufsphy"; 2088 status = "disabled"; 2089 2090 ufs_mem_phy_lanes: phy@1d87400 { 2091 reg = <0 0x01d87400 0 0x16c>, 2092 <0 0x01d87600 0 0x200>, 2093 <0 0x01d87c00 0 0x200>, 2094 <0 0x01d87800 0 0x16c>, 2095 <0 0x01d87a00 0 0x200>; 2096 #phy-cells = <0>; 2097 }; 2098 }; 2099 2100 tcsr_mutex: hwlock@1f40000 { 2101 compatible = "qcom,tcsr-mutex"; 2102 reg = <0x0 0x01f40000 0x0 0x20000>; 2103 #hwlock-cells = <1>; 2104 }; 2105 2106 tcsr_regs_1: syscon@1f60000 { 2107 compatible = "qcom,sm8150-tcsr", "syscon"; 2108 reg = <0x0 0x01f60000 0x0 0x20000>; 2109 }; 2110 2111 remoteproc_slpi: remoteproc@2400000 { 2112 compatible = "qcom,sm8150-slpi-pas"; 2113 reg = <0x0 0x02400000 0x0 0x4040>; 2114 2115 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2116 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2117 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2118 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2119 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2120 interrupt-names = "wdog", "fatal", "ready", 2121 "handover", "stop-ack"; 2122 2123 clocks = <&rpmhcc RPMH_CXO_CLK>; 2124 clock-names = "xo"; 2125 2126 power-domains = <&rpmhpd SM8150_LCX>, 2127 <&rpmhpd SM8150_LMX>; 2128 power-domain-names = "lcx", "lmx"; 2129 2130 memory-region = <&slpi_mem>; 2131 2132 qcom,qmp = <&aoss_qmp>; 2133 2134 qcom,smem-states = <&slpi_smp2p_out 0>; 2135 qcom,smem-state-names = "stop"; 2136 2137 status = "disabled"; 2138 2139 glink-edge { 2140 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2141 label = "dsps"; 2142 qcom,remote-pid = <3>; 2143 mboxes = <&apss_shared 24>; 2144 2145 fastrpc { 2146 compatible = "qcom,fastrpc"; 2147 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2148 label = "sdsp"; 2149 qcom,non-secure-domain; 2150 #address-cells = <1>; 2151 #size-cells = <0>; 2152 2153 compute-cb@1 { 2154 compatible = "qcom,fastrpc-compute-cb"; 2155 reg = <1>; 2156 iommus = <&apps_smmu 0x05a1 0x0>; 2157 }; 2158 2159 compute-cb@2 { 2160 compatible = "qcom,fastrpc-compute-cb"; 2161 reg = <2>; 2162 iommus = <&apps_smmu 0x05a2 0x0>; 2163 }; 2164 2165 compute-cb@3 { 2166 compatible = "qcom,fastrpc-compute-cb"; 2167 reg = <3>; 2168 iommus = <&apps_smmu 0x05a3 0x0>; 2169 /* note: shared-cb = <4> in downstream */ 2170 }; 2171 }; 2172 }; 2173 }; 2174 2175 gpu: gpu@2c00000 { 2176 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2177 reg = <0 0x02c00000 0 0x40000>; 2178 reg-names = "kgsl_3d0_reg_memory"; 2179 2180 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2181 2182 iommus = <&adreno_smmu 0 0x401>; 2183 2184 operating-points-v2 = <&gpu_opp_table>; 2185 2186 qcom,gmu = <&gmu>; 2187 2188 nvmem-cells = <&gpu_speed_bin>; 2189 nvmem-cell-names = "speed_bin"; 2190 2191 status = "disabled"; 2192 2193 zap-shader { 2194 memory-region = <&gpu_mem>; 2195 }; 2196 2197 gpu_opp_table: opp-table { 2198 compatible = "operating-points-v2"; 2199 2200 opp-675000000 { 2201 opp-hz = /bits/ 64 <675000000>; 2202 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2203 opp-supported-hw = <0x2>; 2204 }; 2205 2206 opp-585000000 { 2207 opp-hz = /bits/ 64 <585000000>; 2208 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2209 opp-supported-hw = <0x3>; 2210 }; 2211 2212 opp-499200000 { 2213 opp-hz = /bits/ 64 <499200000>; 2214 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2215 opp-supported-hw = <0x3>; 2216 }; 2217 2218 opp-427000000 { 2219 opp-hz = /bits/ 64 <427000000>; 2220 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2221 opp-supported-hw = <0x3>; 2222 }; 2223 2224 opp-345000000 { 2225 opp-hz = /bits/ 64 <345000000>; 2226 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2227 opp-supported-hw = <0x3>; 2228 }; 2229 2230 opp-257000000 { 2231 opp-hz = /bits/ 64 <257000000>; 2232 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2233 opp-supported-hw = <0x3>; 2234 }; 2235 }; 2236 }; 2237 2238 gmu: gmu@2c6a000 { 2239 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2240 2241 reg = <0 0x02c6a000 0 0x30000>, 2242 <0 0x0b290000 0 0x10000>, 2243 <0 0x0b490000 0 0x10000>; 2244 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2245 2246 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2248 interrupt-names = "hfi", "gmu"; 2249 2250 clocks = <&gpucc GPU_CC_AHB_CLK>, 2251 <&gpucc GPU_CC_CX_GMU_CLK>, 2252 <&gpucc GPU_CC_CXO_CLK>, 2253 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2254 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2255 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2256 2257 power-domains = <&gpucc GPU_CX_GDSC>, 2258 <&gpucc GPU_GX_GDSC>; 2259 power-domain-names = "cx", "gx"; 2260 2261 iommus = <&adreno_smmu 5 0x400>; 2262 2263 operating-points-v2 = <&gmu_opp_table>; 2264 2265 status = "disabled"; 2266 2267 gmu_opp_table: opp-table { 2268 compatible = "operating-points-v2"; 2269 2270 opp-200000000 { 2271 opp-hz = /bits/ 64 <200000000>; 2272 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2273 }; 2274 }; 2275 }; 2276 2277 gpucc: clock-controller@2c90000 { 2278 compatible = "qcom,sm8150-gpucc"; 2279 reg = <0 0x02c90000 0 0x9000>; 2280 clocks = <&rpmhcc RPMH_CXO_CLK>, 2281 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2282 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2283 clock-names = "bi_tcxo", 2284 "gcc_gpu_gpll0_clk_src", 2285 "gcc_gpu_gpll0_div_clk_src"; 2286 #clock-cells = <1>; 2287 #reset-cells = <1>; 2288 #power-domain-cells = <1>; 2289 }; 2290 2291 adreno_smmu: iommu@2ca0000 { 2292 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2293 "qcom,smmu-500", "arm,mmu-500"; 2294 reg = <0 0x02ca0000 0 0x10000>; 2295 #iommu-cells = <2>; 2296 #global-interrupts = <1>; 2297 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2298 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2299 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2300 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2303 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2304 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2305 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2306 clocks = <&gpucc GPU_CC_AHB_CLK>, 2307 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2308 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2309 clock-names = "ahb", "bus", "iface"; 2310 2311 power-domains = <&gpucc GPU_CX_GDSC>; 2312 }; 2313 2314 tlmm: pinctrl@3100000 { 2315 compatible = "qcom,sm8150-pinctrl"; 2316 reg = <0x0 0x03100000 0x0 0x300000>, 2317 <0x0 0x03500000 0x0 0x300000>, 2318 <0x0 0x03900000 0x0 0x300000>, 2319 <0x0 0x03D00000 0x0 0x300000>; 2320 reg-names = "west", "east", "north", "south"; 2321 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2322 gpio-ranges = <&tlmm 0 0 176>; 2323 gpio-controller; 2324 #gpio-cells = <2>; 2325 interrupt-controller; 2326 #interrupt-cells = <2>; 2327 wakeup-parent = <&pdc>; 2328 2329 qup_i2c0_default: qup-i2c0-default-state { 2330 pins = "gpio0", "gpio1"; 2331 function = "qup0"; 2332 drive-strength = <0x02>; 2333 bias-disable; 2334 }; 2335 2336 qup_spi0_default: qup-spi0-default-state { 2337 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2338 function = "qup0"; 2339 drive-strength = <6>; 2340 bias-disable; 2341 }; 2342 2343 qup_i2c1_default: qup-i2c1-default-state { 2344 pins = "gpio114", "gpio115"; 2345 function = "qup1"; 2346 drive-strength = <2>; 2347 bias-disable; 2348 }; 2349 2350 qup_spi1_default: qup-spi1-default-state { 2351 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2352 function = "qup1"; 2353 drive-strength = <6>; 2354 bias-disable; 2355 }; 2356 2357 qup_i2c2_default: qup-i2c2-default-state { 2358 pins = "gpio126", "gpio127"; 2359 function = "qup2"; 2360 drive-strength = <2>; 2361 bias-disable; 2362 }; 2363 2364 qup_spi2_default: qup-spi2-default-state { 2365 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2366 function = "qup2"; 2367 drive-strength = <6>; 2368 bias-disable; 2369 }; 2370 2371 qup_i2c3_default: qup-i2c3-default-state { 2372 pins = "gpio144", "gpio145"; 2373 function = "qup3"; 2374 drive-strength = <2>; 2375 bias-disable; 2376 }; 2377 2378 qup_spi3_default: qup-spi3-default-state { 2379 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2380 function = "qup3"; 2381 drive-strength = <6>; 2382 bias-disable; 2383 }; 2384 2385 qup_i2c4_default: qup-i2c4-default-state { 2386 pins = "gpio51", "gpio52"; 2387 function = "qup4"; 2388 drive-strength = <2>; 2389 bias-disable; 2390 }; 2391 2392 qup_spi4_default: qup-spi4-default-state { 2393 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2394 function = "qup4"; 2395 drive-strength = <6>; 2396 bias-disable; 2397 }; 2398 2399 qup_i2c5_default: qup-i2c5-default-state { 2400 pins = "gpio121", "gpio122"; 2401 function = "qup5"; 2402 drive-strength = <2>; 2403 bias-disable; 2404 }; 2405 2406 qup_spi5_default: qup-spi5-default-state { 2407 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2408 function = "qup5"; 2409 drive-strength = <6>; 2410 bias-disable; 2411 }; 2412 2413 qup_i2c6_default: qup-i2c6-default-state { 2414 pins = "gpio6", "gpio7"; 2415 function = "qup6"; 2416 drive-strength = <2>; 2417 bias-disable; 2418 }; 2419 2420 qup_spi6_default: qup-spi6_default-state { 2421 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2422 function = "qup6"; 2423 drive-strength = <6>; 2424 bias-disable; 2425 }; 2426 2427 qup_i2c7_default: qup-i2c7-default-state { 2428 pins = "gpio98", "gpio99"; 2429 function = "qup7"; 2430 drive-strength = <2>; 2431 bias-disable; 2432 }; 2433 2434 qup_spi7_default: qup-spi7_default-state { 2435 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2436 function = "qup7"; 2437 drive-strength = <6>; 2438 bias-disable; 2439 }; 2440 2441 qup_i2c8_default: qup-i2c8-default-state { 2442 pins = "gpio88", "gpio89"; 2443 function = "qup8"; 2444 drive-strength = <2>; 2445 bias-disable; 2446 }; 2447 2448 qup_spi8_default: qup-spi8-default-state { 2449 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2450 function = "qup8"; 2451 drive-strength = <6>; 2452 bias-disable; 2453 }; 2454 2455 qup_i2c9_default: qup-i2c9-default-state { 2456 pins = "gpio39", "gpio40"; 2457 function = "qup9"; 2458 drive-strength = <2>; 2459 bias-disable; 2460 }; 2461 2462 qup_spi9_default: qup-spi9-default-state { 2463 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2464 function = "qup9"; 2465 drive-strength = <6>; 2466 bias-disable; 2467 }; 2468 2469 qup_uart9_default: qup-uart9-default-state { 2470 pins = "gpio41", "gpio42"; 2471 function = "qup9"; 2472 drive-strength = <2>; 2473 bias-disable; 2474 }; 2475 2476 qup_i2c10_default: qup-i2c10-default-state { 2477 pins = "gpio9", "gpio10"; 2478 function = "qup10"; 2479 drive-strength = <2>; 2480 bias-disable; 2481 }; 2482 2483 qup_spi10_default: qup-spi10-default-state { 2484 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2485 function = "qup10"; 2486 drive-strength = <6>; 2487 bias-disable; 2488 }; 2489 2490 qup_i2c11_default: qup-i2c11-default-state { 2491 pins = "gpio94", "gpio95"; 2492 function = "qup11"; 2493 drive-strength = <2>; 2494 bias-disable; 2495 }; 2496 2497 qup_spi11_default: qup-spi11-default-state { 2498 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2499 function = "qup11"; 2500 drive-strength = <6>; 2501 bias-disable; 2502 }; 2503 2504 qup_i2c12_default: qup-i2c12-default-state { 2505 pins = "gpio83", "gpio84"; 2506 function = "qup12"; 2507 drive-strength = <2>; 2508 bias-disable; 2509 }; 2510 2511 qup_spi12_default: qup-spi12-default-state { 2512 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2513 function = "qup12"; 2514 drive-strength = <6>; 2515 bias-disable; 2516 }; 2517 2518 qup_i2c13_default: qup-i2c13-default-state { 2519 pins = "gpio43", "gpio44"; 2520 function = "qup13"; 2521 drive-strength = <2>; 2522 bias-disable; 2523 }; 2524 2525 qup_spi13_default: qup-spi13-default-state { 2526 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2527 function = "qup13"; 2528 drive-strength = <6>; 2529 bias-disable; 2530 }; 2531 2532 qup_i2c14_default: qup-i2c14-default-state { 2533 pins = "gpio47", "gpio48"; 2534 function = "qup14"; 2535 drive-strength = <2>; 2536 bias-disable; 2537 }; 2538 2539 qup_spi14_default: qup-spi14-default-state { 2540 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2541 function = "qup14"; 2542 drive-strength = <6>; 2543 bias-disable; 2544 }; 2545 2546 qup_i2c15_default: qup-i2c15-default-state { 2547 pins = "gpio27", "gpio28"; 2548 function = "qup15"; 2549 drive-strength = <2>; 2550 bias-disable; 2551 }; 2552 2553 qup_spi15_default: qup-spi15-default-state { 2554 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2555 function = "qup15"; 2556 drive-strength = <6>; 2557 bias-disable; 2558 }; 2559 2560 qup_i2c16_default: qup-i2c16-default-state { 2561 pins = "gpio86", "gpio85"; 2562 function = "qup16"; 2563 drive-strength = <2>; 2564 bias-disable; 2565 }; 2566 2567 qup_spi16_default: qup-spi16-default-state { 2568 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2569 function = "qup16"; 2570 drive-strength = <6>; 2571 bias-disable; 2572 }; 2573 2574 qup_i2c17_default: qup-i2c17-default-state { 2575 pins = "gpio55", "gpio56"; 2576 function = "qup17"; 2577 drive-strength = <2>; 2578 bias-disable; 2579 }; 2580 2581 qup_spi17_default: qup-spi17-default-state { 2582 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2583 function = "qup17"; 2584 drive-strength = <6>; 2585 bias-disable; 2586 }; 2587 2588 qup_i2c18_default: qup-i2c18-default-state { 2589 pins = "gpio23", "gpio24"; 2590 function = "qup18"; 2591 drive-strength = <2>; 2592 bias-disable; 2593 }; 2594 2595 qup_spi18_default: qup-spi18-default-state { 2596 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2597 function = "qup18"; 2598 drive-strength = <6>; 2599 bias-disable; 2600 }; 2601 2602 qup_i2c19_default: qup-i2c19-default-state { 2603 pins = "gpio57", "gpio58"; 2604 function = "qup19"; 2605 drive-strength = <2>; 2606 bias-disable; 2607 }; 2608 2609 qup_spi19_default: qup-spi19-default-state { 2610 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2611 function = "qup19"; 2612 drive-strength = <6>; 2613 bias-disable; 2614 }; 2615 2616 pcie0_default_state: pcie0-default-state { 2617 perst-pins { 2618 pins = "gpio35"; 2619 function = "gpio"; 2620 drive-strength = <2>; 2621 bias-pull-down; 2622 }; 2623 2624 clkreq-pins { 2625 pins = "gpio36"; 2626 function = "pci_e0"; 2627 drive-strength = <2>; 2628 bias-pull-up; 2629 }; 2630 2631 wake-pins { 2632 pins = "gpio37"; 2633 function = "gpio"; 2634 drive-strength = <2>; 2635 bias-pull-up; 2636 }; 2637 }; 2638 2639 pcie1_default_state: pcie1-default-state { 2640 perst-pins { 2641 pins = "gpio102"; 2642 function = "gpio"; 2643 drive-strength = <2>; 2644 bias-pull-down; 2645 }; 2646 2647 clkreq-pins { 2648 pins = "gpio103"; 2649 function = "pci_e1"; 2650 drive-strength = <2>; 2651 bias-pull-up; 2652 }; 2653 2654 wake-pins { 2655 pins = "gpio104"; 2656 function = "gpio"; 2657 drive-strength = <2>; 2658 bias-pull-up; 2659 }; 2660 }; 2661 }; 2662 2663 remoteproc_mpss: remoteproc@4080000 { 2664 compatible = "qcom,sm8150-mpss-pas"; 2665 reg = <0x0 0x04080000 0x0 0x4040>; 2666 2667 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2668 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2669 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2670 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2671 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2672 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2673 interrupt-names = "wdog", "fatal", "ready", "handover", 2674 "stop-ack", "shutdown-ack"; 2675 2676 clocks = <&rpmhcc RPMH_CXO_CLK>; 2677 clock-names = "xo"; 2678 2679 power-domains = <&rpmhpd SM8150_CX>, 2680 <&rpmhpd SM8150_MSS>; 2681 power-domain-names = "cx", "mss"; 2682 2683 memory-region = <&mpss_mem>; 2684 2685 qcom,qmp = <&aoss_qmp>; 2686 2687 qcom,smem-states = <&modem_smp2p_out 0>; 2688 qcom,smem-state-names = "stop"; 2689 2690 status = "disabled"; 2691 2692 glink-edge { 2693 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2694 label = "modem"; 2695 qcom,remote-pid = <1>; 2696 mboxes = <&apss_shared 12>; 2697 }; 2698 }; 2699 2700 stm@6002000 { 2701 compatible = "arm,coresight-stm", "arm,primecell"; 2702 reg = <0 0x06002000 0 0x1000>, 2703 <0 0x16280000 0 0x180000>; 2704 reg-names = "stm-base", "stm-stimulus-base"; 2705 2706 clocks = <&aoss_qmp>; 2707 clock-names = "apb_pclk"; 2708 2709 out-ports { 2710 port { 2711 stm_out: endpoint { 2712 remote-endpoint = <&funnel0_in7>; 2713 }; 2714 }; 2715 }; 2716 }; 2717 2718 funnel@6041000 { 2719 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2720 reg = <0 0x06041000 0 0x1000>; 2721 2722 clocks = <&aoss_qmp>; 2723 clock-names = "apb_pclk"; 2724 2725 out-ports { 2726 port { 2727 funnel0_out: endpoint { 2728 remote-endpoint = <&merge_funnel_in0>; 2729 }; 2730 }; 2731 }; 2732 2733 in-ports { 2734 #address-cells = <1>; 2735 #size-cells = <0>; 2736 2737 port@7 { 2738 reg = <7>; 2739 funnel0_in7: endpoint { 2740 remote-endpoint = <&stm_out>; 2741 }; 2742 }; 2743 }; 2744 }; 2745 2746 funnel@6042000 { 2747 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2748 reg = <0 0x06042000 0 0x1000>; 2749 2750 clocks = <&aoss_qmp>; 2751 clock-names = "apb_pclk"; 2752 2753 out-ports { 2754 port { 2755 funnel1_out: endpoint { 2756 remote-endpoint = <&merge_funnel_in1>; 2757 }; 2758 }; 2759 }; 2760 2761 in-ports { 2762 #address-cells = <1>; 2763 #size-cells = <0>; 2764 2765 port@4 { 2766 reg = <4>; 2767 funnel1_in4: endpoint { 2768 remote-endpoint = <&swao_replicator_out>; 2769 }; 2770 }; 2771 }; 2772 }; 2773 2774 funnel@6043000 { 2775 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2776 reg = <0 0x06043000 0 0x1000>; 2777 2778 clocks = <&aoss_qmp>; 2779 clock-names = "apb_pclk"; 2780 2781 out-ports { 2782 port { 2783 funnel2_out: endpoint { 2784 remote-endpoint = <&merge_funnel_in2>; 2785 }; 2786 }; 2787 }; 2788 2789 in-ports { 2790 #address-cells = <1>; 2791 #size-cells = <0>; 2792 2793 port@2 { 2794 reg = <2>; 2795 funnel2_in2: endpoint { 2796 remote-endpoint = <&apss_merge_funnel_out>; 2797 }; 2798 }; 2799 }; 2800 }; 2801 2802 funnel@6045000 { 2803 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2804 reg = <0 0x06045000 0 0x1000>; 2805 2806 clocks = <&aoss_qmp>; 2807 clock-names = "apb_pclk"; 2808 2809 out-ports { 2810 port { 2811 merge_funnel_out: endpoint { 2812 remote-endpoint = <&etf_in>; 2813 }; 2814 }; 2815 }; 2816 2817 in-ports { 2818 #address-cells = <1>; 2819 #size-cells = <0>; 2820 2821 port@0 { 2822 reg = <0>; 2823 merge_funnel_in0: endpoint { 2824 remote-endpoint = <&funnel0_out>; 2825 }; 2826 }; 2827 2828 port@1 { 2829 reg = <1>; 2830 merge_funnel_in1: endpoint { 2831 remote-endpoint = <&funnel1_out>; 2832 }; 2833 }; 2834 2835 port@2 { 2836 reg = <2>; 2837 merge_funnel_in2: endpoint { 2838 remote-endpoint = <&funnel2_out>; 2839 }; 2840 }; 2841 }; 2842 }; 2843 2844 replicator@6046000 { 2845 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2846 reg = <0 0x06046000 0 0x1000>; 2847 2848 clocks = <&aoss_qmp>; 2849 clock-names = "apb_pclk"; 2850 2851 out-ports { 2852 #address-cells = <1>; 2853 #size-cells = <0>; 2854 2855 port@0 { 2856 reg = <0>; 2857 replicator_out0: endpoint { 2858 remote-endpoint = <&etr_in>; 2859 }; 2860 }; 2861 2862 port@1 { 2863 reg = <1>; 2864 replicator_out1: endpoint { 2865 remote-endpoint = <&replicator1_in>; 2866 }; 2867 }; 2868 }; 2869 2870 in-ports { 2871 port { 2872 replicator_in0: endpoint { 2873 remote-endpoint = <&etf_out>; 2874 }; 2875 }; 2876 }; 2877 }; 2878 2879 etf@6047000 { 2880 compatible = "arm,coresight-tmc", "arm,primecell"; 2881 reg = <0 0x06047000 0 0x1000>; 2882 2883 clocks = <&aoss_qmp>; 2884 clock-names = "apb_pclk"; 2885 2886 out-ports { 2887 port { 2888 etf_out: endpoint { 2889 remote-endpoint = <&replicator_in0>; 2890 }; 2891 }; 2892 }; 2893 2894 in-ports { 2895 port { 2896 etf_in: endpoint { 2897 remote-endpoint = <&merge_funnel_out>; 2898 }; 2899 }; 2900 }; 2901 }; 2902 2903 etr@6048000 { 2904 compatible = "arm,coresight-tmc", "arm,primecell"; 2905 reg = <0 0x06048000 0 0x1000>; 2906 iommus = <&apps_smmu 0x05e0 0x0>; 2907 2908 clocks = <&aoss_qmp>; 2909 clock-names = "apb_pclk"; 2910 arm,scatter-gather; 2911 2912 in-ports { 2913 port { 2914 etr_in: endpoint { 2915 remote-endpoint = <&replicator_out0>; 2916 }; 2917 }; 2918 }; 2919 }; 2920 2921 replicator@604a000 { 2922 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2923 reg = <0 0x0604a000 0 0x1000>; 2924 2925 clocks = <&aoss_qmp>; 2926 clock-names = "apb_pclk"; 2927 2928 out-ports { 2929 #address-cells = <1>; 2930 #size-cells = <0>; 2931 2932 port@1 { 2933 reg = <1>; 2934 replicator1_out: endpoint { 2935 remote-endpoint = <&swao_funnel_in>; 2936 }; 2937 }; 2938 }; 2939 2940 in-ports { 2941 #address-cells = <1>; 2942 #size-cells = <0>; 2943 2944 port@1 { 2945 reg = <1>; 2946 replicator1_in: endpoint { 2947 remote-endpoint = <&replicator_out1>; 2948 }; 2949 }; 2950 }; 2951 }; 2952 2953 funnel@6b08000 { 2954 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2955 reg = <0 0x06b08000 0 0x1000>; 2956 2957 clocks = <&aoss_qmp>; 2958 clock-names = "apb_pclk"; 2959 2960 out-ports { 2961 port { 2962 swao_funnel_out: endpoint { 2963 remote-endpoint = <&swao_etf_in>; 2964 }; 2965 }; 2966 }; 2967 2968 in-ports { 2969 #address-cells = <1>; 2970 #size-cells = <0>; 2971 2972 port@6 { 2973 reg = <6>; 2974 swao_funnel_in: endpoint { 2975 remote-endpoint = <&replicator1_out>; 2976 }; 2977 }; 2978 }; 2979 }; 2980 2981 etf@6b09000 { 2982 compatible = "arm,coresight-tmc", "arm,primecell"; 2983 reg = <0 0x06b09000 0 0x1000>; 2984 2985 clocks = <&aoss_qmp>; 2986 clock-names = "apb_pclk"; 2987 2988 out-ports { 2989 port { 2990 swao_etf_out: endpoint { 2991 remote-endpoint = <&swao_replicator_in>; 2992 }; 2993 }; 2994 }; 2995 2996 in-ports { 2997 port { 2998 swao_etf_in: endpoint { 2999 remote-endpoint = <&swao_funnel_out>; 3000 }; 3001 }; 3002 }; 3003 }; 3004 3005 replicator@6b0a000 { 3006 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3007 reg = <0 0x06b0a000 0 0x1000>; 3008 3009 clocks = <&aoss_qmp>; 3010 clock-names = "apb_pclk"; 3011 qcom,replicator-loses-context; 3012 3013 out-ports { 3014 port { 3015 swao_replicator_out: endpoint { 3016 remote-endpoint = <&funnel1_in4>; 3017 }; 3018 }; 3019 }; 3020 3021 in-ports { 3022 port { 3023 swao_replicator_in: endpoint { 3024 remote-endpoint = <&swao_etf_out>; 3025 }; 3026 }; 3027 }; 3028 }; 3029 3030 etm@7040000 { 3031 compatible = "arm,coresight-etm4x", "arm,primecell"; 3032 reg = <0 0x07040000 0 0x1000>; 3033 3034 cpu = <&CPU0>; 3035 3036 clocks = <&aoss_qmp>; 3037 clock-names = "apb_pclk"; 3038 arm,coresight-loses-context-with-cpu; 3039 qcom,skip-power-up; 3040 3041 out-ports { 3042 port { 3043 etm0_out: endpoint { 3044 remote-endpoint = <&apss_funnel_in0>; 3045 }; 3046 }; 3047 }; 3048 }; 3049 3050 etm@7140000 { 3051 compatible = "arm,coresight-etm4x", "arm,primecell"; 3052 reg = <0 0x07140000 0 0x1000>; 3053 3054 cpu = <&CPU1>; 3055 3056 clocks = <&aoss_qmp>; 3057 clock-names = "apb_pclk"; 3058 arm,coresight-loses-context-with-cpu; 3059 qcom,skip-power-up; 3060 3061 out-ports { 3062 port { 3063 etm1_out: endpoint { 3064 remote-endpoint = <&apss_funnel_in1>; 3065 }; 3066 }; 3067 }; 3068 }; 3069 3070 etm@7240000 { 3071 compatible = "arm,coresight-etm4x", "arm,primecell"; 3072 reg = <0 0x07240000 0 0x1000>; 3073 3074 cpu = <&CPU2>; 3075 3076 clocks = <&aoss_qmp>; 3077 clock-names = "apb_pclk"; 3078 arm,coresight-loses-context-with-cpu; 3079 qcom,skip-power-up; 3080 3081 out-ports { 3082 port { 3083 etm2_out: endpoint { 3084 remote-endpoint = <&apss_funnel_in2>; 3085 }; 3086 }; 3087 }; 3088 }; 3089 3090 etm@7340000 { 3091 compatible = "arm,coresight-etm4x", "arm,primecell"; 3092 reg = <0 0x07340000 0 0x1000>; 3093 3094 cpu = <&CPU3>; 3095 3096 clocks = <&aoss_qmp>; 3097 clock-names = "apb_pclk"; 3098 arm,coresight-loses-context-with-cpu; 3099 qcom,skip-power-up; 3100 3101 out-ports { 3102 port { 3103 etm3_out: endpoint { 3104 remote-endpoint = <&apss_funnel_in3>; 3105 }; 3106 }; 3107 }; 3108 }; 3109 3110 etm@7440000 { 3111 compatible = "arm,coresight-etm4x", "arm,primecell"; 3112 reg = <0 0x07440000 0 0x1000>; 3113 3114 cpu = <&CPU4>; 3115 3116 clocks = <&aoss_qmp>; 3117 clock-names = "apb_pclk"; 3118 arm,coresight-loses-context-with-cpu; 3119 qcom,skip-power-up; 3120 3121 out-ports { 3122 port { 3123 etm4_out: endpoint { 3124 remote-endpoint = <&apss_funnel_in4>; 3125 }; 3126 }; 3127 }; 3128 }; 3129 3130 etm@7540000 { 3131 compatible = "arm,coresight-etm4x", "arm,primecell"; 3132 reg = <0 0x07540000 0 0x1000>; 3133 3134 cpu = <&CPU5>; 3135 3136 clocks = <&aoss_qmp>; 3137 clock-names = "apb_pclk"; 3138 arm,coresight-loses-context-with-cpu; 3139 qcom,skip-power-up; 3140 3141 out-ports { 3142 port { 3143 etm5_out: endpoint { 3144 remote-endpoint = <&apss_funnel_in5>; 3145 }; 3146 }; 3147 }; 3148 }; 3149 3150 etm@7640000 { 3151 compatible = "arm,coresight-etm4x", "arm,primecell"; 3152 reg = <0 0x07640000 0 0x1000>; 3153 3154 cpu = <&CPU6>; 3155 3156 clocks = <&aoss_qmp>; 3157 clock-names = "apb_pclk"; 3158 arm,coresight-loses-context-with-cpu; 3159 qcom,skip-power-up; 3160 3161 out-ports { 3162 port { 3163 etm6_out: endpoint { 3164 remote-endpoint = <&apss_funnel_in6>; 3165 }; 3166 }; 3167 }; 3168 }; 3169 3170 etm@7740000 { 3171 compatible = "arm,coresight-etm4x", "arm,primecell"; 3172 reg = <0 0x07740000 0 0x1000>; 3173 3174 cpu = <&CPU7>; 3175 3176 clocks = <&aoss_qmp>; 3177 clock-names = "apb_pclk"; 3178 arm,coresight-loses-context-with-cpu; 3179 qcom,skip-power-up; 3180 3181 out-ports { 3182 port { 3183 etm7_out: endpoint { 3184 remote-endpoint = <&apss_funnel_in7>; 3185 }; 3186 }; 3187 }; 3188 }; 3189 3190 funnel@7800000 { /* APSS Funnel */ 3191 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3192 reg = <0 0x07800000 0 0x1000>; 3193 3194 clocks = <&aoss_qmp>; 3195 clock-names = "apb_pclk"; 3196 3197 out-ports { 3198 port { 3199 apss_funnel_out: endpoint { 3200 remote-endpoint = <&apss_merge_funnel_in>; 3201 }; 3202 }; 3203 }; 3204 3205 in-ports { 3206 #address-cells = <1>; 3207 #size-cells = <0>; 3208 3209 port@0 { 3210 reg = <0>; 3211 apss_funnel_in0: endpoint { 3212 remote-endpoint = <&etm0_out>; 3213 }; 3214 }; 3215 3216 port@1 { 3217 reg = <1>; 3218 apss_funnel_in1: endpoint { 3219 remote-endpoint = <&etm1_out>; 3220 }; 3221 }; 3222 3223 port@2 { 3224 reg = <2>; 3225 apss_funnel_in2: endpoint { 3226 remote-endpoint = <&etm2_out>; 3227 }; 3228 }; 3229 3230 port@3 { 3231 reg = <3>; 3232 apss_funnel_in3: endpoint { 3233 remote-endpoint = <&etm3_out>; 3234 }; 3235 }; 3236 3237 port@4 { 3238 reg = <4>; 3239 apss_funnel_in4: endpoint { 3240 remote-endpoint = <&etm4_out>; 3241 }; 3242 }; 3243 3244 port@5 { 3245 reg = <5>; 3246 apss_funnel_in5: endpoint { 3247 remote-endpoint = <&etm5_out>; 3248 }; 3249 }; 3250 3251 port@6 { 3252 reg = <6>; 3253 apss_funnel_in6: endpoint { 3254 remote-endpoint = <&etm6_out>; 3255 }; 3256 }; 3257 3258 port@7 { 3259 reg = <7>; 3260 apss_funnel_in7: endpoint { 3261 remote-endpoint = <&etm7_out>; 3262 }; 3263 }; 3264 }; 3265 }; 3266 3267 funnel@7810000 { 3268 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3269 reg = <0 0x07810000 0 0x1000>; 3270 3271 clocks = <&aoss_qmp>; 3272 clock-names = "apb_pclk"; 3273 3274 out-ports { 3275 port { 3276 apss_merge_funnel_out: endpoint { 3277 remote-endpoint = <&funnel2_in2>; 3278 }; 3279 }; 3280 }; 3281 3282 in-ports { 3283 port { 3284 apss_merge_funnel_in: endpoint { 3285 remote-endpoint = <&apss_funnel_out>; 3286 }; 3287 }; 3288 }; 3289 }; 3290 3291 remoteproc_cdsp: remoteproc@8300000 { 3292 compatible = "qcom,sm8150-cdsp-pas"; 3293 reg = <0x0 0x08300000 0x0 0x4040>; 3294 3295 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3296 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3297 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3298 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3299 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3300 interrupt-names = "wdog", "fatal", "ready", 3301 "handover", "stop-ack"; 3302 3303 clocks = <&rpmhcc RPMH_CXO_CLK>; 3304 clock-names = "xo"; 3305 3306 power-domains = <&rpmhpd SM8150_CX>; 3307 3308 memory-region = <&cdsp_mem>; 3309 3310 qcom,qmp = <&aoss_qmp>; 3311 3312 qcom,smem-states = <&cdsp_smp2p_out 0>; 3313 qcom,smem-state-names = "stop"; 3314 3315 status = "disabled"; 3316 3317 glink-edge { 3318 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3319 label = "cdsp"; 3320 qcom,remote-pid = <5>; 3321 mboxes = <&apss_shared 4>; 3322 3323 fastrpc { 3324 compatible = "qcom,fastrpc"; 3325 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3326 label = "cdsp"; 3327 qcom,non-secure-domain; 3328 #address-cells = <1>; 3329 #size-cells = <0>; 3330 3331 compute-cb@1 { 3332 compatible = "qcom,fastrpc-compute-cb"; 3333 reg = <1>; 3334 iommus = <&apps_smmu 0x1001 0x0460>; 3335 }; 3336 3337 compute-cb@2 { 3338 compatible = "qcom,fastrpc-compute-cb"; 3339 reg = <2>; 3340 iommus = <&apps_smmu 0x1002 0x0460>; 3341 }; 3342 3343 compute-cb@3 { 3344 compatible = "qcom,fastrpc-compute-cb"; 3345 reg = <3>; 3346 iommus = <&apps_smmu 0x1003 0x0460>; 3347 }; 3348 3349 compute-cb@4 { 3350 compatible = "qcom,fastrpc-compute-cb"; 3351 reg = <4>; 3352 iommus = <&apps_smmu 0x1004 0x0460>; 3353 }; 3354 3355 compute-cb@5 { 3356 compatible = "qcom,fastrpc-compute-cb"; 3357 reg = <5>; 3358 iommus = <&apps_smmu 0x1005 0x0460>; 3359 }; 3360 3361 compute-cb@6 { 3362 compatible = "qcom,fastrpc-compute-cb"; 3363 reg = <6>; 3364 iommus = <&apps_smmu 0x1006 0x0460>; 3365 }; 3366 3367 compute-cb@7 { 3368 compatible = "qcom,fastrpc-compute-cb"; 3369 reg = <7>; 3370 iommus = <&apps_smmu 0x1007 0x0460>; 3371 }; 3372 3373 compute-cb@8 { 3374 compatible = "qcom,fastrpc-compute-cb"; 3375 reg = <8>; 3376 iommus = <&apps_smmu 0x1008 0x0460>; 3377 }; 3378 3379 /* note: secure cb9 in downstream */ 3380 }; 3381 }; 3382 }; 3383 3384 usb_1_hsphy: phy@88e2000 { 3385 compatible = "qcom,sm8150-usb-hs-phy", 3386 "qcom,usb-snps-hs-7nm-phy"; 3387 reg = <0 0x088e2000 0 0x400>; 3388 status = "disabled"; 3389 #phy-cells = <0>; 3390 3391 clocks = <&rpmhcc RPMH_CXO_CLK>; 3392 clock-names = "ref"; 3393 3394 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3395 }; 3396 3397 usb_2_hsphy: phy@88e3000 { 3398 compatible = "qcom,sm8150-usb-hs-phy", 3399 "qcom,usb-snps-hs-7nm-phy"; 3400 reg = <0 0x088e3000 0 0x400>; 3401 status = "disabled"; 3402 #phy-cells = <0>; 3403 3404 clocks = <&rpmhcc RPMH_CXO_CLK>; 3405 clock-names = "ref"; 3406 3407 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3408 }; 3409 3410 usb_1_qmpphy: phy@88e9000 { 3411 compatible = "qcom,sm8150-qmp-usb3-phy"; 3412 reg = <0 0x088e9000 0 0x18c>, 3413 <0 0x088e8000 0 0x10>; 3414 status = "disabled"; 3415 #address-cells = <2>; 3416 #size-cells = <2>; 3417 ranges; 3418 3419 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3420 <&rpmhcc RPMH_CXO_CLK>, 3421 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3422 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3423 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3424 3425 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3426 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3427 reset-names = "phy", "common"; 3428 3429 usb_1_ssphy: phy@88e9200 { 3430 reg = <0 0x088e9200 0 0x200>, 3431 <0 0x088e9400 0 0x200>, 3432 <0 0x088e9c00 0 0x218>, 3433 <0 0x088e9600 0 0x200>, 3434 <0 0x088e9800 0 0x200>, 3435 <0 0x088e9a00 0 0x100>; 3436 #clock-cells = <0>; 3437 #phy-cells = <0>; 3438 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3439 clock-names = "pipe0"; 3440 clock-output-names = "usb3_phy_pipe_clk_src"; 3441 }; 3442 }; 3443 3444 usb_2_qmpphy: phy@88eb000 { 3445 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3446 reg = <0 0x088eb000 0 0x200>; 3447 status = "disabled"; 3448 #address-cells = <2>; 3449 #size-cells = <2>; 3450 ranges; 3451 3452 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3453 <&rpmhcc RPMH_CXO_CLK>, 3454 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3455 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3456 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3457 3458 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3459 <&gcc GCC_USB3_PHY_SEC_BCR>; 3460 reset-names = "phy", "common"; 3461 3462 usb_2_ssphy: phy@88eb200 { 3463 reg = <0 0x088eb200 0 0x200>, 3464 <0 0x088eb400 0 0x200>, 3465 <0 0x088eb800 0 0x800>, 3466 <0 0x088eb600 0 0x200>; 3467 #clock-cells = <0>; 3468 #phy-cells = <0>; 3469 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3470 clock-names = "pipe0"; 3471 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3472 }; 3473 }; 3474 3475 sdhc_2: mmc@8804000 { 3476 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3477 reg = <0 0x08804000 0 0x1000>; 3478 3479 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3481 interrupt-names = "hc_irq", "pwr_irq"; 3482 3483 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3484 <&gcc GCC_SDCC2_APPS_CLK>, 3485 <&rpmhcc RPMH_CXO_CLK>; 3486 clock-names = "iface", "core", "xo"; 3487 iommus = <&apps_smmu 0x6a0 0x0>; 3488 qcom,dll-config = <0x0007642c>; 3489 qcom,ddr-config = <0x80040868>; 3490 power-domains = <&rpmhpd 0>; 3491 operating-points-v2 = <&sdhc2_opp_table>; 3492 3493 status = "disabled"; 3494 3495 sdhc2_opp_table: opp-table { 3496 compatible = "operating-points-v2"; 3497 3498 opp-19200000 { 3499 opp-hz = /bits/ 64 <19200000>; 3500 required-opps = <&rpmhpd_opp_min_svs>; 3501 }; 3502 3503 opp-50000000 { 3504 opp-hz = /bits/ 64 <50000000>; 3505 required-opps = <&rpmhpd_opp_low_svs>; 3506 }; 3507 3508 opp-100000000 { 3509 opp-hz = /bits/ 64 <100000000>; 3510 required-opps = <&rpmhpd_opp_svs>; 3511 }; 3512 3513 opp-202000000 { 3514 opp-hz = /bits/ 64 <202000000>; 3515 required-opps = <&rpmhpd_opp_svs_l1>; 3516 }; 3517 }; 3518 }; 3519 3520 dc_noc: interconnect@9160000 { 3521 compatible = "qcom,sm8150-dc-noc"; 3522 reg = <0 0x09160000 0 0x3200>; 3523 #interconnect-cells = <1>; 3524 qcom,bcm-voters = <&apps_bcm_voter>; 3525 }; 3526 3527 gem_noc: interconnect@9680000 { 3528 compatible = "qcom,sm8150-gem-noc"; 3529 reg = <0 0x09680000 0 0x3e200>; 3530 #interconnect-cells = <1>; 3531 qcom,bcm-voters = <&apps_bcm_voter>; 3532 }; 3533 3534 usb_1: usb@a6f8800 { 3535 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3536 reg = <0 0x0a6f8800 0 0x400>; 3537 status = "disabled"; 3538 #address-cells = <2>; 3539 #size-cells = <2>; 3540 ranges; 3541 dma-ranges; 3542 3543 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3544 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3545 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3546 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3547 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3548 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3549 clock-names = "cfg_noc", 3550 "core", 3551 "iface", 3552 "sleep", 3553 "mock_utmi", 3554 "xo"; 3555 3556 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3557 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3558 assigned-clock-rates = <19200000>, <200000000>; 3559 3560 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3561 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3564 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3565 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3566 3567 power-domains = <&gcc USB30_PRIM_GDSC>; 3568 3569 resets = <&gcc GCC_USB30_PRIM_BCR>; 3570 3571 usb_1_dwc3: usb@a600000 { 3572 compatible = "snps,dwc3"; 3573 reg = <0 0x0a600000 0 0xcd00>; 3574 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3575 iommus = <&apps_smmu 0x140 0>; 3576 snps,dis_u2_susphy_quirk; 3577 snps,dis_enblslpm_quirk; 3578 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3579 phy-names = "usb2-phy", "usb3-phy"; 3580 }; 3581 }; 3582 3583 usb_2: usb@a8f8800 { 3584 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3585 reg = <0 0x0a8f8800 0 0x400>; 3586 status = "disabled"; 3587 #address-cells = <2>; 3588 #size-cells = <2>; 3589 ranges; 3590 dma-ranges; 3591 3592 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3593 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3594 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3595 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3596 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3597 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3598 clock-names = "cfg_noc", 3599 "core", 3600 "iface", 3601 "sleep", 3602 "mock_utmi", 3603 "xo"; 3604 3605 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3606 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3607 assigned-clock-rates = <19200000>, <200000000>; 3608 3609 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3613 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3614 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3615 3616 power-domains = <&gcc USB30_SEC_GDSC>; 3617 3618 resets = <&gcc GCC_USB30_SEC_BCR>; 3619 3620 usb_2_dwc3: usb@a800000 { 3621 compatible = "snps,dwc3"; 3622 reg = <0 0x0a800000 0 0xcd00>; 3623 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3624 iommus = <&apps_smmu 0x160 0>; 3625 snps,dis_u2_susphy_quirk; 3626 snps,dis_enblslpm_quirk; 3627 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3628 phy-names = "usb2-phy", "usb3-phy"; 3629 }; 3630 }; 3631 3632 camnoc_virt: interconnect@ac00000 { 3633 compatible = "qcom,sm8150-camnoc-virt"; 3634 reg = <0 0x0ac00000 0 0x1000>; 3635 #interconnect-cells = <1>; 3636 qcom,bcm-voters = <&apps_bcm_voter>; 3637 }; 3638 3639 mdss: display-subsystem@ae00000 { 3640 compatible = "qcom,sm8150-mdss"; 3641 reg = <0 0x0ae00000 0 0x1000>; 3642 reg-names = "mdss"; 3643 3644 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3645 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3646 interconnect-names = "mdp0-mem", "mdp1-mem"; 3647 3648 power-domains = <&dispcc MDSS_GDSC>; 3649 3650 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3651 <&gcc GCC_DISP_HF_AXI_CLK>, 3652 <&gcc GCC_DISP_SF_AXI_CLK>, 3653 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3654 clock-names = "iface", "bus", "nrt_bus", "core"; 3655 3656 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3657 interrupt-controller; 3658 #interrupt-cells = <1>; 3659 3660 iommus = <&apps_smmu 0x800 0x420>; 3661 3662 status = "disabled"; 3663 3664 #address-cells = <2>; 3665 #size-cells = <2>; 3666 ranges; 3667 3668 mdss_mdp: display-controller@ae01000 { 3669 compatible = "qcom,sm8150-dpu"; 3670 reg = <0 0x0ae01000 0 0x8f000>, 3671 <0 0x0aeb0000 0 0x2008>; 3672 reg-names = "mdp", "vbif"; 3673 3674 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3675 <&gcc GCC_DISP_HF_AXI_CLK>, 3676 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3677 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3678 clock-names = "iface", "bus", "core", "vsync"; 3679 3680 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3681 assigned-clock-rates = <19200000>; 3682 3683 operating-points-v2 = <&mdp_opp_table>; 3684 power-domains = <&rpmhpd SM8150_MMCX>; 3685 3686 interrupt-parent = <&mdss>; 3687 interrupts = <0>; 3688 3689 ports { 3690 #address-cells = <1>; 3691 #size-cells = <0>; 3692 3693 port@0 { 3694 reg = <0>; 3695 dpu_intf1_out: endpoint { 3696 remote-endpoint = <&mdss_dsi0_in>; 3697 }; 3698 }; 3699 3700 port@1 { 3701 reg = <1>; 3702 dpu_intf2_out: endpoint { 3703 remote-endpoint = <&mdss_dsi1_in>; 3704 }; 3705 }; 3706 }; 3707 3708 mdp_opp_table: opp-table { 3709 compatible = "operating-points-v2"; 3710 3711 opp-171428571 { 3712 opp-hz = /bits/ 64 <171428571>; 3713 required-opps = <&rpmhpd_opp_low_svs>; 3714 }; 3715 3716 opp-300000000 { 3717 opp-hz = /bits/ 64 <300000000>; 3718 required-opps = <&rpmhpd_opp_svs>; 3719 }; 3720 3721 opp-345000000 { 3722 opp-hz = /bits/ 64 <345000000>; 3723 required-opps = <&rpmhpd_opp_svs_l1>; 3724 }; 3725 3726 opp-460000000 { 3727 opp-hz = /bits/ 64 <460000000>; 3728 required-opps = <&rpmhpd_opp_nom>; 3729 }; 3730 }; 3731 }; 3732 3733 mdss_dsi0: dsi@ae94000 { 3734 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3735 reg = <0 0x0ae94000 0 0x400>; 3736 reg-names = "dsi_ctrl"; 3737 3738 interrupt-parent = <&mdss>; 3739 interrupts = <4>; 3740 3741 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3742 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3743 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3744 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3745 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3746 <&gcc GCC_DISP_HF_AXI_CLK>; 3747 clock-names = "byte", 3748 "byte_intf", 3749 "pixel", 3750 "core", 3751 "iface", 3752 "bus"; 3753 3754 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3755 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3756 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3757 <&mdss_dsi0_phy 1>; 3758 3759 operating-points-v2 = <&dsi_opp_table>; 3760 power-domains = <&rpmhpd SM8150_MMCX>; 3761 3762 phys = <&mdss_dsi0_phy>; 3763 3764 status = "disabled"; 3765 3766 #address-cells = <1>; 3767 #size-cells = <0>; 3768 3769 ports { 3770 #address-cells = <1>; 3771 #size-cells = <0>; 3772 3773 port@0 { 3774 reg = <0>; 3775 mdss_dsi0_in: endpoint { 3776 remote-endpoint = <&dpu_intf1_out>; 3777 }; 3778 }; 3779 3780 port@1 { 3781 reg = <1>; 3782 mdss_dsi0_out: endpoint { 3783 }; 3784 }; 3785 }; 3786 3787 dsi_opp_table: opp-table { 3788 compatible = "operating-points-v2"; 3789 3790 opp-187500000 { 3791 opp-hz = /bits/ 64 <187500000>; 3792 required-opps = <&rpmhpd_opp_low_svs>; 3793 }; 3794 3795 opp-300000000 { 3796 opp-hz = /bits/ 64 <300000000>; 3797 required-opps = <&rpmhpd_opp_svs>; 3798 }; 3799 3800 opp-358000000 { 3801 opp-hz = /bits/ 64 <358000000>; 3802 required-opps = <&rpmhpd_opp_svs_l1>; 3803 }; 3804 }; 3805 }; 3806 3807 mdss_dsi0_phy: phy@ae94400 { 3808 compatible = "qcom,dsi-phy-7nm"; 3809 reg = <0 0x0ae94400 0 0x200>, 3810 <0 0x0ae94600 0 0x280>, 3811 <0 0x0ae94900 0 0x260>; 3812 reg-names = "dsi_phy", 3813 "dsi_phy_lane", 3814 "dsi_pll"; 3815 3816 #clock-cells = <1>; 3817 #phy-cells = <0>; 3818 3819 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3820 <&rpmhcc RPMH_CXO_CLK>; 3821 clock-names = "iface", "ref"; 3822 3823 status = "disabled"; 3824 }; 3825 3826 mdss_dsi1: dsi@ae96000 { 3827 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3828 reg = <0 0x0ae96000 0 0x400>; 3829 reg-names = "dsi_ctrl"; 3830 3831 interrupt-parent = <&mdss>; 3832 interrupts = <5>; 3833 3834 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3835 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3836 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3837 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3838 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3839 <&gcc GCC_DISP_HF_AXI_CLK>; 3840 clock-names = "byte", 3841 "byte_intf", 3842 "pixel", 3843 "core", 3844 "iface", 3845 "bus"; 3846 3847 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3848 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3849 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3850 <&mdss_dsi1_phy 1>; 3851 3852 operating-points-v2 = <&dsi_opp_table>; 3853 power-domains = <&rpmhpd SM8150_MMCX>; 3854 3855 phys = <&mdss_dsi1_phy>; 3856 3857 status = "disabled"; 3858 3859 #address-cells = <1>; 3860 #size-cells = <0>; 3861 3862 ports { 3863 #address-cells = <1>; 3864 #size-cells = <0>; 3865 3866 port@0 { 3867 reg = <0>; 3868 mdss_dsi1_in: endpoint { 3869 remote-endpoint = <&dpu_intf2_out>; 3870 }; 3871 }; 3872 3873 port@1 { 3874 reg = <1>; 3875 mdss_dsi1_out: endpoint { 3876 }; 3877 }; 3878 }; 3879 }; 3880 3881 mdss_dsi1_phy: phy@ae96400 { 3882 compatible = "qcom,dsi-phy-7nm"; 3883 reg = <0 0x0ae96400 0 0x200>, 3884 <0 0x0ae96600 0 0x280>, 3885 <0 0x0ae96900 0 0x260>; 3886 reg-names = "dsi_phy", 3887 "dsi_phy_lane", 3888 "dsi_pll"; 3889 3890 #clock-cells = <1>; 3891 #phy-cells = <0>; 3892 3893 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3894 <&rpmhcc RPMH_CXO_CLK>; 3895 clock-names = "iface", "ref"; 3896 3897 status = "disabled"; 3898 }; 3899 }; 3900 3901 dispcc: clock-controller@af00000 { 3902 compatible = "qcom,sm8150-dispcc"; 3903 reg = <0 0x0af00000 0 0x10000>; 3904 clocks = <&rpmhcc RPMH_CXO_CLK>, 3905 <&mdss_dsi0_phy 0>, 3906 <&mdss_dsi0_phy 1>, 3907 <&mdss_dsi1_phy 0>, 3908 <&mdss_dsi1_phy 1>, 3909 <0>, 3910 <0>; 3911 clock-names = "bi_tcxo", 3912 "dsi0_phy_pll_out_byteclk", 3913 "dsi0_phy_pll_out_dsiclk", 3914 "dsi1_phy_pll_out_byteclk", 3915 "dsi1_phy_pll_out_dsiclk", 3916 "dp_phy_pll_link_clk", 3917 "dp_phy_pll_vco_div_clk"; 3918 power-domains = <&rpmhpd SM8150_MMCX>; 3919 #clock-cells = <1>; 3920 #reset-cells = <1>; 3921 #power-domain-cells = <1>; 3922 }; 3923 3924 pdc: interrupt-controller@b220000 { 3925 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3926 reg = <0 0x0b220000 0 0x400>; 3927 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3928 <125 63 1>; 3929 #interrupt-cells = <2>; 3930 interrupt-parent = <&intc>; 3931 interrupt-controller; 3932 }; 3933 3934 aoss_qmp: power-management@c300000 { 3935 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 3936 reg = <0x0 0x0c300000 0x0 0x400>; 3937 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3938 mboxes = <&apss_shared 0>; 3939 3940 #clock-cells = <0>; 3941 }; 3942 3943 sram@c3f0000 { 3944 compatible = "qcom,rpmh-stats"; 3945 reg = <0 0x0c3f0000 0 0x400>; 3946 }; 3947 3948 tsens0: thermal-sensor@c263000 { 3949 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3950 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3951 <0 0x0c222000 0 0x1ff>; /* SROT */ 3952 #qcom,sensors = <16>; 3953 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3955 interrupt-names = "uplow", "critical"; 3956 #thermal-sensor-cells = <1>; 3957 }; 3958 3959 tsens1: thermal-sensor@c265000 { 3960 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3961 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3962 <0 0x0c223000 0 0x1ff>; /* SROT */ 3963 #qcom,sensors = <8>; 3964 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3966 interrupt-names = "uplow", "critical"; 3967 #thermal-sensor-cells = <1>; 3968 }; 3969 3970 spmi_bus: spmi@c440000 { 3971 compatible = "qcom,spmi-pmic-arb"; 3972 reg = <0x0 0x0c440000 0x0 0x0001100>, 3973 <0x0 0x0c600000 0x0 0x2000000>, 3974 <0x0 0x0e600000 0x0 0x0100000>, 3975 <0x0 0x0e700000 0x0 0x00a0000>, 3976 <0x0 0x0c40a000 0x0 0x0026000>; 3977 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3978 interrupt-names = "periph_irq"; 3979 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3980 qcom,ee = <0>; 3981 qcom,channel = <0>; 3982 #address-cells = <2>; 3983 #size-cells = <0>; 3984 interrupt-controller; 3985 #interrupt-cells = <4>; 3986 }; 3987 3988 apps_smmu: iommu@15000000 { 3989 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 3990 reg = <0 0x15000000 0 0x100000>; 3991 #iommu-cells = <2>; 3992 #global-interrupts = <1>; 3993 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3994 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3995 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3996 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3997 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3998 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3999 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4000 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4001 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4002 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4003 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4004 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4005 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4007 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4008 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4009 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4010 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4011 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4027 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4028 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4031 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4032 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4033 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4034 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4035 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4037 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4038 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4039 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4074 }; 4075 4076 remoteproc_adsp: remoteproc@17300000 { 4077 compatible = "qcom,sm8150-adsp-pas"; 4078 reg = <0x0 0x17300000 0x0 0x4040>; 4079 4080 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4081 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4082 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4083 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4084 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4085 interrupt-names = "wdog", "fatal", "ready", 4086 "handover", "stop-ack"; 4087 4088 clocks = <&rpmhcc RPMH_CXO_CLK>; 4089 clock-names = "xo"; 4090 4091 power-domains = <&rpmhpd SM8150_CX>; 4092 4093 memory-region = <&adsp_mem>; 4094 4095 qcom,qmp = <&aoss_qmp>; 4096 4097 qcom,smem-states = <&adsp_smp2p_out 0>; 4098 qcom,smem-state-names = "stop"; 4099 4100 status = "disabled"; 4101 4102 glink-edge { 4103 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4104 label = "lpass"; 4105 qcom,remote-pid = <2>; 4106 mboxes = <&apss_shared 8>; 4107 4108 fastrpc { 4109 compatible = "qcom,fastrpc"; 4110 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4111 label = "adsp"; 4112 qcom,non-secure-domain; 4113 #address-cells = <1>; 4114 #size-cells = <0>; 4115 4116 compute-cb@3 { 4117 compatible = "qcom,fastrpc-compute-cb"; 4118 reg = <3>; 4119 iommus = <&apps_smmu 0x1b23 0x0>; 4120 }; 4121 4122 compute-cb@4 { 4123 compatible = "qcom,fastrpc-compute-cb"; 4124 reg = <4>; 4125 iommus = <&apps_smmu 0x1b24 0x0>; 4126 }; 4127 4128 compute-cb@5 { 4129 compatible = "qcom,fastrpc-compute-cb"; 4130 reg = <5>; 4131 iommus = <&apps_smmu 0x1b25 0x0>; 4132 }; 4133 }; 4134 }; 4135 }; 4136 4137 intc: interrupt-controller@17a00000 { 4138 compatible = "arm,gic-v3"; 4139 interrupt-controller; 4140 #interrupt-cells = <3>; 4141 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4142 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4143 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4144 }; 4145 4146 apss_shared: mailbox@17c00000 { 4147 compatible = "qcom,sm8150-apss-shared", 4148 "qcom,sdm845-apss-shared"; 4149 reg = <0x0 0x17c00000 0x0 0x1000>; 4150 #mbox-cells = <1>; 4151 }; 4152 4153 watchdog@17c10000 { 4154 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4155 reg = <0 0x17c10000 0 0x1000>; 4156 clocks = <&sleep_clk>; 4157 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4158 }; 4159 4160 timer@17c20000 { 4161 #address-cells = <1>; 4162 #size-cells = <1>; 4163 ranges = <0 0 0 0x20000000>; 4164 compatible = "arm,armv7-timer-mem"; 4165 reg = <0x0 0x17c20000 0x0 0x1000>; 4166 clock-frequency = <19200000>; 4167 4168 frame@17c21000 { 4169 frame-number = <0>; 4170 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4172 reg = <0x17c21000 0x1000>, 4173 <0x17c22000 0x1000>; 4174 }; 4175 4176 frame@17c23000 { 4177 frame-number = <1>; 4178 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4179 reg = <0x17c23000 0x1000>; 4180 status = "disabled"; 4181 }; 4182 4183 frame@17c25000 { 4184 frame-number = <2>; 4185 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4186 reg = <0x17c25000 0x1000>; 4187 status = "disabled"; 4188 }; 4189 4190 frame@17c27000 { 4191 frame-number = <3>; 4192 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4193 reg = <0x17c26000 0x1000>; 4194 status = "disabled"; 4195 }; 4196 4197 frame@17c29000 { 4198 frame-number = <4>; 4199 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4200 reg = <0x17c29000 0x1000>; 4201 status = "disabled"; 4202 }; 4203 4204 frame@17c2b000 { 4205 frame-number = <5>; 4206 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4207 reg = <0x17c2b000 0x1000>; 4208 status = "disabled"; 4209 }; 4210 4211 frame@17c2d000 { 4212 frame-number = <6>; 4213 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4214 reg = <0x17c2d000 0x1000>; 4215 status = "disabled"; 4216 }; 4217 }; 4218 4219 apps_rsc: rsc@18200000 { 4220 label = "apps_rsc"; 4221 compatible = "qcom,rpmh-rsc"; 4222 reg = <0x0 0x18200000 0x0 0x10000>, 4223 <0x0 0x18210000 0x0 0x10000>, 4224 <0x0 0x18220000 0x0 0x10000>; 4225 reg-names = "drv-0", "drv-1", "drv-2"; 4226 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4229 qcom,tcs-offset = <0xd00>; 4230 qcom,drv-id = <2>; 4231 qcom,tcs-config = <ACTIVE_TCS 2>, 4232 <SLEEP_TCS 3>, 4233 <WAKE_TCS 3>, 4234 <CONTROL_TCS 1>; 4235 power-domains = <&CLUSTER_PD>; 4236 4237 rpmhcc: clock-controller { 4238 compatible = "qcom,sm8150-rpmh-clk"; 4239 #clock-cells = <1>; 4240 clock-names = "xo"; 4241 clocks = <&xo_board>; 4242 }; 4243 4244 rpmhpd: power-controller { 4245 compatible = "qcom,sm8150-rpmhpd"; 4246 #power-domain-cells = <1>; 4247 operating-points-v2 = <&rpmhpd_opp_table>; 4248 4249 rpmhpd_opp_table: opp-table { 4250 compatible = "operating-points-v2"; 4251 4252 rpmhpd_opp_ret: opp1 { 4253 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4254 }; 4255 4256 rpmhpd_opp_min_svs: opp2 { 4257 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4258 }; 4259 4260 rpmhpd_opp_low_svs: opp3 { 4261 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4262 }; 4263 4264 rpmhpd_opp_svs: opp4 { 4265 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4266 }; 4267 4268 rpmhpd_opp_svs_l1: opp5 { 4269 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4270 }; 4271 4272 rpmhpd_opp_svs_l2: opp6 { 4273 opp-level = <224>; 4274 }; 4275 4276 rpmhpd_opp_nom: opp7 { 4277 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4278 }; 4279 4280 rpmhpd_opp_nom_l1: opp8 { 4281 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4282 }; 4283 4284 rpmhpd_opp_nom_l2: opp9 { 4285 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4286 }; 4287 4288 rpmhpd_opp_turbo: opp10 { 4289 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4290 }; 4291 4292 rpmhpd_opp_turbo_l1: opp11 { 4293 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4294 }; 4295 }; 4296 }; 4297 4298 apps_bcm_voter: bcm-voter { 4299 compatible = "qcom,bcm-voter"; 4300 }; 4301 }; 4302 4303 osm_l3: interconnect@18321000 { 4304 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4305 reg = <0 0x18321000 0 0x1400>; 4306 4307 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4308 clock-names = "xo", "alternate"; 4309 4310 #interconnect-cells = <1>; 4311 }; 4312 4313 cpufreq_hw: cpufreq@18323000 { 4314 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4315 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4316 <0 0x18327800 0 0x1400>; 4317 reg-names = "freq-domain0", "freq-domain1", 4318 "freq-domain2"; 4319 4320 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4321 clock-names = "xo", "alternate"; 4322 4323 #freq-domain-cells = <1>; 4324 #clock-cells = <1>; 4325 }; 4326 4327 lmh_cluster1: lmh@18350800 { 4328 compatible = "qcom,sm8150-lmh"; 4329 reg = <0 0x18350800 0 0x400>; 4330 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4331 cpus = <&CPU4>; 4332 qcom,lmh-temp-arm-millicelsius = <60000>; 4333 qcom,lmh-temp-low-millicelsius = <84500>; 4334 qcom,lmh-temp-high-millicelsius = <85000>; 4335 interrupt-controller; 4336 #interrupt-cells = <1>; 4337 }; 4338 4339 lmh_cluster0: lmh@18358800 { 4340 compatible = "qcom,sm8150-lmh"; 4341 reg = <0 0x18358800 0 0x400>; 4342 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4343 cpus = <&CPU0>; 4344 qcom,lmh-temp-arm-millicelsius = <60000>; 4345 qcom,lmh-temp-low-millicelsius = <84500>; 4346 qcom,lmh-temp-high-millicelsius = <85000>; 4347 interrupt-controller; 4348 #interrupt-cells = <1>; 4349 }; 4350 4351 wifi: wifi@18800000 { 4352 compatible = "qcom,wcn3990-wifi"; 4353 reg = <0 0x18800000 0 0x800000>; 4354 reg-names = "membase"; 4355 memory-region = <&wlan_mem>; 4356 clock-names = "cxo_ref_clk_pin", "qdss"; 4357 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4358 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4370 iommus = <&apps_smmu 0x0640 0x1>; 4371 status = "disabled"; 4372 }; 4373 }; 4374 4375 timer { 4376 compatible = "arm,armv8-timer"; 4377 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4378 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4379 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4380 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4381 }; 4382 4383 thermal-zones { 4384 cpu0-thermal { 4385 polling-delay-passive = <250>; 4386 polling-delay = <1000>; 4387 4388 thermal-sensors = <&tsens0 1>; 4389 4390 trips { 4391 cpu0_alert0: trip-point0 { 4392 temperature = <90000>; 4393 hysteresis = <2000>; 4394 type = "passive"; 4395 }; 4396 4397 cpu0_alert1: trip-point1 { 4398 temperature = <95000>; 4399 hysteresis = <2000>; 4400 type = "passive"; 4401 }; 4402 4403 cpu0_crit: cpu-crit { 4404 temperature = <110000>; 4405 hysteresis = <1000>; 4406 type = "critical"; 4407 }; 4408 }; 4409 4410 cooling-maps { 4411 map0 { 4412 trip = <&cpu0_alert0>; 4413 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4414 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4415 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4417 }; 4418 map1 { 4419 trip = <&cpu0_alert1>; 4420 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4421 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4422 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4424 }; 4425 }; 4426 }; 4427 4428 cpu1-thermal { 4429 polling-delay-passive = <250>; 4430 polling-delay = <1000>; 4431 4432 thermal-sensors = <&tsens0 2>; 4433 4434 trips { 4435 cpu1_alert0: trip-point0 { 4436 temperature = <90000>; 4437 hysteresis = <2000>; 4438 type = "passive"; 4439 }; 4440 4441 cpu1_alert1: trip-point1 { 4442 temperature = <95000>; 4443 hysteresis = <2000>; 4444 type = "passive"; 4445 }; 4446 4447 cpu1_crit: cpu-crit { 4448 temperature = <110000>; 4449 hysteresis = <1000>; 4450 type = "critical"; 4451 }; 4452 }; 4453 4454 cooling-maps { 4455 map0 { 4456 trip = <&cpu1_alert0>; 4457 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4458 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4459 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4460 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4461 }; 4462 map1 { 4463 trip = <&cpu1_alert1>; 4464 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4465 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4466 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4467 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4468 }; 4469 }; 4470 }; 4471 4472 cpu2-thermal { 4473 polling-delay-passive = <250>; 4474 polling-delay = <1000>; 4475 4476 thermal-sensors = <&tsens0 3>; 4477 4478 trips { 4479 cpu2_alert0: trip-point0 { 4480 temperature = <90000>; 4481 hysteresis = <2000>; 4482 type = "passive"; 4483 }; 4484 4485 cpu2_alert1: trip-point1 { 4486 temperature = <95000>; 4487 hysteresis = <2000>; 4488 type = "passive"; 4489 }; 4490 4491 cpu2_crit: cpu-crit { 4492 temperature = <110000>; 4493 hysteresis = <1000>; 4494 type = "critical"; 4495 }; 4496 }; 4497 4498 cooling-maps { 4499 map0 { 4500 trip = <&cpu2_alert0>; 4501 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4502 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4503 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4504 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4505 }; 4506 map1 { 4507 trip = <&cpu2_alert1>; 4508 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4509 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4510 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4511 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4512 }; 4513 }; 4514 }; 4515 4516 cpu3-thermal { 4517 polling-delay-passive = <250>; 4518 polling-delay = <1000>; 4519 4520 thermal-sensors = <&tsens0 4>; 4521 4522 trips { 4523 cpu3_alert0: trip-point0 { 4524 temperature = <90000>; 4525 hysteresis = <2000>; 4526 type = "passive"; 4527 }; 4528 4529 cpu3_alert1: trip-point1 { 4530 temperature = <95000>; 4531 hysteresis = <2000>; 4532 type = "passive"; 4533 }; 4534 4535 cpu3_crit: cpu-crit { 4536 temperature = <110000>; 4537 hysteresis = <1000>; 4538 type = "critical"; 4539 }; 4540 }; 4541 4542 cooling-maps { 4543 map0 { 4544 trip = <&cpu3_alert0>; 4545 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4546 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4547 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4548 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4549 }; 4550 map1 { 4551 trip = <&cpu3_alert1>; 4552 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4553 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4554 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4555 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4556 }; 4557 }; 4558 }; 4559 4560 cpu4-top-thermal { 4561 polling-delay-passive = <250>; 4562 polling-delay = <1000>; 4563 4564 thermal-sensors = <&tsens0 7>; 4565 4566 trips { 4567 cpu4_top_alert0: trip-point0 { 4568 temperature = <90000>; 4569 hysteresis = <2000>; 4570 type = "passive"; 4571 }; 4572 4573 cpu4_top_alert1: trip-point1 { 4574 temperature = <95000>; 4575 hysteresis = <2000>; 4576 type = "passive"; 4577 }; 4578 4579 cpu4_top_crit: cpu-crit { 4580 temperature = <110000>; 4581 hysteresis = <1000>; 4582 type = "critical"; 4583 }; 4584 }; 4585 4586 cooling-maps { 4587 map0 { 4588 trip = <&cpu4_top_alert0>; 4589 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4590 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4591 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4592 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4593 }; 4594 map1 { 4595 trip = <&cpu4_top_alert1>; 4596 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4597 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4598 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4599 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4600 }; 4601 }; 4602 }; 4603 4604 cpu5-top-thermal { 4605 polling-delay-passive = <250>; 4606 polling-delay = <1000>; 4607 4608 thermal-sensors = <&tsens0 8>; 4609 4610 trips { 4611 cpu5_top_alert0: trip-point0 { 4612 temperature = <90000>; 4613 hysteresis = <2000>; 4614 type = "passive"; 4615 }; 4616 4617 cpu5_top_alert1: trip-point1 { 4618 temperature = <95000>; 4619 hysteresis = <2000>; 4620 type = "passive"; 4621 }; 4622 4623 cpu5_top_crit: cpu-crit { 4624 temperature = <110000>; 4625 hysteresis = <1000>; 4626 type = "critical"; 4627 }; 4628 }; 4629 4630 cooling-maps { 4631 map0 { 4632 trip = <&cpu5_top_alert0>; 4633 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4634 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4635 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4637 }; 4638 map1 { 4639 trip = <&cpu5_top_alert1>; 4640 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4641 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4642 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4644 }; 4645 }; 4646 }; 4647 4648 cpu6-top-thermal { 4649 polling-delay-passive = <250>; 4650 polling-delay = <1000>; 4651 4652 thermal-sensors = <&tsens0 9>; 4653 4654 trips { 4655 cpu6_top_alert0: trip-point0 { 4656 temperature = <90000>; 4657 hysteresis = <2000>; 4658 type = "passive"; 4659 }; 4660 4661 cpu6_top_alert1: trip-point1 { 4662 temperature = <95000>; 4663 hysteresis = <2000>; 4664 type = "passive"; 4665 }; 4666 4667 cpu6_top_crit: cpu-crit { 4668 temperature = <110000>; 4669 hysteresis = <1000>; 4670 type = "critical"; 4671 }; 4672 }; 4673 4674 cooling-maps { 4675 map0 { 4676 trip = <&cpu6_top_alert0>; 4677 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4678 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4679 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4680 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4681 }; 4682 map1 { 4683 trip = <&cpu6_top_alert1>; 4684 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4686 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4687 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4688 }; 4689 }; 4690 }; 4691 4692 cpu7-top-thermal { 4693 polling-delay-passive = <250>; 4694 polling-delay = <1000>; 4695 4696 thermal-sensors = <&tsens0 10>; 4697 4698 trips { 4699 cpu7_top_alert0: trip-point0 { 4700 temperature = <90000>; 4701 hysteresis = <2000>; 4702 type = "passive"; 4703 }; 4704 4705 cpu7_top_alert1: trip-point1 { 4706 temperature = <95000>; 4707 hysteresis = <2000>; 4708 type = "passive"; 4709 }; 4710 4711 cpu7_top_crit: cpu-crit { 4712 temperature = <110000>; 4713 hysteresis = <1000>; 4714 type = "critical"; 4715 }; 4716 }; 4717 4718 cooling-maps { 4719 map0 { 4720 trip = <&cpu7_top_alert0>; 4721 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4722 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4723 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4724 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4725 }; 4726 map1 { 4727 trip = <&cpu7_top_alert1>; 4728 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4730 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4731 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4732 }; 4733 }; 4734 }; 4735 4736 cpu4-bottom-thermal { 4737 polling-delay-passive = <250>; 4738 polling-delay = <1000>; 4739 4740 thermal-sensors = <&tsens0 11>; 4741 4742 trips { 4743 cpu4_bottom_alert0: trip-point0 { 4744 temperature = <90000>; 4745 hysteresis = <2000>; 4746 type = "passive"; 4747 }; 4748 4749 cpu4_bottom_alert1: trip-point1 { 4750 temperature = <95000>; 4751 hysteresis = <2000>; 4752 type = "passive"; 4753 }; 4754 4755 cpu4_bottom_crit: cpu-crit { 4756 temperature = <110000>; 4757 hysteresis = <1000>; 4758 type = "critical"; 4759 }; 4760 }; 4761 4762 cooling-maps { 4763 map0 { 4764 trip = <&cpu4_bottom_alert0>; 4765 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4766 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4767 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4768 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4769 }; 4770 map1 { 4771 trip = <&cpu4_bottom_alert1>; 4772 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4773 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4774 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4776 }; 4777 }; 4778 }; 4779 4780 cpu5-bottom-thermal { 4781 polling-delay-passive = <250>; 4782 polling-delay = <1000>; 4783 4784 thermal-sensors = <&tsens0 12>; 4785 4786 trips { 4787 cpu5_bottom_alert0: trip-point0 { 4788 temperature = <90000>; 4789 hysteresis = <2000>; 4790 type = "passive"; 4791 }; 4792 4793 cpu5_bottom_alert1: trip-point1 { 4794 temperature = <95000>; 4795 hysteresis = <2000>; 4796 type = "passive"; 4797 }; 4798 4799 cpu5_bottom_crit: cpu-crit { 4800 temperature = <110000>; 4801 hysteresis = <1000>; 4802 type = "critical"; 4803 }; 4804 }; 4805 4806 cooling-maps { 4807 map0 { 4808 trip = <&cpu5_bottom_alert0>; 4809 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4811 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4812 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4813 }; 4814 map1 { 4815 trip = <&cpu5_bottom_alert1>; 4816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4820 }; 4821 }; 4822 }; 4823 4824 cpu6-bottom-thermal { 4825 polling-delay-passive = <250>; 4826 polling-delay = <1000>; 4827 4828 thermal-sensors = <&tsens0 13>; 4829 4830 trips { 4831 cpu6_bottom_alert0: trip-point0 { 4832 temperature = <90000>; 4833 hysteresis = <2000>; 4834 type = "passive"; 4835 }; 4836 4837 cpu6_bottom_alert1: trip-point1 { 4838 temperature = <95000>; 4839 hysteresis = <2000>; 4840 type = "passive"; 4841 }; 4842 4843 cpu6_bottom_crit: cpu-crit { 4844 temperature = <110000>; 4845 hysteresis = <1000>; 4846 type = "critical"; 4847 }; 4848 }; 4849 4850 cooling-maps { 4851 map0 { 4852 trip = <&cpu6_bottom_alert0>; 4853 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4855 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4856 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4857 }; 4858 map1 { 4859 trip = <&cpu6_bottom_alert1>; 4860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4861 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4862 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4863 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4864 }; 4865 }; 4866 }; 4867 4868 cpu7-bottom-thermal { 4869 polling-delay-passive = <250>; 4870 polling-delay = <1000>; 4871 4872 thermal-sensors = <&tsens0 14>; 4873 4874 trips { 4875 cpu7_bottom_alert0: trip-point0 { 4876 temperature = <90000>; 4877 hysteresis = <2000>; 4878 type = "passive"; 4879 }; 4880 4881 cpu7_bottom_alert1: trip-point1 { 4882 temperature = <95000>; 4883 hysteresis = <2000>; 4884 type = "passive"; 4885 }; 4886 4887 cpu7_bottom_crit: cpu-crit { 4888 temperature = <110000>; 4889 hysteresis = <1000>; 4890 type = "critical"; 4891 }; 4892 }; 4893 4894 cooling-maps { 4895 map0 { 4896 trip = <&cpu7_bottom_alert0>; 4897 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4898 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4899 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4900 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4901 }; 4902 map1 { 4903 trip = <&cpu7_bottom_alert1>; 4904 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4906 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4907 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4908 }; 4909 }; 4910 }; 4911 4912 aoss0-thermal { 4913 polling-delay-passive = <250>; 4914 polling-delay = <1000>; 4915 4916 thermal-sensors = <&tsens0 0>; 4917 4918 trips { 4919 aoss0_alert0: trip-point0 { 4920 temperature = <90000>; 4921 hysteresis = <2000>; 4922 type = "hot"; 4923 }; 4924 }; 4925 }; 4926 4927 cluster0-thermal { 4928 polling-delay-passive = <250>; 4929 polling-delay = <1000>; 4930 4931 thermal-sensors = <&tsens0 5>; 4932 4933 trips { 4934 cluster0_alert0: trip-point0 { 4935 temperature = <90000>; 4936 hysteresis = <2000>; 4937 type = "hot"; 4938 }; 4939 cluster0_crit: cluster0_crit { 4940 temperature = <110000>; 4941 hysteresis = <2000>; 4942 type = "critical"; 4943 }; 4944 }; 4945 }; 4946 4947 cluster1-thermal { 4948 polling-delay-passive = <250>; 4949 polling-delay = <1000>; 4950 4951 thermal-sensors = <&tsens0 6>; 4952 4953 trips { 4954 cluster1_alert0: trip-point0 { 4955 temperature = <90000>; 4956 hysteresis = <2000>; 4957 type = "hot"; 4958 }; 4959 cluster1_crit: cluster1_crit { 4960 temperature = <110000>; 4961 hysteresis = <2000>; 4962 type = "critical"; 4963 }; 4964 }; 4965 }; 4966 4967 gpu-top-thermal { 4968 polling-delay-passive = <250>; 4969 polling-delay = <1000>; 4970 4971 thermal-sensors = <&tsens0 15>; 4972 4973 trips { 4974 gpu1_alert0: trip-point0 { 4975 temperature = <90000>; 4976 hysteresis = <2000>; 4977 type = "hot"; 4978 }; 4979 }; 4980 }; 4981 4982 aoss1-thermal { 4983 polling-delay-passive = <250>; 4984 polling-delay = <1000>; 4985 4986 thermal-sensors = <&tsens1 0>; 4987 4988 trips { 4989 aoss1_alert0: trip-point0 { 4990 temperature = <90000>; 4991 hysteresis = <2000>; 4992 type = "hot"; 4993 }; 4994 }; 4995 }; 4996 4997 wlan-thermal { 4998 polling-delay-passive = <250>; 4999 polling-delay = <1000>; 5000 5001 thermal-sensors = <&tsens1 1>; 5002 5003 trips { 5004 wlan_alert0: trip-point0 { 5005 temperature = <90000>; 5006 hysteresis = <2000>; 5007 type = "hot"; 5008 }; 5009 }; 5010 }; 5011 5012 video-thermal { 5013 polling-delay-passive = <250>; 5014 polling-delay = <1000>; 5015 5016 thermal-sensors = <&tsens1 2>; 5017 5018 trips { 5019 video_alert0: trip-point0 { 5020 temperature = <90000>; 5021 hysteresis = <2000>; 5022 type = "hot"; 5023 }; 5024 }; 5025 }; 5026 5027 mem-thermal { 5028 polling-delay-passive = <250>; 5029 polling-delay = <1000>; 5030 5031 thermal-sensors = <&tsens1 3>; 5032 5033 trips { 5034 mem_alert0: trip-point0 { 5035 temperature = <90000>; 5036 hysteresis = <2000>; 5037 type = "hot"; 5038 }; 5039 }; 5040 }; 5041 5042 q6-hvx-thermal { 5043 polling-delay-passive = <250>; 5044 polling-delay = <1000>; 5045 5046 thermal-sensors = <&tsens1 4>; 5047 5048 trips { 5049 q6_hvx_alert0: trip-point0 { 5050 temperature = <90000>; 5051 hysteresis = <2000>; 5052 type = "hot"; 5053 }; 5054 }; 5055 }; 5056 5057 camera-thermal { 5058 polling-delay-passive = <250>; 5059 polling-delay = <1000>; 5060 5061 thermal-sensors = <&tsens1 5>; 5062 5063 trips { 5064 camera_alert0: trip-point0 { 5065 temperature = <90000>; 5066 hysteresis = <2000>; 5067 type = "hot"; 5068 }; 5069 }; 5070 }; 5071 5072 compute-thermal { 5073 polling-delay-passive = <250>; 5074 polling-delay = <1000>; 5075 5076 thermal-sensors = <&tsens1 6>; 5077 5078 trips { 5079 compute_alert0: trip-point0 { 5080 temperature = <90000>; 5081 hysteresis = <2000>; 5082 type = "hot"; 5083 }; 5084 }; 5085 }; 5086 5087 modem-thermal { 5088 polling-delay-passive = <250>; 5089 polling-delay = <1000>; 5090 5091 thermal-sensors = <&tsens1 7>; 5092 5093 trips { 5094 modem_alert0: trip-point0 { 5095 temperature = <90000>; 5096 hysteresis = <2000>; 5097 type = "hot"; 5098 }; 5099 }; 5100 }; 5101 5102 npu-thermal { 5103 polling-delay-passive = <250>; 5104 polling-delay = <1000>; 5105 5106 thermal-sensors = <&tsens1 8>; 5107 5108 trips { 5109 npu_alert0: trip-point0 { 5110 temperature = <90000>; 5111 hysteresis = <2000>; 5112 type = "hot"; 5113 }; 5114 }; 5115 }; 5116 5117 modem-vec-thermal { 5118 polling-delay-passive = <250>; 5119 polling-delay = <1000>; 5120 5121 thermal-sensors = <&tsens1 9>; 5122 5123 trips { 5124 modem_vec_alert0: trip-point0 { 5125 temperature = <90000>; 5126 hysteresis = <2000>; 5127 type = "hot"; 5128 }; 5129 }; 5130 }; 5131 5132 modem-scl-thermal { 5133 polling-delay-passive = <250>; 5134 polling-delay = <1000>; 5135 5136 thermal-sensors = <&tsens1 10>; 5137 5138 trips { 5139 modem_scl_alert0: trip-point0 { 5140 temperature = <90000>; 5141 hysteresis = <2000>; 5142 type = "hot"; 5143 }; 5144 }; 5145 }; 5146 5147 gpu-bottom-thermal { 5148 polling-delay-passive = <250>; 5149 polling-delay = <1000>; 5150 5151 thermal-sensors = <&tsens1 11>; 5152 5153 trips { 5154 gpu2_alert0: trip-point0 { 5155 temperature = <90000>; 5156 hysteresis = <2000>; 5157 type = "hot"; 5158 }; 5159 }; 5160 }; 5161 }; 5162}; 5163