xref: /freebsd/sys/contrib/device-tree/src/arm64/qcom/sm8150.dtsi (revision 725a9f47324d42037db93c27ceb40d4956872f3e)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited
5 */
6
7#include <dt-bindings/dma/qcom-gpi.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/power/qcom-rpmpd.h>
10#include <dt-bindings/soc/qcom,rpmh-rsc.h>
11#include <dt-bindings/clock/qcom,rpmh.h>
12#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
13#include <dt-bindings/clock/qcom,gcc-sm8150.h>
14#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
15#include <dt-bindings/interconnect/qcom,osm-l3.h>
16#include <dt-bindings/interconnect/qcom,sm8150.h>
17#include <dt-bindings/thermal/thermal.h>
18
19/ {
20	interrupt-parent = <&intc>;
21
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	chosen { };
26
27	clocks {
28		xo_board: xo-board {
29			compatible = "fixed-clock";
30			#clock-cells = <0>;
31			clock-frequency = <38400000>;
32			clock-output-names = "xo_board";
33		};
34
35		sleep_clk: sleep-clk {
36			compatible = "fixed-clock";
37			#clock-cells = <0>;
38			clock-frequency = <32764>;
39			clock-output-names = "sleep_clk";
40		};
41	};
42
43	cpus {
44		#address-cells = <2>;
45		#size-cells = <0>;
46
47		CPU0: cpu@0 {
48			device_type = "cpu";
49			compatible = "qcom,kryo485";
50			reg = <0x0 0x0>;
51			clocks = <&cpufreq_hw 0>;
52			enable-method = "psci";
53			capacity-dmips-mhz = <488>;
54			dynamic-power-coefficient = <232>;
55			next-level-cache = <&L2_0>;
56			qcom,freq-domain = <&cpufreq_hw 0>;
57			operating-points-v2 = <&cpu0_opp_table>;
58			interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
59					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
60			power-domains = <&CPU_PD0>;
61			power-domain-names = "psci";
62			#cooling-cells = <2>;
63			L2_0: l2-cache {
64				compatible = "cache";
65				cache-level = <2>;
66				cache-unified;
67				next-level-cache = <&L3_0>;
68				L3_0: l3-cache {
69					compatible = "cache";
70					cache-level = <3>;
71					cache-unified;
72				};
73			};
74		};
75
76		CPU1: cpu@100 {
77			device_type = "cpu";
78			compatible = "qcom,kryo485";
79			reg = <0x0 0x100>;
80			clocks = <&cpufreq_hw 0>;
81			enable-method = "psci";
82			capacity-dmips-mhz = <488>;
83			dynamic-power-coefficient = <232>;
84			next-level-cache = <&L2_100>;
85			qcom,freq-domain = <&cpufreq_hw 0>;
86			operating-points-v2 = <&cpu0_opp_table>;
87			interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
88					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
89			power-domains = <&CPU_PD1>;
90			power-domain-names = "psci";
91			#cooling-cells = <2>;
92			L2_100: l2-cache {
93				compatible = "cache";
94				cache-level = <2>;
95				cache-unified;
96				next-level-cache = <&L3_0>;
97			};
98		};
99
100		CPU2: cpu@200 {
101			device_type = "cpu";
102			compatible = "qcom,kryo485";
103			reg = <0x0 0x200>;
104			clocks = <&cpufreq_hw 0>;
105			enable-method = "psci";
106			capacity-dmips-mhz = <488>;
107			dynamic-power-coefficient = <232>;
108			next-level-cache = <&L2_200>;
109			qcom,freq-domain = <&cpufreq_hw 0>;
110			operating-points-v2 = <&cpu0_opp_table>;
111			interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
112					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
113			power-domains = <&CPU_PD2>;
114			power-domain-names = "psci";
115			#cooling-cells = <2>;
116			L2_200: l2-cache {
117				compatible = "cache";
118				cache-level = <2>;
119				cache-unified;
120				next-level-cache = <&L3_0>;
121			};
122		};
123
124		CPU3: cpu@300 {
125			device_type = "cpu";
126			compatible = "qcom,kryo485";
127			reg = <0x0 0x300>;
128			clocks = <&cpufreq_hw 0>;
129			enable-method = "psci";
130			capacity-dmips-mhz = <488>;
131			dynamic-power-coefficient = <232>;
132			next-level-cache = <&L2_300>;
133			qcom,freq-domain = <&cpufreq_hw 0>;
134			operating-points-v2 = <&cpu0_opp_table>;
135			interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
136					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
137			power-domains = <&CPU_PD3>;
138			power-domain-names = "psci";
139			#cooling-cells = <2>;
140			L2_300: l2-cache {
141				compatible = "cache";
142				cache-level = <2>;
143				cache-unified;
144				next-level-cache = <&L3_0>;
145			};
146		};
147
148		CPU4: cpu@400 {
149			device_type = "cpu";
150			compatible = "qcom,kryo485";
151			reg = <0x0 0x400>;
152			clocks = <&cpufreq_hw 1>;
153			enable-method = "psci";
154			capacity-dmips-mhz = <1024>;
155			dynamic-power-coefficient = <369>;
156			next-level-cache = <&L2_400>;
157			qcom,freq-domain = <&cpufreq_hw 1>;
158			operating-points-v2 = <&cpu4_opp_table>;
159			interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
160					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
161			power-domains = <&CPU_PD4>;
162			power-domain-names = "psci";
163			#cooling-cells = <2>;
164			L2_400: l2-cache {
165				compatible = "cache";
166				cache-level = <2>;
167				cache-unified;
168				next-level-cache = <&L3_0>;
169			};
170		};
171
172		CPU5: cpu@500 {
173			device_type = "cpu";
174			compatible = "qcom,kryo485";
175			reg = <0x0 0x500>;
176			clocks = <&cpufreq_hw 1>;
177			enable-method = "psci";
178			capacity-dmips-mhz = <1024>;
179			dynamic-power-coefficient = <369>;
180			next-level-cache = <&L2_500>;
181			qcom,freq-domain = <&cpufreq_hw 1>;
182			operating-points-v2 = <&cpu4_opp_table>;
183			interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
184					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
185			power-domains = <&CPU_PD5>;
186			power-domain-names = "psci";
187			#cooling-cells = <2>;
188			L2_500: l2-cache {
189				compatible = "cache";
190				cache-level = <2>;
191				cache-unified;
192				next-level-cache = <&L3_0>;
193			};
194		};
195
196		CPU6: cpu@600 {
197			device_type = "cpu";
198			compatible = "qcom,kryo485";
199			reg = <0x0 0x600>;
200			clocks = <&cpufreq_hw 1>;
201			enable-method = "psci";
202			capacity-dmips-mhz = <1024>;
203			dynamic-power-coefficient = <369>;
204			next-level-cache = <&L2_600>;
205			qcom,freq-domain = <&cpufreq_hw 1>;
206			operating-points-v2 = <&cpu4_opp_table>;
207			interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
208					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
209			power-domains = <&CPU_PD6>;
210			power-domain-names = "psci";
211			#cooling-cells = <2>;
212			L2_600: l2-cache {
213				compatible = "cache";
214				cache-level = <2>;
215				cache-unified;
216				next-level-cache = <&L3_0>;
217			};
218		};
219
220		CPU7: cpu@700 {
221			device_type = "cpu";
222			compatible = "qcom,kryo485";
223			reg = <0x0 0x700>;
224			clocks = <&cpufreq_hw 2>;
225			enable-method = "psci";
226			capacity-dmips-mhz = <1024>;
227			dynamic-power-coefficient = <421>;
228			next-level-cache = <&L2_700>;
229			qcom,freq-domain = <&cpufreq_hw 2>;
230			operating-points-v2 = <&cpu7_opp_table>;
231			interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
232					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
233			power-domains = <&CPU_PD7>;
234			power-domain-names = "psci";
235			#cooling-cells = <2>;
236			L2_700: l2-cache {
237				compatible = "cache";
238				cache-level = <2>;
239				cache-unified;
240				next-level-cache = <&L3_0>;
241			};
242		};
243
244		cpu-map {
245			cluster0 {
246				core0 {
247					cpu = <&CPU0>;
248				};
249
250				core1 {
251					cpu = <&CPU1>;
252				};
253
254				core2 {
255					cpu = <&CPU2>;
256				};
257
258				core3 {
259					cpu = <&CPU3>;
260				};
261
262				core4 {
263					cpu = <&CPU4>;
264				};
265
266				core5 {
267					cpu = <&CPU5>;
268				};
269
270				core6 {
271					cpu = <&CPU6>;
272				};
273
274				core7 {
275					cpu = <&CPU7>;
276				};
277			};
278		};
279
280		idle-states {
281			entry-method = "psci";
282
283			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
284				compatible = "arm,idle-state";
285				idle-state-name = "little-rail-power-collapse";
286				arm,psci-suspend-param = <0x40000004>;
287				entry-latency-us = <355>;
288				exit-latency-us = <909>;
289				min-residency-us = <3934>;
290				local-timer-stop;
291			};
292
293			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
294				compatible = "arm,idle-state";
295				idle-state-name = "big-rail-power-collapse";
296				arm,psci-suspend-param = <0x40000004>;
297				entry-latency-us = <241>;
298				exit-latency-us = <1461>;
299				min-residency-us = <4488>;
300				local-timer-stop;
301			};
302		};
303
304		domain-idle-states {
305			CLUSTER_SLEEP_0: cluster-sleep-0 {
306				compatible = "domain-idle-state";
307				arm,psci-suspend-param = <0x4100c244>;
308				entry-latency-us = <3263>;
309				exit-latency-us = <6562>;
310				min-residency-us = <9987>;
311			};
312		};
313	};
314
315	cpu0_opp_table: opp-table-cpu0 {
316		compatible = "operating-points-v2";
317		opp-shared;
318
319		cpu0_opp1: opp-300000000 {
320			opp-hz = /bits/ 64 <300000000>;
321			opp-peak-kBps = <800000 9600000>;
322		};
323
324		cpu0_opp2: opp-403200000 {
325			opp-hz = /bits/ 64 <403200000>;
326			opp-peak-kBps = <800000 9600000>;
327		};
328
329		cpu0_opp3: opp-499200000 {
330			opp-hz = /bits/ 64 <499200000>;
331			opp-peak-kBps = <800000 12902400>;
332		};
333
334		cpu0_opp4: opp-576000000 {
335			opp-hz = /bits/ 64 <576000000>;
336			opp-peak-kBps = <800000 12902400>;
337		};
338
339		cpu0_opp5: opp-672000000 {
340			opp-hz = /bits/ 64 <672000000>;
341			opp-peak-kBps = <800000 15974400>;
342		};
343
344		cpu0_opp6: opp-768000000 {
345			opp-hz = /bits/ 64 <768000000>;
346			opp-peak-kBps = <1804000 19660800>;
347		};
348
349		cpu0_opp7: opp-844800000 {
350			opp-hz = /bits/ 64 <844800000>;
351			opp-peak-kBps = <1804000 19660800>;
352		};
353
354		cpu0_opp8: opp-940800000 {
355			opp-hz = /bits/ 64 <940800000>;
356			opp-peak-kBps = <1804000 22732800>;
357		};
358
359		cpu0_opp9: opp-1036800000 {
360			opp-hz = /bits/ 64 <1036800000>;
361			opp-peak-kBps = <1804000 22732800>;
362		};
363
364		cpu0_opp10: opp-1113600000 {
365			opp-hz = /bits/ 64 <1113600000>;
366			opp-peak-kBps = <2188000 25804800>;
367		};
368
369		cpu0_opp11: opp-1209600000 {
370			opp-hz = /bits/ 64 <1209600000>;
371			opp-peak-kBps = <2188000 31948800>;
372		};
373
374		cpu0_opp12: opp-1305600000 {
375			opp-hz = /bits/ 64 <1305600000>;
376			opp-peak-kBps = <3072000 31948800>;
377		};
378
379		cpu0_opp13: opp-1382400000 {
380			opp-hz = /bits/ 64 <1382400000>;
381			opp-peak-kBps = <3072000 31948800>;
382		};
383
384		cpu0_opp14: opp-1478400000 {
385			opp-hz = /bits/ 64 <1478400000>;
386			opp-peak-kBps = <3072000 31948800>;
387		};
388
389		cpu0_opp15: opp-1555200000 {
390			opp-hz = /bits/ 64 <1555200000>;
391			opp-peak-kBps = <3072000 40550400>;
392		};
393
394		cpu0_opp16: opp-1632000000 {
395			opp-hz = /bits/ 64 <1632000000>;
396			opp-peak-kBps = <3072000 40550400>;
397		};
398
399		cpu0_opp17: opp-1708800000 {
400			opp-hz = /bits/ 64 <1708800000>;
401			opp-peak-kBps = <3072000 43008000>;
402		};
403
404		cpu0_opp18: opp-1785600000 {
405			opp-hz = /bits/ 64 <1785600000>;
406			opp-peak-kBps = <3072000 43008000>;
407		};
408	};
409
410	cpu4_opp_table: opp-table-cpu4 {
411		compatible = "operating-points-v2";
412		opp-shared;
413
414		cpu4_opp1: opp-710400000 {
415			opp-hz = /bits/ 64 <710400000>;
416			opp-peak-kBps = <1804000 15974400>;
417		};
418
419		cpu4_opp2: opp-825600000 {
420			opp-hz = /bits/ 64 <825600000>;
421			opp-peak-kBps = <2188000 19660800>;
422		};
423
424		cpu4_opp3: opp-940800000 {
425			opp-hz = /bits/ 64 <940800000>;
426			opp-peak-kBps = <2188000 22732800>;
427		};
428
429		cpu4_opp4: opp-1056000000 {
430			opp-hz = /bits/ 64 <1056000000>;
431			opp-peak-kBps = <3072000 25804800>;
432		};
433
434		cpu4_opp5: opp-1171200000 {
435			opp-hz = /bits/ 64 <1171200000>;
436			opp-peak-kBps = <3072000 31948800>;
437		};
438
439		cpu4_opp6: opp-1286400000 {
440			opp-hz = /bits/ 64 <1286400000>;
441			opp-peak-kBps = <4068000 31948800>;
442		};
443
444		cpu4_opp7: opp-1401600000 {
445			opp-hz = /bits/ 64 <1401600000>;
446			opp-peak-kBps = <4068000 31948800>;
447		};
448
449		cpu4_opp8: opp-1497600000 {
450			opp-hz = /bits/ 64 <1497600000>;
451			opp-peak-kBps = <4068000 40550400>;
452		};
453
454		cpu4_opp9: opp-1612800000 {
455			opp-hz = /bits/ 64 <1612800000>;
456			opp-peak-kBps = <4068000 40550400>;
457		};
458
459		cpu4_opp10: opp-1708800000 {
460			opp-hz = /bits/ 64 <1708800000>;
461			opp-peak-kBps = <4068000 43008000>;
462		};
463
464		cpu4_opp11: opp-1804800000 {
465			opp-hz = /bits/ 64 <1804800000>;
466			opp-peak-kBps = <6220000 43008000>;
467		};
468
469		cpu4_opp12: opp-1920000000 {
470			opp-hz = /bits/ 64 <1920000000>;
471			opp-peak-kBps = <6220000 49152000>;
472		};
473
474		cpu4_opp13: opp-2016000000 {
475			opp-hz = /bits/ 64 <2016000000>;
476			opp-peak-kBps = <7216000 49152000>;
477		};
478
479		cpu4_opp14: opp-2131200000 {
480			opp-hz = /bits/ 64 <2131200000>;
481			opp-peak-kBps = <8368000 49152000>;
482		};
483
484		cpu4_opp15: opp-2227200000 {
485			opp-hz = /bits/ 64 <2227200000>;
486			opp-peak-kBps = <8368000 51609600>;
487		};
488
489		cpu4_opp16: opp-2323200000 {
490			opp-hz = /bits/ 64 <2323200000>;
491			opp-peak-kBps = <8368000 51609600>;
492		};
493
494		cpu4_opp17: opp-2419200000 {
495			opp-hz = /bits/ 64 <2419200000>;
496			opp-peak-kBps = <8368000 51609600>;
497		};
498	};
499
500	cpu7_opp_table: opp-table-cpu7 {
501		compatible = "operating-points-v2";
502		opp-shared;
503
504		cpu7_opp1: opp-825600000 {
505			opp-hz = /bits/ 64 <825600000>;
506			opp-peak-kBps = <2188000 19660800>;
507		};
508
509		cpu7_opp2: opp-940800000 {
510			opp-hz = /bits/ 64 <940800000>;
511			opp-peak-kBps = <2188000 22732800>;
512		};
513
514		cpu7_opp3: opp-1056000000 {
515			opp-hz = /bits/ 64 <1056000000>;
516			opp-peak-kBps = <3072000 25804800>;
517		};
518
519		cpu7_opp4: opp-1171200000 {
520			opp-hz = /bits/ 64 <1171200000>;
521			opp-peak-kBps = <3072000 31948800>;
522		};
523
524		cpu7_opp5: opp-1286400000 {
525			opp-hz = /bits/ 64 <1286400000>;
526			opp-peak-kBps = <4068000 31948800>;
527		};
528
529		cpu7_opp6: opp-1401600000 {
530			opp-hz = /bits/ 64 <1401600000>;
531			opp-peak-kBps = <4068000 31948800>;
532		};
533
534		cpu7_opp7: opp-1497600000 {
535			opp-hz = /bits/ 64 <1497600000>;
536			opp-peak-kBps = <4068000 40550400>;
537		};
538
539		cpu7_opp8: opp-1612800000 {
540			opp-hz = /bits/ 64 <1612800000>;
541			opp-peak-kBps = <4068000 40550400>;
542		};
543
544		cpu7_opp9: opp-1708800000 {
545			opp-hz = /bits/ 64 <1708800000>;
546			opp-peak-kBps = <4068000 43008000>;
547		};
548
549		cpu7_opp10: opp-1804800000 {
550			opp-hz = /bits/ 64 <1804800000>;
551			opp-peak-kBps = <6220000 43008000>;
552		};
553
554		cpu7_opp11: opp-1920000000 {
555			opp-hz = /bits/ 64 <1920000000>;
556			opp-peak-kBps = <6220000 49152000>;
557		};
558
559		cpu7_opp12: opp-2016000000 {
560			opp-hz = /bits/ 64 <2016000000>;
561			opp-peak-kBps = <7216000 49152000>;
562		};
563
564		cpu7_opp13: opp-2131200000 {
565			opp-hz = /bits/ 64 <2131200000>;
566			opp-peak-kBps = <8368000 49152000>;
567		};
568
569		cpu7_opp14: opp-2227200000 {
570			opp-hz = /bits/ 64 <2227200000>;
571			opp-peak-kBps = <8368000 51609600>;
572		};
573
574		cpu7_opp15: opp-2323200000 {
575			opp-hz = /bits/ 64 <2323200000>;
576			opp-peak-kBps = <8368000 51609600>;
577		};
578
579		cpu7_opp16: opp-2419200000 {
580			opp-hz = /bits/ 64 <2419200000>;
581			opp-peak-kBps = <8368000 51609600>;
582		};
583
584		cpu7_opp17: opp-2534400000 {
585			opp-hz = /bits/ 64 <2534400000>;
586			opp-peak-kBps = <8368000 51609600>;
587		};
588
589		cpu7_opp18: opp-2649600000 {
590			opp-hz = /bits/ 64 <2649600000>;
591			opp-peak-kBps = <8368000 51609600>;
592		};
593
594		cpu7_opp19: opp-2745600000 {
595			opp-hz = /bits/ 64 <2745600000>;
596			opp-peak-kBps = <8368000 51609600>;
597		};
598
599		cpu7_opp20: opp-2841600000 {
600			opp-hz = /bits/ 64 <2841600000>;
601			opp-peak-kBps = <8368000 51609600>;
602		};
603	};
604
605	firmware {
606		scm: scm {
607			compatible = "qcom,scm-sm8150", "qcom,scm";
608			#reset-cells = <1>;
609		};
610	};
611
612	memory@80000000 {
613		device_type = "memory";
614		/* We expect the bootloader to fill in the size */
615		reg = <0x0 0x80000000 0x0 0x0>;
616	};
617
618	pmu {
619		compatible = "arm,armv8-pmuv3";
620		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
621	};
622
623	psci {
624		compatible = "arm,psci-1.0";
625		method = "smc";
626
627		CPU_PD0: power-domain-cpu0 {
628			#power-domain-cells = <0>;
629			power-domains = <&CLUSTER_PD>;
630			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
631		};
632
633		CPU_PD1: power-domain-cpu1 {
634			#power-domain-cells = <0>;
635			power-domains = <&CLUSTER_PD>;
636			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
637		};
638
639		CPU_PD2: power-domain-cpu2 {
640			#power-domain-cells = <0>;
641			power-domains = <&CLUSTER_PD>;
642			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
643		};
644
645		CPU_PD3: power-domain-cpu3 {
646			#power-domain-cells = <0>;
647			power-domains = <&CLUSTER_PD>;
648			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
649		};
650
651		CPU_PD4: power-domain-cpu4 {
652			#power-domain-cells = <0>;
653			power-domains = <&CLUSTER_PD>;
654			domain-idle-states = <&BIG_CPU_SLEEP_0>;
655		};
656
657		CPU_PD5: power-domain-cpu5 {
658			#power-domain-cells = <0>;
659			power-domains = <&CLUSTER_PD>;
660			domain-idle-states = <&BIG_CPU_SLEEP_0>;
661		};
662
663		CPU_PD6: power-domain-cpu6 {
664			#power-domain-cells = <0>;
665			power-domains = <&CLUSTER_PD>;
666			domain-idle-states = <&BIG_CPU_SLEEP_0>;
667		};
668
669		CPU_PD7: power-domain-cpu7 {
670			#power-domain-cells = <0>;
671			power-domains = <&CLUSTER_PD>;
672			domain-idle-states = <&BIG_CPU_SLEEP_0>;
673		};
674
675		CLUSTER_PD: power-domain-cpu-cluster0 {
676			#power-domain-cells = <0>;
677			domain-idle-states = <&CLUSTER_SLEEP_0>;
678		};
679	};
680
681	reserved-memory {
682		#address-cells = <2>;
683		#size-cells = <2>;
684		ranges;
685
686		hyp_mem: memory@85700000 {
687			reg = <0x0 0x85700000 0x0 0x600000>;
688			no-map;
689		};
690
691		xbl_mem: memory@85d00000 {
692			reg = <0x0 0x85d00000 0x0 0x140000>;
693			no-map;
694		};
695
696		aop_mem: memory@85f00000 {
697			reg = <0x0 0x85f00000 0x0 0x20000>;
698			no-map;
699		};
700
701		aop_cmd_db: memory@85f20000 {
702			compatible = "qcom,cmd-db";
703			reg = <0x0 0x85f20000 0x0 0x20000>;
704			no-map;
705		};
706
707		smem_mem: memory@86000000 {
708			reg = <0x0 0x86000000 0x0 0x200000>;
709			no-map;
710		};
711
712		tz_mem: memory@86200000 {
713			reg = <0x0 0x86200000 0x0 0x3900000>;
714			no-map;
715		};
716
717		rmtfs_mem: memory@89b00000 {
718			compatible = "qcom,rmtfs-mem";
719			reg = <0x0 0x89b00000 0x0 0x200000>;
720			no-map;
721
722			qcom,client-id = <1>;
723			qcom,vmid = <15>;
724		};
725
726		camera_mem: memory@8b700000 {
727			reg = <0x0 0x8b700000 0x0 0x500000>;
728			no-map;
729		};
730
731		wlan_mem: memory@8bc00000 {
732			reg = <0x0 0x8bc00000 0x0 0x180000>;
733			no-map;
734		};
735
736		npu_mem: memory@8bd80000 {
737			reg = <0x0 0x8bd80000 0x0 0x80000>;
738			no-map;
739		};
740
741		adsp_mem: memory@8be00000 {
742			reg = <0x0 0x8be00000 0x0 0x1a00000>;
743			no-map;
744		};
745
746		mpss_mem: memory@8d800000 {
747			reg = <0x0 0x8d800000 0x0 0x9600000>;
748			no-map;
749		};
750
751		venus_mem: memory@96e00000 {
752			reg = <0x0 0x96e00000 0x0 0x500000>;
753			no-map;
754		};
755
756		slpi_mem: memory@97300000 {
757			reg = <0x0 0x97300000 0x0 0x1400000>;
758			no-map;
759		};
760
761		ipa_fw_mem: memory@98700000 {
762			reg = <0x0 0x98700000 0x0 0x10000>;
763			no-map;
764		};
765
766		ipa_gsi_mem: memory@98710000 {
767			reg = <0x0 0x98710000 0x0 0x5000>;
768			no-map;
769		};
770
771		gpu_mem: memory@98715000 {
772			reg = <0x0 0x98715000 0x0 0x2000>;
773			no-map;
774		};
775
776		spss_mem: memory@98800000 {
777			reg = <0x0 0x98800000 0x0 0x100000>;
778			no-map;
779		};
780
781		cdsp_mem: memory@98900000 {
782			reg = <0x0 0x98900000 0x0 0x1400000>;
783			no-map;
784		};
785
786		qseecom_mem: memory@9e400000 {
787			reg = <0x0 0x9e400000 0x0 0x1400000>;
788			no-map;
789		};
790	};
791
792	smem {
793		compatible = "qcom,smem";
794		memory-region = <&smem_mem>;
795		hwlocks = <&tcsr_mutex 3>;
796	};
797
798	smp2p-cdsp {
799		compatible = "qcom,smp2p";
800		qcom,smem = <94>, <432>;
801
802		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
803
804		mboxes = <&apss_shared 6>;
805
806		qcom,local-pid = <0>;
807		qcom,remote-pid = <5>;
808
809		cdsp_smp2p_out: master-kernel {
810			qcom,entry-name = "master-kernel";
811			#qcom,smem-state-cells = <1>;
812		};
813
814		cdsp_smp2p_in: slave-kernel {
815			qcom,entry-name = "slave-kernel";
816
817			interrupt-controller;
818			#interrupt-cells = <2>;
819		};
820	};
821
822	smp2p-lpass {
823		compatible = "qcom,smp2p";
824		qcom,smem = <443>, <429>;
825
826		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
827
828		mboxes = <&apss_shared 10>;
829
830		qcom,local-pid = <0>;
831		qcom,remote-pid = <2>;
832
833		adsp_smp2p_out: master-kernel {
834			qcom,entry-name = "master-kernel";
835			#qcom,smem-state-cells = <1>;
836		};
837
838		adsp_smp2p_in: slave-kernel {
839			qcom,entry-name = "slave-kernel";
840
841			interrupt-controller;
842			#interrupt-cells = <2>;
843		};
844	};
845
846	smp2p-mpss {
847		compatible = "qcom,smp2p";
848		qcom,smem = <435>, <428>;
849
850		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
851
852		mboxes = <&apss_shared 14>;
853
854		qcom,local-pid = <0>;
855		qcom,remote-pid = <1>;
856
857		modem_smp2p_out: master-kernel {
858			qcom,entry-name = "master-kernel";
859			#qcom,smem-state-cells = <1>;
860		};
861
862		modem_smp2p_in: slave-kernel {
863			qcom,entry-name = "slave-kernel";
864
865			interrupt-controller;
866			#interrupt-cells = <2>;
867		};
868	};
869
870	smp2p-slpi {
871		compatible = "qcom,smp2p";
872		qcom,smem = <481>, <430>;
873
874		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
875
876		mboxes = <&apss_shared 26>;
877
878		qcom,local-pid = <0>;
879		qcom,remote-pid = <3>;
880
881		slpi_smp2p_out: master-kernel {
882			qcom,entry-name = "master-kernel";
883			#qcom,smem-state-cells = <1>;
884		};
885
886		slpi_smp2p_in: slave-kernel {
887			qcom,entry-name = "slave-kernel";
888
889			interrupt-controller;
890			#interrupt-cells = <2>;
891		};
892	};
893
894	soc: soc@0 {
895		#address-cells = <2>;
896		#size-cells = <2>;
897		ranges = <0 0 0 0 0x10 0>;
898		dma-ranges = <0 0 0 0 0x10 0>;
899		compatible = "simple-bus";
900
901		gcc: clock-controller@100000 {
902			compatible = "qcom,gcc-sm8150";
903			reg = <0x0 0x00100000 0x0 0x1f0000>;
904			#clock-cells = <1>;
905			#reset-cells = <1>;
906			#power-domain-cells = <1>;
907			clock-names = "bi_tcxo",
908				      "sleep_clk";
909			clocks = <&rpmhcc RPMH_CXO_CLK>,
910				 <&sleep_clk>;
911		};
912
913		gpi_dma0: dma-controller@800000 {
914			compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
915			reg = <0 0x00800000 0 0x60000>;
916			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
917				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
918				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
919				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
920				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
921				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
922				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
923				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
924				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
925				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
926				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
927				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
928				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
929			dma-channels = <13>;
930			dma-channel-mask = <0xfa>;
931			iommus = <&apps_smmu 0x00d6 0x0>;
932			#dma-cells = <3>;
933			status = "disabled";
934		};
935
936		ethernet: ethernet@20000 {
937			compatible = "qcom,sm8150-ethqos";
938			reg = <0x0 0x00020000 0x0 0x10000>,
939			      <0x0 0x00036000 0x0 0x100>;
940			reg-names = "stmmaceth", "rgmii";
941			clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
942			clocks = <&gcc GCC_EMAC_AXI_CLK>,
943				<&gcc GCC_EMAC_SLV_AHB_CLK>,
944				<&gcc GCC_EMAC_PTP_CLK>,
945				<&gcc GCC_EMAC_RGMII_CLK>;
946			interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
947				     <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
948			interrupt-names = "macirq", "eth_lpi";
949
950			power-domains = <&gcc EMAC_GDSC>;
951			resets = <&gcc GCC_EMAC_BCR>;
952
953			iommus = <&apps_smmu 0x3c0 0x0>;
954
955			snps,tso;
956			rx-fifo-depth = <4096>;
957			tx-fifo-depth = <4096>;
958
959			status = "disabled";
960		};
961
962		qfprom: efuse@784000 {
963			compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
964			reg = <0 0x00784000 0 0x8ff>;
965			#address-cells = <1>;
966			#size-cells = <1>;
967
968			gpu_speed_bin: gpu_speed_bin@133 {
969				reg = <0x133 0x1>;
970				bits = <5 3>;
971			};
972		};
973
974		qupv3_id_0: geniqup@8c0000 {
975			compatible = "qcom,geni-se-qup";
976			reg = <0x0 0x008c0000 0x0 0x6000>;
977			clock-names = "m-ahb", "s-ahb";
978			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
979				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
980			iommus = <&apps_smmu 0xc3 0x0>;
981			#address-cells = <2>;
982			#size-cells = <2>;
983			ranges;
984			status = "disabled";
985
986			i2c0: i2c@880000 {
987				compatible = "qcom,geni-i2c";
988				reg = <0 0x00880000 0 0x4000>;
989				clock-names = "se";
990				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
991				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
992				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
993				dma-names = "tx", "rx";
994				pinctrl-names = "default";
995				pinctrl-0 = <&qup_i2c0_default>;
996				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
997				#address-cells = <1>;
998				#size-cells = <0>;
999				status = "disabled";
1000			};
1001
1002			spi0: spi@880000 {
1003				compatible = "qcom,geni-spi";
1004				reg = <0 0x00880000 0 0x4000>;
1005				reg-names = "se";
1006				clock-names = "se";
1007				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1008				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1009				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1010				dma-names = "tx", "rx";
1011				pinctrl-names = "default";
1012				pinctrl-0 = <&qup_spi0_default>;
1013				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1014				spi-max-frequency = <50000000>;
1015				#address-cells = <1>;
1016				#size-cells = <0>;
1017				status = "disabled";
1018			};
1019
1020			i2c1: i2c@884000 {
1021				compatible = "qcom,geni-i2c";
1022				reg = <0 0x00884000 0 0x4000>;
1023				clock-names = "se";
1024				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1025				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1026				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1027				dma-names = "tx", "rx";
1028				pinctrl-names = "default";
1029				pinctrl-0 = <&qup_i2c1_default>;
1030				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1031				#address-cells = <1>;
1032				#size-cells = <0>;
1033				status = "disabled";
1034			};
1035
1036			spi1: spi@884000 {
1037				compatible = "qcom,geni-spi";
1038				reg = <0 0x00884000 0 0x4000>;
1039				reg-names = "se";
1040				clock-names = "se";
1041				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1042				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1043				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1044				dma-names = "tx", "rx";
1045				pinctrl-names = "default";
1046				pinctrl-0 = <&qup_spi1_default>;
1047				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1048				spi-max-frequency = <50000000>;
1049				#address-cells = <1>;
1050				#size-cells = <0>;
1051				status = "disabled";
1052			};
1053
1054			i2c2: i2c@888000 {
1055				compatible = "qcom,geni-i2c";
1056				reg = <0 0x00888000 0 0x4000>;
1057				clock-names = "se";
1058				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1059				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1060				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1061				dma-names = "tx", "rx";
1062				pinctrl-names = "default";
1063				pinctrl-0 = <&qup_i2c2_default>;
1064				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1065				#address-cells = <1>;
1066				#size-cells = <0>;
1067				status = "disabled";
1068			};
1069
1070			spi2: spi@888000 {
1071				compatible = "qcom,geni-spi";
1072				reg = <0 0x00888000 0 0x4000>;
1073				reg-names = "se";
1074				clock-names = "se";
1075				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1076				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1077				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1078				dma-names = "tx", "rx";
1079				pinctrl-names = "default";
1080				pinctrl-0 = <&qup_spi2_default>;
1081				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1082				spi-max-frequency = <50000000>;
1083				#address-cells = <1>;
1084				#size-cells = <0>;
1085				status = "disabled";
1086			};
1087
1088			i2c3: i2c@88c000 {
1089				compatible = "qcom,geni-i2c";
1090				reg = <0 0x0088c000 0 0x4000>;
1091				clock-names = "se";
1092				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1093				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1094				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1095				dma-names = "tx", "rx";
1096				pinctrl-names = "default";
1097				pinctrl-0 = <&qup_i2c3_default>;
1098				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1099				#address-cells = <1>;
1100				#size-cells = <0>;
1101				status = "disabled";
1102			};
1103
1104			spi3: spi@88c000 {
1105				compatible = "qcom,geni-spi";
1106				reg = <0 0x0088c000 0 0x4000>;
1107				reg-names = "se";
1108				clock-names = "se";
1109				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1110				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1111				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1112				dma-names = "tx", "rx";
1113				pinctrl-names = "default";
1114				pinctrl-0 = <&qup_spi3_default>;
1115				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1116				spi-max-frequency = <50000000>;
1117				#address-cells = <1>;
1118				#size-cells = <0>;
1119				status = "disabled";
1120			};
1121
1122			i2c4: i2c@890000 {
1123				compatible = "qcom,geni-i2c";
1124				reg = <0 0x00890000 0 0x4000>;
1125				clock-names = "se";
1126				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1127				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1128				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1129				dma-names = "tx", "rx";
1130				pinctrl-names = "default";
1131				pinctrl-0 = <&qup_i2c4_default>;
1132				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1133				#address-cells = <1>;
1134				#size-cells = <0>;
1135				status = "disabled";
1136			};
1137
1138			spi4: spi@890000 {
1139				compatible = "qcom,geni-spi";
1140				reg = <0 0x00890000 0 0x4000>;
1141				reg-names = "se";
1142				clock-names = "se";
1143				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1144				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1145				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1146				dma-names = "tx", "rx";
1147				pinctrl-names = "default";
1148				pinctrl-0 = <&qup_spi4_default>;
1149				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1150				spi-max-frequency = <50000000>;
1151				#address-cells = <1>;
1152				#size-cells = <0>;
1153				status = "disabled";
1154			};
1155
1156			i2c5: i2c@894000 {
1157				compatible = "qcom,geni-i2c";
1158				reg = <0 0x00894000 0 0x4000>;
1159				clock-names = "se";
1160				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1161				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1162				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1163				dma-names = "tx", "rx";
1164				pinctrl-names = "default";
1165				pinctrl-0 = <&qup_i2c5_default>;
1166				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1167				#address-cells = <1>;
1168				#size-cells = <0>;
1169				status = "disabled";
1170			};
1171
1172			spi5: spi@894000 {
1173				compatible = "qcom,geni-spi";
1174				reg = <0 0x00894000 0 0x4000>;
1175				reg-names = "se";
1176				clock-names = "se";
1177				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1178				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1179				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1180				dma-names = "tx", "rx";
1181				pinctrl-names = "default";
1182				pinctrl-0 = <&qup_spi5_default>;
1183				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1184				spi-max-frequency = <50000000>;
1185				#address-cells = <1>;
1186				#size-cells = <0>;
1187				status = "disabled";
1188			};
1189
1190			i2c6: i2c@898000 {
1191				compatible = "qcom,geni-i2c";
1192				reg = <0 0x00898000 0 0x4000>;
1193				clock-names = "se";
1194				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1195				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1196				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1197				dma-names = "tx", "rx";
1198				pinctrl-names = "default";
1199				pinctrl-0 = <&qup_i2c6_default>;
1200				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1201				#address-cells = <1>;
1202				#size-cells = <0>;
1203				status = "disabled";
1204			};
1205
1206			spi6: spi@898000 {
1207				compatible = "qcom,geni-spi";
1208				reg = <0 0x00898000 0 0x4000>;
1209				reg-names = "se";
1210				clock-names = "se";
1211				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1212				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1213				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1214				dma-names = "tx", "rx";
1215				pinctrl-names = "default";
1216				pinctrl-0 = <&qup_spi6_default>;
1217				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1218				spi-max-frequency = <50000000>;
1219				#address-cells = <1>;
1220				#size-cells = <0>;
1221				status = "disabled";
1222			};
1223
1224			i2c7: i2c@89c000 {
1225				compatible = "qcom,geni-i2c";
1226				reg = <0 0x0089c000 0 0x4000>;
1227				clock-names = "se";
1228				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1229				dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1230				       <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1231				dma-names = "tx", "rx";
1232				pinctrl-names = "default";
1233				pinctrl-0 = <&qup_i2c7_default>;
1234				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1235				#address-cells = <1>;
1236				#size-cells = <0>;
1237				status = "disabled";
1238			};
1239
1240			spi7: spi@89c000 {
1241				compatible = "qcom,geni-spi";
1242				reg = <0 0x0089c000 0 0x4000>;
1243				reg-names = "se";
1244				clock-names = "se";
1245				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1246				dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1247				       <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1248				dma-names = "tx", "rx";
1249				pinctrl-names = "default";
1250				pinctrl-0 = <&qup_spi7_default>;
1251				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1252				spi-max-frequency = <50000000>;
1253				#address-cells = <1>;
1254				#size-cells = <0>;
1255				status = "disabled";
1256			};
1257		};
1258
1259		gpi_dma1: dma-controller@a00000 {
1260			compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1261			reg = <0 0x00a00000 0 0x60000>;
1262			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1263				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1264				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1265				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1266				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1267				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1268				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1269				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1270				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1271				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1272				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1273				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1274				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1275			dma-channels = <13>;
1276			dma-channel-mask = <0xfa>;
1277			iommus = <&apps_smmu 0x0616 0x0>;
1278			#dma-cells = <3>;
1279			status = "disabled";
1280		};
1281
1282		qupv3_id_1: geniqup@ac0000 {
1283			compatible = "qcom,geni-se-qup";
1284			reg = <0x0 0x00ac0000 0x0 0x6000>;
1285			clock-names = "m-ahb", "s-ahb";
1286			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1287				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1288			iommus = <&apps_smmu 0x603 0x0>;
1289			#address-cells = <2>;
1290			#size-cells = <2>;
1291			ranges;
1292			status = "disabled";
1293
1294			i2c8: i2c@a80000 {
1295				compatible = "qcom,geni-i2c";
1296				reg = <0 0x00a80000 0 0x4000>;
1297				clock-names = "se";
1298				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1299				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1300				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1301				dma-names = "tx", "rx";
1302				pinctrl-names = "default";
1303				pinctrl-0 = <&qup_i2c8_default>;
1304				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1305				#address-cells = <1>;
1306				#size-cells = <0>;
1307				status = "disabled";
1308			};
1309
1310			spi8: spi@a80000 {
1311				compatible = "qcom,geni-spi";
1312				reg = <0 0x00a80000 0 0x4000>;
1313				reg-names = "se";
1314				clock-names = "se";
1315				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1316				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1317				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1318				dma-names = "tx", "rx";
1319				pinctrl-names = "default";
1320				pinctrl-0 = <&qup_spi8_default>;
1321				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1322				spi-max-frequency = <50000000>;
1323				#address-cells = <1>;
1324				#size-cells = <0>;
1325				status = "disabled";
1326			};
1327
1328			i2c9: i2c@a84000 {
1329				compatible = "qcom,geni-i2c";
1330				reg = <0 0x00a84000 0 0x4000>;
1331				clock-names = "se";
1332				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1333				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1334				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1335				dma-names = "tx", "rx";
1336				pinctrl-names = "default";
1337				pinctrl-0 = <&qup_i2c9_default>;
1338				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1339				#address-cells = <1>;
1340				#size-cells = <0>;
1341				status = "disabled";
1342			};
1343
1344			spi9: spi@a84000 {
1345				compatible = "qcom,geni-spi";
1346				reg = <0 0x00a84000 0 0x4000>;
1347				reg-names = "se";
1348				clock-names = "se";
1349				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1350				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1351				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1352				dma-names = "tx", "rx";
1353				pinctrl-names = "default";
1354				pinctrl-0 = <&qup_spi9_default>;
1355				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1356				spi-max-frequency = <50000000>;
1357				#address-cells = <1>;
1358				#size-cells = <0>;
1359				status = "disabled";
1360			};
1361
1362			uart9: serial@a84000 {
1363				compatible = "qcom,geni-uart";
1364				reg = <0x0 0x00a84000 0x0 0x4000>;
1365				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1366				clock-names = "se";
1367				pinctrl-0 = <&qup_uart9_default>;
1368				pinctrl-names = "default";
1369				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1370				status = "disabled";
1371			};
1372
1373			i2c10: i2c@a88000 {
1374				compatible = "qcom,geni-i2c";
1375				reg = <0 0x00a88000 0 0x4000>;
1376				clock-names = "se";
1377				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1378				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1379				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1380				dma-names = "tx", "rx";
1381				pinctrl-names = "default";
1382				pinctrl-0 = <&qup_i2c10_default>;
1383				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1384				#address-cells = <1>;
1385				#size-cells = <0>;
1386				status = "disabled";
1387			};
1388
1389			spi10: spi@a88000 {
1390				compatible = "qcom,geni-spi";
1391				reg = <0 0x00a88000 0 0x4000>;
1392				reg-names = "se";
1393				clock-names = "se";
1394				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1395				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1396				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1397				dma-names = "tx", "rx";
1398				pinctrl-names = "default";
1399				pinctrl-0 = <&qup_spi10_default>;
1400				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1401				spi-max-frequency = <50000000>;
1402				#address-cells = <1>;
1403				#size-cells = <0>;
1404				status = "disabled";
1405			};
1406
1407			i2c11: i2c@a8c000 {
1408				compatible = "qcom,geni-i2c";
1409				reg = <0 0x00a8c000 0 0x4000>;
1410				clock-names = "se";
1411				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1412				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1413				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1414				dma-names = "tx", "rx";
1415				pinctrl-names = "default";
1416				pinctrl-0 = <&qup_i2c11_default>;
1417				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1418				#address-cells = <1>;
1419				#size-cells = <0>;
1420				status = "disabled";
1421			};
1422
1423			spi11: spi@a8c000 {
1424				compatible = "qcom,geni-spi";
1425				reg = <0 0x00a8c000 0 0x4000>;
1426				reg-names = "se";
1427				clock-names = "se";
1428				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1429				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1430				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1431				dma-names = "tx", "rx";
1432				pinctrl-names = "default";
1433				pinctrl-0 = <&qup_spi11_default>;
1434				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1435				spi-max-frequency = <50000000>;
1436				#address-cells = <1>;
1437				#size-cells = <0>;
1438				status = "disabled";
1439			};
1440
1441			uart2: serial@a90000 {
1442				compatible = "qcom,geni-debug-uart";
1443				reg = <0x0 0x00a90000 0x0 0x4000>;
1444				clock-names = "se";
1445				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1446				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1447				status = "disabled";
1448			};
1449
1450			i2c12: i2c@a90000 {
1451				compatible = "qcom,geni-i2c";
1452				reg = <0 0x00a90000 0 0x4000>;
1453				clock-names = "se";
1454				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1455				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1456				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1457				dma-names = "tx", "rx";
1458				pinctrl-names = "default";
1459				pinctrl-0 = <&qup_i2c12_default>;
1460				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1461				#address-cells = <1>;
1462				#size-cells = <0>;
1463				status = "disabled";
1464			};
1465
1466			spi12: spi@a90000 {
1467				compatible = "qcom,geni-spi";
1468				reg = <0 0x00a90000 0 0x4000>;
1469				reg-names = "se";
1470				clock-names = "se";
1471				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1472				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1473				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1474				dma-names = "tx", "rx";
1475				pinctrl-names = "default";
1476				pinctrl-0 = <&qup_spi12_default>;
1477				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1478				spi-max-frequency = <50000000>;
1479				#address-cells = <1>;
1480				#size-cells = <0>;
1481				status = "disabled";
1482			};
1483
1484			i2c16: i2c@94000 {
1485				compatible = "qcom,geni-i2c";
1486				reg = <0 0x00094000 0 0x4000>;
1487				clock-names = "se";
1488				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1489				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1490				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1491				dma-names = "tx", "rx";
1492				pinctrl-names = "default";
1493				pinctrl-0 = <&qup_i2c16_default>;
1494				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1495				#address-cells = <1>;
1496				#size-cells = <0>;
1497				status = "disabled";
1498			};
1499
1500			spi16: spi@a94000 {
1501				compatible = "qcom,geni-spi";
1502				reg = <0 0x00a94000 0 0x4000>;
1503				reg-names = "se";
1504				clock-names = "se";
1505				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1506				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1507				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1508				dma-names = "tx", "rx";
1509				pinctrl-names = "default";
1510				pinctrl-0 = <&qup_spi16_default>;
1511				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1512				spi-max-frequency = <50000000>;
1513				#address-cells = <1>;
1514				#size-cells = <0>;
1515				status = "disabled";
1516			};
1517		};
1518
1519		gpi_dma2: dma-controller@c00000 {
1520			compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1521			reg = <0 0x00c00000 0 0x60000>;
1522			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1523				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1524				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1525				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1526				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1527				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1528				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1529				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1530				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1531				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1532				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1533				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1534				     <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1535			dma-channels = <13>;
1536			dma-channel-mask = <0xfa>;
1537			iommus = <&apps_smmu 0x07b6 0x0>;
1538			#dma-cells = <3>;
1539			status = "disabled";
1540		};
1541
1542		qupv3_id_2: geniqup@cc0000 {
1543			compatible = "qcom,geni-se-qup";
1544			reg = <0x0 0x00cc0000 0x0 0x6000>;
1545
1546			clock-names = "m-ahb", "s-ahb";
1547			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1548				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1549			iommus = <&apps_smmu 0x7a3 0x0>;
1550			#address-cells = <2>;
1551			#size-cells = <2>;
1552			ranges;
1553			status = "disabled";
1554
1555			i2c17: i2c@c80000 {
1556				compatible = "qcom,geni-i2c";
1557				reg = <0 0x00c80000 0 0x4000>;
1558				clock-names = "se";
1559				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1560				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1561				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1562				dma-names = "tx", "rx";
1563				pinctrl-names = "default";
1564				pinctrl-0 = <&qup_i2c17_default>;
1565				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1566				#address-cells = <1>;
1567				#size-cells = <0>;
1568				status = "disabled";
1569			};
1570
1571			spi17: spi@c80000 {
1572				compatible = "qcom,geni-spi";
1573				reg = <0 0x00c80000 0 0x4000>;
1574				reg-names = "se";
1575				clock-names = "se";
1576				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1577				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1578				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1579				dma-names = "tx", "rx";
1580				pinctrl-names = "default";
1581				pinctrl-0 = <&qup_spi17_default>;
1582				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1583				spi-max-frequency = <50000000>;
1584				#address-cells = <1>;
1585				#size-cells = <0>;
1586				status = "disabled";
1587			};
1588
1589			i2c18: i2c@c84000 {
1590				compatible = "qcom,geni-i2c";
1591				reg = <0 0x00c84000 0 0x4000>;
1592				clock-names = "se";
1593				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1594				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1595				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1596				dma-names = "tx", "rx";
1597				pinctrl-names = "default";
1598				pinctrl-0 = <&qup_i2c18_default>;
1599				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1600				#address-cells = <1>;
1601				#size-cells = <0>;
1602				status = "disabled";
1603			};
1604
1605			spi18: spi@c84000 {
1606				compatible = "qcom,geni-spi";
1607				reg = <0 0x00c84000 0 0x4000>;
1608				reg-names = "se";
1609				clock-names = "se";
1610				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1611				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1612				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1613				dma-names = "tx", "rx";
1614				pinctrl-names = "default";
1615				pinctrl-0 = <&qup_spi18_default>;
1616				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1617				spi-max-frequency = <50000000>;
1618				#address-cells = <1>;
1619				#size-cells = <0>;
1620				status = "disabled";
1621			};
1622
1623			i2c19: i2c@c88000 {
1624				compatible = "qcom,geni-i2c";
1625				reg = <0 0x00c88000 0 0x4000>;
1626				clock-names = "se";
1627				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1628				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1629				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1630				dma-names = "tx", "rx";
1631				pinctrl-names = "default";
1632				pinctrl-0 = <&qup_i2c19_default>;
1633				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1634				#address-cells = <1>;
1635				#size-cells = <0>;
1636				status = "disabled";
1637			};
1638
1639			spi19: spi@c88000 {
1640				compatible = "qcom,geni-spi";
1641				reg = <0 0x00c88000 0 0x4000>;
1642				reg-names = "se";
1643				clock-names = "se";
1644				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1645				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1646				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1647				dma-names = "tx", "rx";
1648				pinctrl-names = "default";
1649				pinctrl-0 = <&qup_spi19_default>;
1650				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1651				spi-max-frequency = <50000000>;
1652				#address-cells = <1>;
1653				#size-cells = <0>;
1654				status = "disabled";
1655			};
1656
1657			i2c13: i2c@c8c000 {
1658				compatible = "qcom,geni-i2c";
1659				reg = <0 0x00c8c000 0 0x4000>;
1660				clock-names = "se";
1661				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1662				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1663				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1664				dma-names = "tx", "rx";
1665				pinctrl-names = "default";
1666				pinctrl-0 = <&qup_i2c13_default>;
1667				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1668				#address-cells = <1>;
1669				#size-cells = <0>;
1670				status = "disabled";
1671			};
1672
1673			spi13: spi@c8c000 {
1674				compatible = "qcom,geni-spi";
1675				reg = <0 0x00c8c000 0 0x4000>;
1676				reg-names = "se";
1677				clock-names = "se";
1678				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1679				dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1680				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1681				dma-names = "tx", "rx";
1682				pinctrl-names = "default";
1683				pinctrl-0 = <&qup_spi13_default>;
1684				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1685				spi-max-frequency = <50000000>;
1686				#address-cells = <1>;
1687				#size-cells = <0>;
1688				status = "disabled";
1689			};
1690
1691			i2c14: i2c@c90000 {
1692				compatible = "qcom,geni-i2c";
1693				reg = <0 0x00c90000 0 0x4000>;
1694				clock-names = "se";
1695				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1696				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1697				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1698				dma-names = "tx", "rx";
1699				pinctrl-names = "default";
1700				pinctrl-0 = <&qup_i2c14_default>;
1701				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1702				#address-cells = <1>;
1703				#size-cells = <0>;
1704				status = "disabled";
1705			};
1706
1707			spi14: spi@c90000 {
1708				compatible = "qcom,geni-spi";
1709				reg = <0 0x00c90000 0 0x4000>;
1710				reg-names = "se";
1711				clock-names = "se";
1712				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1713				dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1714				       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1715				dma-names = "tx", "rx";
1716				pinctrl-names = "default";
1717				pinctrl-0 = <&qup_spi14_default>;
1718				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1719				spi-max-frequency = <50000000>;
1720				#address-cells = <1>;
1721				#size-cells = <0>;
1722				status = "disabled";
1723			};
1724
1725			i2c15: i2c@c94000 {
1726				compatible = "qcom,geni-i2c";
1727				reg = <0 0x00c94000 0 0x4000>;
1728				clock-names = "se";
1729				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1730				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1731				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1732				dma-names = "tx", "rx";
1733				pinctrl-names = "default";
1734				pinctrl-0 = <&qup_i2c15_default>;
1735				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1736				#address-cells = <1>;
1737				#size-cells = <0>;
1738				status = "disabled";
1739			};
1740
1741			spi15: spi@c94000 {
1742				compatible = "qcom,geni-spi";
1743				reg = <0 0x00c94000 0 0x4000>;
1744				reg-names = "se";
1745				clock-names = "se";
1746				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1747				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1748				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1749				dma-names = "tx", "rx";
1750				pinctrl-names = "default";
1751				pinctrl-0 = <&qup_spi15_default>;
1752				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1753				spi-max-frequency = <50000000>;
1754				#address-cells = <1>;
1755				#size-cells = <0>;
1756				status = "disabled";
1757			};
1758		};
1759
1760		config_noc: interconnect@1500000 {
1761			compatible = "qcom,sm8150-config-noc";
1762			reg = <0 0x01500000 0 0x7400>;
1763			#interconnect-cells = <2>;
1764			qcom,bcm-voters = <&apps_bcm_voter>;
1765		};
1766
1767		system_noc: interconnect@1620000 {
1768			compatible = "qcom,sm8150-system-noc";
1769			reg = <0 0x01620000 0 0x19400>;
1770			#interconnect-cells = <2>;
1771			qcom,bcm-voters = <&apps_bcm_voter>;
1772		};
1773
1774		mc_virt: interconnect@163a000 {
1775			compatible = "qcom,sm8150-mc-virt";
1776			reg = <0 0x0163a000 0 0x1000>;
1777			#interconnect-cells = <2>;
1778			qcom,bcm-voters = <&apps_bcm_voter>;
1779		};
1780
1781		aggre1_noc: interconnect@16e0000 {
1782			compatible = "qcom,sm8150-aggre1-noc";
1783			reg = <0 0x016e0000 0 0xd080>;
1784			#interconnect-cells = <2>;
1785			qcom,bcm-voters = <&apps_bcm_voter>;
1786		};
1787
1788		aggre2_noc: interconnect@1700000 {
1789			compatible = "qcom,sm8150-aggre2-noc";
1790			reg = <0 0x01700000 0 0x20000>;
1791			#interconnect-cells = <2>;
1792			qcom,bcm-voters = <&apps_bcm_voter>;
1793		};
1794
1795		compute_noc: interconnect@1720000 {
1796			compatible = "qcom,sm8150-compute-noc";
1797			reg = <0 0x01720000 0 0x7000>;
1798			#interconnect-cells = <2>;
1799			qcom,bcm-voters = <&apps_bcm_voter>;
1800		};
1801
1802		mmss_noc: interconnect@1740000 {
1803			compatible = "qcom,sm8150-mmss-noc";
1804			reg = <0 0x01740000 0 0x1c100>;
1805			#interconnect-cells = <2>;
1806			qcom,bcm-voters = <&apps_bcm_voter>;
1807		};
1808
1809		system-cache-controller@9200000 {
1810			compatible = "qcom,sm8150-llcc";
1811			reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1812			      <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1813			      <0 0x09600000 0 0x50000>;
1814			reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1815				    "llcc3_base", "llcc_broadcast_base";
1816			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1817		};
1818
1819		dma@10a2000 {
1820			compatible = "qcom,sm8150-dcc", "qcom,dcc";
1821			reg = <0x0 0x010a2000 0x0 0x1000>,
1822			      <0x0 0x010ad000 0x0 0x3000>;
1823		};
1824
1825		pcie0: pci@1c00000 {
1826			compatible = "qcom,pcie-sm8150";
1827			reg = <0 0x01c00000 0 0x3000>,
1828			      <0 0x60000000 0 0xf1d>,
1829			      <0 0x60000f20 0 0xa8>,
1830			      <0 0x60001000 0 0x1000>,
1831			      <0 0x60100000 0 0x100000>;
1832			reg-names = "parf", "dbi", "elbi", "atu", "config";
1833			device_type = "pci";
1834			linux,pci-domain = <0>;
1835			bus-range = <0x00 0xff>;
1836			num-lanes = <1>;
1837
1838			#address-cells = <3>;
1839			#size-cells = <2>;
1840
1841			ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1842				 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1843
1844			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1845			interrupt-names = "msi";
1846			#interrupt-cells = <1>;
1847			interrupt-map-mask = <0 0 0 0x7>;
1848			interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1849					<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1850					<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1851					<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1852
1853			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1854				 <&gcc GCC_PCIE_0_AUX_CLK>,
1855				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1856				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1857				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1858				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1859				 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1860			clock-names = "pipe",
1861				      "aux",
1862				      "cfg",
1863				      "bus_master",
1864				      "bus_slave",
1865				      "slave_q2a",
1866				      "tbu";
1867
1868			iommu-map = <0x0   &apps_smmu 0x1d80 0x1>,
1869				    <0x100 &apps_smmu 0x1d81 0x1>;
1870
1871			resets = <&gcc GCC_PCIE_0_BCR>;
1872			reset-names = "pci";
1873
1874			power-domains = <&gcc PCIE_0_GDSC>;
1875
1876			phys = <&pcie0_lane>;
1877			phy-names = "pciephy";
1878
1879			perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1880			enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1881
1882			pinctrl-names = "default";
1883			pinctrl-0 = <&pcie0_default_state>;
1884
1885			status = "disabled";
1886		};
1887
1888		pcie0_phy: phy@1c06000 {
1889			compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1890			reg = <0 0x01c06000 0 0x1c0>;
1891			#address-cells = <2>;
1892			#size-cells = <2>;
1893			ranges;
1894			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1895				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1896				 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1897			clock-names = "aux", "cfg_ahb", "refgen";
1898
1899			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1900			reset-names = "phy";
1901
1902			assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1903			assigned-clock-rates = <100000000>;
1904
1905			status = "disabled";
1906
1907			pcie0_lane: phy@1c06200 {
1908				reg = <0 0x01c06200 0 0x170>, /* tx */
1909				      <0 0x01c06400 0 0x200>, /* rx */
1910				      <0 0x01c06800 0 0x1f0>, /* pcs */
1911				      <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1912				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1913				clock-names = "pipe0";
1914
1915				#phy-cells = <0>;
1916				clock-output-names = "pcie_0_pipe_clk";
1917			};
1918		};
1919
1920		pcie1: pci@1c08000 {
1921			compatible = "qcom,pcie-sm8150";
1922			reg = <0 0x01c08000 0 0x3000>,
1923			      <0 0x40000000 0 0xf1d>,
1924			      <0 0x40000f20 0 0xa8>,
1925			      <0 0x40001000 0 0x1000>,
1926			      <0 0x40100000 0 0x100000>;
1927			reg-names = "parf", "dbi", "elbi", "atu", "config";
1928			device_type = "pci";
1929			linux,pci-domain = <1>;
1930			bus-range = <0x00 0xff>;
1931			num-lanes = <2>;
1932
1933			#address-cells = <3>;
1934			#size-cells = <2>;
1935
1936			ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1937				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1938
1939			interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1940			interrupt-names = "msi";
1941			#interrupt-cells = <1>;
1942			interrupt-map-mask = <0 0 0 0x7>;
1943			interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1944					<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1945					<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1946					<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1947
1948			clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1949				 <&gcc GCC_PCIE_1_AUX_CLK>,
1950				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1951				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1952				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1953				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1954				 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1955			clock-names = "pipe",
1956				      "aux",
1957				      "cfg",
1958				      "bus_master",
1959				      "bus_slave",
1960				      "slave_q2a",
1961				      "tbu";
1962
1963			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1964			assigned-clock-rates = <19200000>;
1965
1966			iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
1967				    <0x100 &apps_smmu 0x1e01 0x1>;
1968
1969			resets = <&gcc GCC_PCIE_1_BCR>;
1970			reset-names = "pci";
1971
1972			power-domains = <&gcc PCIE_1_GDSC>;
1973
1974			phys = <&pcie1_lane>;
1975			phy-names = "pciephy";
1976
1977			perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
1978			enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
1979
1980			pinctrl-names = "default";
1981			pinctrl-0 = <&pcie1_default_state>;
1982
1983			status = "disabled";
1984		};
1985
1986		pcie1_phy: phy@1c0e000 {
1987			compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
1988			reg = <0 0x01c0e000 0 0x1c0>;
1989			#address-cells = <2>;
1990			#size-cells = <2>;
1991			ranges;
1992			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1993				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1994				 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1995			clock-names = "aux", "cfg_ahb", "refgen";
1996
1997			resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1998			reset-names = "phy";
1999
2000			assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2001			assigned-clock-rates = <100000000>;
2002
2003			status = "disabled";
2004
2005			pcie1_lane: phy@1c0e200 {
2006				reg = <0 0x01c0e200 0 0x170>, /* tx0 */
2007				      <0 0x01c0e400 0 0x200>, /* rx0 */
2008				      <0 0x01c0ea00 0 0x1f0>, /* pcs */
2009				      <0 0x01c0e600 0 0x170>, /* tx1 */
2010				      <0 0x01c0e800 0 0x200>, /* rx1 */
2011				      <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2012				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2013				clock-names = "pipe0";
2014
2015				#phy-cells = <0>;
2016				clock-output-names = "pcie_1_pipe_clk";
2017			};
2018		};
2019
2020		ufs_mem_hc: ufshc@1d84000 {
2021			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2022				     "jedec,ufs-2.0";
2023			reg = <0 0x01d84000 0 0x2500>,
2024			      <0 0x01d90000 0 0x8000>;
2025			reg-names = "std", "ice";
2026			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2027			phys = <&ufs_mem_phy_lanes>;
2028			phy-names = "ufsphy";
2029			lanes-per-direction = <2>;
2030			#reset-cells = <1>;
2031			resets = <&gcc GCC_UFS_PHY_BCR>;
2032			reset-names = "rst";
2033
2034			iommus = <&apps_smmu 0x300 0>;
2035
2036			clock-names =
2037				"core_clk",
2038				"bus_aggr_clk",
2039				"iface_clk",
2040				"core_clk_unipro",
2041				"ref_clk",
2042				"tx_lane0_sync_clk",
2043				"rx_lane0_sync_clk",
2044				"rx_lane1_sync_clk",
2045				"ice_core_clk";
2046			clocks =
2047				<&gcc GCC_UFS_PHY_AXI_CLK>,
2048				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2049				<&gcc GCC_UFS_PHY_AHB_CLK>,
2050				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2051				<&rpmhcc RPMH_CXO_CLK>,
2052				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2053				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2054				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2055				<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2056			freq-table-hz =
2057				<37500000 300000000>,
2058				<0 0>,
2059				<0 0>,
2060				<37500000 300000000>,
2061				<0 0>,
2062				<0 0>,
2063				<0 0>,
2064				<0 0>,
2065				<0 300000000>;
2066
2067			status = "disabled";
2068		};
2069
2070		ufs_mem_phy: phy@1d87000 {
2071			compatible = "qcom,sm8150-qmp-ufs-phy";
2072			reg = <0 0x01d87000 0 0x1c0>;
2073			#address-cells = <2>;
2074			#size-cells = <2>;
2075			ranges;
2076			clock-names = "ref",
2077				      "ref_aux";
2078			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2079				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2080
2081			power-domains = <&gcc UFS_PHY_GDSC>;
2082
2083			resets = <&ufs_mem_hc 0>;
2084			reset-names = "ufsphy";
2085			status = "disabled";
2086
2087			ufs_mem_phy_lanes: phy@1d87400 {
2088				reg = <0 0x01d87400 0 0x16c>,
2089				      <0 0x01d87600 0 0x200>,
2090				      <0 0x01d87c00 0 0x200>,
2091				      <0 0x01d87800 0 0x16c>,
2092				      <0 0x01d87a00 0 0x200>;
2093				#phy-cells = <0>;
2094			};
2095		};
2096
2097		cryptobam: dma-controller@1dc4000 {
2098			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2099			reg = <0 0x01dc4000 0 0x24000>;
2100			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2101			#dma-cells = <1>;
2102			qcom,ee = <0>;
2103			qcom,controlled-remotely;
2104			num-channels = <8>;
2105			qcom,num-ees = <2>;
2106			iommus = <&apps_smmu 0x502 0x0641>,
2107				 <&apps_smmu 0x504 0x0011>,
2108				 <&apps_smmu 0x506 0x0011>,
2109				 <&apps_smmu 0x508 0x0011>,
2110				 <&apps_smmu 0x512 0x0000>;
2111		};
2112
2113		crypto: crypto@1dfa000 {
2114			compatible = "qcom,sm8150-qce", "qcom,qce";
2115			reg = <0 0x01dfa000 0 0x6000>;
2116			dmas = <&cryptobam 4>, <&cryptobam 5>;
2117			dma-names = "rx", "tx";
2118			iommus = <&apps_smmu 0x502 0x0641>,
2119				 <&apps_smmu 0x504 0x0011>,
2120				 <&apps_smmu 0x506 0x0011>,
2121				 <&apps_smmu 0x508 0x0011>,
2122				 <&apps_smmu 0x512 0x0000>;
2123			interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2124			interconnect-names = "memory";
2125		};
2126
2127		tcsr_mutex: hwlock@1f40000 {
2128			compatible = "qcom,tcsr-mutex";
2129			reg = <0x0 0x01f40000 0x0 0x20000>;
2130			#hwlock-cells = <1>;
2131		};
2132
2133		tcsr_regs_1: syscon@1f60000 {
2134			compatible = "qcom,sm8150-tcsr", "syscon";
2135			reg = <0x0 0x01f60000 0x0 0x20000>;
2136		};
2137
2138		remoteproc_slpi: remoteproc@2400000 {
2139			compatible = "qcom,sm8150-slpi-pas";
2140			reg = <0x0 0x02400000 0x0 0x4040>;
2141
2142			interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2143					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2144					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2145					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2146					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2147			interrupt-names = "wdog", "fatal", "ready",
2148					  "handover", "stop-ack";
2149
2150			clocks = <&rpmhcc RPMH_CXO_CLK>;
2151			clock-names = "xo";
2152
2153			power-domains = <&rpmhpd SM8150_LCX>,
2154					<&rpmhpd SM8150_LMX>;
2155			power-domain-names = "lcx", "lmx";
2156
2157			memory-region = <&slpi_mem>;
2158
2159			qcom,qmp = <&aoss_qmp>;
2160
2161			qcom,smem-states = <&slpi_smp2p_out 0>;
2162			qcom,smem-state-names = "stop";
2163
2164			status = "disabled";
2165
2166			glink-edge {
2167				interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2168				label = "dsps";
2169				qcom,remote-pid = <3>;
2170				mboxes = <&apss_shared 24>;
2171
2172				fastrpc {
2173					compatible = "qcom,fastrpc";
2174					qcom,glink-channels = "fastrpcglink-apps-dsp";
2175					label = "sdsp";
2176					qcom,non-secure-domain;
2177					#address-cells = <1>;
2178					#size-cells = <0>;
2179
2180					compute-cb@1 {
2181						compatible = "qcom,fastrpc-compute-cb";
2182						reg = <1>;
2183						iommus = <&apps_smmu 0x05a1 0x0>;
2184					};
2185
2186					compute-cb@2 {
2187						compatible = "qcom,fastrpc-compute-cb";
2188						reg = <2>;
2189						iommus = <&apps_smmu 0x05a2 0x0>;
2190					};
2191
2192					compute-cb@3 {
2193						compatible = "qcom,fastrpc-compute-cb";
2194						reg = <3>;
2195						iommus = <&apps_smmu 0x05a3 0x0>;
2196						/* note: shared-cb = <4> in downstream */
2197					};
2198				};
2199			};
2200		};
2201
2202		gpu: gpu@2c00000 {
2203			compatible = "qcom,adreno-640.1", "qcom,adreno";
2204			reg = <0 0x02c00000 0 0x40000>;
2205			reg-names = "kgsl_3d0_reg_memory";
2206
2207			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2208
2209			iommus = <&adreno_smmu 0 0x401>;
2210
2211			operating-points-v2 = <&gpu_opp_table>;
2212
2213			qcom,gmu = <&gmu>;
2214
2215			nvmem-cells = <&gpu_speed_bin>;
2216			nvmem-cell-names = "speed_bin";
2217
2218			status = "disabled";
2219
2220			zap-shader {
2221				memory-region = <&gpu_mem>;
2222			};
2223
2224			gpu_opp_table: opp-table {
2225				compatible = "operating-points-v2";
2226
2227				opp-675000000 {
2228					opp-hz = /bits/ 64 <675000000>;
2229					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2230					opp-supported-hw = <0x2>;
2231				};
2232
2233				opp-585000000 {
2234					opp-hz = /bits/ 64 <585000000>;
2235					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2236					opp-supported-hw = <0x3>;
2237				};
2238
2239				opp-499200000 {
2240					opp-hz = /bits/ 64 <499200000>;
2241					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2242					opp-supported-hw = <0x3>;
2243				};
2244
2245				opp-427000000 {
2246					opp-hz = /bits/ 64 <427000000>;
2247					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2248					opp-supported-hw = <0x3>;
2249				};
2250
2251				opp-345000000 {
2252					opp-hz = /bits/ 64 <345000000>;
2253					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2254					opp-supported-hw = <0x3>;
2255				};
2256
2257				opp-257000000 {
2258					opp-hz = /bits/ 64 <257000000>;
2259					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2260					opp-supported-hw = <0x3>;
2261				};
2262			};
2263		};
2264
2265		gmu: gmu@2c6a000 {
2266			compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2267
2268			reg = <0 0x02c6a000 0 0x30000>,
2269			      <0 0x0b290000 0 0x10000>,
2270			      <0 0x0b490000 0 0x10000>;
2271			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2272
2273			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2274				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2275			interrupt-names = "hfi", "gmu";
2276
2277			clocks = <&gpucc GPU_CC_AHB_CLK>,
2278				 <&gpucc GPU_CC_CX_GMU_CLK>,
2279				 <&gpucc GPU_CC_CXO_CLK>,
2280				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2281				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2282			clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2283
2284			power-domains = <&gpucc GPU_CX_GDSC>,
2285					<&gpucc GPU_GX_GDSC>;
2286			power-domain-names = "cx", "gx";
2287
2288			iommus = <&adreno_smmu 5 0x400>;
2289
2290			operating-points-v2 = <&gmu_opp_table>;
2291
2292			status = "disabled";
2293
2294			gmu_opp_table: opp-table {
2295				compatible = "operating-points-v2";
2296
2297				opp-200000000 {
2298					opp-hz = /bits/ 64 <200000000>;
2299					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2300				};
2301			};
2302		};
2303
2304		gpucc: clock-controller@2c90000 {
2305			compatible = "qcom,sm8150-gpucc";
2306			reg = <0 0x02c90000 0 0x9000>;
2307			clocks = <&rpmhcc RPMH_CXO_CLK>,
2308				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2309				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2310			clock-names = "bi_tcxo",
2311				      "gcc_gpu_gpll0_clk_src",
2312				      "gcc_gpu_gpll0_div_clk_src";
2313			#clock-cells = <1>;
2314			#reset-cells = <1>;
2315			#power-domain-cells = <1>;
2316		};
2317
2318		adreno_smmu: iommu@2ca0000 {
2319			compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2320				     "qcom,smmu-500", "arm,mmu-500";
2321			reg = <0 0x02ca0000 0 0x10000>;
2322			#iommu-cells = <2>;
2323			#global-interrupts = <1>;
2324			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2325				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2326				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2327				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2328				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2329				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2330				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2331				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2332				<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2333			clocks = <&gpucc GPU_CC_AHB_CLK>,
2334				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2335				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2336			clock-names = "ahb", "bus", "iface";
2337
2338			power-domains = <&gpucc GPU_CX_GDSC>;
2339		};
2340
2341		tlmm: pinctrl@3100000 {
2342			compatible = "qcom,sm8150-pinctrl";
2343			reg = <0x0 0x03100000 0x0 0x300000>,
2344			      <0x0 0x03500000 0x0 0x300000>,
2345			      <0x0 0x03900000 0x0 0x300000>,
2346			      <0x0 0x03D00000 0x0 0x300000>;
2347			reg-names = "west", "east", "north", "south";
2348			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2349			gpio-ranges = <&tlmm 0 0 176>;
2350			gpio-controller;
2351			#gpio-cells = <2>;
2352			interrupt-controller;
2353			#interrupt-cells = <2>;
2354			wakeup-parent = <&pdc>;
2355
2356			qup_i2c0_default: qup-i2c0-default-state {
2357				pins = "gpio0", "gpio1";
2358				function = "qup0";
2359				drive-strength = <0x02>;
2360				bias-disable;
2361			};
2362
2363			qup_spi0_default: qup-spi0-default-state {
2364				pins = "gpio0", "gpio1", "gpio2", "gpio3";
2365				function = "qup0";
2366				drive-strength = <6>;
2367				bias-disable;
2368			};
2369
2370			qup_i2c1_default: qup-i2c1-default-state {
2371				pins = "gpio114", "gpio115";
2372				function = "qup1";
2373				drive-strength = <2>;
2374				bias-disable;
2375			};
2376
2377			qup_spi1_default: qup-spi1-default-state {
2378				pins = "gpio114", "gpio115", "gpio116", "gpio117";
2379				function = "qup1";
2380				drive-strength = <6>;
2381				bias-disable;
2382			};
2383
2384			qup_i2c2_default: qup-i2c2-default-state {
2385				pins = "gpio126", "gpio127";
2386				function = "qup2";
2387				drive-strength = <2>;
2388				bias-disable;
2389			};
2390
2391			qup_spi2_default: qup-spi2-default-state {
2392				pins = "gpio126", "gpio127", "gpio128", "gpio129";
2393				function = "qup2";
2394				drive-strength = <6>;
2395				bias-disable;
2396			};
2397
2398			qup_i2c3_default: qup-i2c3-default-state {
2399				pins = "gpio144", "gpio145";
2400				function = "qup3";
2401				drive-strength = <2>;
2402				bias-disable;
2403			};
2404
2405			qup_spi3_default: qup-spi3-default-state {
2406				pins = "gpio144", "gpio145", "gpio146", "gpio147";
2407				function = "qup3";
2408				drive-strength = <6>;
2409				bias-disable;
2410			};
2411
2412			qup_i2c4_default: qup-i2c4-default-state {
2413				pins = "gpio51", "gpio52";
2414				function = "qup4";
2415				drive-strength = <2>;
2416				bias-disable;
2417			};
2418
2419			qup_spi4_default: qup-spi4-default-state {
2420				pins = "gpio51", "gpio52", "gpio53", "gpio54";
2421				function = "qup4";
2422				drive-strength = <6>;
2423				bias-disable;
2424			};
2425
2426			qup_i2c5_default: qup-i2c5-default-state {
2427				pins = "gpio121", "gpio122";
2428				function = "qup5";
2429				drive-strength = <2>;
2430				bias-disable;
2431			};
2432
2433			qup_spi5_default: qup-spi5-default-state {
2434				pins = "gpio119", "gpio120", "gpio121", "gpio122";
2435				function = "qup5";
2436				drive-strength = <6>;
2437				bias-disable;
2438			};
2439
2440			qup_i2c6_default: qup-i2c6-default-state {
2441				pins = "gpio6", "gpio7";
2442				function = "qup6";
2443				drive-strength = <2>;
2444				bias-disable;
2445			};
2446
2447			qup_spi6_default: qup-spi6_default-state {
2448				pins = "gpio4", "gpio5", "gpio6", "gpio7";
2449				function = "qup6";
2450				drive-strength = <6>;
2451				bias-disable;
2452			};
2453
2454			qup_i2c7_default: qup-i2c7-default-state {
2455				pins = "gpio98", "gpio99";
2456				function = "qup7";
2457				drive-strength = <2>;
2458				bias-disable;
2459			};
2460
2461			qup_spi7_default: qup-spi7_default-state {
2462				pins = "gpio98", "gpio99", "gpio100", "gpio101";
2463				function = "qup7";
2464				drive-strength = <6>;
2465				bias-disable;
2466			};
2467
2468			qup_i2c8_default: qup-i2c8-default-state {
2469				pins = "gpio88", "gpio89";
2470				function = "qup8";
2471				drive-strength = <2>;
2472				bias-disable;
2473			};
2474
2475			qup_spi8_default: qup-spi8-default-state {
2476				pins = "gpio88", "gpio89", "gpio90", "gpio91";
2477				function = "qup8";
2478				drive-strength = <6>;
2479				bias-disable;
2480			};
2481
2482			qup_i2c9_default: qup-i2c9-default-state {
2483				pins = "gpio39", "gpio40";
2484				function = "qup9";
2485				drive-strength = <2>;
2486				bias-disable;
2487			};
2488
2489			qup_spi9_default: qup-spi9-default-state {
2490				pins = "gpio39", "gpio40", "gpio41", "gpio42";
2491				function = "qup9";
2492				drive-strength = <6>;
2493				bias-disable;
2494			};
2495
2496			qup_uart9_default: qup-uart9-default-state {
2497				pins = "gpio41", "gpio42";
2498				function = "qup9";
2499				drive-strength = <2>;
2500				bias-disable;
2501			};
2502
2503			qup_i2c10_default: qup-i2c10-default-state {
2504				pins = "gpio9", "gpio10";
2505				function = "qup10";
2506				drive-strength = <2>;
2507				bias-disable;
2508			};
2509
2510			qup_spi10_default: qup-spi10-default-state {
2511				pins = "gpio9", "gpio10", "gpio11", "gpio12";
2512				function = "qup10";
2513				drive-strength = <6>;
2514				bias-disable;
2515			};
2516
2517			qup_i2c11_default: qup-i2c11-default-state {
2518				pins = "gpio94", "gpio95";
2519				function = "qup11";
2520				drive-strength = <2>;
2521				bias-disable;
2522			};
2523
2524			qup_spi11_default: qup-spi11-default-state {
2525				pins = "gpio92", "gpio93", "gpio94", "gpio95";
2526				function = "qup11";
2527				drive-strength = <6>;
2528				bias-disable;
2529			};
2530
2531			qup_i2c12_default: qup-i2c12-default-state {
2532				pins = "gpio83", "gpio84";
2533				function = "qup12";
2534				drive-strength = <2>;
2535				bias-disable;
2536			};
2537
2538			qup_spi12_default: qup-spi12-default-state {
2539				pins = "gpio83", "gpio84", "gpio85", "gpio86";
2540				function = "qup12";
2541				drive-strength = <6>;
2542				bias-disable;
2543			};
2544
2545			qup_i2c13_default: qup-i2c13-default-state {
2546				pins = "gpio43", "gpio44";
2547				function = "qup13";
2548				drive-strength = <2>;
2549				bias-disable;
2550			};
2551
2552			qup_spi13_default: qup-spi13-default-state {
2553				pins = "gpio43", "gpio44", "gpio45", "gpio46";
2554				function = "qup13";
2555				drive-strength = <6>;
2556				bias-disable;
2557			};
2558
2559			qup_i2c14_default: qup-i2c14-default-state {
2560				pins = "gpio47", "gpio48";
2561				function = "qup14";
2562				drive-strength = <2>;
2563				bias-disable;
2564			};
2565
2566			qup_spi14_default: qup-spi14-default-state {
2567				pins = "gpio47", "gpio48", "gpio49", "gpio50";
2568				function = "qup14";
2569				drive-strength = <6>;
2570				bias-disable;
2571			};
2572
2573			qup_i2c15_default: qup-i2c15-default-state {
2574				pins = "gpio27", "gpio28";
2575				function = "qup15";
2576				drive-strength = <2>;
2577				bias-disable;
2578			};
2579
2580			qup_spi15_default: qup-spi15-default-state {
2581				pins = "gpio27", "gpio28", "gpio29", "gpio30";
2582				function = "qup15";
2583				drive-strength = <6>;
2584				bias-disable;
2585			};
2586
2587			qup_i2c16_default: qup-i2c16-default-state {
2588				pins = "gpio86", "gpio85";
2589				function = "qup16";
2590				drive-strength = <2>;
2591				bias-disable;
2592			};
2593
2594			qup_spi16_default: qup-spi16-default-state {
2595				pins = "gpio83", "gpio84", "gpio85", "gpio86";
2596				function = "qup16";
2597				drive-strength = <6>;
2598				bias-disable;
2599			};
2600
2601			qup_i2c17_default: qup-i2c17-default-state {
2602				pins = "gpio55", "gpio56";
2603				function = "qup17";
2604				drive-strength = <2>;
2605				bias-disable;
2606			};
2607
2608			qup_spi17_default: qup-spi17-default-state {
2609				pins = "gpio55", "gpio56", "gpio57", "gpio58";
2610				function = "qup17";
2611				drive-strength = <6>;
2612				bias-disable;
2613			};
2614
2615			qup_i2c18_default: qup-i2c18-default-state {
2616				pins = "gpio23", "gpio24";
2617				function = "qup18";
2618				drive-strength = <2>;
2619				bias-disable;
2620			};
2621
2622			qup_spi18_default: qup-spi18-default-state {
2623				pins = "gpio23", "gpio24", "gpio25", "gpio26";
2624				function = "qup18";
2625				drive-strength = <6>;
2626				bias-disable;
2627			};
2628
2629			qup_i2c19_default: qup-i2c19-default-state {
2630				pins = "gpio57", "gpio58";
2631				function = "qup19";
2632				drive-strength = <2>;
2633				bias-disable;
2634			};
2635
2636			qup_spi19_default: qup-spi19-default-state {
2637				pins = "gpio55", "gpio56", "gpio57", "gpio58";
2638				function = "qup19";
2639				drive-strength = <6>;
2640				bias-disable;
2641			};
2642
2643			pcie0_default_state: pcie0-default-state {
2644				perst-pins {
2645					pins = "gpio35";
2646					function = "gpio";
2647					drive-strength = <2>;
2648					bias-pull-down;
2649				};
2650
2651				clkreq-pins {
2652					pins = "gpio36";
2653					function = "pci_e0";
2654					drive-strength = <2>;
2655					bias-pull-up;
2656				};
2657
2658				wake-pins {
2659					pins = "gpio37";
2660					function = "gpio";
2661					drive-strength = <2>;
2662					bias-pull-up;
2663				};
2664			};
2665
2666			pcie1_default_state: pcie1-default-state {
2667				perst-pins {
2668					pins = "gpio102";
2669					function = "gpio";
2670					drive-strength = <2>;
2671					bias-pull-down;
2672				};
2673
2674				clkreq-pins {
2675					pins = "gpio103";
2676					function = "pci_e1";
2677					drive-strength = <2>;
2678					bias-pull-up;
2679				};
2680
2681				wake-pins {
2682					pins = "gpio104";
2683					function = "gpio";
2684					drive-strength = <2>;
2685					bias-pull-up;
2686				};
2687			};
2688		};
2689
2690		remoteproc_mpss: remoteproc@4080000 {
2691			compatible = "qcom,sm8150-mpss-pas";
2692			reg = <0x0 0x04080000 0x0 0x4040>;
2693
2694			interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2695					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2696					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2697					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2698					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2699					      <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2700			interrupt-names = "wdog", "fatal", "ready", "handover",
2701					  "stop-ack", "shutdown-ack";
2702
2703			clocks = <&rpmhcc RPMH_CXO_CLK>;
2704			clock-names = "xo";
2705
2706			power-domains = <&rpmhpd SM8150_CX>,
2707					<&rpmhpd SM8150_MSS>;
2708			power-domain-names = "cx", "mss";
2709
2710			memory-region = <&mpss_mem>;
2711
2712			qcom,qmp = <&aoss_qmp>;
2713
2714			qcom,smem-states = <&modem_smp2p_out 0>;
2715			qcom,smem-state-names = "stop";
2716
2717			status = "disabled";
2718
2719			glink-edge {
2720				interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2721				label = "modem";
2722				qcom,remote-pid = <1>;
2723				mboxes = <&apss_shared 12>;
2724			};
2725		};
2726
2727		stm@6002000 {
2728			compatible = "arm,coresight-stm", "arm,primecell";
2729			reg = <0 0x06002000 0 0x1000>,
2730			      <0 0x16280000 0 0x180000>;
2731			reg-names = "stm-base", "stm-stimulus-base";
2732
2733			clocks = <&aoss_qmp>;
2734			clock-names = "apb_pclk";
2735
2736			out-ports {
2737				port {
2738					stm_out: endpoint {
2739						remote-endpoint = <&funnel0_in7>;
2740					};
2741				};
2742			};
2743		};
2744
2745		funnel@6041000 {
2746			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2747			reg = <0 0x06041000 0 0x1000>;
2748
2749			clocks = <&aoss_qmp>;
2750			clock-names = "apb_pclk";
2751
2752			out-ports {
2753				port {
2754					funnel0_out: endpoint {
2755						remote-endpoint = <&merge_funnel_in0>;
2756					};
2757				};
2758			};
2759
2760			in-ports {
2761				#address-cells = <1>;
2762				#size-cells = <0>;
2763
2764				port@7 {
2765					reg = <7>;
2766					funnel0_in7: endpoint {
2767						remote-endpoint = <&stm_out>;
2768					};
2769				};
2770			};
2771		};
2772
2773		funnel@6042000 {
2774			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2775			reg = <0 0x06042000 0 0x1000>;
2776
2777			clocks = <&aoss_qmp>;
2778			clock-names = "apb_pclk";
2779
2780			out-ports {
2781				port {
2782					funnel1_out: endpoint {
2783						remote-endpoint = <&merge_funnel_in1>;
2784					};
2785				};
2786			};
2787
2788			in-ports {
2789				#address-cells = <1>;
2790				#size-cells = <0>;
2791
2792				port@4 {
2793					reg = <4>;
2794					funnel1_in4: endpoint {
2795						remote-endpoint = <&swao_replicator_out>;
2796					};
2797				};
2798			};
2799		};
2800
2801		funnel@6043000 {
2802			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2803			reg = <0 0x06043000 0 0x1000>;
2804
2805			clocks = <&aoss_qmp>;
2806			clock-names = "apb_pclk";
2807
2808			out-ports {
2809				port {
2810					funnel2_out: endpoint {
2811						remote-endpoint = <&merge_funnel_in2>;
2812					};
2813				};
2814			};
2815
2816			in-ports {
2817				#address-cells = <1>;
2818				#size-cells = <0>;
2819
2820				port@2 {
2821					reg = <2>;
2822					funnel2_in2: endpoint {
2823						remote-endpoint = <&apss_merge_funnel_out>;
2824					};
2825				};
2826			};
2827		};
2828
2829		funnel@6045000 {
2830			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2831			reg = <0 0x06045000 0 0x1000>;
2832
2833			clocks = <&aoss_qmp>;
2834			clock-names = "apb_pclk";
2835
2836			out-ports {
2837				port {
2838					merge_funnel_out: endpoint {
2839						remote-endpoint = <&etf_in>;
2840					};
2841				};
2842			};
2843
2844			in-ports {
2845				#address-cells = <1>;
2846				#size-cells = <0>;
2847
2848				port@0 {
2849					reg = <0>;
2850					merge_funnel_in0: endpoint {
2851						remote-endpoint = <&funnel0_out>;
2852					};
2853				};
2854
2855				port@1 {
2856					reg = <1>;
2857					merge_funnel_in1: endpoint {
2858						remote-endpoint = <&funnel1_out>;
2859					};
2860				};
2861
2862				port@2 {
2863					reg = <2>;
2864					merge_funnel_in2: endpoint {
2865						remote-endpoint = <&funnel2_out>;
2866					};
2867				};
2868			};
2869		};
2870
2871		replicator@6046000 {
2872			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2873			reg = <0 0x06046000 0 0x1000>;
2874
2875			clocks = <&aoss_qmp>;
2876			clock-names = "apb_pclk";
2877
2878			out-ports {
2879				#address-cells = <1>;
2880				#size-cells = <0>;
2881
2882				port@0 {
2883					reg = <0>;
2884					replicator_out0: endpoint {
2885						remote-endpoint = <&etr_in>;
2886					};
2887				};
2888
2889				port@1 {
2890					reg = <1>;
2891					replicator_out1: endpoint {
2892						remote-endpoint = <&replicator1_in>;
2893					};
2894				};
2895			};
2896
2897			in-ports {
2898				port {
2899					replicator_in0: endpoint {
2900						remote-endpoint = <&etf_out>;
2901					};
2902				};
2903			};
2904		};
2905
2906		etf@6047000 {
2907			compatible = "arm,coresight-tmc", "arm,primecell";
2908			reg = <0 0x06047000 0 0x1000>;
2909
2910			clocks = <&aoss_qmp>;
2911			clock-names = "apb_pclk";
2912
2913			out-ports {
2914				port {
2915					etf_out: endpoint {
2916						remote-endpoint = <&replicator_in0>;
2917					};
2918				};
2919			};
2920
2921			in-ports {
2922				port {
2923					etf_in: endpoint {
2924						remote-endpoint = <&merge_funnel_out>;
2925					};
2926				};
2927			};
2928		};
2929
2930		etr@6048000 {
2931			compatible = "arm,coresight-tmc", "arm,primecell";
2932			reg = <0 0x06048000 0 0x1000>;
2933			iommus = <&apps_smmu 0x05e0 0x0>;
2934
2935			clocks = <&aoss_qmp>;
2936			clock-names = "apb_pclk";
2937			arm,scatter-gather;
2938
2939			in-ports {
2940				port {
2941					etr_in: endpoint {
2942						remote-endpoint = <&replicator_out0>;
2943					};
2944				};
2945			};
2946		};
2947
2948		replicator@604a000 {
2949			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2950			reg = <0 0x0604a000 0 0x1000>;
2951
2952			clocks = <&aoss_qmp>;
2953			clock-names = "apb_pclk";
2954
2955			out-ports {
2956				#address-cells = <1>;
2957				#size-cells = <0>;
2958
2959				port@1 {
2960					reg = <1>;
2961					replicator1_out: endpoint {
2962						remote-endpoint = <&swao_funnel_in>;
2963					};
2964				};
2965			};
2966
2967			in-ports {
2968				#address-cells = <1>;
2969				#size-cells = <0>;
2970
2971				port@1 {
2972					reg = <1>;
2973					replicator1_in: endpoint {
2974						remote-endpoint = <&replicator_out1>;
2975					};
2976				};
2977			};
2978		};
2979
2980		funnel@6b08000 {
2981			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2982			reg = <0 0x06b08000 0 0x1000>;
2983
2984			clocks = <&aoss_qmp>;
2985			clock-names = "apb_pclk";
2986
2987			out-ports {
2988				port {
2989					swao_funnel_out: endpoint {
2990						remote-endpoint = <&swao_etf_in>;
2991					};
2992				};
2993			};
2994
2995			in-ports {
2996				#address-cells = <1>;
2997				#size-cells = <0>;
2998
2999				port@6 {
3000					reg = <6>;
3001					swao_funnel_in: endpoint {
3002						remote-endpoint = <&replicator1_out>;
3003					};
3004				};
3005			};
3006		};
3007
3008		etf@6b09000 {
3009			compatible = "arm,coresight-tmc", "arm,primecell";
3010			reg = <0 0x06b09000 0 0x1000>;
3011
3012			clocks = <&aoss_qmp>;
3013			clock-names = "apb_pclk";
3014
3015			out-ports {
3016				port {
3017					swao_etf_out: endpoint {
3018						remote-endpoint = <&swao_replicator_in>;
3019					};
3020				};
3021			};
3022
3023			in-ports {
3024				port {
3025					swao_etf_in: endpoint {
3026						remote-endpoint = <&swao_funnel_out>;
3027					};
3028				};
3029			};
3030		};
3031
3032		replicator@6b0a000 {
3033			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3034			reg = <0 0x06b0a000 0 0x1000>;
3035
3036			clocks = <&aoss_qmp>;
3037			clock-names = "apb_pclk";
3038			qcom,replicator-loses-context;
3039
3040			out-ports {
3041				port {
3042					swao_replicator_out: endpoint {
3043						remote-endpoint = <&funnel1_in4>;
3044					};
3045				};
3046			};
3047
3048			in-ports {
3049				port {
3050					swao_replicator_in: endpoint {
3051						remote-endpoint = <&swao_etf_out>;
3052					};
3053				};
3054			};
3055		};
3056
3057		etm@7040000 {
3058			compatible = "arm,coresight-etm4x", "arm,primecell";
3059			reg = <0 0x07040000 0 0x1000>;
3060
3061			cpu = <&CPU0>;
3062
3063			clocks = <&aoss_qmp>;
3064			clock-names = "apb_pclk";
3065			arm,coresight-loses-context-with-cpu;
3066			qcom,skip-power-up;
3067
3068			out-ports {
3069				port {
3070					etm0_out: endpoint {
3071						remote-endpoint = <&apss_funnel_in0>;
3072					};
3073				};
3074			};
3075		};
3076
3077		etm@7140000 {
3078			compatible = "arm,coresight-etm4x", "arm,primecell";
3079			reg = <0 0x07140000 0 0x1000>;
3080
3081			cpu = <&CPU1>;
3082
3083			clocks = <&aoss_qmp>;
3084			clock-names = "apb_pclk";
3085			arm,coresight-loses-context-with-cpu;
3086			qcom,skip-power-up;
3087
3088			out-ports {
3089				port {
3090					etm1_out: endpoint {
3091						remote-endpoint = <&apss_funnel_in1>;
3092					};
3093				};
3094			};
3095		};
3096
3097		etm@7240000 {
3098			compatible = "arm,coresight-etm4x", "arm,primecell";
3099			reg = <0 0x07240000 0 0x1000>;
3100
3101			cpu = <&CPU2>;
3102
3103			clocks = <&aoss_qmp>;
3104			clock-names = "apb_pclk";
3105			arm,coresight-loses-context-with-cpu;
3106			qcom,skip-power-up;
3107
3108			out-ports {
3109				port {
3110					etm2_out: endpoint {
3111						remote-endpoint = <&apss_funnel_in2>;
3112					};
3113				};
3114			};
3115		};
3116
3117		etm@7340000 {
3118			compatible = "arm,coresight-etm4x", "arm,primecell";
3119			reg = <0 0x07340000 0 0x1000>;
3120
3121			cpu = <&CPU3>;
3122
3123			clocks = <&aoss_qmp>;
3124			clock-names = "apb_pclk";
3125			arm,coresight-loses-context-with-cpu;
3126			qcom,skip-power-up;
3127
3128			out-ports {
3129				port {
3130					etm3_out: endpoint {
3131						remote-endpoint = <&apss_funnel_in3>;
3132					};
3133				};
3134			};
3135		};
3136
3137		etm@7440000 {
3138			compatible = "arm,coresight-etm4x", "arm,primecell";
3139			reg = <0 0x07440000 0 0x1000>;
3140
3141			cpu = <&CPU4>;
3142
3143			clocks = <&aoss_qmp>;
3144			clock-names = "apb_pclk";
3145			arm,coresight-loses-context-with-cpu;
3146			qcom,skip-power-up;
3147
3148			out-ports {
3149				port {
3150					etm4_out: endpoint {
3151						remote-endpoint = <&apss_funnel_in4>;
3152					};
3153				};
3154			};
3155		};
3156
3157		etm@7540000 {
3158			compatible = "arm,coresight-etm4x", "arm,primecell";
3159			reg = <0 0x07540000 0 0x1000>;
3160
3161			cpu = <&CPU5>;
3162
3163			clocks = <&aoss_qmp>;
3164			clock-names = "apb_pclk";
3165			arm,coresight-loses-context-with-cpu;
3166			qcom,skip-power-up;
3167
3168			out-ports {
3169				port {
3170					etm5_out: endpoint {
3171						remote-endpoint = <&apss_funnel_in5>;
3172					};
3173				};
3174			};
3175		};
3176
3177		etm@7640000 {
3178			compatible = "arm,coresight-etm4x", "arm,primecell";
3179			reg = <0 0x07640000 0 0x1000>;
3180
3181			cpu = <&CPU6>;
3182
3183			clocks = <&aoss_qmp>;
3184			clock-names = "apb_pclk";
3185			arm,coresight-loses-context-with-cpu;
3186			qcom,skip-power-up;
3187
3188			out-ports {
3189				port {
3190					etm6_out: endpoint {
3191						remote-endpoint = <&apss_funnel_in6>;
3192					};
3193				};
3194			};
3195		};
3196
3197		etm@7740000 {
3198			compatible = "arm,coresight-etm4x", "arm,primecell";
3199			reg = <0 0x07740000 0 0x1000>;
3200
3201			cpu = <&CPU7>;
3202
3203			clocks = <&aoss_qmp>;
3204			clock-names = "apb_pclk";
3205			arm,coresight-loses-context-with-cpu;
3206			qcom,skip-power-up;
3207
3208			out-ports {
3209				port {
3210					etm7_out: endpoint {
3211						remote-endpoint = <&apss_funnel_in7>;
3212					};
3213				};
3214			};
3215		};
3216
3217		funnel@7800000 { /* APSS Funnel */
3218			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3219			reg = <0 0x07800000 0 0x1000>;
3220
3221			clocks = <&aoss_qmp>;
3222			clock-names = "apb_pclk";
3223
3224			out-ports {
3225				port {
3226					apss_funnel_out: endpoint {
3227						remote-endpoint = <&apss_merge_funnel_in>;
3228					};
3229				};
3230			};
3231
3232			in-ports {
3233				#address-cells = <1>;
3234				#size-cells = <0>;
3235
3236				port@0 {
3237					reg = <0>;
3238					apss_funnel_in0: endpoint {
3239						remote-endpoint = <&etm0_out>;
3240					};
3241				};
3242
3243				port@1 {
3244					reg = <1>;
3245					apss_funnel_in1: endpoint {
3246						remote-endpoint = <&etm1_out>;
3247					};
3248				};
3249
3250				port@2 {
3251					reg = <2>;
3252					apss_funnel_in2: endpoint {
3253						remote-endpoint = <&etm2_out>;
3254					};
3255				};
3256
3257				port@3 {
3258					reg = <3>;
3259					apss_funnel_in3: endpoint {
3260						remote-endpoint = <&etm3_out>;
3261					};
3262				};
3263
3264				port@4 {
3265					reg = <4>;
3266					apss_funnel_in4: endpoint {
3267						remote-endpoint = <&etm4_out>;
3268					};
3269				};
3270
3271				port@5 {
3272					reg = <5>;
3273					apss_funnel_in5: endpoint {
3274						remote-endpoint = <&etm5_out>;
3275					};
3276				};
3277
3278				port@6 {
3279					reg = <6>;
3280					apss_funnel_in6: endpoint {
3281						remote-endpoint = <&etm6_out>;
3282					};
3283				};
3284
3285				port@7 {
3286					reg = <7>;
3287					apss_funnel_in7: endpoint {
3288						remote-endpoint = <&etm7_out>;
3289					};
3290				};
3291			};
3292		};
3293
3294		funnel@7810000 {
3295			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3296			reg = <0 0x07810000 0 0x1000>;
3297
3298			clocks = <&aoss_qmp>;
3299			clock-names = "apb_pclk";
3300
3301			out-ports {
3302				port {
3303					apss_merge_funnel_out: endpoint {
3304						remote-endpoint = <&funnel2_in2>;
3305					};
3306				};
3307			};
3308
3309			in-ports {
3310				port {
3311					apss_merge_funnel_in: endpoint {
3312						remote-endpoint = <&apss_funnel_out>;
3313					};
3314				};
3315			};
3316		};
3317
3318		remoteproc_cdsp: remoteproc@8300000 {
3319			compatible = "qcom,sm8150-cdsp-pas";
3320			reg = <0x0 0x08300000 0x0 0x4040>;
3321
3322			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3323					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3324					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3325					      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3326					      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3327			interrupt-names = "wdog", "fatal", "ready",
3328					  "handover", "stop-ack";
3329
3330			clocks = <&rpmhcc RPMH_CXO_CLK>;
3331			clock-names = "xo";
3332
3333			power-domains = <&rpmhpd SM8150_CX>;
3334
3335			memory-region = <&cdsp_mem>;
3336
3337			qcom,qmp = <&aoss_qmp>;
3338
3339			qcom,smem-states = <&cdsp_smp2p_out 0>;
3340			qcom,smem-state-names = "stop";
3341
3342			status = "disabled";
3343
3344			glink-edge {
3345				interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3346				label = "cdsp";
3347				qcom,remote-pid = <5>;
3348				mboxes = <&apss_shared 4>;
3349
3350				fastrpc {
3351					compatible = "qcom,fastrpc";
3352					qcom,glink-channels = "fastrpcglink-apps-dsp";
3353					label = "cdsp";
3354					qcom,non-secure-domain;
3355					#address-cells = <1>;
3356					#size-cells = <0>;
3357
3358					compute-cb@1 {
3359						compatible = "qcom,fastrpc-compute-cb";
3360						reg = <1>;
3361						iommus = <&apps_smmu 0x1001 0x0460>;
3362					};
3363
3364					compute-cb@2 {
3365						compatible = "qcom,fastrpc-compute-cb";
3366						reg = <2>;
3367						iommus = <&apps_smmu 0x1002 0x0460>;
3368					};
3369
3370					compute-cb@3 {
3371						compatible = "qcom,fastrpc-compute-cb";
3372						reg = <3>;
3373						iommus = <&apps_smmu 0x1003 0x0460>;
3374					};
3375
3376					compute-cb@4 {
3377						compatible = "qcom,fastrpc-compute-cb";
3378						reg = <4>;
3379						iommus = <&apps_smmu 0x1004 0x0460>;
3380					};
3381
3382					compute-cb@5 {
3383						compatible = "qcom,fastrpc-compute-cb";
3384						reg = <5>;
3385						iommus = <&apps_smmu 0x1005 0x0460>;
3386					};
3387
3388					compute-cb@6 {
3389						compatible = "qcom,fastrpc-compute-cb";
3390						reg = <6>;
3391						iommus = <&apps_smmu 0x1006 0x0460>;
3392					};
3393
3394					compute-cb@7 {
3395						compatible = "qcom,fastrpc-compute-cb";
3396						reg = <7>;
3397						iommus = <&apps_smmu 0x1007 0x0460>;
3398					};
3399
3400					compute-cb@8 {
3401						compatible = "qcom,fastrpc-compute-cb";
3402						reg = <8>;
3403						iommus = <&apps_smmu 0x1008 0x0460>;
3404					};
3405
3406					/* note: secure cb9 in downstream */
3407				};
3408			};
3409		};
3410
3411		usb_1_hsphy: phy@88e2000 {
3412			compatible = "qcom,sm8150-usb-hs-phy",
3413				     "qcom,usb-snps-hs-7nm-phy";
3414			reg = <0 0x088e2000 0 0x400>;
3415			status = "disabled";
3416			#phy-cells = <0>;
3417
3418			clocks = <&rpmhcc RPMH_CXO_CLK>;
3419			clock-names = "ref";
3420
3421			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3422		};
3423
3424		usb_2_hsphy: phy@88e3000 {
3425			compatible = "qcom,sm8150-usb-hs-phy",
3426				     "qcom,usb-snps-hs-7nm-phy";
3427			reg = <0 0x088e3000 0 0x400>;
3428			status = "disabled";
3429			#phy-cells = <0>;
3430
3431			clocks = <&rpmhcc RPMH_CXO_CLK>;
3432			clock-names = "ref";
3433
3434			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3435		};
3436
3437		usb_1_qmpphy: phy@88e9000 {
3438			compatible = "qcom,sm8150-qmp-usb3-phy";
3439			reg = <0 0x088e9000 0 0x18c>,
3440			      <0 0x088e8000 0 0x10>;
3441			status = "disabled";
3442			#address-cells = <2>;
3443			#size-cells = <2>;
3444			ranges;
3445
3446			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3447				 <&rpmhcc RPMH_CXO_CLK>,
3448				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3449				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3450			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3451
3452			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3453				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3454			reset-names = "phy", "common";
3455
3456			usb_1_ssphy: phy@88e9200 {
3457				reg = <0 0x088e9200 0 0x200>,
3458				      <0 0x088e9400 0 0x200>,
3459				      <0 0x088e9c00 0 0x218>,
3460				      <0 0x088e9600 0 0x200>,
3461				      <0 0x088e9800 0 0x200>,
3462				      <0 0x088e9a00 0 0x100>;
3463				#clock-cells = <0>;
3464				#phy-cells = <0>;
3465				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3466				clock-names = "pipe0";
3467				clock-output-names = "usb3_phy_pipe_clk_src";
3468			};
3469		};
3470
3471		usb_2_qmpphy: phy@88eb000 {
3472			compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3473			reg = <0 0x088eb000 0 0x200>;
3474			status = "disabled";
3475			#address-cells = <2>;
3476			#size-cells = <2>;
3477			ranges;
3478
3479			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3480				 <&rpmhcc RPMH_CXO_CLK>,
3481				 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3482				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3483			clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3484
3485			resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3486				 <&gcc GCC_USB3_PHY_SEC_BCR>;
3487			reset-names = "phy", "common";
3488
3489			usb_2_ssphy: phy@88eb200 {
3490				reg = <0 0x088eb200 0 0x200>,
3491				      <0 0x088eb400 0 0x200>,
3492				      <0 0x088eb800 0 0x800>,
3493				      <0 0x088eb600 0 0x200>;
3494				#clock-cells = <0>;
3495				#phy-cells = <0>;
3496				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3497				clock-names = "pipe0";
3498				clock-output-names = "usb3_uni_phy_pipe_clk_src";
3499			};
3500		};
3501
3502		sdhc_2: mmc@8804000 {
3503			compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3504			reg = <0 0x08804000 0 0x1000>;
3505
3506			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3507				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3508			interrupt-names = "hc_irq", "pwr_irq";
3509
3510			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3511				 <&gcc GCC_SDCC2_APPS_CLK>,
3512				 <&rpmhcc RPMH_CXO_CLK>;
3513			clock-names = "iface", "core", "xo";
3514			iommus = <&apps_smmu 0x6a0 0x0>;
3515			qcom,dll-config = <0x0007642c>;
3516			qcom,ddr-config = <0x80040868>;
3517			power-domains = <&rpmhpd 0>;
3518			operating-points-v2 = <&sdhc2_opp_table>;
3519
3520			status = "disabled";
3521
3522			sdhc2_opp_table: opp-table {
3523				compatible = "operating-points-v2";
3524
3525				opp-19200000 {
3526					opp-hz = /bits/ 64 <19200000>;
3527					required-opps = <&rpmhpd_opp_min_svs>;
3528				};
3529
3530				opp-50000000 {
3531					opp-hz = /bits/ 64 <50000000>;
3532					required-opps = <&rpmhpd_opp_low_svs>;
3533				};
3534
3535				opp-100000000 {
3536					opp-hz = /bits/ 64 <100000000>;
3537					required-opps = <&rpmhpd_opp_svs>;
3538				};
3539
3540				opp-202000000 {
3541					opp-hz = /bits/ 64 <202000000>;
3542					required-opps = <&rpmhpd_opp_svs_l1>;
3543				};
3544			};
3545		};
3546
3547		dc_noc: interconnect@9160000 {
3548			compatible = "qcom,sm8150-dc-noc";
3549			reg = <0 0x09160000 0 0x3200>;
3550			#interconnect-cells = <2>;
3551			qcom,bcm-voters = <&apps_bcm_voter>;
3552		};
3553
3554		gem_noc: interconnect@9680000 {
3555			compatible = "qcom,sm8150-gem-noc";
3556			reg = <0 0x09680000 0 0x3e200>;
3557			#interconnect-cells = <2>;
3558			qcom,bcm-voters = <&apps_bcm_voter>;
3559		};
3560
3561		usb_1: usb@a6f8800 {
3562			compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3563			reg = <0 0x0a6f8800 0 0x400>;
3564			status = "disabled";
3565			#address-cells = <2>;
3566			#size-cells = <2>;
3567			ranges;
3568			dma-ranges;
3569
3570			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3571				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3572				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3573				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3574				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3575				 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3576			clock-names = "cfg_noc",
3577				      "core",
3578				      "iface",
3579				      "sleep",
3580				      "mock_utmi",
3581				      "xo";
3582
3583			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3584					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3585			assigned-clock-rates = <19200000>, <200000000>;
3586
3587			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3588				     <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3589				     <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3590				     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3591			interrupt-names = "hs_phy_irq", "ss_phy_irq",
3592					  "dm_hs_phy_irq", "dp_hs_phy_irq";
3593
3594			power-domains = <&gcc USB30_PRIM_GDSC>;
3595
3596			resets = <&gcc GCC_USB30_PRIM_BCR>;
3597
3598			interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3599					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3600			interconnect-names = "usb-ddr", "apps-usb";
3601
3602			usb_1_dwc3: usb@a600000 {
3603				compatible = "snps,dwc3";
3604				reg = <0 0x0a600000 0 0xcd00>;
3605				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3606				iommus = <&apps_smmu 0x140 0>;
3607				snps,dis_u2_susphy_quirk;
3608				snps,dis_enblslpm_quirk;
3609				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3610				phy-names = "usb2-phy", "usb3-phy";
3611			};
3612		};
3613
3614		usb_2: usb@a8f8800 {
3615			compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3616			reg = <0 0x0a8f8800 0 0x400>;
3617			status = "disabled";
3618			#address-cells = <2>;
3619			#size-cells = <2>;
3620			ranges;
3621			dma-ranges;
3622
3623			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3624				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3625				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3626				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3627				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3628				 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3629			clock-names = "cfg_noc",
3630				      "core",
3631				      "iface",
3632				      "sleep",
3633				      "mock_utmi",
3634				      "xo";
3635
3636			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3637					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
3638			assigned-clock-rates = <19200000>, <200000000>;
3639
3640			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3641				     <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3642				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3643				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3644			interrupt-names = "hs_phy_irq", "ss_phy_irq",
3645					  "dm_hs_phy_irq", "dp_hs_phy_irq";
3646
3647			power-domains = <&gcc USB30_SEC_GDSC>;
3648
3649			resets = <&gcc GCC_USB30_SEC_BCR>;
3650
3651			interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3652					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3653			interconnect-names = "usb-ddr", "apps-usb";
3654
3655			usb_2_dwc3: usb@a800000 {
3656				compatible = "snps,dwc3";
3657				reg = <0 0x0a800000 0 0xcd00>;
3658				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3659				iommus = <&apps_smmu 0x160 0>;
3660				snps,dis_u2_susphy_quirk;
3661				snps,dis_enblslpm_quirk;
3662				phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3663				phy-names = "usb2-phy", "usb3-phy";
3664			};
3665		};
3666
3667		camnoc_virt: interconnect@ac00000 {
3668			compatible = "qcom,sm8150-camnoc-virt";
3669			reg = <0 0x0ac00000 0 0x1000>;
3670			#interconnect-cells = <2>;
3671			qcom,bcm-voters = <&apps_bcm_voter>;
3672		};
3673
3674		mdss: display-subsystem@ae00000 {
3675			compatible = "qcom,sm8150-mdss";
3676			reg = <0 0x0ae00000 0 0x1000>;
3677			reg-names = "mdss";
3678
3679			interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3680					<&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3681			interconnect-names = "mdp0-mem", "mdp1-mem";
3682
3683			power-domains = <&dispcc MDSS_GDSC>;
3684
3685			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3686				 <&gcc GCC_DISP_HF_AXI_CLK>,
3687				 <&gcc GCC_DISP_SF_AXI_CLK>,
3688				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3689			clock-names = "iface", "bus", "nrt_bus", "core";
3690
3691			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3692			interrupt-controller;
3693			#interrupt-cells = <1>;
3694
3695			iommus = <&apps_smmu 0x800 0x420>;
3696
3697			status = "disabled";
3698
3699			#address-cells = <2>;
3700			#size-cells = <2>;
3701			ranges;
3702
3703			mdss_mdp: display-controller@ae01000 {
3704				compatible = "qcom,sm8150-dpu";
3705				reg = <0 0x0ae01000 0 0x8f000>,
3706				      <0 0x0aeb0000 0 0x2008>;
3707				reg-names = "mdp", "vbif";
3708
3709				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3710					 <&gcc GCC_DISP_HF_AXI_CLK>,
3711					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3712					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3713				clock-names = "iface", "bus", "core", "vsync";
3714
3715				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3716				assigned-clock-rates = <19200000>;
3717
3718				operating-points-v2 = <&mdp_opp_table>;
3719				power-domains = <&rpmhpd SM8150_MMCX>;
3720
3721				interrupt-parent = <&mdss>;
3722				interrupts = <0>;
3723
3724				ports {
3725					#address-cells = <1>;
3726					#size-cells = <0>;
3727
3728					port@0 {
3729						reg = <0>;
3730						dpu_intf1_out: endpoint {
3731							remote-endpoint = <&mdss_dsi0_in>;
3732						};
3733					};
3734
3735					port@1 {
3736						reg = <1>;
3737						dpu_intf2_out: endpoint {
3738							remote-endpoint = <&mdss_dsi1_in>;
3739						};
3740					};
3741				};
3742
3743				mdp_opp_table: opp-table {
3744					compatible = "operating-points-v2";
3745
3746					opp-171428571 {
3747						opp-hz = /bits/ 64 <171428571>;
3748						required-opps = <&rpmhpd_opp_low_svs>;
3749					};
3750
3751					opp-300000000 {
3752						opp-hz = /bits/ 64 <300000000>;
3753						required-opps = <&rpmhpd_opp_svs>;
3754					};
3755
3756					opp-345000000 {
3757						opp-hz = /bits/ 64 <345000000>;
3758						required-opps = <&rpmhpd_opp_svs_l1>;
3759					};
3760
3761					opp-460000000 {
3762						opp-hz = /bits/ 64 <460000000>;
3763						required-opps = <&rpmhpd_opp_nom>;
3764					};
3765				};
3766			};
3767
3768			mdss_dsi0: dsi@ae94000 {
3769				compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3770				reg = <0 0x0ae94000 0 0x400>;
3771				reg-names = "dsi_ctrl";
3772
3773				interrupt-parent = <&mdss>;
3774				interrupts = <4>;
3775
3776				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3777					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3778					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3779					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3780					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3781					 <&gcc GCC_DISP_HF_AXI_CLK>;
3782				clock-names = "byte",
3783					      "byte_intf",
3784					      "pixel",
3785					      "core",
3786					      "iface",
3787					      "bus";
3788
3789				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3790						  <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3791				assigned-clock-parents = <&mdss_dsi0_phy 0>,
3792							 <&mdss_dsi0_phy 1>;
3793
3794				operating-points-v2 = <&dsi_opp_table>;
3795				power-domains = <&rpmhpd SM8150_MMCX>;
3796
3797				phys = <&mdss_dsi0_phy>;
3798
3799				status = "disabled";
3800
3801				#address-cells = <1>;
3802				#size-cells = <0>;
3803
3804				ports {
3805					#address-cells = <1>;
3806					#size-cells = <0>;
3807
3808					port@0 {
3809						reg = <0>;
3810						mdss_dsi0_in: endpoint {
3811							remote-endpoint = <&dpu_intf1_out>;
3812						};
3813					};
3814
3815					port@1 {
3816						reg = <1>;
3817						mdss_dsi0_out: endpoint {
3818						};
3819					};
3820				};
3821
3822				dsi_opp_table: opp-table {
3823					compatible = "operating-points-v2";
3824
3825					opp-187500000 {
3826						opp-hz = /bits/ 64 <187500000>;
3827						required-opps = <&rpmhpd_opp_low_svs>;
3828					};
3829
3830					opp-300000000 {
3831						opp-hz = /bits/ 64 <300000000>;
3832						required-opps = <&rpmhpd_opp_svs>;
3833					};
3834
3835					opp-358000000 {
3836						opp-hz = /bits/ 64 <358000000>;
3837						required-opps = <&rpmhpd_opp_svs_l1>;
3838					};
3839				};
3840			};
3841
3842			mdss_dsi0_phy: phy@ae94400 {
3843				compatible = "qcom,dsi-phy-7nm";
3844				reg = <0 0x0ae94400 0 0x200>,
3845				      <0 0x0ae94600 0 0x280>,
3846				      <0 0x0ae94900 0 0x260>;
3847				reg-names = "dsi_phy",
3848					    "dsi_phy_lane",
3849					    "dsi_pll";
3850
3851				#clock-cells = <1>;
3852				#phy-cells = <0>;
3853
3854				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3855					 <&rpmhcc RPMH_CXO_CLK>;
3856				clock-names = "iface", "ref";
3857
3858				status = "disabled";
3859			};
3860
3861			mdss_dsi1: dsi@ae96000 {
3862				compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3863				reg = <0 0x0ae96000 0 0x400>;
3864				reg-names = "dsi_ctrl";
3865
3866				interrupt-parent = <&mdss>;
3867				interrupts = <5>;
3868
3869				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3870					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3871					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3872					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3873					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3874					 <&gcc GCC_DISP_HF_AXI_CLK>;
3875				clock-names = "byte",
3876					      "byte_intf",
3877					      "pixel",
3878					      "core",
3879					      "iface",
3880					      "bus";
3881
3882				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3883						  <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3884				assigned-clock-parents = <&mdss_dsi1_phy 0>,
3885							 <&mdss_dsi1_phy 1>;
3886
3887				operating-points-v2 = <&dsi_opp_table>;
3888				power-domains = <&rpmhpd SM8150_MMCX>;
3889
3890				phys = <&mdss_dsi1_phy>;
3891
3892				status = "disabled";
3893
3894				#address-cells = <1>;
3895				#size-cells = <0>;
3896
3897				ports {
3898					#address-cells = <1>;
3899					#size-cells = <0>;
3900
3901					port@0 {
3902						reg = <0>;
3903						mdss_dsi1_in: endpoint {
3904							remote-endpoint = <&dpu_intf2_out>;
3905						};
3906					};
3907
3908					port@1 {
3909						reg = <1>;
3910						mdss_dsi1_out: endpoint {
3911						};
3912					};
3913				};
3914			};
3915
3916			mdss_dsi1_phy: phy@ae96400 {
3917				compatible = "qcom,dsi-phy-7nm";
3918				reg = <0 0x0ae96400 0 0x200>,
3919				      <0 0x0ae96600 0 0x280>,
3920				      <0 0x0ae96900 0 0x260>;
3921				reg-names = "dsi_phy",
3922					    "dsi_phy_lane",
3923					    "dsi_pll";
3924
3925				#clock-cells = <1>;
3926				#phy-cells = <0>;
3927
3928				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3929					 <&rpmhcc RPMH_CXO_CLK>;
3930				clock-names = "iface", "ref";
3931
3932				status = "disabled";
3933			};
3934		};
3935
3936		dispcc: clock-controller@af00000 {
3937			compatible = "qcom,sm8150-dispcc";
3938			reg = <0 0x0af00000 0 0x10000>;
3939			clocks = <&rpmhcc RPMH_CXO_CLK>,
3940				 <&mdss_dsi0_phy 0>,
3941				 <&mdss_dsi0_phy 1>,
3942				 <&mdss_dsi1_phy 0>,
3943				 <&mdss_dsi1_phy 1>,
3944				 <0>,
3945				 <0>;
3946			clock-names = "bi_tcxo",
3947				      "dsi0_phy_pll_out_byteclk",
3948				      "dsi0_phy_pll_out_dsiclk",
3949				      "dsi1_phy_pll_out_byteclk",
3950				      "dsi1_phy_pll_out_dsiclk",
3951				      "dp_phy_pll_link_clk",
3952				      "dp_phy_pll_vco_div_clk";
3953			power-domains = <&rpmhpd SM8150_MMCX>;
3954			#clock-cells = <1>;
3955			#reset-cells = <1>;
3956			#power-domain-cells = <1>;
3957		};
3958
3959		pdc: interrupt-controller@b220000 {
3960			compatible = "qcom,sm8150-pdc", "qcom,pdc";
3961			reg = <0 0x0b220000 0 0x400>;
3962			qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3963					  <125 63 1>;
3964			#interrupt-cells = <2>;
3965			interrupt-parent = <&intc>;
3966			interrupt-controller;
3967		};
3968
3969		aoss_qmp: power-management@c300000 {
3970			compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
3971			reg = <0x0 0x0c300000 0x0 0x400>;
3972			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3973			mboxes = <&apss_shared 0>;
3974
3975			#clock-cells = <0>;
3976		};
3977
3978		sram@c3f0000 {
3979			compatible = "qcom,rpmh-stats";
3980			reg = <0 0x0c3f0000 0 0x400>;
3981		};
3982
3983		tsens0: thermal-sensor@c263000 {
3984			compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3985			reg = <0 0x0c263000 0 0x1ff>, /* TM */
3986			      <0 0x0c222000 0 0x1ff>; /* SROT */
3987			#qcom,sensors = <16>;
3988			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3989				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3990			interrupt-names = "uplow", "critical";
3991			#thermal-sensor-cells = <1>;
3992		};
3993
3994		tsens1: thermal-sensor@c265000 {
3995			compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3996			reg = <0 0x0c265000 0 0x1ff>, /* TM */
3997			      <0 0x0c223000 0 0x1ff>; /* SROT */
3998			#qcom,sensors = <8>;
3999			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4000				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4001			interrupt-names = "uplow", "critical";
4002			#thermal-sensor-cells = <1>;
4003		};
4004
4005		spmi_bus: spmi@c440000 {
4006			compatible = "qcom,spmi-pmic-arb";
4007			reg = <0x0 0x0c440000 0x0 0x0001100>,
4008			      <0x0 0x0c600000 0x0 0x2000000>,
4009			      <0x0 0x0e600000 0x0 0x0100000>,
4010			      <0x0 0x0e700000 0x0 0x00a0000>,
4011			      <0x0 0x0c40a000 0x0 0x0026000>;
4012			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4013			interrupt-names = "periph_irq";
4014			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4015			qcom,ee = <0>;
4016			qcom,channel = <0>;
4017			#address-cells = <2>;
4018			#size-cells = <0>;
4019			interrupt-controller;
4020			#interrupt-cells = <4>;
4021		};
4022
4023		apps_smmu: iommu@15000000 {
4024			compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4025			reg = <0 0x15000000 0 0x100000>;
4026			#iommu-cells = <2>;
4027			#global-interrupts = <1>;
4028			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4029				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4030				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4031				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4032				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4033				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4034				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4035				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4036				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4037				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4038				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4039				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4040				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4041				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4042				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4043				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4044				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4045				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4046				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4047				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4048				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4049				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4050				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4051				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4052				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4053				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4054				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4055				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4056				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4057				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4058				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4059				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4060				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4061				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4062				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4063				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4064				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4065				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4066				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4067				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4068				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4069				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4070				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4071				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4072				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4073				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4074				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4075				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4076				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4077				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4078				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4079				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4080				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4081				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4082				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4083				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4084				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4085				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4086				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4087				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4088				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4089				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4090				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4091				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4092				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4093				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4094				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4095				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4096				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4097				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4098				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4099				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4100				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4101				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4102				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4103				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4104				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4105				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4106				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4107				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4108				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4109		};
4110
4111		remoteproc_adsp: remoteproc@17300000 {
4112			compatible = "qcom,sm8150-adsp-pas";
4113			reg = <0x0 0x17300000 0x0 0x4040>;
4114
4115			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4116					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4117					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4118					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4119					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4120			interrupt-names = "wdog", "fatal", "ready",
4121					  "handover", "stop-ack";
4122
4123			clocks = <&rpmhcc RPMH_CXO_CLK>;
4124			clock-names = "xo";
4125
4126			power-domains = <&rpmhpd SM8150_CX>;
4127
4128			memory-region = <&adsp_mem>;
4129
4130			qcom,qmp = <&aoss_qmp>;
4131
4132			qcom,smem-states = <&adsp_smp2p_out 0>;
4133			qcom,smem-state-names = "stop";
4134
4135			status = "disabled";
4136
4137			glink-edge {
4138				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4139				label = "lpass";
4140				qcom,remote-pid = <2>;
4141				mboxes = <&apss_shared 8>;
4142
4143				fastrpc {
4144					compatible = "qcom,fastrpc";
4145					qcom,glink-channels = "fastrpcglink-apps-dsp";
4146					label = "adsp";
4147					qcom,non-secure-domain;
4148					#address-cells = <1>;
4149					#size-cells = <0>;
4150
4151					compute-cb@3 {
4152						compatible = "qcom,fastrpc-compute-cb";
4153						reg = <3>;
4154						iommus = <&apps_smmu 0x1b23 0x0>;
4155					};
4156
4157					compute-cb@4 {
4158						compatible = "qcom,fastrpc-compute-cb";
4159						reg = <4>;
4160						iommus = <&apps_smmu 0x1b24 0x0>;
4161					};
4162
4163					compute-cb@5 {
4164						compatible = "qcom,fastrpc-compute-cb";
4165						reg = <5>;
4166						iommus = <&apps_smmu 0x1b25 0x0>;
4167					};
4168				};
4169			};
4170		};
4171
4172		intc: interrupt-controller@17a00000 {
4173			compatible = "arm,gic-v3";
4174			interrupt-controller;
4175			#interrupt-cells = <3>;
4176			reg = <0x0 0x17a00000 0x0 0x10000>,	/* GICD */
4177			      <0x0 0x17a60000 0x0 0x100000>;	/* GICR * 8 */
4178			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4179		};
4180
4181		apss_shared: mailbox@17c00000 {
4182			compatible = "qcom,sm8150-apss-shared",
4183				     "qcom,sdm845-apss-shared";
4184			reg = <0x0 0x17c00000 0x0 0x1000>;
4185			#mbox-cells = <1>;
4186		};
4187
4188		watchdog@17c10000 {
4189			compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4190			reg = <0 0x17c10000 0 0x1000>;
4191			clocks = <&sleep_clk>;
4192			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4193		};
4194
4195		timer@17c20000 {
4196			#address-cells = <1>;
4197			#size-cells = <1>;
4198			ranges = <0 0 0 0x20000000>;
4199			compatible = "arm,armv7-timer-mem";
4200			reg = <0x0 0x17c20000 0x0 0x1000>;
4201			clock-frequency = <19200000>;
4202
4203			frame@17c21000 {
4204				frame-number = <0>;
4205				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4206					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4207				reg = <0x17c21000 0x1000>,
4208				      <0x17c22000 0x1000>;
4209			};
4210
4211			frame@17c23000 {
4212				frame-number = <1>;
4213				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4214				reg = <0x17c23000 0x1000>;
4215				status = "disabled";
4216			};
4217
4218			frame@17c25000 {
4219				frame-number = <2>;
4220				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4221				reg = <0x17c25000 0x1000>;
4222				status = "disabled";
4223			};
4224
4225			frame@17c27000 {
4226				frame-number = <3>;
4227				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4228				reg = <0x17c26000 0x1000>;
4229				status = "disabled";
4230			};
4231
4232			frame@17c29000 {
4233				frame-number = <4>;
4234				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4235				reg = <0x17c29000 0x1000>;
4236				status = "disabled";
4237			};
4238
4239			frame@17c2b000 {
4240				frame-number = <5>;
4241				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4242				reg = <0x17c2b000 0x1000>;
4243				status = "disabled";
4244			};
4245
4246			frame@17c2d000 {
4247				frame-number = <6>;
4248				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4249				reg = <0x17c2d000 0x1000>;
4250				status = "disabled";
4251			};
4252		};
4253
4254		apps_rsc: rsc@18200000 {
4255			label = "apps_rsc";
4256			compatible = "qcom,rpmh-rsc";
4257			reg = <0x0 0x18200000 0x0 0x10000>,
4258			      <0x0 0x18210000 0x0 0x10000>,
4259			      <0x0 0x18220000 0x0 0x10000>;
4260			reg-names = "drv-0", "drv-1", "drv-2";
4261			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4262				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4263				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4264			qcom,tcs-offset = <0xd00>;
4265			qcom,drv-id = <2>;
4266			qcom,tcs-config = <ACTIVE_TCS  2>,
4267					  <SLEEP_TCS   3>,
4268					  <WAKE_TCS    3>,
4269					  <CONTROL_TCS 1>;
4270			power-domains = <&CLUSTER_PD>;
4271
4272			rpmhcc: clock-controller {
4273				compatible = "qcom,sm8150-rpmh-clk";
4274				#clock-cells = <1>;
4275				clock-names = "xo";
4276				clocks = <&xo_board>;
4277			};
4278
4279			rpmhpd: power-controller {
4280				compatible = "qcom,sm8150-rpmhpd";
4281				#power-domain-cells = <1>;
4282				operating-points-v2 = <&rpmhpd_opp_table>;
4283
4284				rpmhpd_opp_table: opp-table {
4285					compatible = "operating-points-v2";
4286
4287					rpmhpd_opp_ret: opp1 {
4288						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4289					};
4290
4291					rpmhpd_opp_min_svs: opp2 {
4292						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4293					};
4294
4295					rpmhpd_opp_low_svs: opp3 {
4296						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4297					};
4298
4299					rpmhpd_opp_svs: opp4 {
4300						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4301					};
4302
4303					rpmhpd_opp_svs_l1: opp5 {
4304						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4305					};
4306
4307					rpmhpd_opp_svs_l2: opp6 {
4308						opp-level = <224>;
4309					};
4310
4311					rpmhpd_opp_nom: opp7 {
4312						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4313					};
4314
4315					rpmhpd_opp_nom_l1: opp8 {
4316						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4317					};
4318
4319					rpmhpd_opp_nom_l2: opp9 {
4320						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4321					};
4322
4323					rpmhpd_opp_turbo: opp10 {
4324						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4325					};
4326
4327					rpmhpd_opp_turbo_l1: opp11 {
4328						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4329					};
4330				};
4331			};
4332
4333			apps_bcm_voter: bcm-voter {
4334				compatible = "qcom,bcm-voter";
4335			};
4336		};
4337
4338		osm_l3: interconnect@18321000 {
4339			compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4340			reg = <0 0x18321000 0 0x1400>;
4341
4342			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4343			clock-names = "xo", "alternate";
4344
4345			#interconnect-cells = <1>;
4346		};
4347
4348		cpufreq_hw: cpufreq@18323000 {
4349			compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4350			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4351			      <0 0x18327800 0 0x1400>;
4352			reg-names = "freq-domain0", "freq-domain1",
4353				    "freq-domain2";
4354
4355			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4356			clock-names = "xo", "alternate";
4357
4358			#freq-domain-cells = <1>;
4359			#clock-cells = <1>;
4360		};
4361
4362		lmh_cluster1: lmh@18350800 {
4363			compatible = "qcom,sm8150-lmh";
4364			reg = <0 0x18350800 0 0x400>;
4365			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4366			cpus = <&CPU4>;
4367			qcom,lmh-temp-arm-millicelsius = <60000>;
4368			qcom,lmh-temp-low-millicelsius = <84500>;
4369			qcom,lmh-temp-high-millicelsius = <85000>;
4370			interrupt-controller;
4371			#interrupt-cells = <1>;
4372		};
4373
4374		lmh_cluster0: lmh@18358800 {
4375			compatible = "qcom,sm8150-lmh";
4376			reg = <0 0x18358800 0 0x400>;
4377			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4378			cpus = <&CPU0>;
4379			qcom,lmh-temp-arm-millicelsius = <60000>;
4380			qcom,lmh-temp-low-millicelsius = <84500>;
4381			qcom,lmh-temp-high-millicelsius = <85000>;
4382			interrupt-controller;
4383			#interrupt-cells = <1>;
4384		};
4385
4386		wifi: wifi@18800000 {
4387			compatible = "qcom,wcn3990-wifi";
4388			reg = <0 0x18800000 0 0x800000>;
4389			reg-names = "membase";
4390			memory-region = <&wlan_mem>;
4391			clock-names = "cxo_ref_clk_pin", "qdss";
4392			clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4393			interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4394				     <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4395				     <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4396				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4397				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4398				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4399				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4400				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4401				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4402				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4403				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4404				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4405			iommus = <&apps_smmu 0x0640 0x1>;
4406			status = "disabled";
4407		};
4408	};
4409
4410	timer {
4411		compatible = "arm,armv8-timer";
4412		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4413			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4414			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4415			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4416	};
4417
4418	thermal-zones {
4419		cpu0-thermal {
4420			polling-delay-passive = <250>;
4421			polling-delay = <1000>;
4422
4423			thermal-sensors = <&tsens0 1>;
4424
4425			trips {
4426				cpu0_alert0: trip-point0 {
4427					temperature = <90000>;
4428					hysteresis = <2000>;
4429					type = "passive";
4430				};
4431
4432				cpu0_alert1: trip-point1 {
4433					temperature = <95000>;
4434					hysteresis = <2000>;
4435					type = "passive";
4436				};
4437
4438				cpu0_crit: cpu-crit {
4439					temperature = <110000>;
4440					hysteresis = <1000>;
4441					type = "critical";
4442				};
4443			};
4444
4445			cooling-maps {
4446				map0 {
4447					trip = <&cpu0_alert0>;
4448					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4449							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4450							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4451							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4452				};
4453				map1 {
4454					trip = <&cpu0_alert1>;
4455					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4456							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4457							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4458							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4459				};
4460			};
4461		};
4462
4463		cpu1-thermal {
4464			polling-delay-passive = <250>;
4465			polling-delay = <1000>;
4466
4467			thermal-sensors = <&tsens0 2>;
4468
4469			trips {
4470				cpu1_alert0: trip-point0 {
4471					temperature = <90000>;
4472					hysteresis = <2000>;
4473					type = "passive";
4474				};
4475
4476				cpu1_alert1: trip-point1 {
4477					temperature = <95000>;
4478					hysteresis = <2000>;
4479					type = "passive";
4480				};
4481
4482				cpu1_crit: cpu-crit {
4483					temperature = <110000>;
4484					hysteresis = <1000>;
4485					type = "critical";
4486				};
4487			};
4488
4489			cooling-maps {
4490				map0 {
4491					trip = <&cpu1_alert0>;
4492					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4493							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4494							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4495							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4496				};
4497				map1 {
4498					trip = <&cpu1_alert1>;
4499					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4500							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4501							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4502							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4503				};
4504			};
4505		};
4506
4507		cpu2-thermal {
4508			polling-delay-passive = <250>;
4509			polling-delay = <1000>;
4510
4511			thermal-sensors = <&tsens0 3>;
4512
4513			trips {
4514				cpu2_alert0: trip-point0 {
4515					temperature = <90000>;
4516					hysteresis = <2000>;
4517					type = "passive";
4518				};
4519
4520				cpu2_alert1: trip-point1 {
4521					temperature = <95000>;
4522					hysteresis = <2000>;
4523					type = "passive";
4524				};
4525
4526				cpu2_crit: cpu-crit {
4527					temperature = <110000>;
4528					hysteresis = <1000>;
4529					type = "critical";
4530				};
4531			};
4532
4533			cooling-maps {
4534				map0 {
4535					trip = <&cpu2_alert0>;
4536					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4537							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4538							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4539							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4540				};
4541				map1 {
4542					trip = <&cpu2_alert1>;
4543					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4544							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4545							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4546							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4547				};
4548			};
4549		};
4550
4551		cpu3-thermal {
4552			polling-delay-passive = <250>;
4553			polling-delay = <1000>;
4554
4555			thermal-sensors = <&tsens0 4>;
4556
4557			trips {
4558				cpu3_alert0: trip-point0 {
4559					temperature = <90000>;
4560					hysteresis = <2000>;
4561					type = "passive";
4562				};
4563
4564				cpu3_alert1: trip-point1 {
4565					temperature = <95000>;
4566					hysteresis = <2000>;
4567					type = "passive";
4568				};
4569
4570				cpu3_crit: cpu-crit {
4571					temperature = <110000>;
4572					hysteresis = <1000>;
4573					type = "critical";
4574				};
4575			};
4576
4577			cooling-maps {
4578				map0 {
4579					trip = <&cpu3_alert0>;
4580					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4581							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4582							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4583							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4584				};
4585				map1 {
4586					trip = <&cpu3_alert1>;
4587					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4588							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4589							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4590							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4591				};
4592			};
4593		};
4594
4595		cpu4-top-thermal {
4596			polling-delay-passive = <250>;
4597			polling-delay = <1000>;
4598
4599			thermal-sensors = <&tsens0 7>;
4600
4601			trips {
4602				cpu4_top_alert0: trip-point0 {
4603					temperature = <90000>;
4604					hysteresis = <2000>;
4605					type = "passive";
4606				};
4607
4608				cpu4_top_alert1: trip-point1 {
4609					temperature = <95000>;
4610					hysteresis = <2000>;
4611					type = "passive";
4612				};
4613
4614				cpu4_top_crit: cpu-crit {
4615					temperature = <110000>;
4616					hysteresis = <1000>;
4617					type = "critical";
4618				};
4619			};
4620
4621			cooling-maps {
4622				map0 {
4623					trip = <&cpu4_top_alert0>;
4624					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4625							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4626							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4627							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4628				};
4629				map1 {
4630					trip = <&cpu4_top_alert1>;
4631					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4632							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4633							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4634							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4635				};
4636			};
4637		};
4638
4639		cpu5-top-thermal {
4640			polling-delay-passive = <250>;
4641			polling-delay = <1000>;
4642
4643			thermal-sensors = <&tsens0 8>;
4644
4645			trips {
4646				cpu5_top_alert0: trip-point0 {
4647					temperature = <90000>;
4648					hysteresis = <2000>;
4649					type = "passive";
4650				};
4651
4652				cpu5_top_alert1: trip-point1 {
4653					temperature = <95000>;
4654					hysteresis = <2000>;
4655					type = "passive";
4656				};
4657
4658				cpu5_top_crit: cpu-crit {
4659					temperature = <110000>;
4660					hysteresis = <1000>;
4661					type = "critical";
4662				};
4663			};
4664
4665			cooling-maps {
4666				map0 {
4667					trip = <&cpu5_top_alert0>;
4668					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4669							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4670							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4671							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4672				};
4673				map1 {
4674					trip = <&cpu5_top_alert1>;
4675					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4676							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4677							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4678							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4679				};
4680			};
4681		};
4682
4683		cpu6-top-thermal {
4684			polling-delay-passive = <250>;
4685			polling-delay = <1000>;
4686
4687			thermal-sensors = <&tsens0 9>;
4688
4689			trips {
4690				cpu6_top_alert0: trip-point0 {
4691					temperature = <90000>;
4692					hysteresis = <2000>;
4693					type = "passive";
4694				};
4695
4696				cpu6_top_alert1: trip-point1 {
4697					temperature = <95000>;
4698					hysteresis = <2000>;
4699					type = "passive";
4700				};
4701
4702				cpu6_top_crit: cpu-crit {
4703					temperature = <110000>;
4704					hysteresis = <1000>;
4705					type = "critical";
4706				};
4707			};
4708
4709			cooling-maps {
4710				map0 {
4711					trip = <&cpu6_top_alert0>;
4712					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4713							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4714							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4715							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4716				};
4717				map1 {
4718					trip = <&cpu6_top_alert1>;
4719					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4720							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4721							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4722							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4723				};
4724			};
4725		};
4726
4727		cpu7-top-thermal {
4728			polling-delay-passive = <250>;
4729			polling-delay = <1000>;
4730
4731			thermal-sensors = <&tsens0 10>;
4732
4733			trips {
4734				cpu7_top_alert0: trip-point0 {
4735					temperature = <90000>;
4736					hysteresis = <2000>;
4737					type = "passive";
4738				};
4739
4740				cpu7_top_alert1: trip-point1 {
4741					temperature = <95000>;
4742					hysteresis = <2000>;
4743					type = "passive";
4744				};
4745
4746				cpu7_top_crit: cpu-crit {
4747					temperature = <110000>;
4748					hysteresis = <1000>;
4749					type = "critical";
4750				};
4751			};
4752
4753			cooling-maps {
4754				map0 {
4755					trip = <&cpu7_top_alert0>;
4756					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4757							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4758							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4759							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4760				};
4761				map1 {
4762					trip = <&cpu7_top_alert1>;
4763					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4764							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4765							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4766							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4767				};
4768			};
4769		};
4770
4771		cpu4-bottom-thermal {
4772			polling-delay-passive = <250>;
4773			polling-delay = <1000>;
4774
4775			thermal-sensors = <&tsens0 11>;
4776
4777			trips {
4778				cpu4_bottom_alert0: trip-point0 {
4779					temperature = <90000>;
4780					hysteresis = <2000>;
4781					type = "passive";
4782				};
4783
4784				cpu4_bottom_alert1: trip-point1 {
4785					temperature = <95000>;
4786					hysteresis = <2000>;
4787					type = "passive";
4788				};
4789
4790				cpu4_bottom_crit: cpu-crit {
4791					temperature = <110000>;
4792					hysteresis = <1000>;
4793					type = "critical";
4794				};
4795			};
4796
4797			cooling-maps {
4798				map0 {
4799					trip = <&cpu4_bottom_alert0>;
4800					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4801							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4802							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4803							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4804				};
4805				map1 {
4806					trip = <&cpu4_bottom_alert1>;
4807					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4808							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4809							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4811				};
4812			};
4813		};
4814
4815		cpu5-bottom-thermal {
4816			polling-delay-passive = <250>;
4817			polling-delay = <1000>;
4818
4819			thermal-sensors = <&tsens0 12>;
4820
4821			trips {
4822				cpu5_bottom_alert0: trip-point0 {
4823					temperature = <90000>;
4824					hysteresis = <2000>;
4825					type = "passive";
4826				};
4827
4828				cpu5_bottom_alert1: trip-point1 {
4829					temperature = <95000>;
4830					hysteresis = <2000>;
4831					type = "passive";
4832				};
4833
4834				cpu5_bottom_crit: cpu-crit {
4835					temperature = <110000>;
4836					hysteresis = <1000>;
4837					type = "critical";
4838				};
4839			};
4840
4841			cooling-maps {
4842				map0 {
4843					trip = <&cpu5_bottom_alert0>;
4844					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4845							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4846							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4847							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4848				};
4849				map1 {
4850					trip = <&cpu5_bottom_alert1>;
4851					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4852							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4855				};
4856			};
4857		};
4858
4859		cpu6-bottom-thermal {
4860			polling-delay-passive = <250>;
4861			polling-delay = <1000>;
4862
4863			thermal-sensors = <&tsens0 13>;
4864
4865			trips {
4866				cpu6_bottom_alert0: trip-point0 {
4867					temperature = <90000>;
4868					hysteresis = <2000>;
4869					type = "passive";
4870				};
4871
4872				cpu6_bottom_alert1: trip-point1 {
4873					temperature = <95000>;
4874					hysteresis = <2000>;
4875					type = "passive";
4876				};
4877
4878				cpu6_bottom_crit: cpu-crit {
4879					temperature = <110000>;
4880					hysteresis = <1000>;
4881					type = "critical";
4882				};
4883			};
4884
4885			cooling-maps {
4886				map0 {
4887					trip = <&cpu6_bottom_alert0>;
4888					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4889							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4890							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4891							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4892				};
4893				map1 {
4894					trip = <&cpu6_bottom_alert1>;
4895					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899				};
4900			};
4901		};
4902
4903		cpu7-bottom-thermal {
4904			polling-delay-passive = <250>;
4905			polling-delay = <1000>;
4906
4907			thermal-sensors = <&tsens0 14>;
4908
4909			trips {
4910				cpu7_bottom_alert0: trip-point0 {
4911					temperature = <90000>;
4912					hysteresis = <2000>;
4913					type = "passive";
4914				};
4915
4916				cpu7_bottom_alert1: trip-point1 {
4917					temperature = <95000>;
4918					hysteresis = <2000>;
4919					type = "passive";
4920				};
4921
4922				cpu7_bottom_crit: cpu-crit {
4923					temperature = <110000>;
4924					hysteresis = <1000>;
4925					type = "critical";
4926				};
4927			};
4928
4929			cooling-maps {
4930				map0 {
4931					trip = <&cpu7_bottom_alert0>;
4932					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4933							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4934							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4935							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4936				};
4937				map1 {
4938					trip = <&cpu7_bottom_alert1>;
4939					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4942							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4943				};
4944			};
4945		};
4946
4947		aoss0-thermal {
4948			polling-delay-passive = <250>;
4949			polling-delay = <1000>;
4950
4951			thermal-sensors = <&tsens0 0>;
4952
4953			trips {
4954				aoss0_alert0: trip-point0 {
4955					temperature = <90000>;
4956					hysteresis = <2000>;
4957					type = "hot";
4958				};
4959			};
4960		};
4961
4962		cluster0-thermal {
4963			polling-delay-passive = <250>;
4964			polling-delay = <1000>;
4965
4966			thermal-sensors = <&tsens0 5>;
4967
4968			trips {
4969				cluster0_alert0: trip-point0 {
4970					temperature = <90000>;
4971					hysteresis = <2000>;
4972					type = "hot";
4973				};
4974				cluster0_crit: cluster0_crit {
4975					temperature = <110000>;
4976					hysteresis = <2000>;
4977					type = "critical";
4978				};
4979			};
4980		};
4981
4982		cluster1-thermal {
4983			polling-delay-passive = <250>;
4984			polling-delay = <1000>;
4985
4986			thermal-sensors = <&tsens0 6>;
4987
4988			trips {
4989				cluster1_alert0: trip-point0 {
4990					temperature = <90000>;
4991					hysteresis = <2000>;
4992					type = "hot";
4993				};
4994				cluster1_crit: cluster1_crit {
4995					temperature = <110000>;
4996					hysteresis = <2000>;
4997					type = "critical";
4998				};
4999			};
5000		};
5001
5002		gpu-top-thermal {
5003			polling-delay-passive = <250>;
5004			polling-delay = <1000>;
5005
5006			thermal-sensors = <&tsens0 15>;
5007
5008			trips {
5009				gpu1_alert0: trip-point0 {
5010					temperature = <90000>;
5011					hysteresis = <2000>;
5012					type = "hot";
5013				};
5014			};
5015		};
5016
5017		aoss1-thermal {
5018			polling-delay-passive = <250>;
5019			polling-delay = <1000>;
5020
5021			thermal-sensors = <&tsens1 0>;
5022
5023			trips {
5024				aoss1_alert0: trip-point0 {
5025					temperature = <90000>;
5026					hysteresis = <2000>;
5027					type = "hot";
5028				};
5029			};
5030		};
5031
5032		wlan-thermal {
5033			polling-delay-passive = <250>;
5034			polling-delay = <1000>;
5035
5036			thermal-sensors = <&tsens1 1>;
5037
5038			trips {
5039				wlan_alert0: trip-point0 {
5040					temperature = <90000>;
5041					hysteresis = <2000>;
5042					type = "hot";
5043				};
5044			};
5045		};
5046
5047		video-thermal {
5048			polling-delay-passive = <250>;
5049			polling-delay = <1000>;
5050
5051			thermal-sensors = <&tsens1 2>;
5052
5053			trips {
5054				video_alert0: trip-point0 {
5055					temperature = <90000>;
5056					hysteresis = <2000>;
5057					type = "hot";
5058				};
5059			};
5060		};
5061
5062		mem-thermal {
5063			polling-delay-passive = <250>;
5064			polling-delay = <1000>;
5065
5066			thermal-sensors = <&tsens1 3>;
5067
5068			trips {
5069				mem_alert0: trip-point0 {
5070					temperature = <90000>;
5071					hysteresis = <2000>;
5072					type = "hot";
5073				};
5074			};
5075		};
5076
5077		q6-hvx-thermal {
5078			polling-delay-passive = <250>;
5079			polling-delay = <1000>;
5080
5081			thermal-sensors = <&tsens1 4>;
5082
5083			trips {
5084				q6_hvx_alert0: trip-point0 {
5085					temperature = <90000>;
5086					hysteresis = <2000>;
5087					type = "hot";
5088				};
5089			};
5090		};
5091
5092		camera-thermal {
5093			polling-delay-passive = <250>;
5094			polling-delay = <1000>;
5095
5096			thermal-sensors = <&tsens1 5>;
5097
5098			trips {
5099				camera_alert0: trip-point0 {
5100					temperature = <90000>;
5101					hysteresis = <2000>;
5102					type = "hot";
5103				};
5104			};
5105		};
5106
5107		compute-thermal {
5108			polling-delay-passive = <250>;
5109			polling-delay = <1000>;
5110
5111			thermal-sensors = <&tsens1 6>;
5112
5113			trips {
5114				compute_alert0: trip-point0 {
5115					temperature = <90000>;
5116					hysteresis = <2000>;
5117					type = "hot";
5118				};
5119			};
5120		};
5121
5122		modem-thermal {
5123			polling-delay-passive = <250>;
5124			polling-delay = <1000>;
5125
5126			thermal-sensors = <&tsens1 7>;
5127
5128			trips {
5129				modem_alert0: trip-point0 {
5130					temperature = <90000>;
5131					hysteresis = <2000>;
5132					type = "hot";
5133				};
5134			};
5135		};
5136
5137		npu-thermal {
5138			polling-delay-passive = <250>;
5139			polling-delay = <1000>;
5140
5141			thermal-sensors = <&tsens1 8>;
5142
5143			trips {
5144				npu_alert0: trip-point0 {
5145					temperature = <90000>;
5146					hysteresis = <2000>;
5147					type = "hot";
5148				};
5149			};
5150		};
5151
5152		modem-vec-thermal {
5153			polling-delay-passive = <250>;
5154			polling-delay = <1000>;
5155
5156			thermal-sensors = <&tsens1 9>;
5157
5158			trips {
5159				modem_vec_alert0: trip-point0 {
5160					temperature = <90000>;
5161					hysteresis = <2000>;
5162					type = "hot";
5163				};
5164			};
5165		};
5166
5167		modem-scl-thermal {
5168			polling-delay-passive = <250>;
5169			polling-delay = <1000>;
5170
5171			thermal-sensors = <&tsens1 10>;
5172
5173			trips {
5174				modem_scl_alert0: trip-point0 {
5175					temperature = <90000>;
5176					hysteresis = <2000>;
5177					type = "hot";
5178				};
5179			};
5180		};
5181
5182		gpu-bottom-thermal {
5183			polling-delay-passive = <250>;
5184			polling-delay = <1000>;
5185
5186			thermal-sensors = <&tsens1 11>;
5187
5188			trips {
5189				gpu2_alert0: trip-point0 {
5190					temperature = <90000>;
5191					hysteresis = <2000>;
5192					type = "hot";
5193				};
5194			};
5195		};
5196	};
5197};
5198