1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/power/qcom-aoss-qmp.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,gcc-sm8150.h> 13#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <38400000>; 30 clock-output-names = "xo_board"; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32764>; 37 clock-output-names = "sleep_clk"; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "qcom,kryo485"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 next-level-cache = <&L2_0>; 51 qcom,freq-domain = <&cpufreq_hw 0>; 52 #cooling-cells = <2>; 53 L2_0: l2-cache { 54 compatible = "cache"; 55 next-level-cache = <&L3_0>; 56 L3_0: l3-cache { 57 compatible = "cache"; 58 }; 59 }; 60 }; 61 62 CPU1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo485"; 65 reg = <0x0 0x100>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_100>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 #cooling-cells = <2>; 70 L2_100: l2-cache { 71 compatible = "cache"; 72 next-level-cache = <&L3_0>; 73 }; 74 75 }; 76 77 CPU2: cpu@200 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo485"; 80 reg = <0x0 0x200>; 81 enable-method = "psci"; 82 next-level-cache = <&L2_200>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 #cooling-cells = <2>; 85 L2_200: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 }; 90 91 CPU3: cpu@300 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo485"; 94 reg = <0x0 0x300>; 95 enable-method = "psci"; 96 next-level-cache = <&L2_300>; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 #cooling-cells = <2>; 99 L2_300: l2-cache { 100 compatible = "cache"; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU4: cpu@400 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo485"; 108 reg = <0x0 0x400>; 109 enable-method = "psci"; 110 next-level-cache = <&L2_400>; 111 qcom,freq-domain = <&cpufreq_hw 1>; 112 #cooling-cells = <2>; 113 L2_400: l2-cache { 114 compatible = "cache"; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU5: cpu@500 { 120 device_type = "cpu"; 121 compatible = "qcom,kryo485"; 122 reg = <0x0 0x500>; 123 enable-method = "psci"; 124 next-level-cache = <&L2_500>; 125 qcom,freq-domain = <&cpufreq_hw 1>; 126 #cooling-cells = <2>; 127 L2_500: l2-cache { 128 compatible = "cache"; 129 next-level-cache = <&L3_0>; 130 }; 131 }; 132 133 CPU6: cpu@600 { 134 device_type = "cpu"; 135 compatible = "qcom,kryo485"; 136 reg = <0x0 0x600>; 137 enable-method = "psci"; 138 next-level-cache = <&L2_600>; 139 qcom,freq-domain = <&cpufreq_hw 1>; 140 #cooling-cells = <2>; 141 L2_600: l2-cache { 142 compatible = "cache"; 143 next-level-cache = <&L3_0>; 144 }; 145 }; 146 147 CPU7: cpu@700 { 148 device_type = "cpu"; 149 compatible = "qcom,kryo485"; 150 reg = <0x0 0x700>; 151 enable-method = "psci"; 152 next-level-cache = <&L2_700>; 153 qcom,freq-domain = <&cpufreq_hw 2>; 154 #cooling-cells = <2>; 155 L2_700: l2-cache { 156 compatible = "cache"; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 }; 161 162 firmware { 163 scm: scm { 164 compatible = "qcom,scm-sm8150", "qcom,scm"; 165 #reset-cells = <1>; 166 }; 167 }; 168 169 tcsr_mutex: hwlock { 170 compatible = "qcom,tcsr-mutex"; 171 syscon = <&tcsr_mutex_regs 0 0x1000>; 172 #hwlock-cells = <1>; 173 }; 174 175 memory@80000000 { 176 device_type = "memory"; 177 /* We expect the bootloader to fill in the size */ 178 reg = <0x0 0x80000000 0x0 0x0>; 179 }; 180 181 pmu { 182 compatible = "arm,armv8-pmuv3"; 183 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 184 }; 185 186 psci { 187 compatible = "arm,psci-1.0"; 188 method = "smc"; 189 }; 190 191 reserved-memory { 192 #address-cells = <2>; 193 #size-cells = <2>; 194 ranges; 195 196 hyp_mem: memory@85700000 { 197 reg = <0x0 0x85700000 0x0 0x600000>; 198 no-map; 199 }; 200 201 xbl_mem: memory@85d00000 { 202 reg = <0x0 0x85d00000 0x0 0x140000>; 203 no-map; 204 }; 205 206 aop_mem: memory@85f00000 { 207 reg = <0x0 0x85f00000 0x0 0x20000>; 208 no-map; 209 }; 210 211 aop_cmd_db: memory@85f20000 { 212 compatible = "qcom,cmd-db"; 213 reg = <0x0 0x85f20000 0x0 0x20000>; 214 no-map; 215 }; 216 217 smem_mem: memory@86000000 { 218 reg = <0x0 0x86000000 0x0 0x200000>; 219 no-map; 220 }; 221 222 tz_mem: memory@86200000 { 223 reg = <0x0 0x86200000 0x0 0x3900000>; 224 no-map; 225 }; 226 227 rmtfs_mem: memory@89b00000 { 228 compatible = "qcom,rmtfs-mem"; 229 reg = <0x0 0x89b00000 0x0 0x200000>; 230 no-map; 231 232 qcom,client-id = <1>; 233 qcom,vmid = <15>; 234 }; 235 236 camera_mem: memory@8b700000 { 237 reg = <0x0 0x8b700000 0x0 0x500000>; 238 no-map; 239 }; 240 241 wlan_mem: memory@8bc00000 { 242 reg = <0x0 0x8bc00000 0x0 0x180000>; 243 no-map; 244 }; 245 246 npu_mem: memory@8bd80000 { 247 reg = <0x0 0x8bd80000 0x0 0x80000>; 248 no-map; 249 }; 250 251 adsp_mem: memory@8be00000 { 252 reg = <0x0 0x8be00000 0x0 0x1a00000>; 253 no-map; 254 }; 255 256 mpss_mem: memory@8d800000 { 257 reg = <0x0 0x8d800000 0x0 0x9600000>; 258 no-map; 259 }; 260 261 venus_mem: memory@96e00000 { 262 reg = <0x0 0x96e00000 0x0 0x500000>; 263 no-map; 264 }; 265 266 slpi_mem: memory@97300000 { 267 reg = <0x0 0x97300000 0x0 0x1400000>; 268 no-map; 269 }; 270 271 ipa_fw_mem: memory@98700000 { 272 reg = <0x0 0x98700000 0x0 0x10000>; 273 no-map; 274 }; 275 276 ipa_gsi_mem: memory@98710000 { 277 reg = <0x0 0x98710000 0x0 0x5000>; 278 no-map; 279 }; 280 281 gpu_mem: memory@98715000 { 282 reg = <0x0 0x98715000 0x0 0x2000>; 283 no-map; 284 }; 285 286 spss_mem: memory@98800000 { 287 reg = <0x0 0x98800000 0x0 0x100000>; 288 no-map; 289 }; 290 291 cdsp_mem: memory@98900000 { 292 reg = <0x0 0x98900000 0x0 0x1400000>; 293 no-map; 294 }; 295 296 qseecom_mem: memory@9e400000 { 297 reg = <0x0 0x9e400000 0x0 0x1400000>; 298 no-map; 299 }; 300 }; 301 302 smem { 303 compatible = "qcom,smem"; 304 memory-region = <&smem_mem>; 305 hwlocks = <&tcsr_mutex 3>; 306 }; 307 308 smp2p-cdsp { 309 compatible = "qcom,smp2p"; 310 qcom,smem = <94>, <432>; 311 312 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 313 314 mboxes = <&apss_shared 6>; 315 316 qcom,local-pid = <0>; 317 qcom,remote-pid = <5>; 318 319 cdsp_smp2p_out: master-kernel { 320 qcom,entry-name = "master-kernel"; 321 #qcom,smem-state-cells = <1>; 322 }; 323 324 cdsp_smp2p_in: slave-kernel { 325 qcom,entry-name = "slave-kernel"; 326 327 interrupt-controller; 328 #interrupt-cells = <2>; 329 }; 330 }; 331 332 smp2p-lpass { 333 compatible = "qcom,smp2p"; 334 qcom,smem = <443>, <429>; 335 336 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 337 338 mboxes = <&apss_shared 10>; 339 340 qcom,local-pid = <0>; 341 qcom,remote-pid = <2>; 342 343 adsp_smp2p_out: master-kernel { 344 qcom,entry-name = "master-kernel"; 345 #qcom,smem-state-cells = <1>; 346 }; 347 348 adsp_smp2p_in: slave-kernel { 349 qcom,entry-name = "slave-kernel"; 350 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 }; 354 }; 355 356 smp2p-mpss { 357 compatible = "qcom,smp2p"; 358 qcom,smem = <435>, <428>; 359 360 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 361 362 mboxes = <&apss_shared 14>; 363 364 qcom,local-pid = <0>; 365 qcom,remote-pid = <1>; 366 367 modem_smp2p_out: master-kernel { 368 qcom,entry-name = "master-kernel"; 369 #qcom,smem-state-cells = <1>; 370 }; 371 372 modem_smp2p_in: slave-kernel { 373 qcom,entry-name = "slave-kernel"; 374 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 }; 378 }; 379 380 smp2p-slpi { 381 compatible = "qcom,smp2p"; 382 qcom,smem = <481>, <430>; 383 384 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 385 386 mboxes = <&apss_shared 26>; 387 388 qcom,local-pid = <0>; 389 qcom,remote-pid = <3>; 390 391 slpi_smp2p_out: master-kernel { 392 qcom,entry-name = "master-kernel"; 393 #qcom,smem-state-cells = <1>; 394 }; 395 396 slpi_smp2p_in: slave-kernel { 397 qcom,entry-name = "slave-kernel"; 398 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 }; 402 }; 403 404 soc: soc@0 { 405 #address-cells = <2>; 406 #size-cells = <2>; 407 ranges = <0 0 0 0 0x10 0>; 408 dma-ranges = <0 0 0 0 0x10 0>; 409 compatible = "simple-bus"; 410 411 gcc: clock-controller@100000 { 412 compatible = "qcom,gcc-sm8150"; 413 reg = <0x0 0x00100000 0x0 0x1f0000>; 414 #clock-cells = <1>; 415 #reset-cells = <1>; 416 #power-domain-cells = <1>; 417 clock-names = "bi_tcxo", 418 "sleep_clk"; 419 clocks = <&rpmhcc RPMH_CXO_CLK>, 420 <&sleep_clk>; 421 }; 422 423 qupv3_id_1: geniqup@ac0000 { 424 compatible = "qcom,geni-se-qup"; 425 reg = <0x0 0x00ac0000 0x0 0x6000>; 426 clock-names = "m-ahb", "s-ahb"; 427 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 428 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 429 #address-cells = <2>; 430 #size-cells = <2>; 431 ranges; 432 status = "disabled"; 433 434 uart2: serial@a90000 { 435 compatible = "qcom,geni-debug-uart"; 436 reg = <0x0 0x00a90000 0x0 0x4000>; 437 clock-names = "se"; 438 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 439 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 440 status = "disabled"; 441 }; 442 }; 443 444 config_noc: interconnect@1500000 { 445 compatible = "qcom,sm8150-config-noc"; 446 reg = <0 0x01500000 0 0x7400>; 447 #interconnect-cells = <1>; 448 qcom,bcm-voters = <&apps_bcm_voter>; 449 }; 450 451 system_noc: interconnect@1620000 { 452 compatible = "qcom,sm8150-system-noc"; 453 reg = <0 0x01620000 0 0x19400>; 454 #interconnect-cells = <1>; 455 qcom,bcm-voters = <&apps_bcm_voter>; 456 }; 457 458 mc_virt: interconnect@163a000 { 459 compatible = "qcom,sm8150-mc-virt"; 460 reg = <0 0x0163a000 0 0x1000>; 461 #interconnect-cells = <1>; 462 qcom,bcm-voters = <&apps_bcm_voter>; 463 }; 464 465 aggre1_noc: interconnect@16e0000 { 466 compatible = "qcom,sm8150-aggre1-noc"; 467 reg = <0 0x016e0000 0 0xd080>; 468 #interconnect-cells = <1>; 469 qcom,bcm-voters = <&apps_bcm_voter>; 470 }; 471 472 aggre2_noc: interconnect@1700000 { 473 compatible = "qcom,sm8150-aggre2-noc"; 474 reg = <0 0x01700000 0 0x20000>; 475 #interconnect-cells = <1>; 476 qcom,bcm-voters = <&apps_bcm_voter>; 477 }; 478 479 compute_noc: interconnect@1720000 { 480 compatible = "qcom,sm8150-compute-noc"; 481 reg = <0 0x01720000 0 0x7000>; 482 #interconnect-cells = <1>; 483 qcom,bcm-voters = <&apps_bcm_voter>; 484 }; 485 486 mmss_noc: interconnect@1740000 { 487 compatible = "qcom,sm8150-mmss-noc"; 488 reg = <0 0x01740000 0 0x1c100>; 489 #interconnect-cells = <1>; 490 qcom,bcm-voters = <&apps_bcm_voter>; 491 }; 492 493 ufs_mem_hc: ufshc@1d84000 { 494 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 495 "jedec,ufs-2.0"; 496 reg = <0 0x01d84000 0 0x2500>; 497 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 498 phys = <&ufs_mem_phy_lanes>; 499 phy-names = "ufsphy"; 500 lanes-per-direction = <2>; 501 #reset-cells = <1>; 502 resets = <&gcc GCC_UFS_PHY_BCR>; 503 reset-names = "rst"; 504 505 clock-names = 506 "core_clk", 507 "bus_aggr_clk", 508 "iface_clk", 509 "core_clk_unipro", 510 "ref_clk", 511 "tx_lane0_sync_clk", 512 "rx_lane0_sync_clk", 513 "rx_lane1_sync_clk"; 514 clocks = 515 <&gcc GCC_UFS_PHY_AXI_CLK>, 516 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 517 <&gcc GCC_UFS_PHY_AHB_CLK>, 518 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 519 <&rpmhcc RPMH_CXO_CLK>, 520 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 521 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 522 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 523 freq-table-hz = 524 <37500000 300000000>, 525 <0 0>, 526 <0 0>, 527 <37500000 300000000>, 528 <0 0>, 529 <0 0>, 530 <0 0>, 531 <0 0>; 532 533 status = "disabled"; 534 }; 535 536 ufs_mem_phy: phy@1d87000 { 537 compatible = "qcom,sm8150-qmp-ufs-phy"; 538 reg = <0 0x01d87000 0 0x1c0>; 539 #address-cells = <2>; 540 #size-cells = <2>; 541 ranges; 542 clock-names = "ref", 543 "ref_aux"; 544 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 545 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 546 547 resets = <&ufs_mem_hc 0>; 548 reset-names = "ufsphy"; 549 status = "disabled"; 550 551 ufs_mem_phy_lanes: lanes@1d87400 { 552 reg = <0 0x01d87400 0 0x108>, 553 <0 0x01d87600 0 0x1e0>, 554 <0 0x01d87c00 0 0x1dc>, 555 <0 0x01d87800 0 0x108>, 556 <0 0x01d87a00 0 0x1e0>; 557 #phy-cells = <0>; 558 }; 559 }; 560 561 ipa_virt: interconnect@1e00000 { 562 compatible = "qcom,sm8150-ipa-virt"; 563 reg = <0 0x01e00000 0 0x1000>; 564 #interconnect-cells = <1>; 565 qcom,bcm-voters = <&apps_bcm_voter>; 566 }; 567 568 tcsr_mutex_regs: syscon@1f40000 { 569 compatible = "syscon"; 570 reg = <0x0 0x01f40000 0x0 0x40000>; 571 }; 572 573 remoteproc_slpi: remoteproc@2400000 { 574 compatible = "qcom,sm8150-slpi-pas"; 575 reg = <0x0 0x02400000 0x0 0x4040>; 576 577 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 578 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 579 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 580 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 581 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 582 interrupt-names = "wdog", "fatal", "ready", 583 "handover", "stop-ack"; 584 585 clocks = <&rpmhcc RPMH_CXO_CLK>; 586 clock-names = "xo"; 587 588 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 589 <&rpmhpd 3>, 590 <&rpmhpd 2>; 591 power-domain-names = "load_state", "lcx", "lmx"; 592 593 memory-region = <&slpi_mem>; 594 595 qcom,smem-states = <&slpi_smp2p_out 0>; 596 qcom,smem-state-names = "stop"; 597 598 status = "disabled"; 599 600 glink-edge { 601 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 602 label = "dsps"; 603 qcom,remote-pid = <3>; 604 mboxes = <&apss_shared 24>; 605 }; 606 }; 607 608 gpu: gpu@2c00000 { 609 /* 610 * note: the amd,imageon compatible makes it possible 611 * to use the drm/msm driver without the display node, 612 * make sure to remove it when display node is added 613 */ 614 compatible = "qcom,adreno-640.1", 615 "qcom,adreno", 616 "amd,imageon"; 617 #stream-id-cells = <16>; 618 619 reg = <0 0x02c00000 0 0x40000>; 620 reg-names = "kgsl_3d0_reg_memory"; 621 622 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 623 624 iommus = <&adreno_smmu 0 0x401>; 625 626 operating-points-v2 = <&gpu_opp_table>; 627 628 qcom,gmu = <&gmu>; 629 630 zap-shader { 631 memory-region = <&gpu_mem>; 632 }; 633 634 /* note: downstream checks gpu binning for 675 Mhz */ 635 gpu_opp_table: opp-table { 636 compatible = "operating-points-v2"; 637 638 opp-675000000 { 639 opp-hz = /bits/ 64 <675000000>; 640 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 641 }; 642 643 opp-585000000 { 644 opp-hz = /bits/ 64 <585000000>; 645 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 646 }; 647 648 opp-499200000 { 649 opp-hz = /bits/ 64 <499200000>; 650 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 651 }; 652 653 opp-427000000 { 654 opp-hz = /bits/ 64 <427000000>; 655 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 656 }; 657 658 opp-345000000 { 659 opp-hz = /bits/ 64 <345000000>; 660 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 661 }; 662 663 opp-257000000 { 664 opp-hz = /bits/ 64 <257000000>; 665 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 666 }; 667 }; 668 }; 669 670 gmu: gmu@2c6a000 { 671 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 672 673 reg = <0 0x02c6a000 0 0x30000>, 674 <0 0x0b290000 0 0x10000>, 675 <0 0x0b490000 0 0x10000>; 676 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 677 678 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 680 interrupt-names = "hfi", "gmu"; 681 682 clocks = <&gpucc GPU_CC_AHB_CLK>, 683 <&gpucc GPU_CC_CX_GMU_CLK>, 684 <&gpucc GPU_CC_CXO_CLK>, 685 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 686 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 687 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 688 689 power-domains = <&gpucc GPU_CX_GDSC>, 690 <&gpucc GPU_GX_GDSC>; 691 power-domain-names = "cx", "gx"; 692 693 iommus = <&adreno_smmu 5 0x400>; 694 695 operating-points-v2 = <&gmu_opp_table>; 696 697 gmu_opp_table: opp-table { 698 compatible = "operating-points-v2"; 699 700 opp-200000000 { 701 opp-hz = /bits/ 64 <200000000>; 702 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 703 }; 704 }; 705 }; 706 707 gpucc: clock-controller@2c90000 { 708 compatible = "qcom,sm8150-gpucc"; 709 reg = <0 0x02c90000 0 0x9000>; 710 clocks = <&rpmhcc RPMH_CXO_CLK>, 711 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 712 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 713 clock-names = "bi_tcxo", 714 "gcc_gpu_gpll0_clk_src", 715 "gcc_gpu_gpll0_div_clk_src"; 716 #clock-cells = <1>; 717 #reset-cells = <1>; 718 #power-domain-cells = <1>; 719 }; 720 721 adreno_smmu: iommu@2ca0000 { 722 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; 723 reg = <0 0x02ca0000 0 0x10000>; 724 #iommu-cells = <2>; 725 #global-interrupts = <1>; 726 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&gpucc GPU_CC_AHB_CLK>, 736 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 737 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 738 clock-names = "ahb", "bus", "iface"; 739 740 power-domains = <&gpucc GPU_CX_GDSC>; 741 }; 742 743 tlmm: pinctrl@3100000 { 744 compatible = "qcom,sm8150-pinctrl"; 745 reg = <0x0 0x03100000 0x0 0x300000>, 746 <0x0 0x03500000 0x0 0x300000>, 747 <0x0 0x03900000 0x0 0x300000>, 748 <0x0 0x03D00000 0x0 0x300000>; 749 reg-names = "west", "east", "north", "south"; 750 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 751 gpio-ranges = <&tlmm 0 0 175>; 752 gpio-controller; 753 #gpio-cells = <2>; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 758 remoteproc_mpss: remoteproc@4080000 { 759 compatible = "qcom,sm8150-mpss-pas"; 760 reg = <0x0 0x04080000 0x0 0x4040>; 761 762 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 763 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 764 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 765 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 766 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 767 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 768 interrupt-names = "wdog", "fatal", "ready", "handover", 769 "stop-ack", "shutdown-ack"; 770 771 clocks = <&rpmhcc RPMH_CXO_CLK>; 772 clock-names = "xo"; 773 774 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 775 <&rpmhpd 7>, 776 <&rpmhpd 0>; 777 power-domain-names = "load_state", "cx", "mss"; 778 779 memory-region = <&mpss_mem>; 780 781 qcom,smem-states = <&modem_smp2p_out 0>; 782 qcom,smem-state-names = "stop"; 783 784 glink-edge { 785 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 786 label = "modem"; 787 qcom,remote-pid = <1>; 788 mboxes = <&apss_shared 12>; 789 }; 790 }; 791 792 remoteproc_cdsp: remoteproc@8300000 { 793 compatible = "qcom,sm8150-cdsp-pas"; 794 reg = <0x0 0x08300000 0x0 0x4040>; 795 796 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 797 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 798 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 799 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 800 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 801 interrupt-names = "wdog", "fatal", "ready", 802 "handover", "stop-ack"; 803 804 clocks = <&rpmhcc RPMH_CXO_CLK>; 805 clock-names = "xo"; 806 807 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 808 <&rpmhpd 7>; 809 power-domain-names = "load_state", "cx"; 810 811 memory-region = <&cdsp_mem>; 812 813 qcom,smem-states = <&cdsp_smp2p_out 0>; 814 qcom,smem-state-names = "stop"; 815 816 status = "disabled"; 817 818 glink-edge { 819 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 820 label = "cdsp"; 821 qcom,remote-pid = <5>; 822 mboxes = <&apss_shared 4>; 823 }; 824 }; 825 826 usb_1_hsphy: phy@88e2000 { 827 compatible = "qcom,sm8150-usb-hs-phy", 828 "qcom,usb-snps-hs-7nm-phy"; 829 reg = <0 0x088e2000 0 0x400>; 830 status = "disabled"; 831 #phy-cells = <0>; 832 833 clocks = <&rpmhcc RPMH_CXO_CLK>; 834 clock-names = "ref"; 835 836 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 837 }; 838 839 usb_1_qmpphy: phy@88e9000 { 840 compatible = "qcom,sm8150-qmp-usb3-phy"; 841 reg = <0 0x088e9000 0 0x18c>, 842 <0 0x088e8000 0 0x10>; 843 reg-names = "reg-base", "dp_com"; 844 status = "disabled"; 845 #clock-cells = <1>; 846 #address-cells = <2>; 847 #size-cells = <2>; 848 ranges; 849 850 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 851 <&rpmhcc RPMH_CXO_CLK>, 852 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 853 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 854 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 855 856 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 857 <&gcc GCC_USB3_PHY_PRIM_BCR>; 858 reset-names = "phy", "common"; 859 860 usb_1_ssphy: lanes@88e9200 { 861 reg = <0 0x088e9200 0 0x200>, 862 <0 0x088e9400 0 0x200>, 863 <0 0x088e9c00 0 0x218>, 864 <0 0x088e9600 0 0x200>, 865 <0 0x088e9800 0 0x200>, 866 <0 0x088e9a00 0 0x100>; 867 #phy-cells = <0>; 868 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 869 clock-names = "pipe0"; 870 clock-output-names = "usb3_phy_pipe_clk_src"; 871 }; 872 }; 873 874 dc_noc: interconnect@9160000 { 875 compatible = "qcom,sm8150-dc-noc"; 876 reg = <0 0x09160000 0 0x3200>; 877 #interconnect-cells = <1>; 878 qcom,bcm-voters = <&apps_bcm_voter>; 879 }; 880 881 gem_noc: interconnect@9680000 { 882 compatible = "qcom,sm8150-gem-noc"; 883 reg = <0 0x09680000 0 0x3e200>; 884 #interconnect-cells = <1>; 885 qcom,bcm-voters = <&apps_bcm_voter>; 886 }; 887 888 usb_1: usb@a6f8800 { 889 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 890 reg = <0 0x0a6f8800 0 0x400>; 891 status = "disabled"; 892 #address-cells = <2>; 893 #size-cells = <2>; 894 ranges; 895 dma-ranges; 896 897 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 898 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 899 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 900 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 901 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 902 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 903 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 904 "sleep", "xo"; 905 906 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 907 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 908 assigned-clock-rates = <19200000>, <200000000>; 909 910 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 914 interrupt-names = "hs_phy_irq", "ss_phy_irq", 915 "dm_hs_phy_irq", "dp_hs_phy_irq"; 916 917 power-domains = <&gcc USB30_PRIM_GDSC>; 918 919 resets = <&gcc GCC_USB30_PRIM_BCR>; 920 921 usb_1_dwc3: dwc3@a600000 { 922 compatible = "snps,dwc3"; 923 reg = <0 0x0a600000 0 0xcd00>; 924 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 925 snps,dis_u2_susphy_quirk; 926 snps,dis_enblslpm_quirk; 927 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 928 phy-names = "usb2-phy", "usb3-phy"; 929 }; 930 }; 931 932 camnoc_virt: interconnect@ac00000 { 933 compatible = "qcom,sm8150-camnoc-virt"; 934 reg = <0 0x0ac00000 0 0x1000>; 935 #interconnect-cells = <1>; 936 qcom,bcm-voters = <&apps_bcm_voter>; 937 }; 938 939 aoss_qmp: power-controller@c300000 { 940 compatible = "qcom,sm8150-aoss-qmp"; 941 reg = <0x0 0x0c300000 0x0 0x100000>; 942 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 943 mboxes = <&apss_shared 0>; 944 945 #clock-cells = <0>; 946 #power-domain-cells = <1>; 947 }; 948 949 tsens0: thermal-sensor@c263000 { 950 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 951 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 952 <0 0x0c222000 0 0x1ff>; /* SROT */ 953 #qcom,sensors = <16>; 954 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 956 interrupt-names = "uplow", "critical"; 957 #thermal-sensor-cells = <1>; 958 }; 959 960 tsens1: thermal-sensor@c265000 { 961 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 962 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 963 <0 0x0c223000 0 0x1ff>; /* SROT */ 964 #qcom,sensors = <8>; 965 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 967 interrupt-names = "uplow", "critical"; 968 #thermal-sensor-cells = <1>; 969 }; 970 971 spmi_bus: spmi@c440000 { 972 compatible = "qcom,spmi-pmic-arb"; 973 reg = <0x0 0x0c440000 0x0 0x0001100>, 974 <0x0 0x0c600000 0x0 0x2000000>, 975 <0x0 0x0e600000 0x0 0x0100000>, 976 <0x0 0x0e700000 0x0 0x00a0000>, 977 <0x0 0x0c40a000 0x0 0x0026000>; 978 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 979 interrupt-names = "periph_irq"; 980 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 981 qcom,ee = <0>; 982 qcom,channel = <0>; 983 #address-cells = <2>; 984 #size-cells = <0>; 985 interrupt-controller; 986 #interrupt-cells = <4>; 987 cell-index = <0>; 988 }; 989 990 remoteproc_adsp: remoteproc@17300000 { 991 compatible = "qcom,sm8150-adsp-pas"; 992 reg = <0x0 0x17300000 0x0 0x4040>; 993 994 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 995 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 996 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 997 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 998 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 999 interrupt-names = "wdog", "fatal", "ready", 1000 "handover", "stop-ack"; 1001 1002 clocks = <&rpmhcc RPMH_CXO_CLK>; 1003 clock-names = "xo"; 1004 1005 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 1006 <&rpmhpd 7>; 1007 power-domain-names = "load_state", "cx"; 1008 1009 memory-region = <&adsp_mem>; 1010 1011 qcom,smem-states = <&adsp_smp2p_out 0>; 1012 qcom,smem-state-names = "stop"; 1013 1014 status = "disabled"; 1015 1016 glink-edge { 1017 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1018 label = "lpass"; 1019 qcom,remote-pid = <2>; 1020 mboxes = <&apss_shared 8>; 1021 }; 1022 }; 1023 1024 intc: interrupt-controller@17a00000 { 1025 compatible = "arm,gic-v3"; 1026 interrupt-controller; 1027 #interrupt-cells = <3>; 1028 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1029 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1030 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1031 }; 1032 1033 apss_shared: mailbox@17c00000 { 1034 compatible = "qcom,sm8150-apss-shared"; 1035 reg = <0x0 0x17c00000 0x0 0x1000>; 1036 #mbox-cells = <1>; 1037 }; 1038 1039 watchdog@17c10000 { 1040 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 1041 reg = <0 0x17c10000 0 0x1000>; 1042 clocks = <&sleep_clk>; 1043 }; 1044 1045 timer@17c20000 { 1046 #address-cells = <2>; 1047 #size-cells = <2>; 1048 ranges; 1049 compatible = "arm,armv7-timer-mem"; 1050 reg = <0x0 0x17c20000 0x0 0x1000>; 1051 clock-frequency = <19200000>; 1052 1053 frame@17c21000{ 1054 frame-number = <0>; 1055 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1057 reg = <0x0 0x17c21000 0x0 0x1000>, 1058 <0x0 0x17c22000 0x0 0x1000>; 1059 }; 1060 1061 frame@17c23000 { 1062 frame-number = <1>; 1063 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1064 reg = <0x0 0x17c23000 0x0 0x1000>; 1065 status = "disabled"; 1066 }; 1067 1068 frame@17c25000 { 1069 frame-number = <2>; 1070 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1071 reg = <0x0 0x17c25000 0x0 0x1000>; 1072 status = "disabled"; 1073 }; 1074 1075 frame@17c27000 { 1076 frame-number = <3>; 1077 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1078 reg = <0x0 0x17c26000 0x0 0x1000>; 1079 status = "disabled"; 1080 }; 1081 1082 frame@17c29000 { 1083 frame-number = <4>; 1084 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1085 reg = <0x0 0x17c29000 0x0 0x1000>; 1086 status = "disabled"; 1087 }; 1088 1089 frame@17c2b000 { 1090 frame-number = <5>; 1091 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1092 reg = <0x0 0x17c2b000 0x0 0x1000>; 1093 status = "disabled"; 1094 }; 1095 1096 frame@17c2d000 { 1097 frame-number = <6>; 1098 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1099 reg = <0x0 0x17c2d000 0x0 0x1000>; 1100 status = "disabled"; 1101 }; 1102 }; 1103 1104 apps_rsc: rsc@18200000 { 1105 label = "apps_rsc"; 1106 compatible = "qcom,rpmh-rsc"; 1107 reg = <0x0 0x18200000 0x0 0x10000>, 1108 <0x0 0x18210000 0x0 0x10000>, 1109 <0x0 0x18220000 0x0 0x10000>; 1110 reg-names = "drv-0", "drv-1", "drv-2"; 1111 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1114 qcom,tcs-offset = <0xd00>; 1115 qcom,drv-id = <2>; 1116 qcom,tcs-config = <ACTIVE_TCS 2>, 1117 <SLEEP_TCS 1>, 1118 <WAKE_TCS 1>, 1119 <CONTROL_TCS 0>; 1120 1121 rpmhcc: clock-controller { 1122 compatible = "qcom,sm8150-rpmh-clk"; 1123 #clock-cells = <1>; 1124 clock-names = "xo"; 1125 clocks = <&xo_board>; 1126 }; 1127 1128 rpmhpd: power-controller { 1129 compatible = "qcom,sm8150-rpmhpd"; 1130 #power-domain-cells = <1>; 1131 operating-points-v2 = <&rpmhpd_opp_table>; 1132 1133 rpmhpd_opp_table: opp-table { 1134 compatible = "operating-points-v2"; 1135 1136 rpmhpd_opp_ret: opp1 { 1137 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1138 }; 1139 1140 rpmhpd_opp_min_svs: opp2 { 1141 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1142 }; 1143 1144 rpmhpd_opp_low_svs: opp3 { 1145 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1146 }; 1147 1148 rpmhpd_opp_svs: opp4 { 1149 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1150 }; 1151 1152 rpmhpd_opp_svs_l1: opp5 { 1153 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1154 }; 1155 1156 rpmhpd_opp_svs_l2: opp6 { 1157 opp-level = <224>; 1158 }; 1159 1160 rpmhpd_opp_nom: opp7 { 1161 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1162 }; 1163 1164 rpmhpd_opp_nom_l1: opp8 { 1165 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1166 }; 1167 1168 rpmhpd_opp_nom_l2: opp9 { 1169 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1170 }; 1171 1172 rpmhpd_opp_turbo: opp10 { 1173 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1174 }; 1175 1176 rpmhpd_opp_turbo_l1: opp11 { 1177 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1178 }; 1179 }; 1180 }; 1181 1182 apps_bcm_voter: bcm_voter { 1183 compatible = "qcom,bcm-voter"; 1184 }; 1185 }; 1186 1187 osm_l3: interconnect@18321000 { 1188 compatible = "qcom,sm8150-osm-l3"; 1189 reg = <0 0x18321000 0 0x1400>; 1190 1191 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1192 clock-names = "xo", "alternate"; 1193 1194 #interconnect-cells = <1>; 1195 }; 1196 1197 cpufreq_hw: cpufreq@18323000 { 1198 compatible = "qcom,cpufreq-hw"; 1199 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 1200 <0 0x18327800 0 0x1400>; 1201 reg-names = "freq-domain0", "freq-domain1", 1202 "freq-domain2"; 1203 1204 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1205 clock-names = "xo", "alternate"; 1206 1207 #freq-domain-cells = <1>; 1208 }; 1209 }; 1210 1211 timer { 1212 compatible = "arm,armv8-timer"; 1213 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 1214 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 1215 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 1216 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 1217 }; 1218 1219 thermal-zones { 1220 cpu0-thermal { 1221 polling-delay-passive = <250>; 1222 polling-delay = <1000>; 1223 1224 thermal-sensors = <&tsens0 1>; 1225 1226 trips { 1227 cpu0_alert0: trip-point0 { 1228 temperature = <90000>; 1229 hysteresis = <2000>; 1230 type = "passive"; 1231 }; 1232 1233 cpu0_alert1: trip-point1 { 1234 temperature = <95000>; 1235 hysteresis = <2000>; 1236 type = "passive"; 1237 }; 1238 1239 cpu0_crit: cpu_crit { 1240 temperature = <110000>; 1241 hysteresis = <1000>; 1242 type = "critical"; 1243 }; 1244 }; 1245 1246 cooling-maps { 1247 map0 { 1248 trip = <&cpu0_alert0>; 1249 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1250 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1251 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1252 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1253 }; 1254 map1 { 1255 trip = <&cpu0_alert1>; 1256 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1257 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1258 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1259 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1260 }; 1261 }; 1262 }; 1263 1264 cpu1-thermal { 1265 polling-delay-passive = <250>; 1266 polling-delay = <1000>; 1267 1268 thermal-sensors = <&tsens0 2>; 1269 1270 trips { 1271 cpu1_alert0: trip-point0 { 1272 temperature = <90000>; 1273 hysteresis = <2000>; 1274 type = "passive"; 1275 }; 1276 1277 cpu1_alert1: trip-point1 { 1278 temperature = <95000>; 1279 hysteresis = <2000>; 1280 type = "passive"; 1281 }; 1282 1283 cpu1_crit: cpu_crit { 1284 temperature = <110000>; 1285 hysteresis = <1000>; 1286 type = "critical"; 1287 }; 1288 }; 1289 1290 cooling-maps { 1291 map0 { 1292 trip = <&cpu1_alert0>; 1293 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1294 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1295 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1296 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1297 }; 1298 map1 { 1299 trip = <&cpu1_alert1>; 1300 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1301 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1302 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1303 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1304 }; 1305 }; 1306 }; 1307 1308 cpu2-thermal { 1309 polling-delay-passive = <250>; 1310 polling-delay = <1000>; 1311 1312 thermal-sensors = <&tsens0 3>; 1313 1314 trips { 1315 cpu2_alert0: trip-point0 { 1316 temperature = <90000>; 1317 hysteresis = <2000>; 1318 type = "passive"; 1319 }; 1320 1321 cpu2_alert1: trip-point1 { 1322 temperature = <95000>; 1323 hysteresis = <2000>; 1324 type = "passive"; 1325 }; 1326 1327 cpu2_crit: cpu_crit { 1328 temperature = <110000>; 1329 hysteresis = <1000>; 1330 type = "critical"; 1331 }; 1332 }; 1333 1334 cooling-maps { 1335 map0 { 1336 trip = <&cpu2_alert0>; 1337 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1338 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1339 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1340 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1341 }; 1342 map1 { 1343 trip = <&cpu2_alert1>; 1344 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1345 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1346 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1347 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1348 }; 1349 }; 1350 }; 1351 1352 cpu3-thermal { 1353 polling-delay-passive = <250>; 1354 polling-delay = <1000>; 1355 1356 thermal-sensors = <&tsens0 4>; 1357 1358 trips { 1359 cpu3_alert0: trip-point0 { 1360 temperature = <90000>; 1361 hysteresis = <2000>; 1362 type = "passive"; 1363 }; 1364 1365 cpu3_alert1: trip-point1 { 1366 temperature = <95000>; 1367 hysteresis = <2000>; 1368 type = "passive"; 1369 }; 1370 1371 cpu3_crit: cpu_crit { 1372 temperature = <110000>; 1373 hysteresis = <1000>; 1374 type = "critical"; 1375 }; 1376 }; 1377 1378 cooling-maps { 1379 map0 { 1380 trip = <&cpu3_alert0>; 1381 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1382 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1383 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1384 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1385 }; 1386 map1 { 1387 trip = <&cpu3_alert1>; 1388 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1389 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1390 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1391 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1392 }; 1393 }; 1394 }; 1395 1396 cpu4-top-thermal { 1397 polling-delay-passive = <250>; 1398 polling-delay = <1000>; 1399 1400 thermal-sensors = <&tsens0 7>; 1401 1402 trips { 1403 cpu4_top_alert0: trip-point0 { 1404 temperature = <90000>; 1405 hysteresis = <2000>; 1406 type = "passive"; 1407 }; 1408 1409 cpu4_top_alert1: trip-point1 { 1410 temperature = <95000>; 1411 hysteresis = <2000>; 1412 type = "passive"; 1413 }; 1414 1415 cpu4_top_crit: cpu_crit { 1416 temperature = <110000>; 1417 hysteresis = <1000>; 1418 type = "critical"; 1419 }; 1420 }; 1421 1422 cooling-maps { 1423 map0 { 1424 trip = <&cpu4_top_alert0>; 1425 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1426 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1427 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1428 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1429 }; 1430 map1 { 1431 trip = <&cpu4_top_alert1>; 1432 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1433 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1434 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1435 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1436 }; 1437 }; 1438 }; 1439 1440 cpu5-top-thermal { 1441 polling-delay-passive = <250>; 1442 polling-delay = <1000>; 1443 1444 thermal-sensors = <&tsens0 8>; 1445 1446 trips { 1447 cpu5_top_alert0: trip-point0 { 1448 temperature = <90000>; 1449 hysteresis = <2000>; 1450 type = "passive"; 1451 }; 1452 1453 cpu5_top_alert1: trip-point1 { 1454 temperature = <95000>; 1455 hysteresis = <2000>; 1456 type = "passive"; 1457 }; 1458 1459 cpu5_top_crit: cpu_crit { 1460 temperature = <110000>; 1461 hysteresis = <1000>; 1462 type = "critical"; 1463 }; 1464 }; 1465 1466 cooling-maps { 1467 map0 { 1468 trip = <&cpu5_top_alert0>; 1469 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1470 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1471 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1472 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1473 }; 1474 map1 { 1475 trip = <&cpu5_top_alert1>; 1476 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1477 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1478 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1479 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1480 }; 1481 }; 1482 }; 1483 1484 cpu6-top-thermal { 1485 polling-delay-passive = <250>; 1486 polling-delay = <1000>; 1487 1488 thermal-sensors = <&tsens0 9>; 1489 1490 trips { 1491 cpu6_top_alert0: trip-point0 { 1492 temperature = <90000>; 1493 hysteresis = <2000>; 1494 type = "passive"; 1495 }; 1496 1497 cpu6_top_alert1: trip-point1 { 1498 temperature = <95000>; 1499 hysteresis = <2000>; 1500 type = "passive"; 1501 }; 1502 1503 cpu6_top_crit: cpu_crit { 1504 temperature = <110000>; 1505 hysteresis = <1000>; 1506 type = "critical"; 1507 }; 1508 }; 1509 1510 cooling-maps { 1511 map0 { 1512 trip = <&cpu6_top_alert0>; 1513 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1514 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1515 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1516 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1517 }; 1518 map1 { 1519 trip = <&cpu6_top_alert1>; 1520 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1521 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1522 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1523 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1524 }; 1525 }; 1526 }; 1527 1528 cpu7-top-thermal { 1529 polling-delay-passive = <250>; 1530 polling-delay = <1000>; 1531 1532 thermal-sensors = <&tsens0 10>; 1533 1534 trips { 1535 cpu7_top_alert0: trip-point0 { 1536 temperature = <90000>; 1537 hysteresis = <2000>; 1538 type = "passive"; 1539 }; 1540 1541 cpu7_top_alert1: trip-point1 { 1542 temperature = <95000>; 1543 hysteresis = <2000>; 1544 type = "passive"; 1545 }; 1546 1547 cpu7_top_crit: cpu_crit { 1548 temperature = <110000>; 1549 hysteresis = <1000>; 1550 type = "critical"; 1551 }; 1552 }; 1553 1554 cooling-maps { 1555 map0 { 1556 trip = <&cpu7_top_alert0>; 1557 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1558 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1559 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1560 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1561 }; 1562 map1 { 1563 trip = <&cpu7_top_alert1>; 1564 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1565 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1566 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1567 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1568 }; 1569 }; 1570 }; 1571 1572 cpu4-bottom-thermal { 1573 polling-delay-passive = <250>; 1574 polling-delay = <1000>; 1575 1576 thermal-sensors = <&tsens0 11>; 1577 1578 trips { 1579 cpu4_bottom_alert0: trip-point0 { 1580 temperature = <90000>; 1581 hysteresis = <2000>; 1582 type = "passive"; 1583 }; 1584 1585 cpu4_bottom_alert1: trip-point1 { 1586 temperature = <95000>; 1587 hysteresis = <2000>; 1588 type = "passive"; 1589 }; 1590 1591 cpu4_bottom_crit: cpu_crit { 1592 temperature = <110000>; 1593 hysteresis = <1000>; 1594 type = "critical"; 1595 }; 1596 }; 1597 1598 cooling-maps { 1599 map0 { 1600 trip = <&cpu4_bottom_alert0>; 1601 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1602 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1603 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1604 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1605 }; 1606 map1 { 1607 trip = <&cpu4_bottom_alert1>; 1608 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1609 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1610 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1611 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1612 }; 1613 }; 1614 }; 1615 1616 cpu5-bottom-thermal { 1617 polling-delay-passive = <250>; 1618 polling-delay = <1000>; 1619 1620 thermal-sensors = <&tsens0 12>; 1621 1622 trips { 1623 cpu5_bottom_alert0: trip-point0 { 1624 temperature = <90000>; 1625 hysteresis = <2000>; 1626 type = "passive"; 1627 }; 1628 1629 cpu5_bottom_alert1: trip-point1 { 1630 temperature = <95000>; 1631 hysteresis = <2000>; 1632 type = "passive"; 1633 }; 1634 1635 cpu5_bottom_crit: cpu_crit { 1636 temperature = <110000>; 1637 hysteresis = <1000>; 1638 type = "critical"; 1639 }; 1640 }; 1641 1642 cooling-maps { 1643 map0 { 1644 trip = <&cpu5_bottom_alert0>; 1645 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1646 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1647 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1648 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1649 }; 1650 map1 { 1651 trip = <&cpu5_bottom_alert1>; 1652 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1653 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1654 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1655 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1656 }; 1657 }; 1658 }; 1659 1660 cpu6-bottom-thermal { 1661 polling-delay-passive = <250>; 1662 polling-delay = <1000>; 1663 1664 thermal-sensors = <&tsens0 13>; 1665 1666 trips { 1667 cpu6_bottom_alert0: trip-point0 { 1668 temperature = <90000>; 1669 hysteresis = <2000>; 1670 type = "passive"; 1671 }; 1672 1673 cpu6_bottom_alert1: trip-point1 { 1674 temperature = <95000>; 1675 hysteresis = <2000>; 1676 type = "passive"; 1677 }; 1678 1679 cpu6_bottom_crit: cpu_crit { 1680 temperature = <110000>; 1681 hysteresis = <1000>; 1682 type = "critical"; 1683 }; 1684 }; 1685 1686 cooling-maps { 1687 map0 { 1688 trip = <&cpu6_bottom_alert0>; 1689 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1690 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1691 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1692 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1693 }; 1694 map1 { 1695 trip = <&cpu6_bottom_alert1>; 1696 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1697 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1698 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1699 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1700 }; 1701 }; 1702 }; 1703 1704 cpu7-bottom-thermal { 1705 polling-delay-passive = <250>; 1706 polling-delay = <1000>; 1707 1708 thermal-sensors = <&tsens0 14>; 1709 1710 trips { 1711 cpu7_bottom_alert0: trip-point0 { 1712 temperature = <90000>; 1713 hysteresis = <2000>; 1714 type = "passive"; 1715 }; 1716 1717 cpu7_bottom_alert1: trip-point1 { 1718 temperature = <95000>; 1719 hysteresis = <2000>; 1720 type = "passive"; 1721 }; 1722 1723 cpu7_bottom_crit: cpu_crit { 1724 temperature = <110000>; 1725 hysteresis = <1000>; 1726 type = "critical"; 1727 }; 1728 }; 1729 1730 cooling-maps { 1731 map0 { 1732 trip = <&cpu7_bottom_alert0>; 1733 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1734 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1735 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1736 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1737 }; 1738 map1 { 1739 trip = <&cpu7_bottom_alert1>; 1740 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1741 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1742 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1743 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1744 }; 1745 }; 1746 }; 1747 1748 aoss0-thermal { 1749 polling-delay-passive = <250>; 1750 polling-delay = <1000>; 1751 1752 thermal-sensors = <&tsens0 0>; 1753 1754 trips { 1755 aoss0_alert0: trip-point0 { 1756 temperature = <90000>; 1757 hysteresis = <2000>; 1758 type = "hot"; 1759 }; 1760 }; 1761 }; 1762 1763 cluster0-thermal { 1764 polling-delay-passive = <250>; 1765 polling-delay = <1000>; 1766 1767 thermal-sensors = <&tsens0 5>; 1768 1769 trips { 1770 cluster0_alert0: trip-point0 { 1771 temperature = <90000>; 1772 hysteresis = <2000>; 1773 type = "hot"; 1774 }; 1775 cluster0_crit: cluster0_crit { 1776 temperature = <110000>; 1777 hysteresis = <2000>; 1778 type = "critical"; 1779 }; 1780 }; 1781 }; 1782 1783 cluster1-thermal { 1784 polling-delay-passive = <250>; 1785 polling-delay = <1000>; 1786 1787 thermal-sensors = <&tsens0 6>; 1788 1789 trips { 1790 cluster1_alert0: trip-point0 { 1791 temperature = <90000>; 1792 hysteresis = <2000>; 1793 type = "hot"; 1794 }; 1795 cluster1_crit: cluster1_crit { 1796 temperature = <110000>; 1797 hysteresis = <2000>; 1798 type = "critical"; 1799 }; 1800 }; 1801 }; 1802 1803 gpu-thermal-top { 1804 polling-delay-passive = <250>; 1805 polling-delay = <1000>; 1806 1807 thermal-sensors = <&tsens0 15>; 1808 1809 trips { 1810 gpu1_alert0: trip-point0 { 1811 temperature = <90000>; 1812 hysteresis = <2000>; 1813 type = "hot"; 1814 }; 1815 }; 1816 }; 1817 1818 aoss1-thermal { 1819 polling-delay-passive = <250>; 1820 polling-delay = <1000>; 1821 1822 thermal-sensors = <&tsens1 0>; 1823 1824 trips { 1825 aoss1_alert0: trip-point0 { 1826 temperature = <90000>; 1827 hysteresis = <2000>; 1828 type = "hot"; 1829 }; 1830 }; 1831 }; 1832 1833 wlan-thermal { 1834 polling-delay-passive = <250>; 1835 polling-delay = <1000>; 1836 1837 thermal-sensors = <&tsens1 1>; 1838 1839 trips { 1840 wlan_alert0: trip-point0 { 1841 temperature = <90000>; 1842 hysteresis = <2000>; 1843 type = "hot"; 1844 }; 1845 }; 1846 }; 1847 1848 video-thermal { 1849 polling-delay-passive = <250>; 1850 polling-delay = <1000>; 1851 1852 thermal-sensors = <&tsens1 2>; 1853 1854 trips { 1855 video_alert0: trip-point0 { 1856 temperature = <90000>; 1857 hysteresis = <2000>; 1858 type = "hot"; 1859 }; 1860 }; 1861 }; 1862 1863 mem-thermal { 1864 polling-delay-passive = <250>; 1865 polling-delay = <1000>; 1866 1867 thermal-sensors = <&tsens1 3>; 1868 1869 trips { 1870 mem_alert0: trip-point0 { 1871 temperature = <90000>; 1872 hysteresis = <2000>; 1873 type = "hot"; 1874 }; 1875 }; 1876 }; 1877 1878 q6-hvx-thermal { 1879 polling-delay-passive = <250>; 1880 polling-delay = <1000>; 1881 1882 thermal-sensors = <&tsens1 4>; 1883 1884 trips { 1885 q6_hvx_alert0: trip-point0 { 1886 temperature = <90000>; 1887 hysteresis = <2000>; 1888 type = "hot"; 1889 }; 1890 }; 1891 }; 1892 1893 camera-thermal { 1894 polling-delay-passive = <250>; 1895 polling-delay = <1000>; 1896 1897 thermal-sensors = <&tsens1 5>; 1898 1899 trips { 1900 camera_alert0: trip-point0 { 1901 temperature = <90000>; 1902 hysteresis = <2000>; 1903 type = "hot"; 1904 }; 1905 }; 1906 }; 1907 1908 compute-thermal { 1909 polling-delay-passive = <250>; 1910 polling-delay = <1000>; 1911 1912 thermal-sensors = <&tsens1 6>; 1913 1914 trips { 1915 compute_alert0: trip-point0 { 1916 temperature = <90000>; 1917 hysteresis = <2000>; 1918 type = "hot"; 1919 }; 1920 }; 1921 }; 1922 1923 modem-thermal { 1924 polling-delay-passive = <250>; 1925 polling-delay = <1000>; 1926 1927 thermal-sensors = <&tsens1 7>; 1928 1929 trips { 1930 modem_alert0: trip-point0 { 1931 temperature = <90000>; 1932 hysteresis = <2000>; 1933 type = "hot"; 1934 }; 1935 }; 1936 }; 1937 1938 npu-thermal { 1939 polling-delay-passive = <250>; 1940 polling-delay = <1000>; 1941 1942 thermal-sensors = <&tsens1 8>; 1943 1944 trips { 1945 npu_alert0: trip-point0 { 1946 temperature = <90000>; 1947 hysteresis = <2000>; 1948 type = "hot"; 1949 }; 1950 }; 1951 }; 1952 1953 modem-vec-thermal { 1954 polling-delay-passive = <250>; 1955 polling-delay = <1000>; 1956 1957 thermal-sensors = <&tsens1 9>; 1958 1959 trips { 1960 modem_vec_alert0: trip-point0 { 1961 temperature = <90000>; 1962 hysteresis = <2000>; 1963 type = "hot"; 1964 }; 1965 }; 1966 }; 1967 1968 modem-scl-thermal { 1969 polling-delay-passive = <250>; 1970 polling-delay = <1000>; 1971 1972 thermal-sensors = <&tsens1 10>; 1973 1974 trips { 1975 modem_scl_alert0: trip-point0 { 1976 temperature = <90000>; 1977 hysteresis = <2000>; 1978 type = "hot"; 1979 }; 1980 }; 1981 }; 1982 1983 gpu-thermal-bottom { 1984 polling-delay-passive = <250>; 1985 polling-delay = <1000>; 1986 1987 thermal-sensors = <&tsens1 11>; 1988 1989 trips { 1990 gpu2_alert0: trip-point0 { 1991 temperature = <90000>; 1992 hysteresis = <2000>; 1993 type = "hot"; 1994 }; 1995 }; 1996 }; 1997 }; 1998}; 1999