1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,sm6375-gcc.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/firmware/qcom,scm.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/mailbox/qcom-ipcc.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 xo_board_clk: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 clock-frequency = <32000>; 31 #clock-cells = <0>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo660"; 42 reg = <0x0 0x0>; 43 clocks = <&cpufreq_hw 0>; 44 enable-method = "psci"; 45 next-level-cache = <&L2_0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 power-domains = <&CPU_PD0>; 48 power-domain-names = "psci"; 49 #cooling-cells = <2>; 50 L2_0: l2-cache { 51 compatible = "cache"; 52 cache-level = <2>; 53 cache-unified; 54 next-level-cache = <&L3_0>; 55 L3_0: l3-cache { 56 compatible = "cache"; 57 cache-level = <3>; 58 cache-unified; 59 }; 60 }; 61 }; 62 63 CPU1: cpu@100 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo660"; 66 reg = <0x0 0x100>; 67 clocks = <&cpufreq_hw 0>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_100>; 70 qcom,freq-domain = <&cpufreq_hw 0>; 71 power-domains = <&CPU_PD1>; 72 power-domain-names = "psci"; 73 #cooling-cells = <2>; 74 L2_100: l2-cache { 75 compatible = "cache"; 76 cache-level = <2>; 77 cache-unified; 78 next-level-cache = <&L3_0>; 79 }; 80 }; 81 82 CPU2: cpu@200 { 83 device_type = "cpu"; 84 compatible = "qcom,kryo660"; 85 reg = <0x0 0x200>; 86 clocks = <&cpufreq_hw 0>; 87 enable-method = "psci"; 88 next-level-cache = <&L2_200>; 89 qcom,freq-domain = <&cpufreq_hw 0>; 90 power-domains = <&CPU_PD2>; 91 power-domain-names = "psci"; 92 #cooling-cells = <2>; 93 L2_200: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&L3_0>; 98 }; 99 }; 100 101 CPU3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo660"; 104 reg = <0x0 0x300>; 105 clocks = <&cpufreq_hw 0>; 106 enable-method = "psci"; 107 next-level-cache = <&L2_300>; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 power-domains = <&CPU_PD3>; 110 power-domain-names = "psci"; 111 #cooling-cells = <2>; 112 L2_300: l2-cache { 113 compatible = "cache"; 114 cache-level = <2>; 115 cache-unified; 116 next-level-cache = <&L3_0>; 117 }; 118 }; 119 120 CPU4: cpu@400 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo660"; 123 reg = <0x0 0x400>; 124 clocks = <&cpufreq_hw 0>; 125 enable-method = "psci"; 126 next-level-cache = <&L2_400>; 127 qcom,freq-domain = <&cpufreq_hw 0>; 128 power-domains = <&CPU_PD4>; 129 power-domain-names = "psci"; 130 #cooling-cells = <2>; 131 L2_400: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 next-level-cache = <&L3_0>; 136 }; 137 }; 138 139 CPU5: cpu@500 { 140 device_type = "cpu"; 141 compatible = "qcom,kryo660"; 142 reg = <0x0 0x500>; 143 clocks = <&cpufreq_hw 0>; 144 enable-method = "psci"; 145 next-level-cache = <&L2_500>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 power-domains = <&CPU_PD5>; 148 power-domain-names = "psci"; 149 #cooling-cells = <2>; 150 L2_500: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&L3_0>; 155 }; 156 }; 157 158 CPU6: cpu@600 { 159 device_type = "cpu"; 160 compatible = "qcom,kryo660"; 161 reg = <0x0 0x600>; 162 clocks = <&cpufreq_hw 1>; 163 enable-method = "psci"; 164 next-level-cache = <&L2_600>; 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 power-domains = <&CPU_PD6>; 167 power-domain-names = "psci"; 168 #cooling-cells = <2>; 169 L2_600: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU7: cpu@700 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo660"; 180 reg = <0x0 0x700>; 181 clocks = <&cpufreq_hw 1>; 182 enable-method = "psci"; 183 next-level-cache = <&L2_700>; 184 qcom,freq-domain = <&cpufreq_hw 1>; 185 power-domains = <&CPU_PD7>; 186 power-domain-names = "psci"; 187 #cooling-cells = <2>; 188 L2_700: l2-cache { 189 compatible = "cache"; 190 cache-level = <2>; 191 cache-unified; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 cpu-map { 197 cluster0 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 214 core4 { 215 cpu = <&CPU4>; 216 }; 217 218 core5 { 219 cpu = <&CPU5>; 220 }; 221 222 core6 { 223 cpu = <&CPU6>; 224 }; 225 226 core7 { 227 cpu = <&CPU7>; 228 }; 229 }; 230 }; 231 232 idle-states { 233 entry-method = "psci"; 234 235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 236 compatible = "arm,idle-state"; 237 idle-state-name = "silver-power-collapse"; 238 arm,psci-suspend-param = <0x40000003>; 239 entry-latency-us = <549>; 240 exit-latency-us = <901>; 241 min-residency-us = <1774>; 242 local-timer-stop; 243 }; 244 245 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "silver-rail-power-collapse"; 248 arm,psci-suspend-param = <0x40000004>; 249 entry-latency-us = <702>; 250 exit-latency-us = <915>; 251 min-residency-us = <4001>; 252 local-timer-stop; 253 }; 254 255 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "gold-power-collapse"; 258 arm,psci-suspend-param = <0x40000003>; 259 entry-latency-us = <523>; 260 exit-latency-us = <1244>; 261 min-residency-us = <2207>; 262 local-timer-stop; 263 }; 264 265 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 266 compatible = "arm,idle-state"; 267 idle-state-name = "gold-rail-power-collapse"; 268 arm,psci-suspend-param = <0x40000004>; 269 entry-latency-us = <526>; 270 exit-latency-us = <1854>; 271 min-residency-us = <5555>; 272 local-timer-stop; 273 }; 274 }; 275 276 domain-idle-states { 277 CLUSTER_SLEEP_0: cluster-sleep-0 { 278 compatible = "domain-idle-state"; 279 arm,psci-suspend-param = <0x41000044>; 280 entry-latency-us = <2752>; 281 exit-latency-us = <3048>; 282 min-residency-us = <6118>; 283 }; 284 }; 285 }; 286 287 firmware { 288 scm { 289 compatible = "qcom,scm-sm6375", "qcom,scm"; 290 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 291 clock-names = "core"; 292 #reset-cells = <1>; 293 }; 294 }; 295 296 memory@80000000 { 297 device_type = "memory"; 298 /* We expect the bootloader to fill in the size */ 299 reg = <0x0 0x80000000 0x0 0x0>; 300 }; 301 302 pmu { 303 compatible = "arm,armv8-pmuv3"; 304 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 305 }; 306 307 psci { 308 compatible = "arm,psci-1.0"; 309 method = "smc"; 310 311 CPU_PD0: power-domain-cpu0 { 312 #power-domain-cells = <0>; 313 power-domains = <&CLUSTER_PD>; 314 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 315 }; 316 317 CPU_PD1: power-domain-cpu1 { 318 #power-domain-cells = <0>; 319 power-domains = <&CLUSTER_PD>; 320 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 321 }; 322 323 CPU_PD2: power-domain-cpu2 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 327 }; 328 329 CPU_PD3: power-domain-cpu3 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 333 }; 334 335 CPU_PD4: power-domain-cpu4 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 339 }; 340 341 CPU_PD5: power-domain-cpu5 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 345 }; 346 347 CPU_PD6: power-domain-cpu6 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD>; 350 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 351 }; 352 353 CPU_PD7: power-domain-cpu7 { 354 #power-domain-cells = <0>; 355 power-domains = <&CLUSTER_PD>; 356 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 357 }; 358 359 CLUSTER_PD: power-domain-cpu-cluster0 { 360 #power-domain-cells = <0>; 361 domain-idle-states = <&CLUSTER_SLEEP_0>; 362 }; 363 }; 364 365 qup_opp_table: opp-table-qup { 366 compatible = "operating-points-v2"; 367 368 opp-75000000 { 369 opp-hz = /bits/ 64 <75000000>; 370 required-opps = <&rpmpd_opp_low_svs>; 371 }; 372 373 opp-100000000 { 374 opp-hz = /bits/ 64 <100000000>; 375 required-opps = <&rpmpd_opp_svs>; 376 }; 377 378 opp-128000000 { 379 opp-hz = /bits/ 64 <128000000>; 380 required-opps = <&rpmpd_opp_nom>; 381 }; 382 }; 383 384 reserved_memory: reserved-memory { 385 #address-cells = <2>; 386 #size-cells = <2>; 387 ranges; 388 389 hyp_mem: hypervisor@80000000 { 390 reg = <0 0x80000000 0 0x600000>; 391 no-map; 392 }; 393 394 xbl_aop_mem: xbl-aop@80700000 { 395 reg = <0 0x80700000 0 0x100000>; 396 no-map; 397 }; 398 399 reserved_xbl_uefi: xbl-uefi-res@80880000 { 400 reg = <0 0x80880000 0 0x14000>; 401 no-map; 402 }; 403 404 smem_mem: smem@80900000 { 405 compatible = "qcom,smem"; 406 reg = <0 0x80900000 0 0x200000>; 407 hwlocks = <&tcsr_mutex 3>; 408 no-map; 409 }; 410 411 fw_mem: fw@80b00000 { 412 reg = <0 0x80b00000 0 0x100000>; 413 no-map; 414 }; 415 416 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { 417 reg = <0 0x80c00000 0 0x1e00000>; 418 no-map; 419 }; 420 421 dfps_data_mem: dpfs-data@85e00000 { 422 reg = <0 0x85e00000 0 0x100000>; 423 no-map; 424 }; 425 426 pil_wlan_mem: pil-wlan@86500000 { 427 reg = <0 0x86500000 0 0x200000>; 428 no-map; 429 }; 430 431 pil_adsp_mem: pil-adsp@86700000 { 432 reg = <0 0x86700000 0 0x2000000>; 433 no-map; 434 }; 435 436 pil_cdsp_mem: pil-cdsp@88700000 { 437 reg = <0 0x88700000 0 0x1e00000>; 438 no-map; 439 }; 440 441 pil_video_mem: pil-video@8a500000 { 442 reg = <0 0x8a500000 0 0x500000>; 443 no-map; 444 }; 445 446 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { 447 reg = <0 0x8aa00000 0 0x10000>; 448 no-map; 449 }; 450 451 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { 452 reg = <0 0x8aa10000 0 0xa000>; 453 no-map; 454 }; 455 456 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { 457 reg = <0 0x8aa1a000 0 0x2000>; 458 no-map; 459 }; 460 461 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { 462 reg = <0 0x8b800000 0 0x10000000>; 463 no-map; 464 }; 465 466 removed_mem: removed@c0000000 { 467 reg = <0 0xc0000000 0 0x5100000>; 468 no-map; 469 }; 470 471 rmtfs_mem: rmtfs@f3900000 { 472 compatible = "qcom,rmtfs-mem"; 473 reg = <0 0xf3900000 0 0x280000>; 474 no-map; 475 476 qcom,client-id = <1>; 477 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 478 }; 479 480 debug_mem: debug@ffb00000 { 481 reg = <0 0xffb00000 0 0xc0000>; 482 no-map; 483 }; 484 485 last_log_mem: lastlog@ffbc0000 { 486 reg = <0 0xffbc0000 0 0x80000>; 487 no-map; 488 }; 489 490 cmdline_region: cmdline@ffd00000 { 491 reg = <0 0xffd00000 0 0x1000>; 492 no-map; 493 }; 494 }; 495 496 rpm-glink { 497 compatible = "qcom,glink-rpm"; 498 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 499 IPCC_MPROC_SIGNAL_GLINK_QMP 500 IRQ_TYPE_EDGE_RISING>; 501 qcom,rpm-msg-ram = <&rpm_msg_ram>; 502 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 503 504 rpm_requests: rpm-requests { 505 compatible = "qcom,rpm-sm6375"; 506 qcom,glink-channels = "rpm_requests"; 507 508 rpmcc: clock-controller { 509 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; 510 clocks = <&xo_board_clk>; 511 clock-names = "xo"; 512 #clock-cells = <1>; 513 }; 514 515 rpmpd: power-controller { 516 compatible = "qcom,sm6375-rpmpd"; 517 #power-domain-cells = <1>; 518 operating-points-v2 = <&rpmpd_opp_table>; 519 520 rpmpd_opp_table: opp-table { 521 compatible = "operating-points-v2"; 522 523 rpmpd_opp_ret: opp1 { 524 opp-level = <RPM_SMD_LEVEL_RETENTION>; 525 }; 526 527 rpmpd_opp_min_svs: opp2 { 528 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 529 }; 530 531 rpmpd_opp_low_svs: opp3 { 532 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 533 }; 534 535 rpmpd_opp_svs: opp4 { 536 opp-level = <RPM_SMD_LEVEL_SVS>; 537 }; 538 539 rpmpd_opp_svs_plus: opp5 { 540 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 541 }; 542 543 rpmpd_opp_nom: opp6 { 544 opp-level = <RPM_SMD_LEVEL_NOM>; 545 }; 546 547 rpmpd_opp_nom_plus: opp7 { 548 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 549 }; 550 551 rpmpd_opp_turbo: opp8 { 552 opp-level = <RPM_SMD_LEVEL_TURBO>; 553 }; 554 555 rpmpd_opp_turbo_no_cpr: opp9 { 556 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 557 }; 558 }; 559 }; 560 }; 561 }; 562 563 smp2p-adsp { 564 compatible = "qcom,smp2p"; 565 qcom,smem = <443>, <429>; 566 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 567 IPCC_MPROC_SIGNAL_SMP2P 568 IRQ_TYPE_EDGE_RISING>; 569 mboxes = <&ipcc IPCC_CLIENT_LPASS 570 IPCC_MPROC_SIGNAL_SMP2P>; 571 572 qcom,local-pid = <0>; 573 qcom,remote-pid = <2>; 574 575 smp2p_adsp_out: master-kernel { 576 qcom,entry-name = "master-kernel"; 577 #qcom,smem-state-cells = <1>; 578 }; 579 580 smp2p_adsp_in: slave-kernel { 581 qcom,entry-name = "slave-kernel"; 582 interrupt-controller; 583 #interrupt-cells = <2>; 584 }; 585 }; 586 587 smp2p-cdsp { 588 compatible = "qcom,smp2p"; 589 qcom,smem = <94>, <432>; 590 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 591 IPCC_MPROC_SIGNAL_SMP2P 592 IRQ_TYPE_EDGE_RISING>; 593 mboxes = <&ipcc IPCC_CLIENT_CDSP 594 IPCC_MPROC_SIGNAL_SMP2P>; 595 596 qcom,local-pid = <0>; 597 qcom,remote-pid = <5>; 598 599 smp2p_cdsp_out: master-kernel { 600 qcom,entry-name = "master-kernel"; 601 #qcom,smem-state-cells = <1>; 602 }; 603 604 smp2p_cdsp_in: slave-kernel { 605 qcom,entry-name = "slave-kernel"; 606 interrupt-controller; 607 #interrupt-cells = <2>; 608 }; 609 }; 610 611 smp2p-modem { 612 compatible = "qcom,smp2p"; 613 qcom,smem = <435>, <428>; 614 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 615 IPCC_MPROC_SIGNAL_SMP2P 616 IRQ_TYPE_EDGE_RISING>; 617 mboxes = <&ipcc IPCC_CLIENT_MPSS 618 IPCC_MPROC_SIGNAL_SMP2P>; 619 620 qcom,local-pid = <0>; 621 qcom,remote-pid = <1>; 622 623 smp2p_modem_out: master-kernel { 624 qcom,entry-name = "master-kernel"; 625 #qcom,smem-state-cells = <1>; 626 }; 627 628 smp2p_modem_in: slave-kernel { 629 qcom,entry-name = "slave-kernel"; 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 }; 633 634 ipa_smp2p_out: ipa-ap-to-modem { 635 qcom,entry-name = "ipa"; 636 #qcom,smem-state-cells = <1>; 637 }; 638 639 ipa_smp2p_in: ipa-modem-to-ap { 640 qcom,entry-name = "ipa"; 641 interrupt-controller; 642 #interrupt-cells = <2>; 643 }; 644 645 wlan_smp2p_in: wlan-wpss-to-ap { 646 qcom,entry-name = "wlan"; 647 interrupt-controller; 648 #interrupt-cells = <2>; 649 }; 650 }; 651 652 soc: soc@0 { 653 #address-cells = <2>; 654 #size-cells = <2>; 655 ranges = <0 0 0 0 0x10 0>; 656 dma-ranges = <0 0 0 0 0x10 0>; 657 compatible = "simple-bus"; 658 659 ipcc: mailbox@208000 { 660 compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; 661 reg = <0 0x00208000 0 0x1000>; 662 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 663 interrupt-controller; 664 #interrupt-cells = <3>; 665 #mbox-cells = <2>; 666 }; 667 668 tcsr_mutex: hwlock@340000 { 669 compatible = "qcom,tcsr-mutex"; 670 reg = <0x0 0x00340000 0x0 0x40000>; 671 #hwlock-cells = <1>; 672 }; 673 674 tlmm: pinctrl@500000 { 675 compatible = "qcom,sm6375-tlmm"; 676 reg = <0 0x00500000 0 0x800000>; 677 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 678 gpio-ranges = <&tlmm 0 0 157>; 679 /* TODO: Hook up MPM as wakeup-parent when it's there */ 680 interrupt-controller; 681 gpio-controller; 682 #interrupt-cells = <2>; 683 #gpio-cells = <2>; 684 685 sdc2_off_state: sdc2-off-state { 686 clk-pins { 687 pins = "sdc2_clk"; 688 drive-strength = <2>; 689 bias-disable; 690 }; 691 692 cmd-pins { 693 pins = "sdc2_cmd"; 694 drive-strength = <2>; 695 bias-pull-up; 696 }; 697 698 data-pins { 699 pins = "sdc2_data"; 700 drive-strength = <2>; 701 bias-pull-up; 702 }; 703 }; 704 705 sdc2_on_state: sdc2-on-state { 706 clk-pins { 707 pins = "sdc2_clk"; 708 drive-strength = <16>; 709 bias-disable; 710 }; 711 712 cmd-pins { 713 pins = "sdc2_cmd"; 714 drive-strength = <10>; 715 bias-pull-up; 716 }; 717 718 data-pins { 719 pins = "sdc2_data"; 720 drive-strength = <10>; 721 bias-pull-up; 722 }; 723 }; 724 725 qup_i2c0_default: qup-i2c0-default-state { 726 pins = "gpio0", "gpio1"; 727 function = "qup00"; 728 drive-strength = <2>; 729 bias-pull-up; 730 }; 731 732 qup_i2c1_default: qup-i2c1-default-state { 733 pins = "gpio61", "gpio62"; 734 function = "qup01"; 735 drive-strength = <2>; 736 bias-pull-up; 737 }; 738 739 qup_i2c2_default: qup-i2c2-default-state { 740 pins = "gpio45", "gpio46"; 741 function = "qup02"; 742 drive-strength = <2>; 743 bias-pull-up; 744 }; 745 746 qup_i2c8_default: qup-i2c8-default-state { 747 pins = "gpio19", "gpio20"; 748 /* TLMM, GCC and vendor DT all have different indices.. */ 749 function = "qup12"; 750 drive-strength = <2>; 751 bias-pull-up; 752 }; 753 754 qup_i2c10_default: qup-i2c10-default-state { 755 pins = "gpio4", "gpio5"; 756 function = "qup10"; 757 drive-strength = <2>; 758 bias-pull-up; 759 }; 760 761 qup_spi0_default: qup-spi0-default-state { 762 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 763 function = "qup00"; 764 drive-strength = <6>; 765 bias-disable; 766 }; 767 }; 768 769 gcc: clock-controller@1400000 { 770 compatible = "qcom,sm6375-gcc"; 771 reg = <0 0x01400000 0 0x1f0000>; 772 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 773 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 774 <&sleep_clk>; 775 #power-domain-cells = <1>; 776 #clock-cells = <1>; 777 #reset-cells = <1>; 778 }; 779 780 usb_1_hsphy: phy@162b000 { 781 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 782 reg = <0 0x0162b000 0 0x400>; 783 784 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 785 clock-names = "ref"; 786 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 787 #phy-cells = <0>; 788 789 status = "disabled"; 790 }; 791 792 spmi_bus: spmi@1c40000 { 793 compatible = "qcom,spmi-pmic-arb"; 794 reg = <0 0x01c40000 0 0x1100>, 795 <0 0x01e00000 0 0x2000000>, 796 <0 0x03e00000 0 0x100000>, 797 <0 0x03f00000 0 0xa0000>, 798 <0 0x01c0a000 0 0x26000>; 799 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 800 interrupt-names = "periph_irq"; 801 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 802 qcom,ee = <0>; 803 qcom,channel = <0>; 804 #address-cells = <2>; 805 #size-cells = <0>; 806 interrupt-controller; 807 #interrupt-cells = <4>; 808 }; 809 810 tsens0: thermal-sensor@4411000 { 811 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 812 reg = <0 0x04411000 0 0x140>, /* TM */ 813 <0 0x04410000 0 0x20>; /* SROT */ 814 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "uplow", "critical"; 817 #thermal-sensor-cells = <1>; 818 #qcom,sensors = <15>; 819 }; 820 821 tsens1: thermal-sensor@4413000 { 822 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; 823 reg = <0 0x04413000 0 0x140>, /* TM */ 824 <0 0x04412000 0 0x20>; /* SROT */ 825 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 827 interrupt-names = "uplow", "critical"; 828 #thermal-sensor-cells = <1>; 829 #qcom,sensors = <11>; 830 }; 831 832 rpm_msg_ram: sram@45f0000 { 833 compatible = "qcom,rpm-msg-ram"; 834 reg = <0 0x045f0000 0 0x7000>; 835 }; 836 837 sram@4690000 { 838 compatible = "qcom,rpm-stats"; 839 reg = <0 0x04690000 0 0x400>; 840 }; 841 842 sdhc_2: mmc@4784000 { 843 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; 844 reg = <0 0x04784000 0 0x1000>; 845 846 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 848 interrupt-names = "hc_irq", "pwr_irq"; 849 850 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 851 <&gcc GCC_SDCC2_APPS_CLK>, 852 <&rpmcc RPM_SMD_XO_CLK_SRC>; 853 clock-names = "iface", "core", "xo"; 854 resets = <&gcc GCC_SDCC2_BCR>; 855 iommus = <&apps_smmu 0x40 0x0>; 856 857 pinctrl-0 = <&sdc2_on_state>; 858 pinctrl-1 = <&sdc2_off_state>; 859 pinctrl-names = "default", "sleep"; 860 861 qcom,dll-config = <0x0007642c>; 862 qcom,ddr-config = <0x80040868>; 863 power-domains = <&rpmpd SM6375_VDDCX>; 864 operating-points-v2 = <&sdhc2_opp_table>; 865 bus-width = <4>; 866 867 status = "disabled"; 868 869 sdhc2_opp_table: opp-table { 870 compatible = "operating-points-v2"; 871 872 opp-100000000 { 873 opp-hz = /bits/ 64 <100000000>; 874 required-opps = <&rpmpd_opp_low_svs>; 875 }; 876 877 opp-202000000 { 878 opp-hz = /bits/ 64 <202000000>; 879 required-opps = <&rpmpd_opp_svs_plus>; 880 }; 881 }; 882 }; 883 884 gpi_dma0: dma-controller@4a00000 { 885 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 886 reg = <0 0x04a00000 0 0x60000>; 887 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 897 dma-channels = <10>; 898 dma-channel-mask = <0x1f>; 899 iommus = <&apps_smmu 0x16 0x0>; 900 #dma-cells = <3>; 901 status = "disabled"; 902 }; 903 904 qupv3_id_0: geniqup@4ac0000 { 905 compatible = "qcom,geni-se-qup"; 906 reg = <0x0 0x04ac0000 0x0 0x2000>; 907 clock-names = "m-ahb", "s-ahb"; 908 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 909 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 910 iommus = <&apps_smmu 0x3 0x0>; 911 #address-cells = <2>; 912 #size-cells = <2>; 913 ranges; 914 status = "disabled"; 915 916 i2c0: i2c@4a80000 { 917 compatible = "qcom,geni-i2c"; 918 reg = <0x0 0x04a80000 0x0 0x4000>; 919 clock-names = "se"; 920 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 921 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&qup_i2c0_default>; 924 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 925 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 926 dma-names = "tx", "rx"; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 status = "disabled"; 930 }; 931 932 spi0: spi@4a80000 { 933 compatible = "qcom,geni-spi"; 934 reg = <0x0 0x04a80000 0x0 0x4000>; 935 clock-names = "se"; 936 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 937 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&qup_spi0_default>; 940 power-domains = <&rpmpd SM6375_VDDCX>; 941 operating-points-v2 = <&qup_opp_table>; 942 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 943 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 944 dma-names = "tx", "rx"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 i2c1: i2c@4a84000 { 951 compatible = "qcom,geni-i2c"; 952 reg = <0x0 0x04a84000 0x0 0x4000>; 953 clock-names = "se"; 954 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 955 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&qup_i2c1_default>; 958 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 959 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 960 dma-names = "tx", "rx"; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 status = "disabled"; 964 }; 965 966 spi1: spi@4a84000 { 967 compatible = "qcom,geni-spi"; 968 reg = <0x0 0x04a84000 0x0 0x4000>; 969 clock-names = "se"; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 971 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 972 power-domains = <&rpmpd SM6375_VDDCX>; 973 operating-points-v2 = <&qup_opp_table>; 974 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 975 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 976 dma-names = "tx", "rx"; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 status = "disabled"; 980 }; 981 982 i2c2: i2c@4a88000 { 983 compatible = "qcom,geni-i2c"; 984 reg = <0x0 0x04a88000 0x0 0x4000>; 985 clock-names = "se"; 986 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 987 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_i2c2_default>; 990 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 991 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 992 dma-names = "tx", "rx"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 status = "disabled"; 996 }; 997 998 spi2: spi@4a88000 { 999 compatible = "qcom,geni-spi"; 1000 reg = <0x0 0x04a88000 0x0 0x4000>; 1001 clock-names = "se"; 1002 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1003 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1004 power-domains = <&rpmpd SM6375_VDDCX>; 1005 operating-points-v2 = <&qup_opp_table>; 1006 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1007 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1008 dma-names = "tx", "rx"; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 status = "disabled"; 1012 }; 1013 1014 /* 1015 * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. 1016 * There is a comment in the included DTSI of another SoC saying that they 1017 * are not "bolled out" (probably meaning not routed to solder balls) 1018 * TLMM driver however, suggests there are as many as 15 QUPs in total! 1019 * Most of which don't even have pin configurations for.. Sad stuff! 1020 */ 1021 }; 1022 1023 gpi_dma1: dma-controller@4c00000 { 1024 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; 1025 reg = <0 0x04c00000 0 0x60000>; 1026 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 1036 dma-channels = <10>; 1037 dma-channel-mask = <0x1f>; 1038 iommus = <&apps_smmu 0xd6 0x0>; 1039 #dma-cells = <3>; 1040 status = "disabled"; 1041 }; 1042 1043 qupv3_id_1: geniqup@4cc0000 { 1044 compatible = "qcom,geni-se-qup"; 1045 reg = <0x0 0x04cc0000 0x0 0x2000>; 1046 clock-names = "m-ahb", "s-ahb"; 1047 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1048 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1049 iommus = <&apps_smmu 0xc3 0x0>; 1050 #address-cells = <2>; 1051 #size-cells = <2>; 1052 ranges; 1053 status = "disabled"; 1054 1055 i2c6: i2c@4c80000 { 1056 compatible = "qcom,geni-i2c"; 1057 reg = <0x0 0x04c80000 0x0 0x4000>; 1058 clock-names = "se"; 1059 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1060 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1061 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1062 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1063 dma-names = "tx", "rx"; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 spi6: spi@4c80000 { 1070 compatible = "qcom,geni-spi"; 1071 reg = <0x0 0x04c80000 0x0 0x4000>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1074 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>; 1075 power-domains = <&rpmpd SM6375_VDDCX>; 1076 operating-points-v2 = <&qup_opp_table>; 1077 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1078 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1079 dma-names = "tx", "rx"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 i2c7: i2c@4c84000 { 1086 compatible = "qcom,geni-i2c"; 1087 reg = <0x0 0x04c84000 0x0 0x4000>; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1090 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1091 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1092 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1093 dma-names = "tx", "rx"; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 spi7: spi@4c84000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0x0 0x04c84000 0x0 0x4000>; 1102 clock-names = "se"; 1103 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1104 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1105 power-domains = <&rpmpd SM6375_VDDCX>; 1106 operating-points-v2 = <&qup_opp_table>; 1107 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1108 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1109 dma-names = "tx", "rx"; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 status = "disabled"; 1113 }; 1114 1115 i2c8: i2c@4c88000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0x0 0x04c88000 0x0 0x4000>; 1118 clock-names = "se"; 1119 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1120 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&qup_i2c8_default>; 1123 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1124 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1125 dma-names = "tx", "rx"; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 status = "disabled"; 1129 }; 1130 1131 spi8: spi@4c88000 { 1132 compatible = "qcom,geni-spi"; 1133 reg = <0x0 0x04c88000 0x0 0x4000>; 1134 clock-names = "se"; 1135 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1136 interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1137 power-domains = <&rpmpd SM6375_VDDCX>; 1138 operating-points-v2 = <&qup_opp_table>; 1139 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1140 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1141 dma-names = "tx", "rx"; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 i2c9: i2c@4c8c000 { 1148 compatible = "qcom,geni-i2c"; 1149 reg = <0x0 0x04c8c000 0x0 0x4000>; 1150 clock-names = "se"; 1151 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1152 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1153 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1154 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1155 dma-names = "tx", "rx"; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 spi9: spi@4c8c000 { 1162 compatible = "qcom,geni-spi"; 1163 reg = <0x0 0x04c8c000 0x0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1166 interrupts = <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 1167 power-domains = <&rpmpd SM6375_VDDCX>; 1168 operating-points-v2 = <&qup_opp_table>; 1169 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1170 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1171 dma-names = "tx", "rx"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 i2c10: i2c@4c90000 { 1178 compatible = "qcom,geni-i2c"; 1179 reg = <0x0 0x04c90000 0x0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1182 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_i2c10_default>; 1185 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1186 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1187 dma-names = "tx", "rx"; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 status = "disabled"; 1191 }; 1192 1193 spi10: spi@4c90000 { 1194 compatible = "qcom,geni-spi"; 1195 reg = <0x0 0x04c90000 0x0 0x4000>; 1196 clock-names = "se"; 1197 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1198 interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>; 1199 power-domains = <&rpmpd SM6375_VDDCX>; 1200 operating-points-v2 = <&qup_opp_table>; 1201 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1202 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1203 dma-names = "tx", "rx"; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 status = "disabled"; 1207 }; 1208 }; 1209 1210 usb_1: usb@4ef8800 { 1211 compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; 1212 reg = <0 0x04ef8800 0 0x400>; 1213 1214 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1215 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1216 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1217 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1218 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1219 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1220 clock-names = "cfg_noc", 1221 "core", 1222 "iface", 1223 "sleep", 1224 "mock_utmi", 1225 "xo"; 1226 1227 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1228 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1229 assigned-clock-rates = <19200000>, <133333333>; 1230 1231 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1235 interrupt-names = "hs_phy_irq", 1236 "ss_phy_irq", 1237 "dm_hs_phy_irq", 1238 "dp_hs_phy_irq"; 1239 1240 power-domains = <&gcc USB30_PRIM_GDSC>; 1241 1242 resets = <&gcc GCC_USB30_PRIM_BCR>; 1243 1244 /* 1245 * This property is there to allow USB2 to work, as 1246 * USB3 is not implemented yet - (re)move it when 1247 * proper support is in place. 1248 */ 1249 qcom,select-utmi-as-pipe-clk; 1250 1251 #address-cells = <2>; 1252 #size-cells = <2>; 1253 ranges; 1254 1255 status = "disabled"; 1256 1257 usb_1_dwc3: usb@4e00000 { 1258 compatible = "snps,dwc3"; 1259 reg = <0 0x04e00000 0 0xcd00>; 1260 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1261 maximum-speed = "high-speed"; 1262 phys = <&usb_1_hsphy>; 1263 phy-names = "usb2-phy"; 1264 iommus = <&apps_smmu 0xe0 0x0>; 1265 1266 /* Yes, this impl *does* have an unfunny number of quirks.. */ 1267 snps,hird-threshold = /bits/ 8 <0x10>; 1268 snps,usb2-gadget-lpm-disable; 1269 snps,dis_u2_susphy_quirk; 1270 snps,is-utmi-l1-suspend; 1271 snps,dis-u1-entry-quirk; 1272 snps,dis-u2-entry-quirk; 1273 snps,usb3_lpm_capable; 1274 snps,has-lpm-erratum; 1275 tx-fifo-resize; 1276 }; 1277 }; 1278 1279 remoteproc_mss: remoteproc@6000000 { 1280 compatible = "qcom,sm6375-mpss-pas"; 1281 reg = <0 0x06000000 0 0x4040>; 1282 1283 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1284 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1285 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1286 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1287 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1288 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1289 interrupt-names = "wdog", 1290 "fatal", 1291 "ready", 1292 "handover", 1293 "stop-ack", 1294 "shutdown-ack"; 1295 1296 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1297 clock-names = "xo"; 1298 1299 power-domains = <&rpmpd SM6375_VDDCX>; 1300 power-domain-names = "cx"; 1301 1302 memory-region = <&pil_mpss_wlan_mem>; 1303 1304 qcom,smem-states = <&smp2p_modem_out 0>; 1305 qcom,smem-state-names = "stop"; 1306 1307 status = "disabled"; 1308 1309 glink-edge { 1310 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1311 IPCC_MPROC_SIGNAL_GLINK_QMP 1312 IRQ_TYPE_EDGE_RISING>; 1313 mboxes = <&ipcc IPCC_CLIENT_MPSS 1314 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1315 label = "modem"; 1316 qcom,remote-pid = <1>; 1317 }; 1318 }; 1319 1320 remoteproc_adsp: remoteproc@a400000 { 1321 compatible = "qcom,sm6375-adsp-pas"; 1322 reg = <0 0x0a400000 0 0x100>; 1323 1324 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1325 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1326 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1327 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1328 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1329 interrupt-names = "wdog", "fatal", "ready", 1330 "handover", "stop-ack"; 1331 1332 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1333 clock-names = "xo"; 1334 1335 power-domains = <&rpmpd SM6375_VDD_LPI_CX>, 1336 <&rpmpd SM6375_VDD_LPI_MX>; 1337 power-domain-names = "lcx", "lmx"; 1338 1339 memory-region = <&pil_adsp_mem>; 1340 1341 qcom,smem-states = <&smp2p_adsp_out 0>; 1342 qcom,smem-state-names = "stop"; 1343 1344 status = "disabled"; 1345 1346 glink-edge { 1347 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1348 IPCC_MPROC_SIGNAL_GLINK_QMP 1349 IRQ_TYPE_EDGE_RISING>; 1350 mboxes = <&ipcc IPCC_CLIENT_LPASS 1351 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1352 1353 label = "lpass"; 1354 qcom,remote-pid = <2>; 1355 }; 1356 }; 1357 1358 remoteproc_cdsp: remoteproc@b000000 { 1359 compatible = "qcom,sm6375-cdsp-pas"; 1360 reg = <0x0 0x0b000000 0x0 0x100000>; 1361 1362 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 1363 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1364 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1365 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1366 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1367 interrupt-names = "wdog", "fatal", "ready", 1368 "handover", "stop-ack"; 1369 1370 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1371 clock-names = "xo"; 1372 1373 power-domains = <&rpmpd SM6375_VDDCX>; 1374 power-domain-names = "cx"; 1375 1376 memory-region = <&pil_cdsp_mem>; 1377 1378 qcom,smem-states = <&smp2p_cdsp_out 0>; 1379 qcom,smem-state-names = "stop"; 1380 1381 status = "disabled"; 1382 1383 glink-edge { 1384 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1385 IPCC_MPROC_SIGNAL_GLINK_QMP 1386 IRQ_TYPE_EDGE_RISING>; 1387 mboxes = <&ipcc IPCC_CLIENT_CDSP 1388 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1389 label = "cdsp"; 1390 qcom,remote-pid = <5>; 1391 }; 1392 }; 1393 1394 sram@c125000 { 1395 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; 1396 reg = <0 0x0c125000 0 0x1000>; 1397 ranges = <0 0 0x0c125000 0x1000>; 1398 1399 #address-cells = <1>; 1400 #size-cells = <1>; 1401 1402 pil-reloc@94c { 1403 compatible = "qcom,pil-reloc-info"; 1404 reg = <0x94c 0xc8>; 1405 }; 1406 }; 1407 1408 apps_smmu: iommu@c600000 { 1409 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; 1410 reg = <0 0x0c600000 0 0x100000>; 1411 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1476 1477 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, 1478 <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, 1479 <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 1480 #global-interrupts = <1>; 1481 #iommu-cells = <2>; 1482 }; 1483 1484 wifi: wifi@c800000 { 1485 compatible = "qcom,wcn3990-wifi"; 1486 reg = <0 0x0c800000 0 0x800000>; 1487 reg-names = "membase"; 1488 memory-region = <&pil_wlan_mem>; 1489 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1501 iommus = <&apps_smmu 0x80 0x1>; 1502 qcom,msa-fixed-perm; 1503 status = "disabled"; 1504 }; 1505 1506 intc: interrupt-controller@f200000 { 1507 compatible = "arm,gic-v3"; 1508 reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ 1509 <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ 1510 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1511 #redistributor-regions = <1>; 1512 #interrupt-cells = <3>; 1513 redistributor-stride = <0 0x20000>; 1514 interrupt-controller; 1515 }; 1516 1517 timer@f420000 { 1518 compatible = "arm,armv7-timer-mem"; 1519 reg = <0 0x0f420000 0 0x1000>; 1520 ranges = <0 0 0 0x20000000>; 1521 #address-cells = <1>; 1522 #size-cells = <1>; 1523 1524 frame@f421000 { 1525 reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; 1526 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1528 frame-number = <0>; 1529 }; 1530 1531 frame@f423000 { 1532 reg = <0x0f243000 0x1000>; 1533 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1534 frame-number = <1>; 1535 status = "disabled"; 1536 }; 1537 1538 frame@f425000 { 1539 reg = <0x0f425000 0x1000>; 1540 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1541 frame-number = <2>; 1542 status = "disabled"; 1543 }; 1544 1545 frame@f427000 { 1546 reg = <0x0f427000 0x1000>; 1547 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1548 frame-number = <3>; 1549 status = "disabled"; 1550 }; 1551 1552 frame@f429000 { 1553 reg = <0x0f429000 0x1000>; 1554 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1555 frame-number = <4>; 1556 status = "disabled"; 1557 }; 1558 1559 frame@f42b000 { 1560 reg = <0x0f42b000 0x1000>; 1561 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1562 frame-number = <5>; 1563 status = "disabled"; 1564 }; 1565 1566 frame@f42d000 { 1567 reg = <0x0f42d000 0x1000>; 1568 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1569 frame-number = <6>; 1570 status = "disabled"; 1571 }; 1572 }; 1573 1574 cpucp_l3: interconnect@fd90000 { 1575 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; 1576 reg = <0 0x0fd90000 0 0x1000>; 1577 1578 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1579 clock-names = "xo", "alternate"; 1580 #interconnect-cells = <1>; 1581 }; 1582 1583 cpufreq_hw: cpufreq@fd91000 { 1584 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; 1585 reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; 1586 reg-names = "freq-domain0", "freq-domain1"; 1587 1588 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1589 clock-names = "xo", "alternate"; 1590 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1592 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 1593 #freq-domain-cells = <1>; 1594 #clock-cells = <1>; 1595 }; 1596 }; 1597 1598 thermal-zones { 1599 mapss0-thermal { 1600 polling-delay-passive = <0>; 1601 polling-delay = <0>; 1602 1603 thermal-sensors = <&tsens0 0>; 1604 1605 trips { 1606 mapss0_alert0: trip-point0 { 1607 temperature = <90000>; 1608 hysteresis = <2000>; 1609 type = "passive"; 1610 }; 1611 1612 mapss0_alert1: trip-point1 { 1613 temperature = <95000>; 1614 hysteresis = <2000>; 1615 type = "passive"; 1616 }; 1617 1618 mapss0_crit: mapss-crit { 1619 temperature = <110000>; 1620 hysteresis = <1000>; 1621 type = "critical"; 1622 }; 1623 }; 1624 }; 1625 1626 cpu0-thermal { 1627 polling-delay-passive = <0>; 1628 polling-delay = <0>; 1629 1630 thermal-sensors = <&tsens0 1>; 1631 1632 trips { 1633 cpu0_alert0: trip-point0 { 1634 temperature = <90000>; 1635 hysteresis = <2000>; 1636 type = "passive"; 1637 }; 1638 1639 cpu0_alert1: trip-point1 { 1640 temperature = <95000>; 1641 hysteresis = <2000>; 1642 type = "passive"; 1643 }; 1644 1645 cpu0_crit: cpu-crit { 1646 temperature = <110000>; 1647 hysteresis = <1000>; 1648 type = "critical"; 1649 }; 1650 }; 1651 }; 1652 1653 cpu1-thermal { 1654 polling-delay-passive = <0>; 1655 polling-delay = <0>; 1656 1657 thermal-sensors = <&tsens0 2>; 1658 1659 trips { 1660 cpu1_alert0: trip-point0 { 1661 temperature = <90000>; 1662 hysteresis = <2000>; 1663 type = "passive"; 1664 }; 1665 1666 cpu1_alert1: trip-point1 { 1667 temperature = <95000>; 1668 hysteresis = <2000>; 1669 type = "passive"; 1670 }; 1671 1672 cpu1_crit: cpu-crit { 1673 temperature = <110000>; 1674 hysteresis = <1000>; 1675 type = "critical"; 1676 }; 1677 }; 1678 }; 1679 1680 cpu2-thermal { 1681 polling-delay-passive = <0>; 1682 polling-delay = <0>; 1683 1684 thermal-sensors = <&tsens0 3>; 1685 1686 trips { 1687 cpu2_alert0: trip-point0 { 1688 temperature = <90000>; 1689 hysteresis = <2000>; 1690 type = "passive"; 1691 }; 1692 1693 cpu2_alert1: trip-point1 { 1694 temperature = <95000>; 1695 hysteresis = <2000>; 1696 type = "passive"; 1697 }; 1698 1699 cpu2_crit: cpu-crit { 1700 temperature = <110000>; 1701 hysteresis = <1000>; 1702 type = "critical"; 1703 }; 1704 }; 1705 }; 1706 1707 cpu3-thermal { 1708 polling-delay-passive = <0>; 1709 polling-delay = <0>; 1710 1711 thermal-sensors = <&tsens0 4>; 1712 1713 trips { 1714 cpu3_alert0: trip-point0 { 1715 temperature = <90000>; 1716 hysteresis = <2000>; 1717 type = "passive"; 1718 }; 1719 1720 cpu3_alert1: trip-point1 { 1721 temperature = <95000>; 1722 hysteresis = <2000>; 1723 type = "passive"; 1724 }; 1725 1726 cpu3_crit: cpu-crit { 1727 temperature = <110000>; 1728 hysteresis = <1000>; 1729 type = "critical"; 1730 }; 1731 }; 1732 }; 1733 1734 cpu4-thermal { 1735 polling-delay-passive = <0>; 1736 polling-delay = <0>; 1737 1738 thermal-sensors = <&tsens0 5>; 1739 1740 trips { 1741 cpu4_alert0: trip-point0 { 1742 temperature = <90000>; 1743 hysteresis = <2000>; 1744 type = "passive"; 1745 }; 1746 1747 cpu4_alert1: trip-point1 { 1748 temperature = <95000>; 1749 hysteresis = <2000>; 1750 type = "passive"; 1751 }; 1752 1753 cpu4_crit: cpu-crit { 1754 temperature = <110000>; 1755 hysteresis = <1000>; 1756 type = "critical"; 1757 }; 1758 }; 1759 }; 1760 1761 cpu5-thermal { 1762 polling-delay-passive = <0>; 1763 polling-delay = <0>; 1764 1765 thermal-sensors = <&tsens0 6>; 1766 1767 trips { 1768 cpu5_alert0: trip-point0 { 1769 temperature = <90000>; 1770 hysteresis = <2000>; 1771 type = "passive"; 1772 }; 1773 1774 cpu5_alert1: trip-point1 { 1775 temperature = <95000>; 1776 hysteresis = <2000>; 1777 type = "passive"; 1778 }; 1779 1780 cpu5_crit: cpu-crit { 1781 temperature = <110000>; 1782 hysteresis = <1000>; 1783 type = "critical"; 1784 }; 1785 }; 1786 }; 1787 1788 cluster0-thermal { 1789 polling-delay-passive = <0>; 1790 polling-delay = <0>; 1791 1792 thermal-sensors = <&tsens0 7>; 1793 1794 trips { 1795 cluster0_alert0: trip-point0 { 1796 temperature = <90000>; 1797 hysteresis = <2000>; 1798 type = "passive"; 1799 }; 1800 1801 cluster0_alert1: trip-point1 { 1802 temperature = <95000>; 1803 hysteresis = <2000>; 1804 type = "passive"; 1805 }; 1806 1807 cluster0_crit: cpu-crit { 1808 temperature = <110000>; 1809 hysteresis = <1000>; 1810 type = "critical"; 1811 }; 1812 }; 1813 }; 1814 1815 cluster1-thermal { 1816 polling-delay-passive = <0>; 1817 polling-delay = <0>; 1818 1819 thermal-sensors = <&tsens0 8>; 1820 1821 trips { 1822 cluster1_alert0: trip-point0 { 1823 temperature = <90000>; 1824 hysteresis = <2000>; 1825 type = "passive"; 1826 }; 1827 1828 cluster1_alert1: trip-point1 { 1829 temperature = <95000>; 1830 hysteresis = <2000>; 1831 type = "passive"; 1832 }; 1833 1834 cluster1_crit: cpu-crit { 1835 temperature = <110000>; 1836 hysteresis = <1000>; 1837 type = "critical"; 1838 }; 1839 }; 1840 }; 1841 1842 cpu6-thermal { 1843 polling-delay-passive = <0>; 1844 polling-delay = <0>; 1845 1846 thermal-sensors = <&tsens0 9>; 1847 1848 trips { 1849 cpu6_alert0: trip-point0 { 1850 temperature = <90000>; 1851 hysteresis = <2000>; 1852 type = "passive"; 1853 }; 1854 1855 cpu6_alert1: trip-point1 { 1856 temperature = <95000>; 1857 hysteresis = <2000>; 1858 type = "passive"; 1859 }; 1860 1861 cpu6_crit: cpu-crit { 1862 temperature = <110000>; 1863 hysteresis = <1000>; 1864 type = "critical"; 1865 }; 1866 }; 1867 }; 1868 1869 cpu7-thermal { 1870 polling-delay-passive = <0>; 1871 polling-delay = <0>; 1872 1873 thermal-sensors = <&tsens0 10>; 1874 1875 trips { 1876 cpu7_alert0: trip-point0 { 1877 temperature = <90000>; 1878 hysteresis = <2000>; 1879 type = "passive"; 1880 }; 1881 1882 cpu7_alert1: trip-point1 { 1883 temperature = <95000>; 1884 hysteresis = <2000>; 1885 type = "passive"; 1886 }; 1887 1888 cpu7_crit: cpu-crit { 1889 temperature = <110000>; 1890 hysteresis = <1000>; 1891 type = "critical"; 1892 }; 1893 }; 1894 }; 1895 1896 cpu-unk0-thermal { 1897 polling-delay-passive = <0>; 1898 polling-delay = <0>; 1899 1900 thermal-sensors = <&tsens0 11>; 1901 1902 trips { 1903 cpu_unk0_alert0: trip-point0 { 1904 temperature = <90000>; 1905 hysteresis = <2000>; 1906 type = "passive"; 1907 }; 1908 1909 cpu_unk0_alert1: trip-point1 { 1910 temperature = <95000>; 1911 hysteresis = <2000>; 1912 type = "passive"; 1913 }; 1914 1915 cpu_unk0_crit: cpu-crit { 1916 temperature = <110000>; 1917 hysteresis = <1000>; 1918 type = "critical"; 1919 }; 1920 }; 1921 }; 1922 1923 cpu-unk1-thermal { 1924 polling-delay-passive = <0>; 1925 polling-delay = <0>; 1926 1927 thermal-sensors = <&tsens0 12>; 1928 1929 trips { 1930 cpu_unk1_alert0: trip-point0 { 1931 temperature = <90000>; 1932 hysteresis = <2000>; 1933 type = "passive"; 1934 }; 1935 1936 cpu_unk1_alert1: trip-point1 { 1937 temperature = <95000>; 1938 hysteresis = <2000>; 1939 type = "passive"; 1940 }; 1941 1942 cpu_unk1_crit: cpu-crit { 1943 temperature = <110000>; 1944 hysteresis = <1000>; 1945 type = "critical"; 1946 }; 1947 }; 1948 }; 1949 1950 gpuss0-thermal { 1951 polling-delay-passive = <0>; 1952 polling-delay = <0>; 1953 1954 thermal-sensors = <&tsens0 13>; 1955 1956 trips { 1957 gpuss0_alert0: trip-point0 { 1958 temperature = <90000>; 1959 hysteresis = <2000>; 1960 type = "passive"; 1961 }; 1962 1963 gpuss0_alert1: trip-point1 { 1964 temperature = <95000>; 1965 hysteresis = <2000>; 1966 type = "passive"; 1967 }; 1968 1969 gpuss0_crit: gpu-crit { 1970 temperature = <110000>; 1971 hysteresis = <1000>; 1972 type = "critical"; 1973 }; 1974 }; 1975 }; 1976 1977 gpuss1-thermal { 1978 polling-delay-passive = <0>; 1979 polling-delay = <0>; 1980 1981 thermal-sensors = <&tsens0 14>; 1982 1983 trips { 1984 gpuss1_alert0: trip-point0 { 1985 temperature = <90000>; 1986 hysteresis = <2000>; 1987 type = "passive"; 1988 }; 1989 1990 gpuss1_alert1: trip-point1 { 1991 temperature = <95000>; 1992 hysteresis = <2000>; 1993 type = "passive"; 1994 }; 1995 1996 gpuss1_crit: gpu-crit { 1997 temperature = <110000>; 1998 hysteresis = <1000>; 1999 type = "critical"; 2000 }; 2001 }; 2002 }; 2003 2004 mapss1-thermal { 2005 polling-delay-passive = <0>; 2006 polling-delay = <0>; 2007 2008 thermal-sensors = <&tsens1 0>; 2009 2010 trips { 2011 mapss1_alert0: trip-point0 { 2012 temperature = <90000>; 2013 hysteresis = <2000>; 2014 type = "passive"; 2015 }; 2016 2017 mapss1_alert1: trip-point1 { 2018 temperature = <95000>; 2019 hysteresis = <2000>; 2020 type = "passive"; 2021 }; 2022 2023 mapss1_crit: mapss-crit { 2024 temperature = <110000>; 2025 hysteresis = <1000>; 2026 type = "critical"; 2027 }; 2028 }; 2029 }; 2030 2031 cwlan-thermal { 2032 polling-delay-passive = <0>; 2033 polling-delay = <0>; 2034 2035 thermal-sensors = <&tsens1 1>; 2036 2037 trips { 2038 cwlan_alert0: trip-point0 { 2039 temperature = <90000>; 2040 hysteresis = <2000>; 2041 type = "passive"; 2042 }; 2043 2044 cwlan_alert1: trip-point1 { 2045 temperature = <95000>; 2046 hysteresis = <2000>; 2047 type = "passive"; 2048 }; 2049 2050 cwlan_crit: cwlan-crit { 2051 temperature = <110000>; 2052 hysteresis = <1000>; 2053 type = "critical"; 2054 }; 2055 }; 2056 }; 2057 2058 audio-thermal { 2059 polling-delay-passive = <0>; 2060 polling-delay = <0>; 2061 2062 thermal-sensors = <&tsens1 2>; 2063 2064 trips { 2065 audio_alert0: trip-point0 { 2066 temperature = <90000>; 2067 hysteresis = <2000>; 2068 type = "passive"; 2069 }; 2070 2071 audio_alert1: trip-point1 { 2072 temperature = <95000>; 2073 hysteresis = <2000>; 2074 type = "passive"; 2075 }; 2076 2077 audio_crit: audio-crit { 2078 temperature = <110000>; 2079 hysteresis = <1000>; 2080 type = "critical"; 2081 }; 2082 }; 2083 }; 2084 2085 ddr-thermal { 2086 polling-delay-passive = <0>; 2087 polling-delay = <0>; 2088 2089 thermal-sensors = <&tsens1 3>; 2090 2091 trips { 2092 ddr_alert0: trip-point0 { 2093 temperature = <90000>; 2094 hysteresis = <2000>; 2095 type = "passive"; 2096 }; 2097 2098 ddr_alert1: trip-point1 { 2099 temperature = <95000>; 2100 hysteresis = <2000>; 2101 type = "passive"; 2102 }; 2103 2104 ddr_crit: ddr-crit { 2105 temperature = <110000>; 2106 hysteresis = <1000>; 2107 type = "critical"; 2108 }; 2109 }; 2110 }; 2111 2112 q6hvx-thermal { 2113 polling-delay-passive = <0>; 2114 polling-delay = <0>; 2115 2116 thermal-sensors = <&tsens1 4>; 2117 2118 trips { 2119 q6hvx_alert0: trip-point0 { 2120 temperature = <90000>; 2121 hysteresis = <2000>; 2122 type = "passive"; 2123 }; 2124 2125 q6hvx_alert1: trip-point1 { 2126 temperature = <95000>; 2127 hysteresis = <2000>; 2128 type = "passive"; 2129 }; 2130 2131 q6hvx_crit: q6hvx-crit { 2132 temperature = <110000>; 2133 hysteresis = <1000>; 2134 type = "critical"; 2135 }; 2136 }; 2137 }; 2138 2139 camera-thermal { 2140 polling-delay-passive = <0>; 2141 polling-delay = <0>; 2142 2143 thermal-sensors = <&tsens1 5>; 2144 2145 trips { 2146 camera_alert0: trip-point0 { 2147 temperature = <90000>; 2148 hysteresis = <2000>; 2149 type = "passive"; 2150 }; 2151 2152 camera_alert1: trip-point1 { 2153 temperature = <95000>; 2154 hysteresis = <2000>; 2155 type = "passive"; 2156 }; 2157 2158 camera_crit: camera-crit { 2159 temperature = <110000>; 2160 hysteresis = <1000>; 2161 type = "critical"; 2162 }; 2163 }; 2164 }; 2165 2166 mdm-core0-thermal { 2167 polling-delay-passive = <0>; 2168 polling-delay = <0>; 2169 2170 thermal-sensors = <&tsens1 6>; 2171 2172 trips { 2173 mdm_core0_alert0: trip-point0 { 2174 temperature = <90000>; 2175 hysteresis = <2000>; 2176 type = "passive"; 2177 }; 2178 2179 mdm_core0_alert1: trip-point1 { 2180 temperature = <95000>; 2181 hysteresis = <2000>; 2182 type = "passive"; 2183 }; 2184 2185 mdm_core0_crit: mdm-core0-crit { 2186 temperature = <110000>; 2187 hysteresis = <1000>; 2188 type = "critical"; 2189 }; 2190 }; 2191 }; 2192 2193 mdm-core1-thermal { 2194 polling-delay-passive = <0>; 2195 polling-delay = <0>; 2196 2197 thermal-sensors = <&tsens1 7>; 2198 2199 trips { 2200 mdm_core1_alert0: trip-point0 { 2201 temperature = <90000>; 2202 hysteresis = <2000>; 2203 type = "passive"; 2204 }; 2205 2206 mdm_core1_alert1: trip-point1 { 2207 temperature = <95000>; 2208 hysteresis = <2000>; 2209 type = "passive"; 2210 }; 2211 2212 mdm_core1_crit: mdm-core1-crit { 2213 temperature = <110000>; 2214 hysteresis = <1000>; 2215 type = "critical"; 2216 }; 2217 }; 2218 }; 2219 2220 mdm-vec-thermal { 2221 polling-delay-passive = <0>; 2222 polling-delay = <0>; 2223 2224 thermal-sensors = <&tsens1 8>; 2225 2226 trips { 2227 mdm_vec_alert0: trip-point0 { 2228 temperature = <90000>; 2229 hysteresis = <2000>; 2230 type = "passive"; 2231 }; 2232 2233 mdm_vec_alert1: trip-point1 { 2234 temperature = <95000>; 2235 hysteresis = <2000>; 2236 type = "passive"; 2237 }; 2238 2239 mdm_vec_crit: mdm-vec-crit { 2240 temperature = <110000>; 2241 hysteresis = <1000>; 2242 type = "critical"; 2243 }; 2244 }; 2245 }; 2246 2247 msm-scl-thermal { 2248 polling-delay-passive = <0>; 2249 polling-delay = <0>; 2250 2251 thermal-sensors = <&tsens1 9>; 2252 2253 trips { 2254 msm_scl_alert0: trip-point0 { 2255 temperature = <90000>; 2256 hysteresis = <2000>; 2257 type = "passive"; 2258 }; 2259 2260 msm_scl_alert1: trip-point1 { 2261 temperature = <95000>; 2262 hysteresis = <2000>; 2263 type = "passive"; 2264 }; 2265 2266 msm_scl_crit: msm-scl-crit { 2267 temperature = <110000>; 2268 hysteresis = <1000>; 2269 type = "critical"; 2270 }; 2271 }; 2272 }; 2273 2274 video-thermal { 2275 polling-delay-passive = <0>; 2276 polling-delay = <0>; 2277 2278 thermal-sensors = <&tsens1 10>; 2279 2280 trips { 2281 video_alert0: trip-point0 { 2282 temperature = <90000>; 2283 hysteresis = <2000>; 2284 type = "passive"; 2285 }; 2286 2287 video_alert1: trip-point1 { 2288 temperature = <95000>; 2289 hysteresis = <2000>; 2290 type = "passive"; 2291 }; 2292 2293 video_crit: video-crit { 2294 temperature = <110000>; 2295 hysteresis = <1000>; 2296 type = "critical"; 2297 }; 2298 }; 2299 }; 2300 }; 2301 2302 timer { 2303 compatible = "arm,armv8-timer"; 2304 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2305 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2306 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2307 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2308 }; 2309}; 2310