1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6125.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 clocks { 21 xo_board: xo-board { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <19200000>; 25 clock-output-names = "xo_board"; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32000>; 32 clock-output-names = "sleep_clk"; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 CPU0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "qcom,kryo260"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 capacity-dmips-mhz = <1024>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 cache-unified; 51 }; 52 }; 53 54 CPU1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "qcom,kryo260"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 capacity-dmips-mhz = <1024>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 CPU2: cpu@2 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo260"; 66 reg = <0x0 0x2>; 67 enable-method = "psci"; 68 capacity-dmips-mhz = <1024>; 69 next-level-cache = <&L2_0>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "qcom,kryo260"; 75 reg = <0x0 0x3>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <1024>; 78 next-level-cache = <&L2_0>; 79 }; 80 81 CPU4: cpu@100 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo260"; 84 reg = <0x0 0x100>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <1638>; 87 next-level-cache = <&L2_1>; 88 L2_1: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 }; 93 }; 94 95 CPU5: cpu@101 { 96 device_type = "cpu"; 97 compatible = "qcom,kryo260"; 98 reg = <0x0 0x101>; 99 enable-method = "psci"; 100 capacity-dmips-mhz = <1638>; 101 next-level-cache = <&L2_1>; 102 }; 103 104 CPU6: cpu@102 { 105 device_type = "cpu"; 106 compatible = "qcom,kryo260"; 107 reg = <0x0 0x102>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <1638>; 110 next-level-cache = <&L2_1>; 111 }; 112 113 CPU7: cpu@103 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo260"; 116 reg = <0x0 0x103>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <1638>; 119 next-level-cache = <&L2_1>; 120 }; 121 122 cpu-map { 123 cluster0 { 124 core0 { 125 cpu = <&CPU0>; 126 }; 127 128 core1 { 129 cpu = <&CPU1>; 130 }; 131 132 core2 { 133 cpu = <&CPU2>; 134 }; 135 136 core3 { 137 cpu = <&CPU3>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&CPU4>; 144 }; 145 146 core1 { 147 cpu = <&CPU5>; 148 }; 149 150 core2 { 151 cpu = <&CPU6>; 152 }; 153 154 core3 { 155 cpu = <&CPU7>; 156 }; 157 }; 158 }; 159 }; 160 161 firmware { 162 scm: scm { 163 compatible = "qcom,scm-sm6125", "qcom,scm"; 164 #reset-cells = <1>; 165 }; 166 }; 167 168 memory@40000000 { 169 /* We expect the bootloader to fill in the size */ 170 reg = <0x0 0x40000000 0x0 0x0>; 171 device_type = "memory"; 172 }; 173 174 pmu { 175 compatible = "arm,armv8-pmuv3"; 176 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 reserved_memory: reserved-memory { 185 #address-cells = <2>; 186 #size-cells = <2>; 187 ranges; 188 189 hyp_mem: memory@45700000 { 190 reg = <0x0 0x45700000 0x0 0x600000>; 191 no-map; 192 }; 193 194 xbl_aop_mem: memory@45e00000 { 195 reg = <0x0 0x45e00000 0x0 0x140000>; 196 no-map; 197 }; 198 199 sec_apps_mem: memory@45fff000 { 200 reg = <0x0 0x45fff000 0x0 0x1000>; 201 no-map; 202 }; 203 204 smem_mem: memory@46000000 { 205 reg = <0x0 0x46000000 0x0 0x200000>; 206 no-map; 207 }; 208 209 reserved_mem1: memory@46200000 { 210 reg = <0x0 0x46200000 0x0 0x2d00000>; 211 no-map; 212 }; 213 214 camera_mem: memory@4ab00000 { 215 reg = <0x0 0x4ab00000 0x0 0x500000>; 216 no-map; 217 }; 218 219 modem_mem: memory@4b000000 { 220 reg = <0x0 0x4b000000 0x0 0x7e00000>; 221 no-map; 222 }; 223 224 venus_mem: memory@52e00000 { 225 reg = <0x0 0x52e00000 0x0 0x500000>; 226 no-map; 227 }; 228 229 wlan_msa_mem: memory@53300000 { 230 reg = <0x0 0x53300000 0x0 0x200000>; 231 no-map; 232 }; 233 234 cdsp_mem: memory@53500000 { 235 reg = <0x0 0x53500000 0x0 0x1e00000>; 236 no-map; 237 }; 238 239 adsp_pil_mem: memory@55300000 { 240 reg = <0x0 0x55300000 0x0 0x1e00000>; 241 no-map; 242 }; 243 244 ipa_fw_mem: memory@57100000 { 245 reg = <0x0 0x57100000 0x0 0x10000>; 246 no-map; 247 }; 248 249 ipa_gsi_mem: memory@57110000 { 250 reg = <0x0 0x57110000 0x0 0x5000>; 251 no-map; 252 }; 253 254 gpu_mem: memory@57115000 { 255 reg = <0x0 0x57115000 0x0 0x2000>; 256 no-map; 257 }; 258 259 cont_splash_mem: memory@5c000000 { 260 reg = <0x0 0x5c000000 0x0 0x00f00000>; 261 no-map; 262 }; 263 264 dfps_data_mem: memory@5cf00000 { 265 reg = <0x0 0x5cf00000 0x0 0x0100000>; 266 no-map; 267 }; 268 269 cdsp_sec_mem: memory@5f800000 { 270 reg = <0x0 0x5f800000 0x0 0x1e00000>; 271 no-map; 272 }; 273 274 qseecom_mem: memory@5e400000 { 275 reg = <0x0 0x5e400000 0x0 0x1400000>; 276 no-map; 277 }; 278 279 sdsp_mem: memory@f3000000 { 280 reg = <0x0 0xf3000000 0x0 0x400000>; 281 no-map; 282 }; 283 284 adsp_mem: memory@f3400000 { 285 reg = <0x0 0xf3400000 0x0 0x800000>; 286 no-map; 287 }; 288 289 qseecom_ta_mem: memory@13fc00000 { 290 reg = <0x1 0x3fc00000 0x0 0x400000>; 291 no-map; 292 }; 293 }; 294 295 rpm-glink { 296 compatible = "qcom,glink-rpm"; 297 298 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 299 qcom,rpm-msg-ram = <&rpm_msg_ram>; 300 mboxes = <&apcs_glb 0>; 301 302 rpm_requests: rpm-requests { 303 compatible = "qcom,rpm-sm6125"; 304 qcom,glink-channels = "rpm_requests"; 305 306 rpmcc: clock-controller { 307 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; 308 #clock-cells = <1>; 309 }; 310 311 rpmpd: power-controller { 312 compatible = "qcom,sm6125-rpmpd"; 313 #power-domain-cells = <1>; 314 operating-points-v2 = <&rpmpd_opp_table>; 315 316 rpmpd_opp_table: opp-table { 317 compatible = "operating-points-v2"; 318 319 rpmpd_opp_ret: opp1 { 320 opp-level = <RPM_SMD_LEVEL_RETENTION>; 321 }; 322 323 rpmpd_opp_ret_plus: opp2 { 324 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 325 }; 326 327 rpmpd_opp_min_svs: opp3 { 328 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 329 }; 330 331 rpmpd_opp_low_svs: opp4 { 332 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 333 }; 334 335 rpmpd_opp_svs: opp5 { 336 opp-level = <RPM_SMD_LEVEL_SVS>; 337 }; 338 339 rpmpd_opp_svs_plus: opp6 { 340 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 341 }; 342 343 rpmpd_opp_nom: opp7 { 344 opp-level = <RPM_SMD_LEVEL_NOM>; 345 }; 346 347 rpmpd_opp_nom_plus: opp8 { 348 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 349 }; 350 351 rpmpd_opp_turbo: opp9 { 352 opp-level = <RPM_SMD_LEVEL_TURBO>; 353 }; 354 355 rpmpd_opp_turbo_no_cpr: opp10 { 356 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 357 }; 358 }; 359 }; 360 }; 361 }; 362 363 smem: smem { 364 compatible = "qcom,smem"; 365 memory-region = <&smem_mem>; 366 hwlocks = <&tcsr_mutex 3>; 367 }; 368 369 soc@0 { 370 #address-cells = <1>; 371 #size-cells = <1>; 372 ranges = <0x00 0x00 0x00 0xffffffff>; 373 compatible = "simple-bus"; 374 375 tcsr_mutex: hwlock@340000 { 376 compatible = "qcom,tcsr-mutex"; 377 reg = <0x00340000 0x20000>; 378 #hwlock-cells = <1>; 379 }; 380 381 tlmm: pinctrl@500000 { 382 compatible = "qcom,sm6125-tlmm"; 383 reg = <0x00500000 0x400000>, 384 <0x00900000 0x400000>, 385 <0x00d00000 0x400000>; 386 reg-names = "west", "south", "east"; 387 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 388 gpio-controller; 389 gpio-ranges = <&tlmm 0 0 134>; 390 #gpio-cells = <2>; 391 interrupt-controller; 392 #interrupt-cells = <2>; 393 394 sdc2_off_state: sdc2-off-state { 395 clk-pins { 396 pins = "sdc2_clk"; 397 drive-strength = <2>; 398 bias-disable; 399 }; 400 401 cmd-pins { 402 pins = "sdc2_cmd"; 403 drive-strength = <2>; 404 bias-pull-up; 405 }; 406 407 data-pins { 408 pins = "sdc2_data"; 409 drive-strength = <2>; 410 bias-pull-up; 411 }; 412 }; 413 414 sdc2_on_state: sdc2-on-state { 415 clk-pins { 416 pins = "sdc2_clk"; 417 drive-strength = <16>; 418 bias-disable; 419 }; 420 421 cmd-pins { 422 pins = "sdc2_cmd"; 423 drive-strength = <10>; 424 bias-pull-up; 425 }; 426 427 data-pins { 428 pins = "sdc2_data"; 429 drive-strength = <10>; 430 bias-pull-up; 431 }; 432 }; 433 434 qup_i2c0_default: qup-i2c0-default-state { 435 pins = "gpio0", "gpio1"; 436 function = "qup00"; 437 drive-strength = <2>; 438 bias-disable; 439 }; 440 441 qup_i2c0_sleep: qup-i2c0-sleep-state { 442 pins = "gpio0", "gpio1"; 443 function = "gpio"; 444 drive-strength = <2>; 445 bias-pull-up; 446 }; 447 448 qup_i2c1_default: qup-i2c1-default-state { 449 pins = "gpio4", "gpio5"; 450 function = "qup01"; 451 drive-strength = <2>; 452 bias-disable; 453 }; 454 455 qup_i2c1_sleep: qup-i2c1-sleep-state { 456 pins = "gpio4", "gpio5"; 457 function = "gpio"; 458 drive-strength = <2>; 459 bias-pull-up; 460 }; 461 462 qup_i2c2_default: qup-i2c2-default-state { 463 pins = "gpio6", "gpio7"; 464 function = "qup02"; 465 drive-strength = <2>; 466 bias-disable; 467 }; 468 469 qup_i2c2_sleep: qup-i2c2-sleep-state { 470 pins = "gpio6", "gpio7"; 471 function = "gpio"; 472 drive-strength = <2>; 473 bias-pull-up; 474 }; 475 476 qup_i2c3_default: qup-i2c3-default-state { 477 pins = "gpio14", "gpio15"; 478 function = "qup03"; 479 drive-strength = <2>; 480 bias-disable; 481 }; 482 483 qup_i2c3_sleep: qup-i2c3-sleep-state { 484 pins = "gpio14", "gpio15"; 485 function = "gpio"; 486 drive-strength = <2>; 487 bias-pull-up; 488 }; 489 490 qup_i2c4_default: qup-i2c4-default-state { 491 pins = "gpio16", "gpio17"; 492 function = "qup04"; 493 drive-strength = <2>; 494 bias-disable; 495 }; 496 497 qup_i2c4_sleep: qup-i2c4-sleep-state { 498 pins = "gpio16", "gpio17"; 499 function = "gpio"; 500 drive-strength = <2>; 501 bias-pull-up; 502 }; 503 504 qup_i2c5_default: qup-i2c5-default-state { 505 pins = "gpio22", "gpio23"; 506 function = "qup10"; 507 drive-strength = <2>; 508 bias-disable; 509 }; 510 511 qup_i2c5_sleep: qup-i2c5-sleep-state { 512 pins = "gpio22", "gpio23"; 513 function = "gpio"; 514 drive-strength = <2>; 515 bias-pull-up; 516 }; 517 518 qup_i2c6_default: qup-i2c6-default-state { 519 pins = "gpio30", "gpio31"; 520 function = "qup11"; 521 drive-strength = <2>; 522 bias-disable; 523 }; 524 525 qup_i2c6_sleep: qup-i2c6-sleep-state { 526 pins = "gpio30", "gpio31"; 527 function = "gpio"; 528 drive-strength = <2>; 529 bias-pull-up; 530 }; 531 532 qup_i2c7_default: qup-i2c7-default-state { 533 pins = "gpio28", "gpio29"; 534 function = "qup12"; 535 drive-strength = <2>; 536 bias-disable; 537 }; 538 539 qup_i2c7_sleep: qup-i2c7-sleep-state { 540 pins = "gpio28", "gpio29"; 541 function = "gpio"; 542 drive-strength = <2>; 543 bias-pull-up; 544 }; 545 546 qup_i2c8_default: qup-i2c8-default-state { 547 pins = "gpio18", "gpio19"; 548 function = "qup13"; 549 drive-strength = <2>; 550 bias-disable; 551 }; 552 553 qup_i2c8_sleep: qup-i2c8-sleep-state { 554 pins = "gpio18", "gpio19"; 555 function = "gpio"; 556 drive-strength = <2>; 557 bias-pull-up; 558 }; 559 560 qup_i2c9_default: qup-i2c9-default-state { 561 pins = "gpio10", "gpio11"; 562 function = "qup14"; 563 drive-strength = <2>; 564 bias-disable; 565 }; 566 567 qup_i2c9_sleep: qup-i2c9-sleep-state { 568 pins = "gpio10", "gpio11"; 569 function = "gpio"; 570 drive-strength = <2>; 571 bias-pull-up; 572 }; 573 574 qup_spi0_default: qup-spi0-default-state { 575 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 576 function = "qup00"; 577 drive-strength = <6>; 578 bias-disable; 579 }; 580 581 qup_spi0_sleep: qup-spi0-sleep-state { 582 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 583 function = "gpio"; 584 drive-strength = <6>; 585 bias-disable; 586 }; 587 588 qup_spi2_default: qup-spi2-default-state { 589 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 590 function = "qup02"; 591 drive-strength = <6>; 592 bias-disable; 593 }; 594 595 qup_spi2_sleep: qup-spi2-sleep-state { 596 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 597 function = "gpio"; 598 drive-strength = <6>; 599 bias-disable; 600 }; 601 602 qup_spi5_default: qup-spi5-default-state { 603 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 604 function = "qup10"; 605 drive-strength = <6>; 606 bias-disable; 607 }; 608 609 qup_spi5_sleep: qup-spi5-sleep-state { 610 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 611 function = "gpio"; 612 drive-strength = <6>; 613 bias-disable; 614 }; 615 616 qup_spi6_default: qup-spi6-default-state { 617 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 618 function = "qup11"; 619 drive-strength = <6>; 620 bias-disable; 621 }; 622 623 qup_spi6_sleep: qup-spi6-sleep-state { 624 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 625 function = "gpio"; 626 drive-strength = <6>; 627 bias-disable; 628 }; 629 630 qup_spi8_default: qup-spi8-default-state { 631 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 632 function = "qup13"; 633 drive-strength = <6>; 634 bias-disable; 635 }; 636 637 qup_spi8_sleep: qup-spi8-sleep-state { 638 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 639 function = "gpio"; 640 drive-strength = <6>; 641 bias-disable; 642 }; 643 644 qup_spi9_default: qup-spi9-default-state { 645 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 646 function = "qup14"; 647 drive-strength = <6>; 648 bias-disable; 649 }; 650 651 qup_spi9_sleep: qup-spi9-sleep-state { 652 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 653 function = "gpio"; 654 drive-strength = <6>; 655 bias-disable; 656 }; 657 }; 658 659 gcc: clock-controller@1400000 { 660 compatible = "qcom,gcc-sm6125"; 661 reg = <0x01400000 0x1f0000>; 662 #clock-cells = <1>; 663 #reset-cells = <1>; 664 #power-domain-cells = <1>; 665 clock-names = "bi_tcxo", "sleep_clk"; 666 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 667 }; 668 669 hsusb_phy1: phy@1613000 { 670 compatible = "qcom,msm8996-qusb2-phy"; 671 reg = <0x01613000 0x180>; 672 #phy-cells = <0>; 673 674 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 675 <&rpmcc RPM_SMD_XO_CLK_SRC>; 676 clock-names = "cfg_ahb", "ref"; 677 678 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 679 status = "disabled"; 680 }; 681 682 rpm_msg_ram: sram@45f0000 { 683 compatible = "qcom,rpm-msg-ram"; 684 reg = <0x045f0000 0x7000>; 685 }; 686 687 sdhc_1: mmc@4744000 { 688 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 689 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 690 reg-names = "hc", "cqhci"; 691 692 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 694 interrupt-names = "hc_irq", "pwr_irq"; 695 696 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 697 <&gcc GCC_SDCC1_APPS_CLK>, 698 <&xo_board>; 699 clock-names = "iface", "core", "xo"; 700 iommus = <&apps_smmu 0x160 0x0>; 701 702 power-domains = <&rpmpd SM6125_VDDCX>; 703 704 qcom,dll-config = <0x000f642c>; 705 qcom,ddr-config = <0x80040873>; 706 707 bus-width = <8>; 708 non-removable; 709 supports-cqe; 710 711 status = "disabled"; 712 }; 713 714 sdhc_2: mmc@4784000 { 715 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 716 reg = <0x04784000 0x1000>; 717 reg-names = "hc"; 718 719 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 721 interrupt-names = "hc_irq", "pwr_irq"; 722 723 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 724 <&gcc GCC_SDCC2_APPS_CLK>, 725 <&xo_board>; 726 clock-names = "iface", "core", "xo"; 727 iommus = <&apps_smmu 0x180 0x0>; 728 729 pinctrl-0 = <&sdc2_on_state>; 730 pinctrl-1 = <&sdc2_off_state>; 731 pinctrl-names = "default", "sleep"; 732 733 power-domains = <&rpmpd SM6125_VDDCX>; 734 735 qcom,dll-config = <0x0007642c>; 736 qcom,ddr-config = <0x80040873>; 737 738 bus-width = <4>; 739 status = "disabled"; 740 }; 741 742 ufs_mem_hc: ufs@4804000 { 743 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 744 reg = <0x04804000 0x3000>, <0x04810000 0x8000>; 745 reg-names = "std", "ice"; 746 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 747 748 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 749 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 750 <&gcc GCC_UFS_PHY_AHB_CLK>, 751 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 752 <&rpmcc RPM_SMD_XO_CLK_SRC>, 753 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 754 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 755 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 756 clock-names = "core_clk", 757 "bus_aggr_clk", 758 "iface_clk", 759 "core_clk_unipro", 760 "ref_clk", 761 "tx_lane0_sync_clk", 762 "rx_lane0_sync_clk", 763 "ice_core_clk"; 764 freq-table-hz = <50000000 240000000>, 765 <0 0>, 766 <0 0>, 767 <37500000 150000000>, 768 <0 0>, 769 <0 0>, 770 <0 0>, 771 <75000000 300000000>; 772 773 resets = <&gcc GCC_UFS_PHY_BCR>; 774 reset-names = "rst"; 775 #reset-cells = <1>; 776 777 phys = <&ufs_mem_phy>; 778 phy-names = "ufsphy"; 779 780 lanes-per-direction = <1>; 781 782 iommus = <&apps_smmu 0x200 0x0>; 783 784 status = "disabled"; 785 }; 786 787 ufs_mem_phy: phy@4807000 { 788 compatible = "qcom,sm6125-qmp-ufs-phy"; 789 reg = <0x04807000 0xdb8>; 790 791 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 792 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 793 clock-names = "ref", 794 "ref_aux"; 795 796 resets = <&ufs_mem_hc 0>; 797 reset-names = "ufsphy"; 798 799 power-domains = <&gcc UFS_PHY_GDSC>; 800 801 #phy-cells = <0>; 802 803 status = "disabled"; 804 }; 805 806 gpi_dma0: dma-controller@4a00000 { 807 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 808 reg = <0x04a00000 0x60000>; 809 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 817 dma-channels = <8>; 818 dma-channel-mask = <0x1f>; 819 iommus = <&apps_smmu 0x136 0x0>; 820 #dma-cells = <3>; 821 status = "disabled"; 822 }; 823 824 qupv3_id_0: geniqup@4ac0000 { 825 compatible = "qcom,geni-se-qup"; 826 reg = <0x04ac0000 0x2000>; 827 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 828 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 829 clock-names = "m-ahb", "s-ahb"; 830 iommus = <&apps_smmu 0x123 0x0>; 831 #address-cells = <1>; 832 #size-cells = <1>; 833 ranges; 834 status = "disabled"; 835 836 i2c0: i2c@4a80000 { 837 compatible = "qcom,geni-i2c"; 838 reg = <0x04a80000 0x4000>; 839 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 840 clock-names = "se"; 841 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 842 pinctrl-0 = <&qup_i2c0_default>; 843 pinctrl-1 = <&qup_i2c0_sleep>; 844 pinctrl-names = "default", "sleep"; 845 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 846 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 847 dma-names = "tx", "rx"; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 status = "disabled"; 851 }; 852 853 spi0: spi@4a80000 { 854 compatible = "qcom,geni-spi"; 855 reg = <0x04a80000 0x4000>; 856 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 857 clock-names = "se"; 858 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 859 pinctrl-0 = <&qup_spi0_default>; 860 pinctrl-1 = <&qup_spi0_sleep>; 861 pinctrl-names = "default", "sleep"; 862 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 863 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 864 dma-names = "tx", "rx"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 status = "disabled"; 868 }; 869 870 i2c1: i2c@4a84000 { 871 compatible = "qcom,geni-i2c"; 872 reg = <0x04a84000 0x4000>; 873 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 874 clock-names = "se"; 875 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 876 pinctrl-0 = <&qup_i2c1_default>; 877 pinctrl-1 = <&qup_i2c1_sleep>; 878 pinctrl-names = "default", "sleep"; 879 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 880 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 881 dma-names = "tx", "rx"; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 status = "disabled"; 885 }; 886 887 i2c2: i2c@4a88000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0x04a88000 0x4000>; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 891 clock-names = "se"; 892 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 893 pinctrl-0 = <&qup_i2c2_default>; 894 pinctrl-1 = <&qup_i2c2_sleep>; 895 pinctrl-names = "default", "sleep"; 896 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 897 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 898 dma-names = "tx", "rx"; 899 #address-cells = <1>; 900 #size-cells = <0>; 901 status = "disabled"; 902 }; 903 904 spi2: spi@4a88000 { 905 compatible = "qcom,geni-spi"; 906 reg = <0x04a88000 0x4000>; 907 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 908 clock-names = "se"; 909 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 910 pinctrl-0 = <&qup_spi2_default>; 911 pinctrl-1 = <&qup_spi2_sleep>; 912 pinctrl-names = "default", "sleep"; 913 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 914 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 915 dma-names = "tx", "rx"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 status = "disabled"; 919 }; 920 921 i2c3: i2c@4a8c000 { 922 compatible = "qcom,geni-i2c"; 923 reg = <0x04a8c000 0x4000>; 924 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 925 clock-names = "se"; 926 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 927 pinctrl-0 = <&qup_i2c3_default>; 928 pinctrl-1 = <&qup_i2c3_sleep>; 929 pinctrl-names = "default", "sleep"; 930 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 931 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 932 dma-names = "tx", "rx"; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 status = "disabled"; 936 }; 937 938 i2c4: i2c@4a90000 { 939 compatible = "qcom,geni-i2c"; 940 reg = <0x04a90000 0x4000>; 941 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 942 clock-names = "se"; 943 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 944 pinctrl-0 = <&qup_i2c4_default>; 945 pinctrl-1 = <&qup_i2c4_sleep>; 946 pinctrl-names = "default", "sleep"; 947 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 948 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 949 dma-names = "tx", "rx"; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 status = "disabled"; 953 }; 954 }; 955 956 gpi_dma1: dma-controller@4c00000 { 957 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 958 reg = <0x04c00000 0x60000>; 959 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 967 dma-channels = <8>; 968 dma-channel-mask = <0x0f>; 969 iommus = <&apps_smmu 0x156 0x0>; 970 #dma-cells = <3>; 971 status = "disabled"; 972 }; 973 974 qupv3_id_1: geniqup@4cc0000 { 975 compatible = "qcom,geni-se-qup"; 976 reg = <0x04cc0000 0x2000>; 977 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 978 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 979 clock-names = "m-ahb", "s-ahb"; 980 iommus = <&apps_smmu 0x143 0x0>; 981 #address-cells = <1>; 982 #size-cells = <1>; 983 ranges; 984 status = "disabled"; 985 986 i2c5: i2c@4c80000 { 987 compatible = "qcom,geni-i2c"; 988 reg = <0x04c80000 0x4000>; 989 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 990 clock-names = "se"; 991 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 992 pinctrl-0 = <&qup_i2c5_default>; 993 pinctrl-1 = <&qup_i2c5_sleep>; 994 pinctrl-names = "default", "sleep"; 995 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 996 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 spi5: spi@4c80000 { 1004 compatible = "qcom,geni-spi"; 1005 reg = <0x04c80000 0x4000>; 1006 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1007 clock-names = "se"; 1008 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 1009 pinctrl-0 = <&qup_spi5_default>; 1010 pinctrl-1 = <&qup_spi5_sleep>; 1011 pinctrl-names = "default", "sleep"; 1012 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1013 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1014 dma-names = "tx", "rx"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 i2c6: i2c@4c84000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0x04c84000 0x4000>; 1023 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1024 clock-names = "se"; 1025 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1026 pinctrl-0 = <&qup_i2c6_default>; 1027 pinctrl-1 = <&qup_i2c6_sleep>; 1028 pinctrl-names = "default", "sleep"; 1029 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1030 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1031 dma-names = "tx", "rx"; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 spi6: spi@4c84000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0x04c84000 0x4000>; 1040 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1041 clock-names = "se"; 1042 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1043 pinctrl-0 = <&qup_spi6_default>; 1044 pinctrl-1 = <&qup_spi6_sleep>; 1045 pinctrl-names = "default", "sleep"; 1046 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1047 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1048 dma-names = "tx", "rx"; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 status = "disabled"; 1052 }; 1053 1054 i2c7: i2c@4c88000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0x04c88000 0x4000>; 1057 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1058 clock-names = "se"; 1059 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1060 pinctrl-0 = <&qup_i2c7_default>; 1061 pinctrl-1 = <&qup_i2c7_sleep>; 1062 pinctrl-names = "default", "sleep"; 1063 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1064 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1065 dma-names = "tx", "rx"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 i2c8: i2c@4c8c000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0x04c8c000 0x4000>; 1074 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1075 clock-names = "se"; 1076 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1077 pinctrl-0 = <&qup_i2c8_default>; 1078 pinctrl-1 = <&qup_i2c8_sleep>; 1079 pinctrl-names = "default", "sleep"; 1080 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1081 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1082 dma-names = "tx", "rx"; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 status = "disabled"; 1086 }; 1087 1088 spi8: spi@4c8c000 { 1089 compatible = "qcom,geni-spi"; 1090 reg = <0x04c8c000 0x4000>; 1091 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1092 clock-names = "se"; 1093 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1094 pinctrl-0 = <&qup_spi8_default>; 1095 pinctrl-1 = <&qup_spi8_sleep>; 1096 pinctrl-names = "default", "sleep"; 1097 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1098 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1099 dma-names = "tx", "rx"; 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 status = "disabled"; 1103 }; 1104 1105 i2c9: i2c@4c90000 { 1106 compatible = "qcom,geni-i2c"; 1107 reg = <0x04c90000 0x4000>; 1108 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1109 clock-names = "se"; 1110 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1111 pinctrl-0 = <&qup_i2c9_default>; 1112 pinctrl-1 = <&qup_i2c9_sleep>; 1113 pinctrl-names = "default", "sleep"; 1114 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1115 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1116 dma-names = "tx", "rx"; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 status = "disabled"; 1120 }; 1121 1122 spi9: spi@4c90000 { 1123 compatible = "qcom,geni-spi"; 1124 reg = <0x04c90000 0x4000>; 1125 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1126 clock-names = "se"; 1127 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1128 pinctrl-0 = <&qup_spi9_default>; 1129 pinctrl-1 = <&qup_spi9_sleep>; 1130 pinctrl-names = "default", "sleep"; 1131 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1132 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1133 dma-names = "tx", "rx"; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 }; 1139 1140 usb3: usb@4ef8800 { 1141 compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; 1142 reg = <0x04ef8800 0x400>; 1143 #address-cells = <1>; 1144 #size-cells = <1>; 1145 ranges; 1146 1147 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1148 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1149 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1150 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1151 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1152 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1153 clock-names = "cfg_noc", 1154 "core", 1155 "iface", 1156 "sleep", 1157 "mock_utmi", 1158 "xo"; 1159 1160 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1161 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1162 assigned-clock-rates = <19200000>, <66666667>; 1163 1164 power-domains = <&gcc USB30_PRIM_GDSC>; 1165 qcom,select-utmi-as-pipe-clk; 1166 status = "disabled"; 1167 1168 usb3_dwc3: usb@4e00000 { 1169 compatible = "snps,dwc3"; 1170 reg = <0x04e00000 0xcd00>; 1171 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1172 iommus = <&apps_smmu 0x100 0x0>; 1173 phys = <&hsusb_phy1>; 1174 phy-names = "usb2-phy"; 1175 snps,dis_u2_susphy_quirk; 1176 snps,dis_enblslpm_quirk; 1177 maximum-speed = "high-speed"; 1178 dr_mode = "peripheral"; 1179 }; 1180 }; 1181 1182 sram@4690000 { 1183 compatible = "qcom,rpm-stats"; 1184 reg = <0x04690000 0x10000>; 1185 }; 1186 1187 spmi_bus: spmi@1c40000 { 1188 compatible = "qcom,spmi-pmic-arb"; 1189 reg = <0x01c40000 0x1100>, 1190 <0x01e00000 0x2000000>, 1191 <0x03e00000 0x100000>, 1192 <0x03f00000 0xa0000>, 1193 <0x01c0a000 0x26000>; 1194 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1195 interrupt-names = "periph_irq"; 1196 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1197 qcom,ee = <0>; 1198 qcom,channel = <0>; 1199 #address-cells = <2>; 1200 #size-cells = <0>; 1201 interrupt-controller; 1202 #interrupt-cells = <4>; 1203 }; 1204 1205 apps_smmu: iommu@c600000 { 1206 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1207 reg = <0xc600000 0x80000>; 1208 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1273 1274 #global-interrupts = <1>; 1275 #iommu-cells = <2>; 1276 }; 1277 1278 apcs_glb: mailbox@f111000 { 1279 compatible = "qcom,sm6125-apcs-hmss-global", 1280 "qcom,msm8994-apcs-kpss-global"; 1281 reg = <0x0f111000 0x1000>; 1282 1283 #mbox-cells = <1>; 1284 }; 1285 1286 timer@f120000 { 1287 compatible = "arm,armv7-timer-mem"; 1288 #address-cells = <1>; 1289 #size-cells = <1>; 1290 ranges; 1291 reg = <0x0f120000 0x1000>; 1292 clock-frequency = <19200000>; 1293 1294 frame@f121000 { 1295 frame-number = <0>; 1296 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1298 reg = <0x0f121000 0x1000>, 1299 <0x0f122000 0x1000>; 1300 }; 1301 1302 frame@f123000 { 1303 frame-number = <1>; 1304 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1305 reg = <0x0f123000 0x1000>; 1306 status = "disabled"; 1307 }; 1308 1309 frame@f124000 { 1310 frame-number = <2>; 1311 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1312 reg = <0x0f124000 0x1000>; 1313 status = "disabled"; 1314 }; 1315 1316 frame@f125000 { 1317 frame-number = <3>; 1318 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1319 reg = <0x0f125000 0x1000>; 1320 status = "disabled"; 1321 }; 1322 1323 frame@f126000 { 1324 frame-number = <4>; 1325 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1326 reg = <0x0f126000 0x1000>; 1327 status = "disabled"; 1328 }; 1329 1330 frame@f127000 { 1331 frame-number = <5>; 1332 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1333 reg = <0x0f127000 0x1000>; 1334 status = "disabled"; 1335 }; 1336 1337 frame@f128000 { 1338 frame-number = <6>; 1339 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1340 reg = <0x0f128000 0x1000>; 1341 status = "disabled"; 1342 }; 1343 }; 1344 1345 intc: interrupt-controller@f200000 { 1346 compatible = "arm,gic-v3"; 1347 reg = <0x0f200000 0x20000>, 1348 <0x0f300000 0x100000>; 1349 #interrupt-cells = <3>; 1350 interrupt-controller; 1351 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1352 }; 1353 }; 1354 1355 timer { 1356 compatible = "arm,armv8-timer"; 1357 interrupts = <GIC_PPI 1 0xf08 1358 GIC_PPI 2 0xf08 1359 GIC_PPI 3 0xf08 1360 GIC_PPI 0 0xf08>; 1361 clock-frequency = <19200000>; 1362 }; 1363}; 1364