1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,rpm-icc.h> 14#include <dt-bindings/interconnect/qcom,sm6115.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 CPU0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "qcom,kryo260"; 45 reg = <0x0 0x0>; 46 clocks = <&cpufreq_hw 0>; 47 capacity-dmips-mhz = <1024>; 48 dynamic-power-coefficient = <100>; 49 enable-method = "psci"; 50 next-level-cache = <&L2_0>; 51 qcom,freq-domain = <&cpufreq_hw 0>; 52 power-domains = <&CPU_PD0>; 53 power-domain-names = "psci"; 54 L2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 cache-unified; 58 }; 59 }; 60 61 CPU1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "qcom,kryo260"; 64 reg = <0x0 0x1>; 65 clocks = <&cpufreq_hw 0>; 66 capacity-dmips-mhz = <1024>; 67 dynamic-power-coefficient = <100>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_0>; 70 qcom,freq-domain = <&cpufreq_hw 0>; 71 power-domains = <&CPU_PD1>; 72 power-domain-names = "psci"; 73 }; 74 75 CPU2: cpu@2 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo260"; 78 reg = <0x0 0x2>; 79 clocks = <&cpufreq_hw 0>; 80 capacity-dmips-mhz = <1024>; 81 dynamic-power-coefficient = <100>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_0>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 power-domains = <&CPU_PD2>; 86 power-domain-names = "psci"; 87 }; 88 89 CPU3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo260"; 92 reg = <0x0 0x3>; 93 clocks = <&cpufreq_hw 0>; 94 capacity-dmips-mhz = <1024>; 95 dynamic-power-coefficient = <100>; 96 enable-method = "psci"; 97 next-level-cache = <&L2_0>; 98 qcom,freq-domain = <&cpufreq_hw 0>; 99 power-domains = <&CPU_PD3>; 100 power-domain-names = "psci"; 101 }; 102 103 CPU4: cpu@100 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo260"; 106 reg = <0x0 0x100>; 107 clocks = <&cpufreq_hw 1>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <1638>; 110 dynamic-power-coefficient = <282>; 111 next-level-cache = <&L2_1>; 112 qcom,freq-domain = <&cpufreq_hw 1>; 113 power-domains = <&CPU_PD4>; 114 power-domain-names = "psci"; 115 L2_1: l2-cache { 116 compatible = "cache"; 117 cache-level = <2>; 118 cache-unified; 119 }; 120 }; 121 122 CPU5: cpu@101 { 123 device_type = "cpu"; 124 compatible = "qcom,kryo260"; 125 reg = <0x0 0x101>; 126 clocks = <&cpufreq_hw 1>; 127 capacity-dmips-mhz = <1638>; 128 dynamic-power-coefficient = <282>; 129 enable-method = "psci"; 130 next-level-cache = <&L2_1>; 131 qcom,freq-domain = <&cpufreq_hw 1>; 132 power-domains = <&CPU_PD5>; 133 power-domain-names = "psci"; 134 }; 135 136 CPU6: cpu@102 { 137 device_type = "cpu"; 138 compatible = "qcom,kryo260"; 139 reg = <0x0 0x102>; 140 clocks = <&cpufreq_hw 1>; 141 capacity-dmips-mhz = <1638>; 142 dynamic-power-coefficient = <282>; 143 enable-method = "psci"; 144 next-level-cache = <&L2_1>; 145 qcom,freq-domain = <&cpufreq_hw 1>; 146 power-domains = <&CPU_PD6>; 147 power-domain-names = "psci"; 148 }; 149 150 CPU7: cpu@103 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo260"; 153 reg = <0x0 0x103>; 154 clocks = <&cpufreq_hw 1>; 155 capacity-dmips-mhz = <1638>; 156 dynamic-power-coefficient = <282>; 157 enable-method = "psci"; 158 next-level-cache = <&L2_1>; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 power-domains = <&CPU_PD7>; 161 power-domain-names = "psci"; 162 }; 163 164 cpu-map { 165 cluster0 { 166 core0 { 167 cpu = <&CPU0>; 168 }; 169 170 core1 { 171 cpu = <&CPU1>; 172 }; 173 174 core2 { 175 cpu = <&CPU2>; 176 }; 177 178 core3 { 179 cpu = <&CPU3>; 180 }; 181 }; 182 183 cluster1 { 184 core0 { 185 cpu = <&CPU4>; 186 }; 187 188 core1 { 189 cpu = <&CPU5>; 190 }; 191 192 core2 { 193 cpu = <&CPU6>; 194 }; 195 196 core3 { 197 cpu = <&CPU7>; 198 }; 199 }; 200 }; 201 202 idle-states { 203 entry-method = "psci"; 204 205 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 206 compatible = "arm,idle-state"; 207 idle-state-name = "silver-rail-power-collapse"; 208 arm,psci-suspend-param = <0x40000003>; 209 entry-latency-us = <290>; 210 exit-latency-us = <376>; 211 min-residency-us = <1182>; 212 local-timer-stop; 213 }; 214 215 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 216 compatible = "arm,idle-state"; 217 idle-state-name = "gold-rail-power-collapse"; 218 arm,psci-suspend-param = <0x40000003>; 219 entry-latency-us = <297>; 220 exit-latency-us = <324>; 221 min-residency-us = <1110>; 222 local-timer-stop; 223 }; 224 }; 225 226 domain-idle-states { 227 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { 228 /* GDHS */ 229 compatible = "domain-idle-state"; 230 arm,psci-suspend-param = <0x40000022>; 231 entry-latency-us = <360>; 232 exit-latency-us = <421>; 233 min-residency-us = <782>; 234 }; 235 236 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { 237 /* Power Collapse */ 238 compatible = "domain-idle-state"; 239 arm,psci-suspend-param = <0x41000044>; 240 entry-latency-us = <800>; 241 exit-latency-us = <2118>; 242 min-residency-us = <7376>; 243 }; 244 245 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { 246 /* GDHS */ 247 compatible = "domain-idle-state"; 248 arm,psci-suspend-param = <0x40000042>; 249 entry-latency-us = <314>; 250 exit-latency-us = <345>; 251 min-residency-us = <660>; 252 }; 253 254 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { 255 /* Power Collapse */ 256 compatible = "domain-idle-state"; 257 arm,psci-suspend-param = <0x41000044>; 258 entry-latency-us = <640>; 259 exit-latency-us = <1654>; 260 min-residency-us = <8094>; 261 }; 262 }; 263 }; 264 265 firmware { 266 scm: scm { 267 compatible = "qcom,scm-sm6115", "qcom,scm"; 268 #reset-cells = <1>; 269 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 270 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 271 }; 272 }; 273 274 memory@80000000 { 275 device_type = "memory"; 276 /* We expect the bootloader to fill in the size */ 277 reg = <0 0x80000000 0 0>; 278 }; 279 280 qup_opp_table: opp-table-qup { 281 compatible = "operating-points-v2"; 282 283 opp-75000000 { 284 opp-hz = /bits/ 64 <75000000>; 285 required-opps = <&rpmpd_opp_low_svs>; 286 }; 287 288 opp-100000000 { 289 opp-hz = /bits/ 64 <100000000>; 290 required-opps = <&rpmpd_opp_svs>; 291 }; 292 293 opp-128000000 { 294 opp-hz = /bits/ 64 <128000000>; 295 required-opps = <&rpmpd_opp_nom>; 296 }; 297 }; 298 299 pmu { 300 compatible = "arm,armv8-pmuv3"; 301 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 302 }; 303 304 psci { 305 compatible = "arm,psci-1.0"; 306 method = "smc"; 307 308 CPU_PD0: power-domain-cpu0 { 309 #power-domain-cells = <0>; 310 power-domains = <&CLUSTER_0_PD>; 311 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 312 }; 313 314 CPU_PD1: power-domain-cpu1 { 315 #power-domain-cells = <0>; 316 power-domains = <&CLUSTER_0_PD>; 317 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 318 }; 319 320 CPU_PD2: power-domain-cpu2 { 321 #power-domain-cells = <0>; 322 power-domains = <&CLUSTER_0_PD>; 323 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 324 }; 325 326 CPU_PD3: power-domain-cpu3 { 327 #power-domain-cells = <0>; 328 power-domains = <&CLUSTER_0_PD>; 329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 330 }; 331 332 CPU_PD4: power-domain-cpu4 { 333 #power-domain-cells = <0>; 334 power-domains = <&CLUSTER_1_PD>; 335 domain-idle-states = <&BIG_CPU_SLEEP_0>; 336 }; 337 338 CPU_PD5: power-domain-cpu5 { 339 #power-domain-cells = <0>; 340 power-domains = <&CLUSTER_1_PD>; 341 domain-idle-states = <&BIG_CPU_SLEEP_0>; 342 }; 343 344 CPU_PD6: power-domain-cpu6 { 345 #power-domain-cells = <0>; 346 power-domains = <&CLUSTER_1_PD>; 347 domain-idle-states = <&BIG_CPU_SLEEP_0>; 348 }; 349 350 CPU_PD7: power-domain-cpu7 { 351 #power-domain-cells = <0>; 352 power-domains = <&CLUSTER_1_PD>; 353 domain-idle-states = <&BIG_CPU_SLEEP_0>; 354 }; 355 356 CLUSTER_0_PD: power-domain-cpu-cluster0 { 357 #power-domain-cells = <0>; 358 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; 359 }; 360 361 CLUSTER_1_PD: power-domain-cpu-cluster1 { 362 #power-domain-cells = <0>; 363 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; 364 }; 365 }; 366 367 rpm: remoteproc { 368 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; 369 370 glink-edge { 371 compatible = "qcom,glink-rpm"; 372 373 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 374 qcom,rpm-msg-ram = <&rpm_msg_ram>; 375 mboxes = <&apcs_glb 0>; 376 377 rpm_requests: rpm-requests { 378 compatible = "qcom,rpm-sm6115"; 379 qcom,glink-channels = "rpm_requests"; 380 381 rpmcc: clock-controller { 382 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 383 clocks = <&xo_board>; 384 clock-names = "xo"; 385 #clock-cells = <1>; 386 }; 387 388 rpmpd: power-controller { 389 compatible = "qcom,sm6115-rpmpd"; 390 #power-domain-cells = <1>; 391 operating-points-v2 = <&rpmpd_opp_table>; 392 393 rpmpd_opp_table: opp-table { 394 compatible = "operating-points-v2"; 395 396 rpmpd_opp_min_svs: opp1 { 397 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 398 }; 399 400 rpmpd_opp_low_svs: opp2 { 401 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 402 }; 403 404 rpmpd_opp_svs: opp3 { 405 opp-level = <RPM_SMD_LEVEL_SVS>; 406 }; 407 408 rpmpd_opp_svs_plus: opp4 { 409 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 410 }; 411 412 rpmpd_opp_nom: opp5 { 413 opp-level = <RPM_SMD_LEVEL_NOM>; 414 }; 415 416 rpmpd_opp_nom_plus: opp6 { 417 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 418 }; 419 420 rpmpd_opp_turbo: opp7 { 421 opp-level = <RPM_SMD_LEVEL_TURBO>; 422 }; 423 424 rpmpd_opp_turbo_plus: opp8 { 425 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 426 }; 427 }; 428 }; 429 }; 430 }; 431 }; 432 433 reserved_memory: reserved-memory { 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges; 437 438 hyp_mem: memory@45700000 { 439 reg = <0x0 0x45700000 0x0 0x600000>; 440 no-map; 441 }; 442 443 xbl_aop_mem: memory@45e00000 { 444 reg = <0x0 0x45e00000 0x0 0x140000>; 445 no-map; 446 }; 447 448 sec_apps_mem: memory@45fff000 { 449 reg = <0x0 0x45fff000 0x0 0x1000>; 450 no-map; 451 }; 452 453 smem_mem: memory@46000000 { 454 compatible = "qcom,smem"; 455 reg = <0x0 0x46000000 0x0 0x200000>; 456 no-map; 457 458 hwlocks = <&tcsr_mutex 3>; 459 qcom,rpm-msg-ram = <&rpm_msg_ram>; 460 }; 461 462 cdsp_sec_mem: memory@46200000 { 463 reg = <0x0 0x46200000 0x0 0x1e00000>; 464 no-map; 465 }; 466 467 pil_modem_mem: memory@4ab00000 { 468 reg = <0x0 0x4ab00000 0x0 0x6900000>; 469 no-map; 470 }; 471 472 pil_video_mem: memory@51400000 { 473 reg = <0x0 0x51400000 0x0 0x500000>; 474 no-map; 475 }; 476 477 wlan_msa_mem: memory@51900000 { 478 reg = <0x0 0x51900000 0x0 0x100000>; 479 no-map; 480 }; 481 482 pil_cdsp_mem: memory@51a00000 { 483 reg = <0x0 0x51a00000 0x0 0x1e00000>; 484 no-map; 485 }; 486 487 pil_adsp_mem: memory@53800000 { 488 reg = <0x0 0x53800000 0x0 0x2800000>; 489 no-map; 490 }; 491 492 pil_ipa_fw_mem: memory@56100000 { 493 reg = <0x0 0x56100000 0x0 0x10000>; 494 no-map; 495 }; 496 497 pil_ipa_gsi_mem: memory@56110000 { 498 reg = <0x0 0x56110000 0x0 0x5000>; 499 no-map; 500 }; 501 502 pil_gpu_mem: memory@56115000 { 503 reg = <0x0 0x56115000 0x0 0x2000>; 504 no-map; 505 }; 506 507 cont_splash_memory: memory@5c000000 { 508 reg = <0x0 0x5c000000 0x0 0x00f00000>; 509 no-map; 510 }; 511 512 dfps_data_memory: memory@5cf00000 { 513 reg = <0x0 0x5cf00000 0x0 0x0100000>; 514 no-map; 515 }; 516 517 removed_mem: memory@60000000 { 518 reg = <0x0 0x60000000 0x0 0x3900000>; 519 no-map; 520 }; 521 522 rmtfs_mem: memory@89b01000 { 523 compatible = "qcom,rmtfs-mem"; 524 reg = <0x0 0x89b01000 0x0 0x200000>; 525 no-map; 526 527 qcom,client-id = <1>; 528 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 529 }; 530 }; 531 532 smp2p-adsp { 533 compatible = "qcom,smp2p"; 534 qcom,smem = <443>, <429>; 535 536 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 537 538 mboxes = <&apcs_glb 10>; 539 540 qcom,local-pid = <0>; 541 qcom,remote-pid = <2>; 542 543 adsp_smp2p_out: master-kernel { 544 qcom,entry-name = "master-kernel"; 545 #qcom,smem-state-cells = <1>; 546 }; 547 548 adsp_smp2p_in: slave-kernel { 549 qcom,entry-name = "slave-kernel"; 550 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 }; 554 }; 555 556 smp2p-cdsp { 557 compatible = "qcom,smp2p"; 558 qcom,smem = <94>, <432>; 559 560 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 561 562 mboxes = <&apcs_glb 30>; 563 564 qcom,local-pid = <0>; 565 qcom,remote-pid = <5>; 566 567 cdsp_smp2p_out: master-kernel { 568 qcom,entry-name = "master-kernel"; 569 #qcom,smem-state-cells = <1>; 570 }; 571 572 cdsp_smp2p_in: slave-kernel { 573 qcom,entry-name = "slave-kernel"; 574 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 }; 578 }; 579 580 smp2p-mpss { 581 compatible = "qcom,smp2p"; 582 qcom,smem = <435>, <428>; 583 584 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 585 586 mboxes = <&apcs_glb 14>; 587 588 qcom,local-pid = <0>; 589 qcom,remote-pid = <1>; 590 591 modem_smp2p_out: master-kernel { 592 qcom,entry-name = "master-kernel"; 593 #qcom,smem-state-cells = <1>; 594 }; 595 596 modem_smp2p_in: slave-kernel { 597 qcom,entry-name = "slave-kernel"; 598 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 }; 602 }; 603 604 soc: soc@0 { 605 compatible = "simple-bus"; 606 #address-cells = <2>; 607 #size-cells = <2>; 608 ranges = <0 0 0 0 0x10 0>; 609 dma-ranges = <0 0 0 0 0x10 0>; 610 611 tcsr_mutex: hwlock@340000 { 612 compatible = "qcom,tcsr-mutex"; 613 reg = <0x0 0x00340000 0x0 0x20000>; 614 #hwlock-cells = <1>; 615 }; 616 617 tlmm: pinctrl@500000 { 618 compatible = "qcom,sm6115-tlmm"; 619 reg = <0x0 0x00500000 0x0 0x400000>, 620 <0x0 0x00900000 0x0 0x400000>, 621 <0x0 0x00d00000 0x0 0x400000>; 622 reg-names = "west", "south", "east"; 623 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 624 gpio-controller; 625 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 626 #gpio-cells = <2>; 627 interrupt-controller; 628 #interrupt-cells = <2>; 629 630 qup_i2c0_default: qup-i2c0-default-state { 631 pins = "gpio0", "gpio1"; 632 function = "qup0"; 633 drive-strength = <2>; 634 bias-pull-up; 635 }; 636 637 qup_i2c1_default: qup-i2c1-default-state { 638 pins = "gpio4", "gpio5"; 639 function = "qup1"; 640 drive-strength = <2>; 641 bias-pull-up; 642 }; 643 644 qup_i2c2_default: qup-i2c2-default-state { 645 pins = "gpio6", "gpio7"; 646 function = "qup2"; 647 drive-strength = <2>; 648 bias-pull-up; 649 }; 650 651 qup_i2c3_default: qup-i2c3-default-state { 652 pins = "gpio8", "gpio9"; 653 function = "qup3"; 654 drive-strength = <2>; 655 bias-pull-up; 656 }; 657 658 qup_i2c4_default: qup-i2c4-default-state { 659 pins = "gpio12", "gpio13"; 660 function = "qup4"; 661 drive-strength = <2>; 662 bias-pull-up; 663 }; 664 665 qup_i2c5_default: qup-i2c5-default-state { 666 pins = "gpio14", "gpio15"; 667 function = "qup5"; 668 drive-strength = <2>; 669 bias-pull-up; 670 }; 671 672 qup_spi0_default: qup-spi0-default-state { 673 pins = "gpio0", "gpio1","gpio2", "gpio3"; 674 function = "qup0"; 675 drive-strength = <2>; 676 bias-pull-up; 677 }; 678 679 qup_spi1_default: qup-spi1-default-state { 680 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 681 function = "qup1"; 682 drive-strength = <2>; 683 bias-pull-up; 684 }; 685 686 qup_spi2_default: qup-spi2-default-state { 687 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 688 function = "qup2"; 689 drive-strength = <2>; 690 bias-pull-up; 691 }; 692 693 qup_spi3_default: qup-spi3-default-state { 694 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 695 function = "qup3"; 696 drive-strength = <2>; 697 bias-pull-up; 698 }; 699 700 qup_spi4_default: qup-spi4-default-state { 701 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 702 function = "qup4"; 703 drive-strength = <2>; 704 bias-pull-up; 705 }; 706 707 qup_spi5_default: qup-spi5-default-state { 708 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 709 function = "qup5"; 710 drive-strength = <2>; 711 bias-pull-up; 712 }; 713 714 sdc1_state_on: sdc1-on-state { 715 clk-pins { 716 pins = "sdc1_clk"; 717 bias-disable; 718 drive-strength = <16>; 719 }; 720 721 cmd-pins { 722 pins = "sdc1_cmd"; 723 bias-pull-up; 724 drive-strength = <10>; 725 }; 726 727 data-pins { 728 pins = "sdc1_data"; 729 bias-pull-up; 730 drive-strength = <10>; 731 }; 732 733 rclk-pins { 734 pins = "sdc1_rclk"; 735 bias-pull-down; 736 }; 737 }; 738 739 sdc1_state_off: sdc1-off-state { 740 clk-pins { 741 pins = "sdc1_clk"; 742 bias-disable; 743 drive-strength = <2>; 744 }; 745 746 cmd-pins { 747 pins = "sdc1_cmd"; 748 bias-pull-up; 749 drive-strength = <2>; 750 }; 751 752 data-pins { 753 pins = "sdc1_data"; 754 bias-pull-up; 755 drive-strength = <2>; 756 }; 757 758 rclk-pins { 759 pins = "sdc1_rclk"; 760 bias-pull-down; 761 }; 762 }; 763 764 sdc2_state_on: sdc2-on-state { 765 clk-pins { 766 pins = "sdc2_clk"; 767 bias-disable; 768 drive-strength = <16>; 769 }; 770 771 cmd-pins { 772 pins = "sdc2_cmd"; 773 bias-pull-up; 774 drive-strength = <10>; 775 }; 776 777 data-pins { 778 pins = "sdc2_data"; 779 bias-pull-up; 780 drive-strength = <10>; 781 }; 782 }; 783 784 sdc2_state_off: sdc2-off-state { 785 clk-pins { 786 pins = "sdc2_clk"; 787 bias-disable; 788 drive-strength = <2>; 789 }; 790 791 cmd-pins { 792 pins = "sdc2_cmd"; 793 bias-pull-up; 794 drive-strength = <2>; 795 }; 796 797 data-pins { 798 pins = "sdc2_data"; 799 bias-pull-up; 800 drive-strength = <2>; 801 }; 802 }; 803 }; 804 805 gcc: clock-controller@1400000 { 806 compatible = "qcom,gcc-sm6115"; 807 reg = <0x0 0x01400000 0x0 0x1f0000>; 808 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 809 clock-names = "bi_tcxo", "sleep_clk"; 810 #clock-cells = <1>; 811 #reset-cells = <1>; 812 #power-domain-cells = <1>; 813 }; 814 815 usb_hsphy: phy@1613000 { 816 compatible = "qcom,sm6115-qusb2-phy"; 817 reg = <0x0 0x01613000 0x0 0x180>; 818 #phy-cells = <0>; 819 820 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 821 clock-names = "cfg_ahb", "ref"; 822 823 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 824 nvmem-cells = <&qusb2_hstx_trim>; 825 826 status = "disabled"; 827 }; 828 829 cryptobam: dma-controller@1b04000 { 830 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 831 reg = <0x0 0x01b04000 0x0 0x24000>; 832 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 834 clock-names = "bam_clk"; 835 #dma-cells = <1>; 836 qcom,ee = <0>; 837 qcom,controlled-remotely; 838 iommus = <&apps_smmu 0x92 0>, 839 <&apps_smmu 0x94 0x11>, 840 <&apps_smmu 0x96 0x11>, 841 <&apps_smmu 0x98 0x1>, 842 <&apps_smmu 0x9F 0>; 843 }; 844 845 crypto: crypto@1b3a000 { 846 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 847 reg = <0x0 0x01b3a000 0x0 0x6000>; 848 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 849 clock-names = "core"; 850 851 dmas = <&cryptobam 6>, <&cryptobam 7>; 852 dma-names = "rx", "tx"; 853 iommus = <&apps_smmu 0x92 0>, 854 <&apps_smmu 0x94 0x11>, 855 <&apps_smmu 0x96 0x11>, 856 <&apps_smmu 0x98 0x1>, 857 <&apps_smmu 0x9F 0>; 858 }; 859 860 usb_qmpphy: phy@1615000 { 861 compatible = "qcom,sm6115-qmp-usb3-phy"; 862 reg = <0x0 0x01615000 0x0 0x1000>; 863 864 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 865 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 866 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 867 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 868 clock-names = "cfg_ahb", 869 "ref", 870 "com_aux", 871 "pipe"; 872 873 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 874 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 875 reset-names = "phy", "phy_phy"; 876 877 #clock-cells = <0>; 878 clock-output-names = "usb3_phy_pipe_clk_src"; 879 880 #phy-cells = <0>; 881 882 status = "disabled"; 883 }; 884 885 system_noc: interconnect@1880000 { 886 compatible = "qcom,sm6115-snoc"; 887 reg = <0x0 0x01880000 0x0 0x5f080>; 888 clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>, 889 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 890 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 891 <&rpmcc RPM_SMD_IPA_CLK>; 892 clock-names = "cpu_axi", 893 "ufs_axi", 894 "usb_axi", 895 "ipa"; 896 #interconnect-cells = <2>; 897 898 clk_virt: interconnect-clk { 899 compatible = "qcom,sm6115-clk-virt"; 900 #interconnect-cells = <2>; 901 }; 902 903 mmrt_virt: interconnect-mmrt { 904 compatible = "qcom,sm6115-mmrt-virt"; 905 #interconnect-cells = <2>; 906 }; 907 908 mmnrt_virt: interconnect-mmnrt { 909 compatible = "qcom,sm6115-mmnrt-virt"; 910 #interconnect-cells = <2>; 911 }; 912 }; 913 914 config_noc: interconnect@1900000 { 915 compatible = "qcom,sm6115-cnoc"; 916 reg = <0x0 0x01900000 0x0 0x6200>; 917 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; 918 clock-names = "usb_axi"; 919 #interconnect-cells = <2>; 920 }; 921 922 qfprom@1b40000 { 923 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 924 reg = <0x0 0x01b40000 0x0 0x7000>; 925 #address-cells = <1>; 926 #size-cells = <1>; 927 928 qusb2_hstx_trim: hstx-trim@25b { 929 reg = <0x25b 0x1>; 930 bits = <1 4>; 931 }; 932 933 gpu_speed_bin: gpu-speed-bin@6006 { 934 reg = <0x6006 0x2>; 935 bits = <5 8>; 936 }; 937 }; 938 939 rng: rng@1b53000 { 940 compatible = "qcom,prng-ee"; 941 reg = <0x0 0x01b53000 0x0 0x1000>; 942 clocks = <&gcc GCC_PRNG_AHB_CLK>; 943 clock-names = "core"; 944 }; 945 946 pmu@1b8e300 { 947 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon"; 948 reg = <0x0 0x01b8e300 0x0 0x600>; 949 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 950 951 operating-points-v2 = <&cpu_bwmon_opp_table>; 952 interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 953 &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; 954 955 cpu_bwmon_opp_table: opp-table { 956 compatible = "operating-points-v2"; 957 958 opp-0 { 959 opp-peak-kBps = <(200 * 4 * 1000)>; 960 }; 961 962 opp-1 { 963 opp-peak-kBps = <(300 * 4 * 1000)>; 964 }; 965 966 opp-2 { 967 opp-peak-kBps = <(451 * 4 * 1000)>; 968 }; 969 970 opp-3 { 971 opp-peak-kBps = <(547 * 4 * 1000)>; 972 }; 973 974 opp-4 { 975 opp-peak-kBps = <(681 * 4 * 1000)>; 976 }; 977 978 opp-5 { 979 opp-peak-kBps = <(768 * 4 * 1000)>; 980 }; 981 982 opp-6 { 983 opp-peak-kBps = <(1017 * 4 * 1000)>; 984 }; 985 986 opp-7 { 987 opp-peak-kBps = <(1353 * 4 * 1000)>; 988 }; 989 990 opp-8 { 991 opp-peak-kBps = <(1555 * 4 * 1000)>; 992 }; 993 994 opp-9 { 995 opp-peak-kBps = <(1804 * 4 * 1000)>; 996 }; 997 }; 998 }; 999 1000 spmi_bus: spmi@1c40000 { 1001 compatible = "qcom,spmi-pmic-arb"; 1002 reg = <0x0 0x01c40000 0x0 0x1100>, 1003 <0x0 0x01e00000 0x0 0x2000000>, 1004 <0x0 0x03e00000 0x0 0x100000>, 1005 <0x0 0x03f00000 0x0 0xa0000>, 1006 <0x0 0x01c0a000 0x0 0x26000>; 1007 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1008 interrupt-names = "periph_irq"; 1009 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1010 qcom,ee = <0>; 1011 qcom,channel = <0>; 1012 #address-cells = <2>; 1013 #size-cells = <0>; 1014 interrupt-controller; 1015 #interrupt-cells = <4>; 1016 }; 1017 1018 tsens0: thermal-sensor@4411000 { 1019 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 1020 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 1021 <0x0 0x04410000 0x0 0x8>; /* SROT */ 1022 #qcom,sensors = <16>; 1023 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1025 interrupt-names = "uplow", "critical"; 1026 #thermal-sensor-cells = <1>; 1027 }; 1028 1029 bimc: interconnect@4480000 { 1030 compatible = "qcom,sm6115-bimc"; 1031 reg = <0x0 0x04480000 0x0 0x80000>; 1032 #interconnect-cells = <2>; 1033 }; 1034 1035 rpm_msg_ram: sram@45f0000 { 1036 compatible = "qcom,rpm-msg-ram"; 1037 reg = <0x0 0x045f0000 0x0 0x7000>; 1038 }; 1039 1040 sram@4690000 { 1041 compatible = "qcom,rpm-stats"; 1042 reg = <0x0 0x04690000 0x0 0x10000>; 1043 }; 1044 1045 sdhc_1: mmc@4744000 { 1046 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1047 reg = <0x0 0x04744000 0x0 0x1000>, 1048 <0x0 0x04745000 0x0 0x1000>, 1049 <0x0 0x04748000 0x0 0x8000>; 1050 reg-names = "hc", "cqhci", "ice"; 1051 1052 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1054 interrupt-names = "hc_irq", "pwr_irq"; 1055 1056 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1057 <&gcc GCC_SDCC1_APPS_CLK>, 1058 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1059 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1060 clock-names = "iface", "core", "xo", "ice"; 1061 1062 power-domains = <&rpmpd SM6115_VDDCX>; 1063 operating-points-v2 = <&sdhc1_opp_table>; 1064 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 1065 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1066 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1067 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 1068 interconnect-names = "sdhc-ddr", 1069 "cpu-sdhc"; 1070 1071 bus-width = <8>; 1072 status = "disabled"; 1073 1074 sdhc1_opp_table: opp-table { 1075 compatible = "operating-points-v2"; 1076 1077 opp-100000000 { 1078 opp-hz = /bits/ 64 <100000000>; 1079 required-opps = <&rpmpd_opp_low_svs>; 1080 opp-peak-kBps = <250000 133320>; 1081 opp-avg-kBps = <102400 65000>; 1082 }; 1083 1084 opp-192000000 { 1085 opp-hz = /bits/ 64 <192000000>; 1086 required-opps = <&rpmpd_opp_low_svs>; 1087 opp-peak-kBps = <800000 300000>; 1088 opp-avg-kBps = <204800 200000>; 1089 }; 1090 1091 opp-384000000 { 1092 opp-hz = /bits/ 64 <384000000>; 1093 required-opps = <&rpmpd_opp_svs_plus>; 1094 opp-peak-kBps = <800000 300000>; 1095 opp-avg-kBps = <204800 200000>; 1096 }; 1097 }; 1098 }; 1099 1100 sdhc_2: mmc@4784000 { 1101 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1102 reg = <0x0 0x04784000 0x0 0x1000>; 1103 reg-names = "hc"; 1104 1105 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1107 interrupt-names = "hc_irq", "pwr_irq"; 1108 1109 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1110 <&gcc GCC_SDCC2_APPS_CLK>, 1111 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1112 clock-names = "iface", "core", "xo"; 1113 1114 power-domains = <&rpmpd SM6115_VDDCX>; 1115 operating-points-v2 = <&sdhc2_opp_table>; 1116 iommus = <&apps_smmu 0x00a0 0x0>; 1117 resets = <&gcc GCC_SDCC2_BCR>; 1118 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1119 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1120 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1121 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1122 interconnect-names = "sdhc-ddr", 1123 "cpu-sdhc"; 1124 1125 bus-width = <4>; 1126 qcom,dll-config = <0x0007642c>; 1127 qcom,ddr-config = <0x80040868>; 1128 status = "disabled"; 1129 1130 sdhc2_opp_table: opp-table { 1131 compatible = "operating-points-v2"; 1132 1133 opp-100000000 { 1134 opp-hz = /bits/ 64 <100000000>; 1135 required-opps = <&rpmpd_opp_low_svs>; 1136 opp-peak-kBps = <250000 133320>; 1137 opp-avg-kBps = <261438 150000>; 1138 }; 1139 1140 opp-202000000 { 1141 opp-hz = /bits/ 64 <202000000>; 1142 required-opps = <&rpmpd_opp_nom>; 1143 opp-peak-kBps = <800000 300000>; 1144 opp-avg-kBps = <261438 300000>; 1145 }; 1146 }; 1147 }; 1148 1149 ufs_mem_hc: ufs@4804000 { 1150 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1151 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 1152 reg-names = "std", "ice"; 1153 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1154 phys = <&ufs_mem_phy>; 1155 phy-names = "ufsphy"; 1156 lanes-per-direction = <1>; 1157 #reset-cells = <1>; 1158 resets = <&gcc GCC_UFS_PHY_BCR>; 1159 reset-names = "rst"; 1160 1161 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1162 iommus = <&apps_smmu 0x100 0>; 1163 1164 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1165 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 1166 <&gcc GCC_UFS_PHY_AHB_CLK>, 1167 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1168 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1169 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1170 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1171 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1172 clock-names = "core_clk", 1173 "bus_aggr_clk", 1174 "iface_clk", 1175 "core_clk_unipro", 1176 "ref_clk", 1177 "tx_lane0_sync_clk", 1178 "rx_lane0_sync_clk", 1179 "ice_core_clk"; 1180 1181 freq-table-hz = <50000000 200000000>, 1182 <0 0>, 1183 <0 0>, 1184 <37500000 150000000>, 1185 <0 0>, 1186 <0 0>, 1187 <0 0>, 1188 <75000000 300000000>; 1189 1190 status = "disabled"; 1191 }; 1192 1193 ufs_mem_phy: phy@4807000 { 1194 compatible = "qcom,sm6115-qmp-ufs-phy"; 1195 reg = <0x0 0x04807000 0x0 0x1000>; 1196 1197 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1198 clock-names = "ref", "ref_aux"; 1199 1200 resets = <&ufs_mem_hc 0>; 1201 reset-names = "ufsphy"; 1202 1203 #phy-cells = <0>; 1204 1205 status = "disabled"; 1206 }; 1207 1208 gpi_dma0: dma-controller@4a00000 { 1209 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1210 reg = <0x0 0x04a00000 0x0 0x60000>; 1211 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1221 dma-channels = <10>; 1222 dma-channel-mask = <0xf>; 1223 iommus = <&apps_smmu 0xf6 0x0>; 1224 #dma-cells = <3>; 1225 status = "disabled"; 1226 }; 1227 1228 qupv3_id_0: geniqup@4ac0000 { 1229 compatible = "qcom,geni-se-qup"; 1230 reg = <0x0 0x04ac0000 0x0 0x2000>; 1231 clock-names = "m-ahb", "s-ahb"; 1232 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1233 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1234 #address-cells = <2>; 1235 #size-cells = <2>; 1236 iommus = <&apps_smmu 0xe3 0x0>; 1237 ranges; 1238 status = "disabled"; 1239 1240 i2c0: i2c@4a80000 { 1241 compatible = "qcom,geni-i2c"; 1242 reg = <0x0 0x04a80000 0x0 0x4000>; 1243 clock-names = "se"; 1244 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&qup_i2c0_default>; 1247 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1248 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1249 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1250 dma-names = "tx", "rx"; 1251 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1252 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1253 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1254 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1255 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1256 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1257 interconnect-names = "qup-core", 1258 "qup-config", 1259 "qup-memory"; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 status = "disabled"; 1263 }; 1264 1265 spi0: spi@4a80000 { 1266 compatible = "qcom,geni-spi"; 1267 reg = <0x0 0x04a80000 0x0 0x4000>; 1268 clock-names = "se"; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1270 pinctrl-names = "default"; 1271 pinctrl-0 = <&qup_spi0_default>; 1272 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1273 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1274 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1275 dma-names = "tx", "rx"; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1277 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1278 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1279 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1280 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1281 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1282 interconnect-names = "qup-core", 1283 "qup-config", 1284 "qup-memory"; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 i2c1: i2c@4a84000 { 1291 compatible = "qcom,geni-i2c"; 1292 reg = <0x0 0x04a84000 0x0 0x4000>; 1293 clock-names = "se"; 1294 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1295 pinctrl-names = "default"; 1296 pinctrl-0 = <&qup_i2c1_default>; 1297 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1298 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1299 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1300 dma-names = "tx", "rx"; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1302 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1303 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1304 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1305 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1306 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1307 interconnect-names = "qup-core", 1308 "qup-config", 1309 "qup-memory"; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 spi1: spi@4a84000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0x0 0x04a84000 0x0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_spi1_default>; 1322 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1323 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1324 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1325 dma-names = "tx", "rx"; 1326 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1327 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1328 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1329 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1330 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1331 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1332 interconnect-names = "qup-core", 1333 "qup-config", 1334 "qup-memory"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 i2c2: i2c@4a88000 { 1341 compatible = "qcom,geni-i2c"; 1342 reg = <0x0 0x04a88000 0x0 0x4000>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&qup_i2c2_default>; 1347 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1348 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1349 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1350 dma-names = "tx", "rx"; 1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1352 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1353 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1354 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1355 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1356 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1357 interconnect-names = "qup-core", 1358 "qup-config", 1359 "qup-memory"; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 spi2: spi@4a88000 { 1366 compatible = "qcom,geni-spi"; 1367 reg = <0x0 0x04a88000 0x0 0x4000>; 1368 clock-names = "se"; 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_spi2_default>; 1372 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1373 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1374 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1375 dma-names = "tx", "rx"; 1376 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1377 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1378 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1379 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1380 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1381 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1382 interconnect-names = "qup-core", 1383 "qup-config", 1384 "qup-memory"; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 status = "disabled"; 1388 }; 1389 1390 i2c3: i2c@4a8c000 { 1391 compatible = "qcom,geni-i2c"; 1392 reg = <0x0 0x04a8c000 0x0 0x4000>; 1393 clock-names = "se"; 1394 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1395 pinctrl-names = "default"; 1396 pinctrl-0 = <&qup_i2c3_default>; 1397 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1398 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1399 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1400 dma-names = "tx", "rx"; 1401 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1402 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1403 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1404 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1405 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1406 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1407 interconnect-names = "qup-core", 1408 "qup-config", 1409 "qup-memory"; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 status = "disabled"; 1413 }; 1414 1415 spi3: spi@4a8c000 { 1416 compatible = "qcom,geni-spi"; 1417 reg = <0x0 0x04a8c000 0x0 0x4000>; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_spi3_default>; 1422 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1423 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1424 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1425 dma-names = "tx", "rx"; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1427 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1428 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1429 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1430 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1431 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1432 interconnect-names = "qup-core", 1433 "qup-config", 1434 "qup-memory"; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 status = "disabled"; 1438 }; 1439 1440 uart3: serial@4a8c000 { 1441 compatible = "qcom,geni-uart"; 1442 reg = <0x0 0x04a8c000 0x0 0x4000>; 1443 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1444 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1445 clock-names = "se"; 1446 power-domains = <&rpmpd SM6115_VDDCX>; 1447 operating-points-v2 = <&qup_opp_table>; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1449 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1450 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1451 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1452 interconnect-names = "qup-core", 1453 "qup-config"; 1454 status = "disabled"; 1455 }; 1456 1457 i2c4: i2c@4a90000 { 1458 compatible = "qcom,geni-i2c"; 1459 reg = <0x0 0x04a90000 0x0 0x4000>; 1460 clock-names = "se"; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_i2c4_default>; 1464 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1465 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1466 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1467 dma-names = "tx", "rx"; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1469 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1470 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1471 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1472 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1473 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1474 interconnect-names = "qup-core", 1475 "qup-config", 1476 "qup-memory"; 1477 #address-cells = <1>; 1478 #size-cells = <0>; 1479 status = "disabled"; 1480 }; 1481 1482 spi4: spi@4a90000 { 1483 compatible = "qcom,geni-spi"; 1484 reg = <0x0 0x04a90000 0x0 0x4000>; 1485 clock-names = "se"; 1486 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1487 pinctrl-names = "default"; 1488 pinctrl-0 = <&qup_spi4_default>; 1489 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1490 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1491 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1492 dma-names = "tx", "rx"; 1493 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1494 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1495 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1496 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1497 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1498 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1499 interconnect-names = "qup-core", 1500 "qup-config", 1501 "qup-memory"; 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 status = "disabled"; 1505 }; 1506 1507 uart4: serial@4a90000 { 1508 compatible = "qcom,geni-debug-uart"; 1509 reg = <0x0 0x04a90000 0x0 0x4000>; 1510 clock-names = "se"; 1511 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1512 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1513 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1514 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1515 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1516 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1517 interconnect-names = "qup-core", 1518 "qup-config"; 1519 status = "disabled"; 1520 }; 1521 1522 i2c5: i2c@4a94000 { 1523 compatible = "qcom,geni-i2c"; 1524 reg = <0x0 0x04a94000 0x0 0x4000>; 1525 clock-names = "se"; 1526 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1527 pinctrl-names = "default"; 1528 pinctrl-0 = <&qup_i2c5_default>; 1529 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1530 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1531 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1532 dma-names = "tx", "rx"; 1533 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1534 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1535 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1536 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1537 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1538 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1539 interconnect-names = "qup-core", 1540 "qup-config", 1541 "qup-memory"; 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 status = "disabled"; 1545 }; 1546 1547 spi5: spi@4a94000 { 1548 compatible = "qcom,geni-spi"; 1549 reg = <0x0 0x04a94000 0x0 0x4000>; 1550 clock-names = "se"; 1551 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1552 pinctrl-names = "default"; 1553 pinctrl-0 = <&qup_spi5_default>; 1554 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1555 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1556 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1557 dma-names = "tx", "rx"; 1558 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1559 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1560 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1561 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1562 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1563 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1564 interconnect-names = "qup-core", 1565 "qup-config", 1566 "qup-memory"; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 status = "disabled"; 1570 }; 1571 }; 1572 1573 usb: usb@4ef8800 { 1574 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1575 reg = <0x0 0x04ef8800 0x0 0x400>; 1576 #address-cells = <2>; 1577 #size-cells = <2>; 1578 ranges; 1579 1580 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1581 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1582 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1583 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1584 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1585 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1586 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1587 1588 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1589 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1590 assigned-clock-rates = <19200000>, <66666667>; 1591 1592 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1594 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1595 1596 resets = <&gcc GCC_USB30_PRIM_BCR>; 1597 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1598 /* TODO: USB<->IPA path */ 1599 interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG 1600 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1601 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1602 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1603 interconnect-names = "usb-ddr", 1604 "apps-usb"; 1605 1606 qcom,select-utmi-as-pipe-clk; 1607 status = "disabled"; 1608 1609 usb_dwc3: usb@4e00000 { 1610 compatible = "snps,dwc3"; 1611 reg = <0x0 0x04e00000 0x0 0xcd00>; 1612 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1613 phys = <&usb_hsphy>, <&usb_qmpphy>; 1614 phy-names = "usb2-phy", "usb3-phy"; 1615 iommus = <&apps_smmu 0x120 0x0>; 1616 snps,dis_u2_susphy_quirk; 1617 snps,dis_enblslpm_quirk; 1618 snps,has-lpm-erratum; 1619 snps,hird-threshold = /bits/ 8 <0x10>; 1620 snps,usb3_lpm_capable; 1621 }; 1622 }; 1623 1624 gpu: gpu@5900000 { 1625 compatible = "qcom,adreno-610.0", "qcom,adreno"; 1626 reg = <0x0 0x05900000 0x0 0x40000>; 1627 reg-names = "kgsl_3d0_reg_memory"; 1628 1629 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ 1630 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1631 <&gpucc GPU_CC_AHB_CLK>, 1632 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1633 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1634 <&gpucc GPU_CC_CX_GMU_CLK>, 1635 <&gpucc GPU_CC_CXO_CLK>; 1636 clock-names = "core", 1637 "iface", 1638 "mem_iface", 1639 "alt_mem_iface", 1640 "gmu", 1641 "xo"; 1642 1643 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1644 1645 iommus = <&adreno_smmu 0 1>; 1646 operating-points-v2 = <&gpu_opp_table>; 1647 power-domains = <&rpmpd SM6115_VDDCX>; 1648 qcom,gmu = <&gmu_wrapper>; 1649 1650 nvmem-cells = <&gpu_speed_bin>; 1651 nvmem-cell-names = "speed_bin"; 1652 1653 status = "disabled"; 1654 1655 zap-shader { 1656 memory-region = <&pil_gpu_mem>; 1657 }; 1658 1659 gpu_opp_table: opp-table { 1660 compatible = "operating-points-v2"; 1661 1662 opp-320000000 { 1663 opp-hz = /bits/ 64 <320000000>; 1664 required-opps = <&rpmpd_opp_low_svs>; 1665 opp-supported-hw = <0x1f>; 1666 }; 1667 1668 opp-465000000 { 1669 opp-hz = /bits/ 64 <465000000>; 1670 required-opps = <&rpmpd_opp_svs>; 1671 opp-supported-hw = <0x1f>; 1672 }; 1673 1674 opp-600000000 { 1675 opp-hz = /bits/ 64 <600000000>; 1676 required-opps = <&rpmpd_opp_svs_plus>; 1677 opp-supported-hw = <0x1f>; 1678 }; 1679 1680 opp-745000000 { 1681 opp-hz = /bits/ 64 <745000000>; 1682 required-opps = <&rpmpd_opp_nom>; 1683 opp-supported-hw = <0xf>; 1684 }; 1685 1686 opp-820000000 { 1687 opp-hz = /bits/ 64 <820000000>; 1688 required-opps = <&rpmpd_opp_nom_plus>; 1689 opp-supported-hw = <0x7>; 1690 }; 1691 1692 opp-900000000 { 1693 opp-hz = /bits/ 64 <900000000>; 1694 required-opps = <&rpmpd_opp_turbo>; 1695 opp-supported-hw = <0x7>; 1696 }; 1697 1698 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ 1699 opp-950000000 { 1700 opp-hz = /bits/ 64 <950000000>; 1701 required-opps = <&rpmpd_opp_turbo_plus>; 1702 opp-supported-hw = <0x4>; 1703 }; 1704 1705 opp-980000000 { 1706 opp-hz = /bits/ 64 <980000000>; 1707 required-opps = <&rpmpd_opp_turbo_plus>; 1708 opp-supported-hw = <0x3>; 1709 }; 1710 }; 1711 }; 1712 1713 gmu_wrapper: gmu@596a000 { 1714 compatible = "qcom,adreno-gmu-wrapper"; 1715 reg = <0x0 0x0596a000 0x0 0x30000>; 1716 reg-names = "gmu"; 1717 power-domains = <&gpucc GPU_CX_GDSC>, 1718 <&gpucc GPU_GX_GDSC>; 1719 power-domain-names = "cx", "gx"; 1720 }; 1721 1722 gpucc: clock-controller@5990000 { 1723 compatible = "qcom,sm6115-gpucc"; 1724 reg = <0x0 0x05990000 0x0 0x9000>; 1725 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1726 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1727 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1728 #clock-cells = <1>; 1729 #reset-cells = <1>; 1730 #power-domain-cells = <1>; 1731 }; 1732 1733 adreno_smmu: iommu@59a0000 { 1734 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1735 "qcom,smmu-500", "arm,mmu-500"; 1736 reg = <0x0 0x059a0000 0x0 0x10000>; 1737 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1746 1747 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1748 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1749 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1750 clock-names = "mem", 1751 "hlos", 1752 "iface"; 1753 power-domains = <&gpucc GPU_CX_GDSC>; 1754 1755 #global-interrupts = <1>; 1756 #iommu-cells = <2>; 1757 }; 1758 1759 mdss: display-subsystem@5e00000 { 1760 compatible = "qcom,sm6115-mdss"; 1761 reg = <0x0 0x05e00000 0x0 0x1000>; 1762 reg-names = "mdss"; 1763 1764 power-domains = <&dispcc MDSS_GDSC>; 1765 1766 clocks = <&gcc GCC_DISP_AHB_CLK>, 1767 <&gcc GCC_DISP_HF_AXI_CLK>, 1768 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1769 1770 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1771 interrupt-controller; 1772 #interrupt-cells = <1>; 1773 1774 iommus = <&apps_smmu 0x420 0x2>, 1775 <&apps_smmu 0x421 0x0>; 1776 1777 interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG 1778 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1779 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1780 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1781 interconnect-names = "mdp0-mem", 1782 "cpu-cfg"; 1783 1784 #address-cells = <2>; 1785 #size-cells = <2>; 1786 ranges; 1787 1788 status = "disabled"; 1789 1790 mdp: display-controller@5e01000 { 1791 compatible = "qcom,sm6115-dpu"; 1792 reg = <0x0 0x05e01000 0x0 0x8f000>, 1793 <0x0 0x05eb0000 0x0 0x2008>; 1794 reg-names = "mdp", "vbif"; 1795 1796 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1797 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1798 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1799 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1800 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1801 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1802 clock-names = "bus", 1803 "iface", 1804 "core", 1805 "lut", 1806 "rot", 1807 "vsync"; 1808 1809 operating-points-v2 = <&mdp_opp_table>; 1810 power-domains = <&rpmpd SM6115_VDDCX>; 1811 1812 interrupt-parent = <&mdss>; 1813 interrupts = <0>; 1814 1815 ports { 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 1819 port@0 { 1820 reg = <0>; 1821 dpu_intf1_out: endpoint { 1822 remote-endpoint = <&mdss_dsi0_in>; 1823 }; 1824 }; 1825 }; 1826 1827 mdp_opp_table: opp-table { 1828 compatible = "operating-points-v2"; 1829 1830 opp-19200000 { 1831 opp-hz = /bits/ 64 <19200000>; 1832 required-opps = <&rpmpd_opp_min_svs>; 1833 }; 1834 1835 opp-192000000 { 1836 opp-hz = /bits/ 64 <192000000>; 1837 required-opps = <&rpmpd_opp_low_svs>; 1838 }; 1839 1840 opp-256000000 { 1841 opp-hz = /bits/ 64 <256000000>; 1842 required-opps = <&rpmpd_opp_svs>; 1843 }; 1844 1845 opp-307200000 { 1846 opp-hz = /bits/ 64 <307200000>; 1847 required-opps = <&rpmpd_opp_svs_plus>; 1848 }; 1849 1850 opp-384000000 { 1851 opp-hz = /bits/ 64 <384000000>; 1852 required-opps = <&rpmpd_opp_nom>; 1853 }; 1854 }; 1855 }; 1856 1857 mdss_dsi0: dsi@5e94000 { 1858 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1859 reg = <0x0 0x05e94000 0x0 0x400>; 1860 reg-names = "dsi_ctrl"; 1861 1862 interrupt-parent = <&mdss>; 1863 interrupts = <4>; 1864 1865 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1866 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1867 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1868 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1869 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1870 <&gcc GCC_DISP_HF_AXI_CLK>; 1871 clock-names = "byte", 1872 "byte_intf", 1873 "pixel", 1874 "core", 1875 "iface", 1876 "bus"; 1877 1878 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1879 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1880 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1881 1882 operating-points-v2 = <&dsi_opp_table>; 1883 power-domains = <&rpmpd SM6115_VDDCX>; 1884 phys = <&mdss_dsi0_phy>; 1885 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 1889 status = "disabled"; 1890 1891 ports { 1892 #address-cells = <1>; 1893 #size-cells = <0>; 1894 1895 port@0 { 1896 reg = <0>; 1897 mdss_dsi0_in: endpoint { 1898 remote-endpoint = <&dpu_intf1_out>; 1899 }; 1900 }; 1901 1902 port@1 { 1903 reg = <1>; 1904 mdss_dsi0_out: endpoint { 1905 }; 1906 }; 1907 }; 1908 1909 dsi_opp_table: opp-table { 1910 compatible = "operating-points-v2"; 1911 1912 opp-19200000 { 1913 opp-hz = /bits/ 64 <19200000>; 1914 required-opps = <&rpmpd_opp_min_svs>; 1915 }; 1916 1917 opp-164000000 { 1918 opp-hz = /bits/ 64 <164000000>; 1919 required-opps = <&rpmpd_opp_low_svs>; 1920 }; 1921 1922 opp-187500000 { 1923 opp-hz = /bits/ 64 <187500000>; 1924 required-opps = <&rpmpd_opp_svs>; 1925 }; 1926 }; 1927 }; 1928 1929 mdss_dsi0_phy: phy@5e94400 { 1930 compatible = "qcom,dsi-phy-14nm-2290"; 1931 reg = <0x0 0x05e94400 0x0 0x100>, 1932 <0x0 0x05e94500 0x0 0x300>, 1933 <0x0 0x05e94800 0x0 0x188>; 1934 reg-names = "dsi_phy", 1935 "dsi_phy_lane", 1936 "dsi_pll"; 1937 1938 #clock-cells = <1>; 1939 #phy-cells = <0>; 1940 1941 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1942 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1943 clock-names = "iface", "ref"; 1944 1945 status = "disabled"; 1946 }; 1947 }; 1948 1949 dispcc: clock-controller@5f00000 { 1950 compatible = "qcom,sm6115-dispcc"; 1951 reg = <0x0 0x05f00000 0 0x20000>; 1952 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1953 <&sleep_clk>, 1954 <&mdss_dsi0_phy 0>, 1955 <&mdss_dsi0_phy 1>, 1956 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1957 #clock-cells = <1>; 1958 #reset-cells = <1>; 1959 #power-domain-cells = <1>; 1960 }; 1961 1962 remoteproc_mpss: remoteproc@6080000 { 1963 compatible = "qcom,sm6115-mpss-pas"; 1964 reg = <0x0 0x06080000 0x0 0x100>; 1965 1966 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1967 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1968 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1969 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1970 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1971 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1972 interrupt-names = "wdog", "fatal", "ready", "handover", 1973 "stop-ack", "shutdown-ack"; 1974 1975 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1976 clock-names = "xo"; 1977 1978 power-domains = <&rpmpd SM6115_VDDCX>; 1979 1980 memory-region = <&pil_modem_mem>; 1981 1982 qcom,smem-states = <&modem_smp2p_out 0>; 1983 qcom,smem-state-names = "stop"; 1984 1985 status = "disabled"; 1986 1987 glink-edge { 1988 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1989 label = "mpss"; 1990 qcom,remote-pid = <1>; 1991 mboxes = <&apcs_glb 12>; 1992 }; 1993 }; 1994 1995 stm@8002000 { 1996 compatible = "arm,coresight-stm", "arm,primecell"; 1997 reg = <0x0 0x08002000 0x0 0x1000>, 1998 <0x0 0x0e280000 0x0 0x180000>; 1999 reg-names = "stm-base", "stm-stimulus-base"; 2000 2001 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2002 clock-names = "apb_pclk"; 2003 2004 status = "disabled"; 2005 2006 out-ports { 2007 port { 2008 stm_out: endpoint { 2009 remote-endpoint = <&funnel_in0_in>; 2010 }; 2011 }; 2012 }; 2013 }; 2014 2015 cti0: cti@8010000 { 2016 compatible = "arm,coresight-cti", "arm,primecell"; 2017 reg = <0x0 0x08010000 0x0 0x1000>; 2018 2019 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2020 clock-names = "apb_pclk"; 2021 2022 status = "disabled"; 2023 }; 2024 2025 cti1: cti@8011000 { 2026 compatible = "arm,coresight-cti", "arm,primecell"; 2027 reg = <0x0 0x08011000 0x0 0x1000>; 2028 2029 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2030 clock-names = "apb_pclk"; 2031 2032 status = "disabled"; 2033 }; 2034 2035 cti2: cti@8012000 { 2036 compatible = "arm,coresight-cti", "arm,primecell"; 2037 reg = <0x0 0x08012000 0x0 0x1000>; 2038 2039 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2040 clock-names = "apb_pclk"; 2041 2042 status = "disabled"; 2043 }; 2044 2045 cti3: cti@8013000 { 2046 compatible = "arm,coresight-cti", "arm,primecell"; 2047 reg = <0x0 0x08013000 0x0 0x1000>; 2048 2049 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2050 clock-names = "apb_pclk"; 2051 2052 status = "disabled"; 2053 }; 2054 2055 cti4: cti@8014000 { 2056 compatible = "arm,coresight-cti", "arm,primecell"; 2057 reg = <0x0 0x08014000 0x0 0x1000>; 2058 2059 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2060 clock-names = "apb_pclk"; 2061 2062 status = "disabled"; 2063 }; 2064 2065 cti5: cti@8015000 { 2066 compatible = "arm,coresight-cti", "arm,primecell"; 2067 reg = <0x0 0x08015000 0x0 0x1000>; 2068 2069 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2070 clock-names = "apb_pclk"; 2071 2072 status = "disabled"; 2073 }; 2074 2075 cti6: cti@8016000 { 2076 compatible = "arm,coresight-cti", "arm,primecell"; 2077 reg = <0x0 0x08016000 0x0 0x1000>; 2078 2079 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2080 clock-names = "apb_pclk"; 2081 2082 status = "disabled"; 2083 }; 2084 2085 cti7: cti@8017000 { 2086 compatible = "arm,coresight-cti", "arm,primecell"; 2087 reg = <0x0 0x08017000 0x0 0x1000>; 2088 2089 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2090 clock-names = "apb_pclk"; 2091 2092 status = "disabled"; 2093 }; 2094 2095 cti8: cti@8018000 { 2096 compatible = "arm,coresight-cti", "arm,primecell"; 2097 reg = <0x0 0x08018000 0x0 0x1000>; 2098 2099 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2100 clock-names = "apb_pclk"; 2101 2102 status = "disabled"; 2103 }; 2104 2105 cti9: cti@8019000 { 2106 compatible = "arm,coresight-cti", "arm,primecell"; 2107 reg = <0x0 0x08019000 0x0 0x1000>; 2108 2109 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2110 clock-names = "apb_pclk"; 2111 2112 status = "disabled"; 2113 }; 2114 2115 cti10: cti@801a000 { 2116 compatible = "arm,coresight-cti", "arm,primecell"; 2117 reg = <0x0 0x0801a000 0x0 0x1000>; 2118 2119 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2120 clock-names = "apb_pclk"; 2121 2122 status = "disabled"; 2123 }; 2124 2125 cti11: cti@801b000 { 2126 compatible = "arm,coresight-cti", "arm,primecell"; 2127 reg = <0x0 0x0801b000 0x0 0x1000>; 2128 2129 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2130 clock-names = "apb_pclk"; 2131 2132 status = "disabled"; 2133 }; 2134 2135 cti12: cti@801c000 { 2136 compatible = "arm,coresight-cti", "arm,primecell"; 2137 reg = <0x0 0x0801c000 0x0 0x1000>; 2138 2139 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2140 clock-names = "apb_pclk"; 2141 2142 status = "disabled"; 2143 }; 2144 2145 cti13: cti@801d000 { 2146 compatible = "arm,coresight-cti", "arm,primecell"; 2147 reg = <0x0 0x0801d000 0x0 0x1000>; 2148 2149 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2150 clock-names = "apb_pclk"; 2151 2152 status = "disabled"; 2153 }; 2154 2155 cti14: cti@801e000 { 2156 compatible = "arm,coresight-cti", "arm,primecell"; 2157 reg = <0x0 0x0801e000 0x0 0x1000>; 2158 2159 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2160 clock-names = "apb_pclk"; 2161 2162 status = "disabled"; 2163 }; 2164 2165 cti15: cti@801f000 { 2166 compatible = "arm,coresight-cti", "arm,primecell"; 2167 reg = <0x0 0x0801f000 0x0 0x1000>; 2168 2169 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2170 clock-names = "apb_pclk"; 2171 2172 status = "disabled"; 2173 }; 2174 2175 replicator@8046000 { 2176 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2177 reg = <0x0 0x08046000 0x0 0x1000>; 2178 2179 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2180 clock-names = "apb_pclk"; 2181 2182 status = "disabled"; 2183 2184 out-ports { 2185 port { 2186 replicator_out: endpoint { 2187 remote-endpoint = <&etr_in>; 2188 }; 2189 }; 2190 }; 2191 2192 in-ports { 2193 port { 2194 replicator_in: endpoint { 2195 remote-endpoint = <&etf_out>; 2196 }; 2197 }; 2198 }; 2199 }; 2200 2201 etf@8047000 { 2202 compatible = "arm,coresight-tmc", "arm,primecell"; 2203 reg = <0x0 0x08047000 0x0 0x1000>; 2204 2205 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2206 clock-names = "apb_pclk"; 2207 2208 status = "disabled"; 2209 2210 in-ports { 2211 port { 2212 etf_in: endpoint { 2213 remote-endpoint = <&merge_funnel_out>; 2214 }; 2215 }; 2216 }; 2217 2218 out-ports { 2219 port { 2220 etf_out: endpoint { 2221 remote-endpoint = <&replicator_in>; 2222 }; 2223 }; 2224 }; 2225 }; 2226 2227 etr@8048000 { 2228 compatible = "arm,coresight-tmc", "arm,primecell"; 2229 reg = <0x0 0x08048000 0x0 0x1000>; 2230 2231 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2232 clock-names = "apb_pclk"; 2233 2234 status = "disabled"; 2235 2236 in-ports { 2237 port { 2238 etr_in: endpoint { 2239 remote-endpoint = <&replicator_out>; 2240 }; 2241 }; 2242 }; 2243 }; 2244 2245 funnel@8041000 { 2246 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2247 reg = <0x0 0x08041000 0x0 0x1000>; 2248 2249 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2250 clock-names = "apb_pclk"; 2251 2252 status = "disabled"; 2253 2254 out-ports { 2255 port { 2256 funnel_in0_out: endpoint { 2257 remote-endpoint = <&merge_funnel_in0>; 2258 }; 2259 }; 2260 }; 2261 2262 in-ports { 2263 port { 2264 funnel_in0_in: endpoint { 2265 remote-endpoint = <&stm_out>; 2266 }; 2267 }; 2268 }; 2269 }; 2270 2271 funnel@8042000 { 2272 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2273 reg = <0x0 0x08042000 0x0 0x1000>; 2274 2275 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2276 clock-names = "apb_pclk"; 2277 2278 status = "disabled"; 2279 2280 out-ports { 2281 port { 2282 funnel_in1_out: endpoint { 2283 remote-endpoint = <&merge_funnel_in1>; 2284 }; 2285 }; 2286 }; 2287 2288 in-ports { 2289 port { 2290 funnel_in1_in: endpoint { 2291 remote-endpoint = <&funnel_apss1_out>; 2292 }; 2293 }; 2294 }; 2295 }; 2296 2297 funnel@8045000 { 2298 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2299 reg = <0x0 0x08045000 0x0 0x1000>; 2300 2301 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2302 clock-names = "apb_pclk"; 2303 2304 status = "disabled"; 2305 2306 out-ports { 2307 port { 2308 merge_funnel_out: endpoint { 2309 remote-endpoint = <&etf_in>; 2310 }; 2311 }; 2312 }; 2313 2314 in-ports { 2315 #address-cells = <1>; 2316 #size-cells = <0>; 2317 2318 port@0 { 2319 reg = <0>; 2320 merge_funnel_in0: endpoint { 2321 remote-endpoint = <&funnel_in0_out>; 2322 }; 2323 }; 2324 2325 port@1 { 2326 reg = <1>; 2327 merge_funnel_in1: endpoint { 2328 remote-endpoint = <&funnel_in1_out>; 2329 }; 2330 }; 2331 }; 2332 }; 2333 2334 etm@9040000 { 2335 compatible = "arm,coresight-etm4x", "arm,primecell"; 2336 reg = <0x0 0x09040000 0x0 0x1000>; 2337 2338 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2339 clock-names = "apb_pclk"; 2340 arm,coresight-loses-context-with-cpu; 2341 2342 cpu = <&CPU0>; 2343 2344 status = "disabled"; 2345 2346 out-ports { 2347 port { 2348 etm0_out: endpoint { 2349 remote-endpoint = <&funnel_apss0_in0>; 2350 }; 2351 }; 2352 }; 2353 }; 2354 2355 etm@9140000 { 2356 compatible = "arm,coresight-etm4x", "arm,primecell"; 2357 reg = <0x0 0x09140000 0x0 0x1000>; 2358 2359 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2360 clock-names = "apb_pclk"; 2361 arm,coresight-loses-context-with-cpu; 2362 2363 cpu = <&CPU1>; 2364 2365 status = "disabled"; 2366 2367 out-ports { 2368 port { 2369 etm1_out: endpoint { 2370 remote-endpoint = <&funnel_apss0_in1>; 2371 }; 2372 }; 2373 }; 2374 }; 2375 2376 etm@9240000 { 2377 compatible = "arm,coresight-etm4x", "arm,primecell"; 2378 reg = <0x0 0x09240000 0x0 0x1000>; 2379 2380 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2381 clock-names = "apb_pclk"; 2382 arm,coresight-loses-context-with-cpu; 2383 2384 cpu = <&CPU2>; 2385 2386 status = "disabled"; 2387 2388 out-ports { 2389 port { 2390 etm2_out: endpoint { 2391 remote-endpoint = <&funnel_apss0_in2>; 2392 }; 2393 }; 2394 }; 2395 }; 2396 2397 etm@9340000 { 2398 compatible = "arm,coresight-etm4x", "arm,primecell"; 2399 reg = <0x0 0x09340000 0x0 0x1000>; 2400 2401 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2402 clock-names = "apb_pclk"; 2403 arm,coresight-loses-context-with-cpu; 2404 2405 cpu = <&CPU3>; 2406 2407 status = "disabled"; 2408 2409 out-ports { 2410 port { 2411 etm3_out: endpoint { 2412 remote-endpoint = <&funnel_apss0_in3>; 2413 }; 2414 }; 2415 }; 2416 }; 2417 2418 etm@9440000 { 2419 compatible = "arm,coresight-etm4x", "arm,primecell"; 2420 reg = <0x0 0x09440000 0x0 0x1000>; 2421 2422 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2423 clock-names = "apb_pclk"; 2424 arm,coresight-loses-context-with-cpu; 2425 2426 cpu = <&CPU4>; 2427 2428 status = "disabled"; 2429 2430 out-ports { 2431 port { 2432 etm4_out: endpoint { 2433 remote-endpoint = <&funnel_apss0_in4>; 2434 }; 2435 }; 2436 }; 2437 }; 2438 2439 etm@9540000 { 2440 compatible = "arm,coresight-etm4x", "arm,primecell"; 2441 reg = <0x0 0x09540000 0x0 0x1000>; 2442 2443 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2444 clock-names = "apb_pclk"; 2445 arm,coresight-loses-context-with-cpu; 2446 2447 cpu = <&CPU5>; 2448 2449 status = "disabled"; 2450 2451 out-ports { 2452 port { 2453 etm5_out: endpoint { 2454 remote-endpoint = <&funnel_apss0_in5>; 2455 }; 2456 }; 2457 }; 2458 }; 2459 2460 etm@9640000 { 2461 compatible = "arm,coresight-etm4x", "arm,primecell"; 2462 reg = <0x0 0x09640000 0x0 0x1000>; 2463 2464 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2465 clock-names = "apb_pclk"; 2466 arm,coresight-loses-context-with-cpu; 2467 2468 cpu = <&CPU6>; 2469 2470 status = "disabled"; 2471 2472 out-ports { 2473 port { 2474 etm6_out: endpoint { 2475 remote-endpoint = <&funnel_apss0_in6>; 2476 }; 2477 }; 2478 }; 2479 }; 2480 2481 etm@9740000 { 2482 compatible = "arm,coresight-etm4x", "arm,primecell"; 2483 reg = <0x0 0x09740000 0x0 0x1000>; 2484 2485 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2486 clock-names = "apb_pclk"; 2487 arm,coresight-loses-context-with-cpu; 2488 2489 cpu = <&CPU7>; 2490 2491 status = "disabled"; 2492 2493 out-ports { 2494 port { 2495 etm7_out: endpoint { 2496 remote-endpoint = <&funnel_apss0_in7>; 2497 }; 2498 }; 2499 }; 2500 }; 2501 2502 funnel@9800000 { 2503 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2504 reg = <0x0 0x09800000 0x0 0x1000>; 2505 2506 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2507 clock-names = "apb_pclk"; 2508 2509 status = "disabled"; 2510 2511 out-ports { 2512 port { 2513 funnel_apss0_out: endpoint { 2514 remote-endpoint = <&funnel_apss1_in>; 2515 }; 2516 }; 2517 }; 2518 2519 in-ports { 2520 #address-cells = <1>; 2521 #size-cells = <0>; 2522 2523 port@0 { 2524 reg = <0>; 2525 funnel_apss0_in0: endpoint { 2526 remote-endpoint = <&etm0_out>; 2527 }; 2528 }; 2529 2530 port@1 { 2531 reg = <1>; 2532 funnel_apss0_in1: endpoint { 2533 remote-endpoint = <&etm1_out>; 2534 }; 2535 }; 2536 2537 port@2 { 2538 reg = <2>; 2539 funnel_apss0_in2: endpoint { 2540 remote-endpoint = <&etm2_out>; 2541 }; 2542 }; 2543 2544 port@3 { 2545 reg = <3>; 2546 funnel_apss0_in3: endpoint { 2547 remote-endpoint = <&etm3_out>; 2548 }; 2549 }; 2550 2551 port@4 { 2552 reg = <4>; 2553 funnel_apss0_in4: endpoint { 2554 remote-endpoint = <&etm4_out>; 2555 }; 2556 }; 2557 2558 port@5 { 2559 reg = <5>; 2560 funnel_apss0_in5: endpoint { 2561 remote-endpoint = <&etm5_out>; 2562 }; 2563 }; 2564 2565 port@6 { 2566 reg = <6>; 2567 funnel_apss0_in6: endpoint { 2568 remote-endpoint = <&etm6_out>; 2569 }; 2570 }; 2571 2572 port@7 { 2573 reg = <7>; 2574 funnel_apss0_in7: endpoint { 2575 remote-endpoint = <&etm7_out>; 2576 }; 2577 }; 2578 }; 2579 }; 2580 2581 funnel@9810000 { 2582 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2583 reg = <0x0 0x09810000 0x0 0x1000>; 2584 2585 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2586 clock-names = "apb_pclk"; 2587 2588 status = "disabled"; 2589 2590 out-ports { 2591 port { 2592 funnel_apss1_out: endpoint { 2593 remote-endpoint = <&funnel_in1_in>; 2594 }; 2595 }; 2596 }; 2597 2598 in-ports { 2599 port { 2600 funnel_apss1_in: endpoint { 2601 remote-endpoint = <&funnel_apss0_out>; 2602 }; 2603 }; 2604 }; 2605 }; 2606 2607 remoteproc_adsp: remoteproc@ab00000 { 2608 compatible = "qcom,sm6115-adsp-pas"; 2609 reg = <0x0 0x0ab00000 0x0 0x100>; 2610 2611 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2612 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2613 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2614 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2615 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2616 interrupt-names = "wdog", "fatal", "ready", 2617 "handover", "stop-ack"; 2618 2619 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2620 clock-names = "xo"; 2621 2622 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2623 <&rpmpd SM6115_VDD_LPI_MX>; 2624 2625 memory-region = <&pil_adsp_mem>; 2626 2627 qcom,smem-states = <&adsp_smp2p_out 0>; 2628 qcom,smem-state-names = "stop"; 2629 2630 status = "disabled"; 2631 2632 glink-edge { 2633 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2634 label = "lpass"; 2635 qcom,remote-pid = <2>; 2636 mboxes = <&apcs_glb 8>; 2637 2638 fastrpc { 2639 compatible = "qcom,fastrpc"; 2640 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2641 label = "adsp"; 2642 qcom,non-secure-domain; 2643 #address-cells = <1>; 2644 #size-cells = <0>; 2645 2646 compute-cb@3 { 2647 compatible = "qcom,fastrpc-compute-cb"; 2648 reg = <3>; 2649 iommus = <&apps_smmu 0x01c3 0x0>; 2650 }; 2651 2652 compute-cb@4 { 2653 compatible = "qcom,fastrpc-compute-cb"; 2654 reg = <4>; 2655 iommus = <&apps_smmu 0x01c4 0x0>; 2656 }; 2657 2658 compute-cb@5 { 2659 compatible = "qcom,fastrpc-compute-cb"; 2660 reg = <5>; 2661 iommus = <&apps_smmu 0x01c5 0x0>; 2662 }; 2663 2664 compute-cb@6 { 2665 compatible = "qcom,fastrpc-compute-cb"; 2666 reg = <6>; 2667 iommus = <&apps_smmu 0x01c6 0x0>; 2668 }; 2669 2670 compute-cb@7 { 2671 compatible = "qcom,fastrpc-compute-cb"; 2672 reg = <7>; 2673 iommus = <&apps_smmu 0x01c7 0x0>; 2674 }; 2675 }; 2676 }; 2677 }; 2678 2679 remoteproc_cdsp: remoteproc@b300000 { 2680 compatible = "qcom,sm6115-cdsp-pas"; 2681 reg = <0x0 0x0b300000 0x0 0x100000>; 2682 2683 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2684 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2685 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2686 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2687 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2688 interrupt-names = "wdog", "fatal", "ready", 2689 "handover", "stop-ack"; 2690 2691 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2692 clock-names = "xo"; 2693 2694 power-domains = <&rpmpd SM6115_VDDCX>; 2695 2696 memory-region = <&pil_cdsp_mem>; 2697 2698 qcom,smem-states = <&cdsp_smp2p_out 0>; 2699 qcom,smem-state-names = "stop"; 2700 2701 status = "disabled"; 2702 2703 glink-edge { 2704 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2705 label = "cdsp"; 2706 qcom,remote-pid = <5>; 2707 mboxes = <&apcs_glb 28>; 2708 2709 fastrpc { 2710 compatible = "qcom,fastrpc"; 2711 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2712 label = "cdsp"; 2713 qcom,non-secure-domain; 2714 #address-cells = <1>; 2715 #size-cells = <0>; 2716 2717 compute-cb@1 { 2718 compatible = "qcom,fastrpc-compute-cb"; 2719 reg = <1>; 2720 iommus = <&apps_smmu 0x0c01 0x0>; 2721 }; 2722 2723 compute-cb@2 { 2724 compatible = "qcom,fastrpc-compute-cb"; 2725 reg = <2>; 2726 iommus = <&apps_smmu 0x0c02 0x0>; 2727 }; 2728 2729 compute-cb@3 { 2730 compatible = "qcom,fastrpc-compute-cb"; 2731 reg = <3>; 2732 iommus = <&apps_smmu 0x0c03 0x0>; 2733 }; 2734 2735 compute-cb@4 { 2736 compatible = "qcom,fastrpc-compute-cb"; 2737 reg = <4>; 2738 iommus = <&apps_smmu 0x0c04 0x0>; 2739 }; 2740 2741 compute-cb@5 { 2742 compatible = "qcom,fastrpc-compute-cb"; 2743 reg = <5>; 2744 iommus = <&apps_smmu 0x0c05 0x0>; 2745 }; 2746 2747 compute-cb@6 { 2748 compatible = "qcom,fastrpc-compute-cb"; 2749 reg = <6>; 2750 iommus = <&apps_smmu 0x0c06 0x0>; 2751 }; 2752 2753 /* note: secure cb9 in downstream */ 2754 }; 2755 }; 2756 }; 2757 2758 apps_smmu: iommu@c600000 { 2759 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2760 reg = <0x0 0x0c600000 0x0 0x80000>; 2761 #iommu-cells = <2>; 2762 #global-interrupts = <1>; 2763 2764 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2768 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2769 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2770 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2771 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2772 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2773 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2774 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2775 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2776 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2777 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2778 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2779 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2781 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2782 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2783 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2789 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2790 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2791 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2792 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2794 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2795 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2797 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2798 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2799 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2800 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2801 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2802 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2803 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2804 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2805 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2806 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2807 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2808 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2809 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2810 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2811 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2812 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2813 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2814 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2815 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2816 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2817 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2818 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2819 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2820 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2821 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2822 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2823 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2824 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2825 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2826 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2827 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2828 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2829 }; 2830 2831 wifi: wifi@c800000 { 2832 compatible = "qcom,wcn3990-wifi"; 2833 reg = <0x0 0x0c800000 0x0 0x800000>; 2834 reg-names = "membase"; 2835 memory-region = <&wlan_msa_mem>; 2836 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2837 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2838 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2839 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2840 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2841 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2842 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2843 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2844 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2845 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2847 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2848 iommus = <&apps_smmu 0x1a0 0x1>; 2849 qcom,msa-fixed-perm; 2850 status = "disabled"; 2851 }; 2852 2853 watchdog@f017000 { 2854 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2855 reg = <0x0 0x0f017000 0x0 0x1000>; 2856 clocks = <&sleep_clk>; 2857 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2858 }; 2859 2860 apcs_glb: mailbox@f111000 { 2861 compatible = "qcom,sm6115-apcs-hmss-global", 2862 "qcom,msm8994-apcs-kpss-global"; 2863 reg = <0x0 0x0f111000 0x0 0x1000>; 2864 2865 #mbox-cells = <1>; 2866 }; 2867 2868 timer@f120000 { 2869 compatible = "arm,armv7-timer-mem"; 2870 reg = <0x0 0x0f120000 0x0 0x1000>; 2871 #address-cells = <2>; 2872 #size-cells = <1>; 2873 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 2874 clock-frequency = <19200000>; 2875 2876 frame@f121000 { 2877 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>; 2878 frame-number = <0>; 2879 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2880 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2881 }; 2882 2883 frame@f123000 { 2884 reg = <0x0 0x0f123000 0x1000>; 2885 frame-number = <1>; 2886 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2887 status = "disabled"; 2888 }; 2889 2890 frame@f124000 { 2891 reg = <0x0 0x0f124000 0x1000>; 2892 frame-number = <2>; 2893 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2894 status = "disabled"; 2895 }; 2896 2897 frame@f125000 { 2898 reg = <0x0 0x0f125000 0x1000>; 2899 frame-number = <3>; 2900 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2901 status = "disabled"; 2902 }; 2903 2904 frame@f126000 { 2905 reg = <0x0 0x0f126000 0x1000>; 2906 frame-number = <4>; 2907 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2908 status = "disabled"; 2909 }; 2910 2911 frame@f127000 { 2912 reg = <0x0 0x0f127000 0x1000>; 2913 frame-number = <5>; 2914 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2915 status = "disabled"; 2916 }; 2917 2918 frame@f128000 { 2919 reg = <0x0 0x0f128000 0x1000>; 2920 frame-number = <6>; 2921 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2922 status = "disabled"; 2923 }; 2924 }; 2925 2926 intc: interrupt-controller@f200000 { 2927 compatible = "arm,gic-v3"; 2928 reg = <0x0 0x0f200000 0x0 0x10000>, 2929 <0x0 0x0f300000 0x0 0x100000>; 2930 #interrupt-cells = <3>; 2931 interrupt-controller; 2932 interrupt-parent = <&intc>; 2933 #redistributor-regions = <1>; 2934 redistributor-stride = <0x0 0x20000>; 2935 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2936 }; 2937 2938 cpufreq_hw: cpufreq@f521000 { 2939 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 2940 reg = <0x0 0x0f521000 0x0 0x1000>, 2941 <0x0 0x0f523000 0x0 0x1000>; 2942 2943 reg-names = "freq-domain0", "freq-domain1"; 2944 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2945 clock-names = "xo", "alternate"; 2946 2947 #freq-domain-cells = <1>; 2948 #clock-cells = <1>; 2949 }; 2950 }; 2951 2952 thermal-zones { 2953 mapss-thermal { 2954 polling-delay-passive = <0>; 2955 polling-delay = <0>; 2956 thermal-sensors = <&tsens0 0>; 2957 2958 trips { 2959 trip-point0 { 2960 temperature = <115000>; 2961 hysteresis = <5000>; 2962 type = "passive"; 2963 }; 2964 2965 trip-point1 { 2966 temperature = <125000>; 2967 hysteresis = <1000>; 2968 type = "passive"; 2969 }; 2970 }; 2971 }; 2972 2973 cdsp-hvx-thermal { 2974 polling-delay-passive = <0>; 2975 polling-delay = <0>; 2976 thermal-sensors = <&tsens0 1>; 2977 2978 trips { 2979 trip-point0 { 2980 temperature = <115000>; 2981 hysteresis = <5000>; 2982 type = "passive"; 2983 }; 2984 2985 trip-point1 { 2986 temperature = <125000>; 2987 hysteresis = <1000>; 2988 type = "passive"; 2989 }; 2990 }; 2991 }; 2992 2993 wlan-thermal { 2994 polling-delay-passive = <0>; 2995 polling-delay = <0>; 2996 thermal-sensors = <&tsens0 2>; 2997 2998 trips { 2999 trip-point0 { 3000 temperature = <115000>; 3001 hysteresis = <5000>; 3002 type = "passive"; 3003 }; 3004 3005 trip-point1 { 3006 temperature = <125000>; 3007 hysteresis = <1000>; 3008 type = "passive"; 3009 }; 3010 }; 3011 }; 3012 3013 camera-thermal { 3014 polling-delay-passive = <0>; 3015 polling-delay = <0>; 3016 thermal-sensors = <&tsens0 3>; 3017 3018 trips { 3019 trip-point0 { 3020 temperature = <115000>; 3021 hysteresis = <5000>; 3022 type = "passive"; 3023 }; 3024 3025 trip-point1 { 3026 temperature = <125000>; 3027 hysteresis = <1000>; 3028 type = "passive"; 3029 }; 3030 }; 3031 }; 3032 3033 video-thermal { 3034 polling-delay-passive = <0>; 3035 polling-delay = <0>; 3036 thermal-sensors = <&tsens0 4>; 3037 3038 trips { 3039 trip-point0 { 3040 temperature = <115000>; 3041 hysteresis = <5000>; 3042 type = "passive"; 3043 }; 3044 3045 trip-point1 { 3046 temperature = <125000>; 3047 hysteresis = <1000>; 3048 type = "passive"; 3049 }; 3050 }; 3051 }; 3052 3053 modem1-thermal { 3054 polling-delay-passive = <0>; 3055 polling-delay = <0>; 3056 thermal-sensors = <&tsens0 5>; 3057 3058 trips { 3059 trip-point0 { 3060 temperature = <115000>; 3061 hysteresis = <5000>; 3062 type = "passive"; 3063 }; 3064 3065 trip-point1 { 3066 temperature = <125000>; 3067 hysteresis = <1000>; 3068 type = "passive"; 3069 }; 3070 }; 3071 }; 3072 3073 cpu4-thermal { 3074 polling-delay-passive = <0>; 3075 polling-delay = <0>; 3076 thermal-sensors = <&tsens0 6>; 3077 3078 trips { 3079 cpu4_alert0: trip-point0 { 3080 temperature = <90000>; 3081 hysteresis = <2000>; 3082 type = "passive"; 3083 }; 3084 3085 cpu4_alert1: trip-point1 { 3086 temperature = <95000>; 3087 hysteresis = <2000>; 3088 type = "passive"; 3089 }; 3090 3091 cpu4_crit: cpu_crit { 3092 temperature = <110000>; 3093 hysteresis = <1000>; 3094 type = "critical"; 3095 }; 3096 }; 3097 }; 3098 3099 cpu5-thermal { 3100 polling-delay-passive = <0>; 3101 polling-delay = <0>; 3102 thermal-sensors = <&tsens0 7>; 3103 3104 trips { 3105 cpu5_alert0: trip-point0 { 3106 temperature = <90000>; 3107 hysteresis = <2000>; 3108 type = "passive"; 3109 }; 3110 3111 cpu5_alert1: trip-point1 { 3112 temperature = <95000>; 3113 hysteresis = <2000>; 3114 type = "passive"; 3115 }; 3116 3117 cpu5_crit: cpu_crit { 3118 temperature = <110000>; 3119 hysteresis = <1000>; 3120 type = "critical"; 3121 }; 3122 }; 3123 }; 3124 3125 cpu6-thermal { 3126 polling-delay-passive = <0>; 3127 polling-delay = <0>; 3128 thermal-sensors = <&tsens0 8>; 3129 3130 trips { 3131 cpu6_alert0: trip-point0 { 3132 temperature = <90000>; 3133 hysteresis = <2000>; 3134 type = "passive"; 3135 }; 3136 3137 cpu6_alert1: trip-point1 { 3138 temperature = <95000>; 3139 hysteresis = <2000>; 3140 type = "passive"; 3141 }; 3142 3143 cpu6_crit: cpu_crit { 3144 temperature = <110000>; 3145 hysteresis = <1000>; 3146 type = "critical"; 3147 }; 3148 }; 3149 }; 3150 3151 cpu7-thermal { 3152 polling-delay-passive = <0>; 3153 polling-delay = <0>; 3154 thermal-sensors = <&tsens0 9>; 3155 3156 trips { 3157 cpu7_alert0: trip-point0 { 3158 temperature = <90000>; 3159 hysteresis = <2000>; 3160 type = "passive"; 3161 }; 3162 3163 cpu7_alert1: trip-point1 { 3164 temperature = <95000>; 3165 hysteresis = <2000>; 3166 type = "passive"; 3167 }; 3168 3169 cpu7_crit: cpu_crit { 3170 temperature = <110000>; 3171 hysteresis = <1000>; 3172 type = "critical"; 3173 }; 3174 }; 3175 }; 3176 3177 cpu45-thermal { 3178 polling-delay-passive = <0>; 3179 polling-delay = <0>; 3180 thermal-sensors = <&tsens0 10>; 3181 3182 trips { 3183 cpu45_alert0: trip-point0 { 3184 temperature = <90000>; 3185 hysteresis = <2000>; 3186 type = "passive"; 3187 }; 3188 3189 cpu45_alert1: trip-point1 { 3190 temperature = <95000>; 3191 hysteresis = <2000>; 3192 type = "passive"; 3193 }; 3194 3195 cpu45_crit: cpu_crit { 3196 temperature = <110000>; 3197 hysteresis = <1000>; 3198 type = "critical"; 3199 }; 3200 }; 3201 }; 3202 3203 cpu67-thermal { 3204 polling-delay-passive = <0>; 3205 polling-delay = <0>; 3206 thermal-sensors = <&tsens0 11>; 3207 3208 trips { 3209 cpu67_alert0: trip-point0 { 3210 temperature = <90000>; 3211 hysteresis = <2000>; 3212 type = "passive"; 3213 }; 3214 3215 cpu67_alert1: trip-point1 { 3216 temperature = <95000>; 3217 hysteresis = <2000>; 3218 type = "passive"; 3219 }; 3220 3221 cpu67_crit: cpu_crit { 3222 temperature = <110000>; 3223 hysteresis = <1000>; 3224 type = "critical"; 3225 }; 3226 }; 3227 }; 3228 3229 cpu0123-thermal { 3230 polling-delay-passive = <0>; 3231 polling-delay = <0>; 3232 thermal-sensors = <&tsens0 12>; 3233 3234 trips { 3235 cpu0123_alert0: trip-point0 { 3236 temperature = <90000>; 3237 hysteresis = <2000>; 3238 type = "passive"; 3239 }; 3240 3241 cpu0123_alert1: trip-point1 { 3242 temperature = <95000>; 3243 hysteresis = <2000>; 3244 type = "passive"; 3245 }; 3246 3247 cpu0123_crit: cpu_crit { 3248 temperature = <110000>; 3249 hysteresis = <1000>; 3250 type = "critical"; 3251 }; 3252 }; 3253 }; 3254 3255 modem0-thermal { 3256 polling-delay-passive = <0>; 3257 polling-delay = <0>; 3258 thermal-sensors = <&tsens0 13>; 3259 3260 trips { 3261 trip-point0 { 3262 temperature = <115000>; 3263 hysteresis = <5000>; 3264 type = "passive"; 3265 }; 3266 3267 trip-point1 { 3268 temperature = <125000>; 3269 hysteresis = <1000>; 3270 type = "passive"; 3271 }; 3272 }; 3273 }; 3274 3275 display-thermal { 3276 polling-delay-passive = <0>; 3277 polling-delay = <0>; 3278 thermal-sensors = <&tsens0 14>; 3279 3280 trips { 3281 trip-point0 { 3282 temperature = <115000>; 3283 hysteresis = <5000>; 3284 type = "passive"; 3285 }; 3286 3287 trip-point1 { 3288 temperature = <125000>; 3289 hysteresis = <1000>; 3290 type = "passive"; 3291 }; 3292 }; 3293 }; 3294 3295 gpu-thermal { 3296 polling-delay-passive = <0>; 3297 polling-delay = <0>; 3298 thermal-sensors = <&tsens0 15>; 3299 3300 trips { 3301 trip-point0 { 3302 temperature = <115000>; 3303 hysteresis = <5000>; 3304 type = "passive"; 3305 }; 3306 3307 trip-point1 { 3308 temperature = <125000>; 3309 hysteresis = <1000>; 3310 type = "passive"; 3311 }; 3312 }; 3313 }; 3314 }; 3315 3316 timer { 3317 compatible = "arm,armv8-timer"; 3318 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3319 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3320 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3321 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3322 }; 3323}; 3324