1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm4450-gcc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 clocks{ 21 xo_board: xo-board { 22 compatible = "fixed-clock"; 23 clock-frequency = <76800000>; 24 #clock-cells = <0>; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <32000>; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a55"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 next-level-cache = <&L2_0>; 44 power-domains = <&CPU_PD0>; 45 power-domain-names = "psci"; 46 #cooling-cells = <2>; 47 48 L2_0: l2-cache { 49 compatible = "cache"; 50 cache-level = <2>; 51 cache-unified; 52 next-level-cache = <&L3_0>; 53 54 L3_0: l3-cache { 55 compatible = "cache"; 56 cache-level = <3>; 57 cache-unified; 58 }; 59 }; 60 }; 61 62 CPU1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x0 0x100>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_100>; 68 power-domains = <&CPU_PD0>; 69 power-domain-names = "psci"; 70 #cooling-cells = <2>; 71 72 L2_100: l2-cache { 73 compatible = "cache"; 74 cache-level = <2>; 75 cache-unified; 76 next-level-cache = <&L3_0>; 77 }; 78 }; 79 80 CPU2: cpu@200 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x200>; 84 enable-method = "psci"; 85 next-level-cache = <&L2_200>; 86 power-domains = <&CPU_PD0>; 87 power-domain-names = "psci"; 88 #cooling-cells = <2>; 89 90 L2_200: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&L3_0>; 95 }; 96 }; 97 98 CPU3: cpu@300 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a55"; 101 reg = <0x0 0x300>; 102 enable-method = "psci"; 103 next-level-cache = <&L2_300>; 104 power-domains = <&CPU_PD0>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 108 L2_300: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU4: cpu@400 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x0 0x400>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_400>; 122 power-domains = <&CPU_PD0>; 123 power-domain-names = "psci"; 124 #cooling-cells = <2>; 125 126 L2_400: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU5: cpu@500 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a55"; 137 reg = <0x0 0x500>; 138 enable-method = "psci"; 139 next-level-cache = <&L2_500>; 140 power-domains = <&CPU_PD0>; 141 power-domain-names = "psci"; 142 #cooling-cells = <2>; 143 144 L2_500: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU6: cpu@600 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a78"; 155 reg = <0x0 0x600>; 156 enable-method = "psci"; 157 next-level-cache = <&L2_600>; 158 power-domains = <&CPU_PD0>; 159 power-domain-names = "psci"; 160 #cooling-cells = <2>; 161 162 L2_600: l2-cache { 163 compatible = "cache"; 164 cache-level = <2>; 165 cache-unified; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU7: cpu@700 { 171 device_type = "cpu"; 172 compatible = "arm,cortex-a78"; 173 reg = <0x0 0x700>; 174 enable-method = "psci"; 175 next-level-cache = <&L2_700>; 176 power-domains = <&CPU_PD0>; 177 power-domain-names = "psci"; 178 #cooling-cells = <2>; 179 180 L2_700: l2-cache { 181 compatible = "cache"; 182 cache-level = <2>; 183 cache-unified; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 cpu-map { 189 cluster0 { 190 core0 { 191 cpu = <&CPU0>; 192 }; 193 194 core1 { 195 cpu = <&CPU1>; 196 }; 197 198 core2 { 199 cpu = <&CPU2>; 200 }; 201 202 core3 { 203 cpu = <&CPU3>; 204 }; 205 206 core4 { 207 cpu = <&CPU4>; 208 }; 209 210 core5 { 211 cpu = <&CPU5>; 212 }; 213 214 core6 { 215 cpu = <&CPU6>; 216 }; 217 218 core7 { 219 cpu = <&CPU7>; 220 }; 221 }; 222 }; 223 224 idle-states { 225 entry-method = "psci"; 226 227 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 228 compatible = "arm,idle-state"; 229 arm,psci-suspend-param = <0x40000004>; 230 entry-latency-us = <800>; 231 exit-latency-us = <750>; 232 min-residency-us = <4090>; 233 local-timer-stop; 234 }; 235 236 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 237 compatible = "arm,idle-state"; 238 arm,psci-suspend-param = <0x40000004>; 239 entry-latency-us = <600>; 240 exit-latency-us = <1550>; 241 min-residency-us = <4791>; 242 local-timer-stop; 243 }; 244 }; 245 246 domain-idle-states { 247 CLUSTER_SLEEP_0: cluster-sleep-0 { 248 compatible = "domain-idle-state"; 249 arm,psci-suspend-param = <0x41000044>; 250 entry-latency-us = <1050>; 251 exit-latency-us = <2500>; 252 min-residency-us = <5309>; 253 }; 254 255 CLUSTER_SLEEP_1: cluster-sleep-1 { 256 compatible = "domain-idle-state"; 257 arm,psci-suspend-param = <0x41003344>; 258 entry-latency-us = <1561>; 259 exit-latency-us = <2801>; 260 min-residency-us = <8550>; 261 }; 262 }; 263 }; 264 265 memory@a0000000 { 266 device_type = "memory"; 267 /* We expect the bootloader to fill in the size */ 268 reg = <0x0 0xa0000000 0x0 0x0>; 269 }; 270 271 pmu { 272 compatible = "arm,armv8-pmuv3"; 273 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 274 }; 275 276 psci { 277 compatible = "arm,psci-1.0"; 278 method = "smc"; 279 280 CPU_PD0: power-domain-cpu0 { 281 #power-domain-cells = <0>; 282 power-domains = <&CLUSTER_PD>; 283 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 284 }; 285 286 CPU_PD1: power-domain-cpu1 { 287 #power-domain-cells = <0>; 288 power-domains = <&CLUSTER_PD>; 289 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 290 }; 291 292 CPU_PD2: power-domain-cpu2 { 293 #power-domain-cells = <0>; 294 power-domains = <&CLUSTER_PD>; 295 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 296 }; 297 298 CPU_PD3: power-domain-cpu3 { 299 #power-domain-cells = <0>; 300 power-domains = <&CLUSTER_PD>; 301 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 302 }; 303 304 CPU_PD4: power-domain-cpu4 { 305 #power-domain-cells = <0>; 306 power-domains = <&CLUSTER_PD>; 307 domain-idle-states = <&BIG_CPU_SLEEP_0>; 308 }; 309 310 CPU_PD5: power-domain-cpu5 { 311 #power-domain-cells = <0>; 312 power-domains = <&CLUSTER_PD>; 313 domain-idle-states = <&BIG_CPU_SLEEP_0>; 314 }; 315 316 CPU_PD6: power-domain-cpu6 { 317 #power-domain-cells = <0>; 318 power-domains = <&CLUSTER_PD>; 319 domain-idle-states = <&BIG_CPU_SLEEP_0>; 320 }; 321 322 CPU_PD7: power-domain-cpu7 { 323 #power-domain-cells = <0>; 324 power-domains = <&CLUSTER_PD>; 325 domain-idle-states = <&BIG_CPU_SLEEP_0>; 326 }; 327 328 CLUSTER_PD: power-domain-cpu-cluster0 { 329 #power-domain-cells = <0>; 330 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 331 }; 332 }; 333 334 reserved_memory: reserved-memory { 335 #address-cells = <2>; 336 #size-cells = <2>; 337 ranges; 338 339 aop_cmd_db_mem: cmd-db@80860000 { 340 compatible = "qcom,cmd-db"; 341 reg = <0x0 0x80860000 0x0 0x20000>; 342 no-map; 343 }; 344 }; 345 346 soc: soc@0 { 347 #address-cells = <2>; 348 #size-cells = <2>; 349 ranges = <0 0 0 0 0x10 0>; 350 dma-ranges = <0 0 0 0 0x10 0>; 351 compatible = "simple-bus"; 352 353 gcc: clock-controller@100000 { 354 compatible = "qcom,sm4450-gcc"; 355 reg = <0x0 0x00100000 0x0 0x1f4200>; 356 #clock-cells = <1>; 357 #reset-cells = <1>; 358 #power-domain-cells = <1>; 359 clocks = <&rpmhcc RPMH_CXO_CLK>, 360 <&sleep_clk>, 361 <0>, 362 <0>, 363 <0>, 364 <0>; 365 }; 366 367 qupv3_id_0: geniqup@ac0000 { 368 compatible = "qcom,geni-se-qup"; 369 reg = <0x0 0x00ac0000 0x0 0x2000>; 370 ranges; 371 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 372 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 373 clock-names = "m-ahb", "s-ahb"; 374 #address-cells = <2>; 375 #size-cells = <2>; 376 status = "disabled"; 377 378 uart7: serial@a88000 { 379 compatible = "qcom,geni-debug-uart"; 380 reg = <0x0 0x00a88000 0x0 0x4000>; 381 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 382 clock-names = "se"; 383 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 384 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 385 pinctrl-names = "default"; 386 status = "disabled"; 387 }; 388 }; 389 390 tcsr_mutex: hwlock@1f40000 { 391 compatible = "qcom,tcsr-mutex"; 392 reg = <0x0 0x01f40000 0x0 0x40000>; 393 #hwlock-cells = <1>; 394 }; 395 396 pdc: interrupt-controller@b220000 { 397 compatible = "qcom,sm4450-pdc", "qcom,pdc"; 398 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 399 qcom,pdc-ranges = <0 480 94>, <94 494 31>, 400 <125 63 1>; 401 #interrupt-cells = <2>; 402 interrupt-parent = <&intc>; 403 interrupt-controller; 404 }; 405 406 tlmm: pinctrl@f100000 { 407 compatible = "qcom,sm4450-tlmm"; 408 reg = <0x0 0x0f100000 0x0 0x300000>; 409 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 410 gpio-controller; 411 #gpio-cells = <2>; 412 interrupt-controller; 413 #interrupt-cells = <2>; 414 gpio-ranges = <&tlmm 0 0 137>; 415 wakeup-parent = <&pdc>; 416 417 qup_uart7_rx: qup-uart7-rx-state { 418 pins = "gpio23"; 419 function = "qup1_se2_l2"; 420 drive-strength = <2>; 421 bias-disable; 422 }; 423 424 qup_uart7_tx: qup-uart7-tx-state { 425 pins = "gpio22"; 426 function = "qup1_se2_l2"; 427 drive-strength = <2>; 428 bias-disable; 429 }; 430 }; 431 432 intc: interrupt-controller@17200000 { 433 compatible = "arm,gic-v3"; 434 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ 435 <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */ 436 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 437 #interrupt-cells = <3>; 438 interrupt-controller; 439 #redistributor-regions = <1>; 440 redistributor-stride = <0x0 0x20000>; 441 }; 442 443 timer@17420000 { 444 compatible = "arm,armv7-timer-mem"; 445 reg = <0x0 0x17420000 0x0 0x1000>; 446 ranges = <0 0 0 0x20000000>; 447 #address-cells = <1>; 448 #size-cells = <1>; 449 450 frame@17421000 { 451 reg = <0x17421000 0x1000>, 452 <0x17422000 0x1000>; 453 frame-number = <0>; 454 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 456 }; 457 458 frame@17423000 { 459 reg = <0x17423000 0x1000>; 460 frame-number = <1>; 461 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 462 status = "disabled"; 463 }; 464 465 frame@17425000 { 466 reg = <0x17425000 0x1000>; 467 frame-number = <2>; 468 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 469 status = "disabled"; 470 }; 471 472 frame@17427000 { 473 reg = <0x17427000 0x1000>; 474 frame-number = <3>; 475 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 476 status = "disabled"; 477 }; 478 479 frame@17429000 { 480 reg = <0x17429000 0x1000>; 481 frame-number = <4>; 482 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 483 status = "disabled"; 484 }; 485 486 frame@1742b000 { 487 reg = <0x1742b000 0x1000>; 488 frame-number = <5>; 489 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 490 status = "disabled"; 491 }; 492 493 frame@1742d000 { 494 reg = <0x1742d000 0x1000>; 495 frame-number = <6>; 496 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 497 status = "disabled"; 498 }; 499 }; 500 501 apps_rsc: rsc@17a00000 { 502 compatible = "qcom,rpmh-rsc"; 503 reg = <0x0 0x17a00000 0x0 0x10000>, 504 <0x0 0x17a10000 0x0 0x10000>, 505 <0x0 0x17a20000 0x0 0x10000>; 506 reg-names = "drv-0", "drv-1", "drv-2"; 507 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 510 label = "apps_rsc"; 511 qcom,tcs-offset = <0xd00>; 512 qcom,drv-id = <2>; 513 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 514 <WAKE_TCS 3>, <CONTROL_TCS 0>; 515 power-domains = <&CLUSTER_PD>; 516 517 apps_bcm_voter: bcm-voter { 518 compatible = "qcom,bcm-voter"; 519 }; 520 521 rpmhcc: clock-controller { 522 compatible = "qcom,sm4450-rpmh-clk"; 523 #clock-cells = <1>; 524 clocks = <&xo_board>; 525 clock-names = "xo"; 526 }; 527 }; 528 529 }; 530 531 timer { 532 compatible = "arm,armv8-timer"; 533 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 534 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 535 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 536 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 537 }; 538}; 539