1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sdm845.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qusb2.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/clock/qcom,gcc-sdm845.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 chosen { }; 69 70 memory@80000000 { 71 device_type = "memory"; 72 /* We expect the bootloader to fill in the size */ 73 reg = <0 0x80000000 0 0>; 74 }; 75 76 reserved-memory { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges; 80 81 hyp_mem: memory@85700000 { 82 reg = <0 0x85700000 0 0x600000>; 83 no-map; 84 }; 85 86 xbl_mem: memory@85e00000 { 87 reg = <0 0x85e00000 0 0x100000>; 88 no-map; 89 }; 90 91 aop_mem: memory@85fc0000 { 92 reg = <0 0x85fc0000 0 0x20000>; 93 no-map; 94 }; 95 96 aop_cmd_db_mem: memory@85fe0000 { 97 compatible = "qcom,cmd-db"; 98 reg = <0x0 0x85fe0000 0 0x20000>; 99 no-map; 100 }; 101 102 smem_mem: memory@86000000 { 103 reg = <0x0 0x86000000 0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@86200000 { 108 reg = <0 0x86200000 0 0x2d00000>; 109 no-map; 110 }; 111 112 rmtfs_mem: memory@88f00000 { 113 compatible = "qcom,rmtfs-mem"; 114 reg = <0 0x88f00000 0 0x200000>; 115 no-map; 116 117 qcom,client-id = <1>; 118 qcom,vmid = <15>; 119 }; 120 121 qseecom_mem: memory@8ab00000 { 122 reg = <0 0x8ab00000 0 0x1400000>; 123 no-map; 124 }; 125 126 camera_mem: memory@8bf00000 { 127 reg = <0 0x8bf00000 0 0x500000>; 128 no-map; 129 }; 130 131 ipa_fw_mem: memory@8c400000 { 132 reg = <0 0x8c400000 0 0x10000>; 133 no-map; 134 }; 135 136 ipa_gsi_mem: memory@8c410000 { 137 reg = <0 0x8c410000 0 0x5000>; 138 no-map; 139 }; 140 141 gpu_mem: memory@8c415000 { 142 reg = <0 0x8c415000 0 0x2000>; 143 no-map; 144 }; 145 146 adsp_mem: memory@8c500000 { 147 reg = <0 0x8c500000 0 0x1a00000>; 148 no-map; 149 }; 150 151 wlan_msa_mem: memory@8df00000 { 152 reg = <0 0x8df00000 0 0x100000>; 153 no-map; 154 }; 155 156 mpss_region: memory@8e000000 { 157 reg = <0 0x8e000000 0 0x7800000>; 158 no-map; 159 }; 160 161 venus_mem: memory@95800000 { 162 reg = <0 0x95800000 0 0x500000>; 163 no-map; 164 }; 165 166 cdsp_mem: memory@95d00000 { 167 reg = <0 0x95d00000 0 0x800000>; 168 no-map; 169 }; 170 171 mba_region: memory@96500000 { 172 reg = <0 0x96500000 0 0x200000>; 173 no-map; 174 }; 175 176 slpi_mem: memory@96700000 { 177 reg = <0 0x96700000 0 0x1400000>; 178 no-map; 179 }; 180 181 spss_mem: memory@97b00000 { 182 reg = <0 0x97b00000 0 0x100000>; 183 no-map; 184 }; 185 }; 186 187 cpus { 188 #address-cells = <2>; 189 #size-cells = <0>; 190 191 CPU0: cpu@0 { 192 device_type = "cpu"; 193 compatible = "qcom,kryo385"; 194 reg = <0x0 0x0>; 195 enable-method = "psci"; 196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 197 &LITTLE_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 capacity-dmips-mhz = <607>; 200 dynamic-power-coefficient = <100>; 201 qcom,freq-domain = <&cpufreq_hw 0>; 202 operating-points-v2 = <&cpu0_opp_table>; 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 #cooling-cells = <2>; 206 next-level-cache = <&L2_0>; 207 L2_0: l2-cache { 208 compatible = "cache"; 209 next-level-cache = <&L3_0>; 210 L3_0: l3-cache { 211 compatible = "cache"; 212 }; 213 }; 214 }; 215 216 CPU1: cpu@100 { 217 device_type = "cpu"; 218 compatible = "qcom,kryo385"; 219 reg = <0x0 0x100>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 capacity-dmips-mhz = <607>; 225 dynamic-power-coefficient = <100>; 226 qcom,freq-domain = <&cpufreq_hw 0>; 227 operating-points-v2 = <&cpu0_opp_table>; 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 #cooling-cells = <2>; 231 next-level-cache = <&L2_100>; 232 L2_100: l2-cache { 233 compatible = "cache"; 234 next-level-cache = <&L3_0>; 235 }; 236 }; 237 238 CPU2: cpu@200 { 239 device_type = "cpu"; 240 compatible = "qcom,kryo385"; 241 reg = <0x0 0x200>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 capacity-dmips-mhz = <607>; 247 dynamic-power-coefficient = <100>; 248 qcom,freq-domain = <&cpufreq_hw 0>; 249 operating-points-v2 = <&cpu0_opp_table>; 250 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 252 #cooling-cells = <2>; 253 next-level-cache = <&L2_200>; 254 L2_200: l2-cache { 255 compatible = "cache"; 256 next-level-cache = <&L3_0>; 257 }; 258 }; 259 260 CPU3: cpu@300 { 261 device_type = "cpu"; 262 compatible = "qcom,kryo385"; 263 reg = <0x0 0x300>; 264 enable-method = "psci"; 265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 266 &LITTLE_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 capacity-dmips-mhz = <607>; 269 dynamic-power-coefficient = <100>; 270 qcom,freq-domain = <&cpufreq_hw 0>; 271 operating-points-v2 = <&cpu0_opp_table>; 272 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 274 #cooling-cells = <2>; 275 next-level-cache = <&L2_300>; 276 L2_300: l2-cache { 277 compatible = "cache"; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 CPU4: cpu@400 { 283 device_type = "cpu"; 284 compatible = "qcom,kryo385"; 285 reg = <0x0 0x400>; 286 enable-method = "psci"; 287 capacity-dmips-mhz = <1024>; 288 cpu-idle-states = <&BIG_CPU_SLEEP_0 289 &BIG_CPU_SLEEP_1 290 &CLUSTER_SLEEP_0>; 291 dynamic-power-coefficient = <396>; 292 qcom,freq-domain = <&cpufreq_hw 1>; 293 operating-points-v2 = <&cpu4_opp_table>; 294 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 296 #cooling-cells = <2>; 297 next-level-cache = <&L2_400>; 298 L2_400: l2-cache { 299 compatible = "cache"; 300 next-level-cache = <&L3_0>; 301 }; 302 }; 303 304 CPU5: cpu@500 { 305 device_type = "cpu"; 306 compatible = "qcom,kryo385"; 307 reg = <0x0 0x500>; 308 enable-method = "psci"; 309 capacity-dmips-mhz = <1024>; 310 cpu-idle-states = <&BIG_CPU_SLEEP_0 311 &BIG_CPU_SLEEP_1 312 &CLUSTER_SLEEP_0>; 313 dynamic-power-coefficient = <396>; 314 qcom,freq-domain = <&cpufreq_hw 1>; 315 operating-points-v2 = <&cpu4_opp_table>; 316 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 317 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 318 #cooling-cells = <2>; 319 next-level-cache = <&L2_500>; 320 L2_500: l2-cache { 321 compatible = "cache"; 322 next-level-cache = <&L3_0>; 323 }; 324 }; 325 326 CPU6: cpu@600 { 327 device_type = "cpu"; 328 compatible = "qcom,kryo385"; 329 reg = <0x0 0x600>; 330 enable-method = "psci"; 331 capacity-dmips-mhz = <1024>; 332 cpu-idle-states = <&BIG_CPU_SLEEP_0 333 &BIG_CPU_SLEEP_1 334 &CLUSTER_SLEEP_0>; 335 dynamic-power-coefficient = <396>; 336 qcom,freq-domain = <&cpufreq_hw 1>; 337 operating-points-v2 = <&cpu4_opp_table>; 338 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 339 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 340 #cooling-cells = <2>; 341 next-level-cache = <&L2_600>; 342 L2_600: l2-cache { 343 compatible = "cache"; 344 next-level-cache = <&L3_0>; 345 }; 346 }; 347 348 CPU7: cpu@700 { 349 device_type = "cpu"; 350 compatible = "qcom,kryo385"; 351 reg = <0x0 0x700>; 352 enable-method = "psci"; 353 capacity-dmips-mhz = <1024>; 354 cpu-idle-states = <&BIG_CPU_SLEEP_0 355 &BIG_CPU_SLEEP_1 356 &CLUSTER_SLEEP_0>; 357 dynamic-power-coefficient = <396>; 358 qcom,freq-domain = <&cpufreq_hw 1>; 359 operating-points-v2 = <&cpu4_opp_table>; 360 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 361 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 362 #cooling-cells = <2>; 363 next-level-cache = <&L2_700>; 364 L2_700: l2-cache { 365 compatible = "cache"; 366 next-level-cache = <&L3_0>; 367 }; 368 }; 369 370 cpu-map { 371 cluster0 { 372 core0 { 373 cpu = <&CPU0>; 374 }; 375 376 core1 { 377 cpu = <&CPU1>; 378 }; 379 380 core2 { 381 cpu = <&CPU2>; 382 }; 383 384 core3 { 385 cpu = <&CPU3>; 386 }; 387 388 core4 { 389 cpu = <&CPU4>; 390 }; 391 392 core5 { 393 cpu = <&CPU5>; 394 }; 395 396 core6 { 397 cpu = <&CPU6>; 398 }; 399 400 core7 { 401 cpu = <&CPU7>; 402 }; 403 }; 404 }; 405 406 idle-states { 407 entry-method = "psci"; 408 409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "little-power-down"; 412 arm,psci-suspend-param = <0x40000003>; 413 entry-latency-us = <350>; 414 exit-latency-us = <461>; 415 min-residency-us = <1890>; 416 local-timer-stop; 417 }; 418 419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "little-rail-power-down"; 422 arm,psci-suspend-param = <0x40000004>; 423 entry-latency-us = <360>; 424 exit-latency-us = <531>; 425 min-residency-us = <3934>; 426 local-timer-stop; 427 }; 428 429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 430 compatible = "arm,idle-state"; 431 idle-state-name = "big-power-down"; 432 arm,psci-suspend-param = <0x40000003>; 433 entry-latency-us = <264>; 434 exit-latency-us = <621>; 435 min-residency-us = <952>; 436 local-timer-stop; 437 }; 438 439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 440 compatible = "arm,idle-state"; 441 idle-state-name = "big-rail-power-down"; 442 arm,psci-suspend-param = <0x40000004>; 443 entry-latency-us = <702>; 444 exit-latency-us = <1061>; 445 min-residency-us = <4488>; 446 local-timer-stop; 447 }; 448 449 CLUSTER_SLEEP_0: cluster-sleep-0 { 450 compatible = "arm,idle-state"; 451 idle-state-name = "cluster-power-down"; 452 arm,psci-suspend-param = <0x400000F4>; 453 entry-latency-us = <3263>; 454 exit-latency-us = <6562>; 455 min-residency-us = <9987>; 456 local-timer-stop; 457 }; 458 }; 459 }; 460 461 cpu0_opp_table: cpu0_opp_table { 462 compatible = "operating-points-v2"; 463 opp-shared; 464 465 cpu0_opp1: opp-300000000 { 466 opp-hz = /bits/ 64 <300000000>; 467 opp-peak-kBps = <800000 4800000>; 468 }; 469 470 cpu0_opp2: opp-403200000 { 471 opp-hz = /bits/ 64 <403200000>; 472 opp-peak-kBps = <800000 4800000>; 473 }; 474 475 cpu0_opp3: opp-480000000 { 476 opp-hz = /bits/ 64 <480000000>; 477 opp-peak-kBps = <800000 6451200>; 478 }; 479 480 cpu0_opp4: opp-576000000 { 481 opp-hz = /bits/ 64 <576000000>; 482 opp-peak-kBps = <800000 6451200>; 483 }; 484 485 cpu0_opp5: opp-652800000 { 486 opp-hz = /bits/ 64 <652800000>; 487 opp-peak-kBps = <800000 7680000>; 488 }; 489 490 cpu0_opp6: opp-748800000 { 491 opp-hz = /bits/ 64 <748800000>; 492 opp-peak-kBps = <1804000 9216000>; 493 }; 494 495 cpu0_opp7: opp-825600000 { 496 opp-hz = /bits/ 64 <825600000>; 497 opp-peak-kBps = <1804000 9216000>; 498 }; 499 500 cpu0_opp8: opp-902400000 { 501 opp-hz = /bits/ 64 <902400000>; 502 opp-peak-kBps = <1804000 10444800>; 503 }; 504 505 cpu0_opp9: opp-979200000 { 506 opp-hz = /bits/ 64 <979200000>; 507 opp-peak-kBps = <1804000 11980800>; 508 }; 509 510 cpu0_opp10: opp-1056000000 { 511 opp-hz = /bits/ 64 <1056000000>; 512 opp-peak-kBps = <1804000 11980800>; 513 }; 514 515 cpu0_opp11: opp-1132800000 { 516 opp-hz = /bits/ 64 <1132800000>; 517 opp-peak-kBps = <2188000 13516800>; 518 }; 519 520 cpu0_opp12: opp-1228800000 { 521 opp-hz = /bits/ 64 <1228800000>; 522 opp-peak-kBps = <2188000 15052800>; 523 }; 524 525 cpu0_opp13: opp-1324800000 { 526 opp-hz = /bits/ 64 <1324800000>; 527 opp-peak-kBps = <2188000 16588800>; 528 }; 529 530 cpu0_opp14: opp-1420800000 { 531 opp-hz = /bits/ 64 <1420800000>; 532 opp-peak-kBps = <3072000 18124800>; 533 }; 534 535 cpu0_opp15: opp-1516800000 { 536 opp-hz = /bits/ 64 <1516800000>; 537 opp-peak-kBps = <3072000 19353600>; 538 }; 539 540 cpu0_opp16: opp-1612800000 { 541 opp-hz = /bits/ 64 <1612800000>; 542 opp-peak-kBps = <4068000 19353600>; 543 }; 544 545 cpu0_opp17: opp-1689600000 { 546 opp-hz = /bits/ 64 <1689600000>; 547 opp-peak-kBps = <4068000 20889600>; 548 }; 549 550 cpu0_opp18: opp-1766400000 { 551 opp-hz = /bits/ 64 <1766400000>; 552 opp-peak-kBps = <4068000 22425600>; 553 }; 554 }; 555 556 cpu4_opp_table: cpu4_opp_table { 557 compatible = "operating-points-v2"; 558 opp-shared; 559 560 cpu4_opp1: opp-300000000 { 561 opp-hz = /bits/ 64 <300000000>; 562 opp-peak-kBps = <800000 4800000>; 563 }; 564 565 cpu4_opp2: opp-403200000 { 566 opp-hz = /bits/ 64 <403200000>; 567 opp-peak-kBps = <800000 4800000>; 568 }; 569 570 cpu4_opp3: opp-480000000 { 571 opp-hz = /bits/ 64 <480000000>; 572 opp-peak-kBps = <1804000 4800000>; 573 }; 574 575 cpu4_opp4: opp-576000000 { 576 opp-hz = /bits/ 64 <576000000>; 577 opp-peak-kBps = <1804000 4800000>; 578 }; 579 580 cpu4_opp5: opp-652800000 { 581 opp-hz = /bits/ 64 <652800000>; 582 opp-peak-kBps = <1804000 4800000>; 583 }; 584 585 cpu4_opp6: opp-748800000 { 586 opp-hz = /bits/ 64 <748800000>; 587 opp-peak-kBps = <1804000 4800000>; 588 }; 589 590 cpu4_opp7: opp-825600000 { 591 opp-hz = /bits/ 64 <825600000>; 592 opp-peak-kBps = <2188000 9216000>; 593 }; 594 595 cpu4_opp8: opp-902400000 { 596 opp-hz = /bits/ 64 <902400000>; 597 opp-peak-kBps = <2188000 9216000>; 598 }; 599 600 cpu4_opp9: opp-979200000 { 601 opp-hz = /bits/ 64 <979200000>; 602 opp-peak-kBps = <2188000 9216000>; 603 }; 604 605 cpu4_opp10: opp-1056000000 { 606 opp-hz = /bits/ 64 <1056000000>; 607 opp-peak-kBps = <3072000 9216000>; 608 }; 609 610 cpu4_opp11: opp-1132800000 { 611 opp-hz = /bits/ 64 <1132800000>; 612 opp-peak-kBps = <3072000 11980800>; 613 }; 614 615 cpu4_opp12: opp-1209600000 { 616 opp-hz = /bits/ 64 <1209600000>; 617 opp-peak-kBps = <4068000 11980800>; 618 }; 619 620 cpu4_opp13: opp-1286400000 { 621 opp-hz = /bits/ 64 <1286400000>; 622 opp-peak-kBps = <4068000 11980800>; 623 }; 624 625 cpu4_opp14: opp-1363200000 { 626 opp-hz = /bits/ 64 <1363200000>; 627 opp-peak-kBps = <4068000 15052800>; 628 }; 629 630 cpu4_opp15: opp-1459200000 { 631 opp-hz = /bits/ 64 <1459200000>; 632 opp-peak-kBps = <4068000 15052800>; 633 }; 634 635 cpu4_opp16: opp-1536000000 { 636 opp-hz = /bits/ 64 <1536000000>; 637 opp-peak-kBps = <5412000 15052800>; 638 }; 639 640 cpu4_opp17: opp-1612800000 { 641 opp-hz = /bits/ 64 <1612800000>; 642 opp-peak-kBps = <5412000 15052800>; 643 }; 644 645 cpu4_opp18: opp-1689600000 { 646 opp-hz = /bits/ 64 <1689600000>; 647 opp-peak-kBps = <5412000 19353600>; 648 }; 649 650 cpu4_opp19: opp-1766400000 { 651 opp-hz = /bits/ 64 <1766400000>; 652 opp-peak-kBps = <6220000 19353600>; 653 }; 654 655 cpu4_opp20: opp-1843200000 { 656 opp-hz = /bits/ 64 <1843200000>; 657 opp-peak-kBps = <6220000 19353600>; 658 }; 659 660 cpu4_opp21: opp-1920000000 { 661 opp-hz = /bits/ 64 <1920000000>; 662 opp-peak-kBps = <7216000 19353600>; 663 }; 664 665 cpu4_opp22: opp-1996800000 { 666 opp-hz = /bits/ 64 <1996800000>; 667 opp-peak-kBps = <7216000 20889600>; 668 }; 669 670 cpu4_opp23: opp-2092800000 { 671 opp-hz = /bits/ 64 <2092800000>; 672 opp-peak-kBps = <7216000 20889600>; 673 }; 674 675 cpu4_opp24: opp-2169600000 { 676 opp-hz = /bits/ 64 <2169600000>; 677 opp-peak-kBps = <7216000 20889600>; 678 }; 679 680 cpu4_opp25: opp-2246400000 { 681 opp-hz = /bits/ 64 <2246400000>; 682 opp-peak-kBps = <7216000 20889600>; 683 }; 684 685 cpu4_opp26: opp-2323200000 { 686 opp-hz = /bits/ 64 <2323200000>; 687 opp-peak-kBps = <7216000 20889600>; 688 }; 689 690 cpu4_opp27: opp-2400000000 { 691 opp-hz = /bits/ 64 <2400000000>; 692 opp-peak-kBps = <7216000 22425600>; 693 }; 694 695 cpu4_opp28: opp-2476800000 { 696 opp-hz = /bits/ 64 <2476800000>; 697 opp-peak-kBps = <7216000 22425600>; 698 }; 699 700 cpu4_opp29: opp-2553600000 { 701 opp-hz = /bits/ 64 <2553600000>; 702 opp-peak-kBps = <7216000 22425600>; 703 }; 704 705 cpu4_opp30: opp-2649600000 { 706 opp-hz = /bits/ 64 <2649600000>; 707 opp-peak-kBps = <7216000 22425600>; 708 }; 709 710 cpu4_opp31: opp-2745600000 { 711 opp-hz = /bits/ 64 <2745600000>; 712 opp-peak-kBps = <7216000 25497600>; 713 }; 714 715 cpu4_opp32: opp-2803200000 { 716 opp-hz = /bits/ 64 <2803200000>; 717 opp-peak-kBps = <7216000 25497600>; 718 }; 719 }; 720 721 pmu { 722 compatible = "arm,armv8-pmuv3"; 723 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 724 }; 725 726 timer { 727 compatible = "arm,armv8-timer"; 728 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 729 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 730 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 732 }; 733 734 clocks { 735 xo_board: xo-board { 736 compatible = "fixed-clock"; 737 #clock-cells = <0>; 738 clock-frequency = <38400000>; 739 clock-output-names = "xo_board"; 740 }; 741 742 sleep_clk: sleep-clk { 743 compatible = "fixed-clock"; 744 #clock-cells = <0>; 745 clock-frequency = <32764>; 746 }; 747 }; 748 749 firmware { 750 scm { 751 compatible = "qcom,scm-sdm845", "qcom,scm"; 752 }; 753 }; 754 755 adsp_pas: remoteproc-adsp { 756 compatible = "qcom,sdm845-adsp-pas"; 757 758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 760 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 761 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 762 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 763 interrupt-names = "wdog", "fatal", "ready", 764 "handover", "stop-ack"; 765 766 clocks = <&rpmhcc RPMH_CXO_CLK>; 767 clock-names = "xo"; 768 769 memory-region = <&adsp_mem>; 770 771 qcom,smem-states = <&adsp_smp2p_out 0>; 772 qcom,smem-state-names = "stop"; 773 774 status = "disabled"; 775 776 glink-edge { 777 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 778 label = "lpass"; 779 qcom,remote-pid = <2>; 780 mboxes = <&apss_shared 8>; 781 782 apr { 783 compatible = "qcom,apr-v2"; 784 qcom,glink-channels = "apr_audio_svc"; 785 qcom,apr-domain = <APR_DOMAIN_ADSP>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 qcom,intents = <512 20>; 789 790 apr-service@3 { 791 reg = <APR_SVC_ADSP_CORE>; 792 compatible = "qcom,q6core"; 793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 794 }; 795 796 q6afe: apr-service@4 { 797 compatible = "qcom,q6afe"; 798 reg = <APR_SVC_AFE>; 799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 800 q6afedai: dais { 801 compatible = "qcom,q6afe-dais"; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 #sound-dai-cells = <1>; 805 }; 806 }; 807 808 q6asm: apr-service@7 { 809 compatible = "qcom,q6asm"; 810 reg = <APR_SVC_ASM>; 811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 812 q6asmdai: dais { 813 compatible = "qcom,q6asm-dais"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 #sound-dai-cells = <1>; 817 iommus = <&apps_smmu 0x1821 0x0>; 818 }; 819 }; 820 821 q6adm: apr-service@8 { 822 compatible = "qcom,q6adm"; 823 reg = <APR_SVC_ADM>; 824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 825 q6routing: routing { 826 compatible = "qcom,q6adm-routing"; 827 #sound-dai-cells = <0>; 828 }; 829 }; 830 }; 831 832 fastrpc { 833 compatible = "qcom,fastrpc"; 834 qcom,glink-channels = "fastrpcglink-apps-dsp"; 835 label = "adsp"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 compute-cb@3 { 840 compatible = "qcom,fastrpc-compute-cb"; 841 reg = <3>; 842 iommus = <&apps_smmu 0x1823 0x0>; 843 }; 844 845 compute-cb@4 { 846 compatible = "qcom,fastrpc-compute-cb"; 847 reg = <4>; 848 iommus = <&apps_smmu 0x1824 0x0>; 849 }; 850 }; 851 }; 852 }; 853 854 cdsp_pas: remoteproc-cdsp { 855 compatible = "qcom,sdm845-cdsp-pas"; 856 857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 859 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 860 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 861 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 862 interrupt-names = "wdog", "fatal", "ready", 863 "handover", "stop-ack"; 864 865 clocks = <&rpmhcc RPMH_CXO_CLK>; 866 clock-names = "xo"; 867 868 memory-region = <&cdsp_mem>; 869 870 qcom,smem-states = <&cdsp_smp2p_out 0>; 871 qcom,smem-state-names = "stop"; 872 873 status = "disabled"; 874 875 glink-edge { 876 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 877 label = "turing"; 878 qcom,remote-pid = <5>; 879 mboxes = <&apss_shared 4>; 880 fastrpc { 881 compatible = "qcom,fastrpc"; 882 qcom,glink-channels = "fastrpcglink-apps-dsp"; 883 label = "cdsp"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 887 compute-cb@1 { 888 compatible = "qcom,fastrpc-compute-cb"; 889 reg = <1>; 890 iommus = <&apps_smmu 0x1401 0x30>; 891 }; 892 893 compute-cb@2 { 894 compatible = "qcom,fastrpc-compute-cb"; 895 reg = <2>; 896 iommus = <&apps_smmu 0x1402 0x30>; 897 }; 898 899 compute-cb@3 { 900 compatible = "qcom,fastrpc-compute-cb"; 901 reg = <3>; 902 iommus = <&apps_smmu 0x1403 0x30>; 903 }; 904 905 compute-cb@4 { 906 compatible = "qcom,fastrpc-compute-cb"; 907 reg = <4>; 908 iommus = <&apps_smmu 0x1404 0x30>; 909 }; 910 911 compute-cb@5 { 912 compatible = "qcom,fastrpc-compute-cb"; 913 reg = <5>; 914 iommus = <&apps_smmu 0x1405 0x30>; 915 }; 916 917 compute-cb@6 { 918 compatible = "qcom,fastrpc-compute-cb"; 919 reg = <6>; 920 iommus = <&apps_smmu 0x1406 0x30>; 921 }; 922 923 compute-cb@7 { 924 compatible = "qcom,fastrpc-compute-cb"; 925 reg = <7>; 926 iommus = <&apps_smmu 0x1407 0x30>; 927 }; 928 929 compute-cb@8 { 930 compatible = "qcom,fastrpc-compute-cb"; 931 reg = <8>; 932 iommus = <&apps_smmu 0x1408 0x30>; 933 }; 934 }; 935 }; 936 }; 937 938 tcsr_mutex: hwlock { 939 compatible = "qcom,tcsr-mutex"; 940 syscon = <&tcsr_mutex_regs 0 0x1000>; 941 #hwlock-cells = <1>; 942 }; 943 944 smem { 945 compatible = "qcom,smem"; 946 memory-region = <&smem_mem>; 947 hwlocks = <&tcsr_mutex 3>; 948 }; 949 950 smp2p-cdsp { 951 compatible = "qcom,smp2p"; 952 qcom,smem = <94>, <432>; 953 954 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 955 956 mboxes = <&apss_shared 6>; 957 958 qcom,local-pid = <0>; 959 qcom,remote-pid = <5>; 960 961 cdsp_smp2p_out: master-kernel { 962 qcom,entry-name = "master-kernel"; 963 #qcom,smem-state-cells = <1>; 964 }; 965 966 cdsp_smp2p_in: slave-kernel { 967 qcom,entry-name = "slave-kernel"; 968 969 interrupt-controller; 970 #interrupt-cells = <2>; 971 }; 972 }; 973 974 smp2p-lpass { 975 compatible = "qcom,smp2p"; 976 qcom,smem = <443>, <429>; 977 978 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 979 980 mboxes = <&apss_shared 10>; 981 982 qcom,local-pid = <0>; 983 qcom,remote-pid = <2>; 984 985 adsp_smp2p_out: master-kernel { 986 qcom,entry-name = "master-kernel"; 987 #qcom,smem-state-cells = <1>; 988 }; 989 990 adsp_smp2p_in: slave-kernel { 991 qcom,entry-name = "slave-kernel"; 992 993 interrupt-controller; 994 #interrupt-cells = <2>; 995 }; 996 }; 997 998 smp2p-mpss { 999 compatible = "qcom,smp2p"; 1000 qcom,smem = <435>, <428>; 1001 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1002 mboxes = <&apss_shared 14>; 1003 qcom,local-pid = <0>; 1004 qcom,remote-pid = <1>; 1005 1006 modem_smp2p_out: master-kernel { 1007 qcom,entry-name = "master-kernel"; 1008 #qcom,smem-state-cells = <1>; 1009 }; 1010 1011 modem_smp2p_in: slave-kernel { 1012 qcom,entry-name = "slave-kernel"; 1013 interrupt-controller; 1014 #interrupt-cells = <2>; 1015 }; 1016 1017 ipa_smp2p_out: ipa-ap-to-modem { 1018 qcom,entry-name = "ipa"; 1019 #qcom,smem-state-cells = <1>; 1020 }; 1021 1022 ipa_smp2p_in: ipa-modem-to-ap { 1023 qcom,entry-name = "ipa"; 1024 interrupt-controller; 1025 #interrupt-cells = <2>; 1026 }; 1027 }; 1028 1029 smp2p-slpi { 1030 compatible = "qcom,smp2p"; 1031 qcom,smem = <481>, <430>; 1032 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1033 mboxes = <&apss_shared 26>; 1034 qcom,local-pid = <0>; 1035 qcom,remote-pid = <3>; 1036 1037 slpi_smp2p_out: master-kernel { 1038 qcom,entry-name = "master-kernel"; 1039 #qcom,smem-state-cells = <1>; 1040 }; 1041 1042 slpi_smp2p_in: slave-kernel { 1043 qcom,entry-name = "slave-kernel"; 1044 interrupt-controller; 1045 #interrupt-cells = <2>; 1046 }; 1047 }; 1048 1049 psci { 1050 compatible = "arm,psci-1.0"; 1051 method = "smc"; 1052 }; 1053 1054 soc: soc@0 { 1055 #address-cells = <2>; 1056 #size-cells = <2>; 1057 ranges = <0 0 0 0 0x10 0>; 1058 dma-ranges = <0 0 0 0 0x10 0>; 1059 compatible = "simple-bus"; 1060 1061 gcc: clock-controller@100000 { 1062 compatible = "qcom,gcc-sdm845"; 1063 reg = <0 0x00100000 0 0x1f0000>; 1064 #clock-cells = <1>; 1065 #reset-cells = <1>; 1066 #power-domain-cells = <1>; 1067 }; 1068 1069 qfprom@784000 { 1070 compatible = "qcom,qfprom"; 1071 reg = <0 0x00784000 0 0x8ff>; 1072 #address-cells = <1>; 1073 #size-cells = <1>; 1074 1075 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1076 reg = <0x1eb 0x1>; 1077 bits = <1 4>; 1078 }; 1079 1080 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1081 reg = <0x1eb 0x2>; 1082 bits = <6 4>; 1083 }; 1084 }; 1085 1086 rng: rng@793000 { 1087 compatible = "qcom,prng-ee"; 1088 reg = <0 0x00793000 0 0x1000>; 1089 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1090 clock-names = "core"; 1091 }; 1092 1093 qup_opp_table: qup-opp-table { 1094 compatible = "operating-points-v2"; 1095 1096 opp-50000000 { 1097 opp-hz = /bits/ 64 <50000000>; 1098 required-opps = <&rpmhpd_opp_min_svs>; 1099 }; 1100 1101 opp-75000000 { 1102 opp-hz = /bits/ 64 <75000000>; 1103 required-opps = <&rpmhpd_opp_low_svs>; 1104 }; 1105 1106 opp-100000000 { 1107 opp-hz = /bits/ 64 <100000000>; 1108 required-opps = <&rpmhpd_opp_svs>; 1109 }; 1110 1111 opp-128000000 { 1112 opp-hz = /bits/ 64 <128000000>; 1113 required-opps = <&rpmhpd_opp_nom>; 1114 }; 1115 }; 1116 1117 qupv3_id_0: geniqup@8c0000 { 1118 compatible = "qcom,geni-se-qup"; 1119 reg = <0 0x008c0000 0 0x6000>; 1120 clock-names = "m-ahb", "s-ahb"; 1121 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1122 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1123 #address-cells = <2>; 1124 #size-cells = <2>; 1125 ranges; 1126 status = "disabled"; 1127 1128 i2c0: i2c@880000 { 1129 compatible = "qcom,geni-i2c"; 1130 reg = <0 0x00880000 0 0x4000>; 1131 clock-names = "se"; 1132 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1133 pinctrl-names = "default"; 1134 pinctrl-0 = <&qup_i2c0_default>; 1135 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 power-domains = <&rpmhpd SDM845_CX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 status = "disabled"; 1141 }; 1142 1143 spi0: spi@880000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0 0x00880000 0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&qup_spi0_default>; 1150 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 uart0: serial@880000 { 1157 compatible = "qcom,geni-uart"; 1158 reg = <0 0x00880000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_uart0_default>; 1163 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1164 power-domains = <&rpmhpd SDM845_CX>; 1165 operating-points-v2 = <&qup_opp_table>; 1166 status = "disabled"; 1167 }; 1168 1169 i2c1: i2c@884000 { 1170 compatible = "qcom,geni-i2c"; 1171 reg = <0 0x00884000 0 0x4000>; 1172 clock-names = "se"; 1173 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_i2c1_default>; 1176 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 power-domains = <&rpmhpd SDM845_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 status = "disabled"; 1182 }; 1183 1184 spi1: spi@884000 { 1185 compatible = "qcom,geni-spi"; 1186 reg = <0 0x00884000 0 0x4000>; 1187 clock-names = "se"; 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_spi1_default>; 1191 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 uart1: serial@884000 { 1198 compatible = "qcom,geni-uart"; 1199 reg = <0 0x00884000 0 0x4000>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1202 pinctrl-names = "default"; 1203 pinctrl-0 = <&qup_uart1_default>; 1204 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1205 power-domains = <&rpmhpd SDM845_CX>; 1206 operating-points-v2 = <&qup_opp_table>; 1207 status = "disabled"; 1208 }; 1209 1210 i2c2: i2c@888000 { 1211 compatible = "qcom,geni-i2c"; 1212 reg = <0 0x00888000 0 0x4000>; 1213 clock-names = "se"; 1214 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&qup_i2c2_default>; 1217 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 power-domains = <&rpmhpd SDM845_CX>; 1221 operating-points-v2 = <&qup_opp_table>; 1222 status = "disabled"; 1223 }; 1224 1225 spi2: spi@888000 { 1226 compatible = "qcom,geni-spi"; 1227 reg = <0 0x00888000 0 0x4000>; 1228 clock-names = "se"; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&qup_spi2_default>; 1232 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 1238 uart2: serial@888000 { 1239 compatible = "qcom,geni-uart"; 1240 reg = <0 0x00888000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_uart2_default>; 1245 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1246 power-domains = <&rpmhpd SDM845_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 status = "disabled"; 1249 }; 1250 1251 i2c3: i2c@88c000 { 1252 compatible = "qcom,geni-i2c"; 1253 reg = <0 0x0088c000 0 0x4000>; 1254 clock-names = "se"; 1255 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_i2c3_default>; 1258 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 power-domains = <&rpmhpd SDM845_CX>; 1262 operating-points-v2 = <&qup_opp_table>; 1263 status = "disabled"; 1264 }; 1265 1266 spi3: spi@88c000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0 0x0088c000 0 0x4000>; 1269 clock-names = "se"; 1270 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_spi3_default>; 1273 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 status = "disabled"; 1277 }; 1278 1279 uart3: serial@88c000 { 1280 compatible = "qcom,geni-uart"; 1281 reg = <0 0x0088c000 0 0x4000>; 1282 clock-names = "se"; 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_uart3_default>; 1286 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1287 power-domains = <&rpmhpd SDM845_CX>; 1288 operating-points-v2 = <&qup_opp_table>; 1289 status = "disabled"; 1290 }; 1291 1292 i2c4: i2c@890000 { 1293 compatible = "qcom,geni-i2c"; 1294 reg = <0 0x00890000 0 0x4000>; 1295 clock-names = "se"; 1296 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_i2c4_default>; 1299 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 power-domains = <&rpmhpd SDM845_CX>; 1303 operating-points-v2 = <&qup_opp_table>; 1304 status = "disabled"; 1305 }; 1306 1307 spi4: spi@890000 { 1308 compatible = "qcom,geni-spi"; 1309 reg = <0 0x00890000 0 0x4000>; 1310 clock-names = "se"; 1311 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1312 pinctrl-names = "default"; 1313 pinctrl-0 = <&qup_spi4_default>; 1314 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 status = "disabled"; 1318 }; 1319 1320 uart4: serial@890000 { 1321 compatible = "qcom,geni-uart"; 1322 reg = <0 0x00890000 0 0x4000>; 1323 clock-names = "se"; 1324 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1325 pinctrl-names = "default"; 1326 pinctrl-0 = <&qup_uart4_default>; 1327 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1328 power-domains = <&rpmhpd SDM845_CX>; 1329 operating-points-v2 = <&qup_opp_table>; 1330 status = "disabled"; 1331 }; 1332 1333 i2c5: i2c@894000 { 1334 compatible = "qcom,geni-i2c"; 1335 reg = <0 0x00894000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_i2c5_default>; 1340 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 power-domains = <&rpmhpd SDM845_CX>; 1344 operating-points-v2 = <&qup_opp_table>; 1345 status = "disabled"; 1346 }; 1347 1348 spi5: spi@894000 { 1349 compatible = "qcom,geni-spi"; 1350 reg = <0 0x00894000 0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_spi5_default>; 1355 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 status = "disabled"; 1359 }; 1360 1361 uart5: serial@894000 { 1362 compatible = "qcom,geni-uart"; 1363 reg = <0 0x00894000 0 0x4000>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_uart5_default>; 1368 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1369 power-domains = <&rpmhpd SDM845_CX>; 1370 operating-points-v2 = <&qup_opp_table>; 1371 status = "disabled"; 1372 }; 1373 1374 i2c6: i2c@898000 { 1375 compatible = "qcom,geni-i2c"; 1376 reg = <0 0x00898000 0 0x4000>; 1377 clock-names = "se"; 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&qup_i2c6_default>; 1381 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 power-domains = <&rpmhpd SDM845_CX>; 1385 operating-points-v2 = <&qup_opp_table>; 1386 status = "disabled"; 1387 }; 1388 1389 spi6: spi@898000 { 1390 compatible = "qcom,geni-spi"; 1391 reg = <0 0x00898000 0 0x4000>; 1392 clock-names = "se"; 1393 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&qup_spi6_default>; 1396 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 status = "disabled"; 1400 }; 1401 1402 uart6: serial@898000 { 1403 compatible = "qcom,geni-uart"; 1404 reg = <0 0x00898000 0 0x4000>; 1405 clock-names = "se"; 1406 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_uart6_default>; 1409 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1410 power-domains = <&rpmhpd SDM845_CX>; 1411 operating-points-v2 = <&qup_opp_table>; 1412 status = "disabled"; 1413 }; 1414 1415 i2c7: i2c@89c000 { 1416 compatible = "qcom,geni-i2c"; 1417 reg = <0 0x0089c000 0 0x4000>; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_i2c7_default>; 1422 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 power-domains = <&rpmhpd SDM845_CX>; 1426 operating-points-v2 = <&qup_opp_table>; 1427 status = "disabled"; 1428 }; 1429 1430 spi7: spi@89c000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x0089c000 0 0x4000>; 1433 clock-names = "se"; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_spi7_default>; 1437 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 status = "disabled"; 1441 }; 1442 1443 uart7: serial@89c000 { 1444 compatible = "qcom,geni-uart"; 1445 reg = <0 0x0089c000 0 0x4000>; 1446 clock-names = "se"; 1447 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1448 pinctrl-names = "default"; 1449 pinctrl-0 = <&qup_uart7_default>; 1450 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1451 power-domains = <&rpmhpd SDM845_CX>; 1452 operating-points-v2 = <&qup_opp_table>; 1453 status = "disabled"; 1454 }; 1455 }; 1456 1457 qupv3_id_1: geniqup@ac0000 { 1458 compatible = "qcom,geni-se-qup"; 1459 reg = <0 0x00ac0000 0 0x6000>; 1460 clock-names = "m-ahb", "s-ahb"; 1461 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1462 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1463 #address-cells = <2>; 1464 #size-cells = <2>; 1465 ranges; 1466 status = "disabled"; 1467 1468 i2c8: i2c@a80000 { 1469 compatible = "qcom,geni-i2c"; 1470 reg = <0 0x00a80000 0 0x4000>; 1471 clock-names = "se"; 1472 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1473 pinctrl-names = "default"; 1474 pinctrl-0 = <&qup_i2c8_default>; 1475 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 power-domains = <&rpmhpd SDM845_CX>; 1479 operating-points-v2 = <&qup_opp_table>; 1480 status = "disabled"; 1481 }; 1482 1483 spi8: spi@a80000 { 1484 compatible = "qcom,geni-spi"; 1485 reg = <0 0x00a80000 0 0x4000>; 1486 clock-names = "se"; 1487 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1488 pinctrl-names = "default"; 1489 pinctrl-0 = <&qup_spi8_default>; 1490 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 uart8: serial@a80000 { 1497 compatible = "qcom,geni-uart"; 1498 reg = <0 0x00a80000 0 0x4000>; 1499 clock-names = "se"; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_uart8_default>; 1503 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1504 power-domains = <&rpmhpd SDM845_CX>; 1505 operating-points-v2 = <&qup_opp_table>; 1506 status = "disabled"; 1507 }; 1508 1509 i2c9: i2c@a84000 { 1510 compatible = "qcom,geni-i2c"; 1511 reg = <0 0x00a84000 0 0x4000>; 1512 clock-names = "se"; 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&qup_i2c9_default>; 1516 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 power-domains = <&rpmhpd SDM845_CX>; 1520 operating-points-v2 = <&qup_opp_table>; 1521 status = "disabled"; 1522 }; 1523 1524 spi9: spi@a84000 { 1525 compatible = "qcom,geni-spi"; 1526 reg = <0 0x00a84000 0 0x4000>; 1527 clock-names = "se"; 1528 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1529 pinctrl-names = "default"; 1530 pinctrl-0 = <&qup_spi9_default>; 1531 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 status = "disabled"; 1535 }; 1536 1537 uart9: serial@a84000 { 1538 compatible = "qcom,geni-debug-uart"; 1539 reg = <0 0x00a84000 0 0x4000>; 1540 clock-names = "se"; 1541 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1542 pinctrl-names = "default"; 1543 pinctrl-0 = <&qup_uart9_default>; 1544 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1545 power-domains = <&rpmhpd SDM845_CX>; 1546 operating-points-v2 = <&qup_opp_table>; 1547 status = "disabled"; 1548 }; 1549 1550 i2c10: i2c@a88000 { 1551 compatible = "qcom,geni-i2c"; 1552 reg = <0 0x00a88000 0 0x4000>; 1553 clock-names = "se"; 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1555 pinctrl-names = "default"; 1556 pinctrl-0 = <&qup_i2c10_default>; 1557 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 power-domains = <&rpmhpd SDM845_CX>; 1561 operating-points-v2 = <&qup_opp_table>; 1562 status = "disabled"; 1563 }; 1564 1565 spi10: spi@a88000 { 1566 compatible = "qcom,geni-spi"; 1567 reg = <0 0x00a88000 0 0x4000>; 1568 clock-names = "se"; 1569 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1570 pinctrl-names = "default"; 1571 pinctrl-0 = <&qup_spi10_default>; 1572 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1573 #address-cells = <1>; 1574 #size-cells = <0>; 1575 status = "disabled"; 1576 }; 1577 1578 uart10: serial@a88000 { 1579 compatible = "qcom,geni-uart"; 1580 reg = <0 0x00a88000 0 0x4000>; 1581 clock-names = "se"; 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&qup_uart10_default>; 1585 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1586 power-domains = <&rpmhpd SDM845_CX>; 1587 operating-points-v2 = <&qup_opp_table>; 1588 status = "disabled"; 1589 }; 1590 1591 i2c11: i2c@a8c000 { 1592 compatible = "qcom,geni-i2c"; 1593 reg = <0 0x00a8c000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&qup_i2c11_default>; 1598 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 power-domains = <&rpmhpd SDM845_CX>; 1602 operating-points-v2 = <&qup_opp_table>; 1603 status = "disabled"; 1604 }; 1605 1606 spi11: spi@a8c000 { 1607 compatible = "qcom,geni-spi"; 1608 reg = <0 0x00a8c000 0 0x4000>; 1609 clock-names = "se"; 1610 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1611 pinctrl-names = "default"; 1612 pinctrl-0 = <&qup_spi11_default>; 1613 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 status = "disabled"; 1617 }; 1618 1619 uart11: serial@a8c000 { 1620 compatible = "qcom,geni-uart"; 1621 reg = <0 0x00a8c000 0 0x4000>; 1622 clock-names = "se"; 1623 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1624 pinctrl-names = "default"; 1625 pinctrl-0 = <&qup_uart11_default>; 1626 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1627 power-domains = <&rpmhpd SDM845_CX>; 1628 operating-points-v2 = <&qup_opp_table>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c12: i2c@a90000 { 1633 compatible = "qcom,geni-i2c"; 1634 reg = <0 0x00a90000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_i2c12_default>; 1639 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 power-domains = <&rpmhpd SDM845_CX>; 1643 operating-points-v2 = <&qup_opp_table>; 1644 status = "disabled"; 1645 }; 1646 1647 spi12: spi@a90000 { 1648 compatible = "qcom,geni-spi"; 1649 reg = <0 0x00a90000 0 0x4000>; 1650 clock-names = "se"; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_spi12_default>; 1654 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 status = "disabled"; 1658 }; 1659 1660 uart12: serial@a90000 { 1661 compatible = "qcom,geni-uart"; 1662 reg = <0 0x00a90000 0 0x4000>; 1663 clock-names = "se"; 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1665 pinctrl-names = "default"; 1666 pinctrl-0 = <&qup_uart12_default>; 1667 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1668 power-domains = <&rpmhpd SDM845_CX>; 1669 operating-points-v2 = <&qup_opp_table>; 1670 status = "disabled"; 1671 }; 1672 1673 i2c13: i2c@a94000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0 0x00a94000 0 0x4000>; 1676 clock-names = "se"; 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_i2c13_default>; 1680 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 power-domains = <&rpmhpd SDM845_CX>; 1684 operating-points-v2 = <&qup_opp_table>; 1685 status = "disabled"; 1686 }; 1687 1688 spi13: spi@a94000 { 1689 compatible = "qcom,geni-spi"; 1690 reg = <0 0x00a94000 0 0x4000>; 1691 clock-names = "se"; 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_spi13_default>; 1695 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 status = "disabled"; 1699 }; 1700 1701 uart13: serial@a94000 { 1702 compatible = "qcom,geni-uart"; 1703 reg = <0 0x00a94000 0 0x4000>; 1704 clock-names = "se"; 1705 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1706 pinctrl-names = "default"; 1707 pinctrl-0 = <&qup_uart13_default>; 1708 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1709 power-domains = <&rpmhpd SDM845_CX>; 1710 operating-points-v2 = <&qup_opp_table>; 1711 status = "disabled"; 1712 }; 1713 1714 i2c14: i2c@a98000 { 1715 compatible = "qcom,geni-i2c"; 1716 reg = <0 0x00a98000 0 0x4000>; 1717 clock-names = "se"; 1718 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1719 pinctrl-names = "default"; 1720 pinctrl-0 = <&qup_i2c14_default>; 1721 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 power-domains = <&rpmhpd SDM845_CX>; 1725 operating-points-v2 = <&qup_opp_table>; 1726 status = "disabled"; 1727 }; 1728 1729 spi14: spi@a98000 { 1730 compatible = "qcom,geni-spi"; 1731 reg = <0 0x00a98000 0 0x4000>; 1732 clock-names = "se"; 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1734 pinctrl-names = "default"; 1735 pinctrl-0 = <&qup_spi14_default>; 1736 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 status = "disabled"; 1740 }; 1741 1742 uart14: serial@a98000 { 1743 compatible = "qcom,geni-uart"; 1744 reg = <0 0x00a98000 0 0x4000>; 1745 clock-names = "se"; 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_uart14_default>; 1749 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1750 power-domains = <&rpmhpd SDM845_CX>; 1751 operating-points-v2 = <&qup_opp_table>; 1752 status = "disabled"; 1753 }; 1754 1755 i2c15: i2c@a9c000 { 1756 compatible = "qcom,geni-i2c"; 1757 reg = <0 0x00a9c000 0 0x4000>; 1758 clock-names = "se"; 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1760 pinctrl-names = "default"; 1761 pinctrl-0 = <&qup_i2c15_default>; 1762 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 power-domains = <&rpmhpd SDM845_CX>; 1766 operating-points-v2 = <&qup_opp_table>; 1767 status = "disabled"; 1768 }; 1769 1770 spi15: spi@a9c000 { 1771 compatible = "qcom,geni-spi"; 1772 reg = <0 0x00a9c000 0 0x4000>; 1773 clock-names = "se"; 1774 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1775 pinctrl-names = "default"; 1776 pinctrl-0 = <&qup_spi15_default>; 1777 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 status = "disabled"; 1781 }; 1782 1783 uart15: serial@a9c000 { 1784 compatible = "qcom,geni-uart"; 1785 reg = <0 0x00a9c000 0 0x4000>; 1786 clock-names = "se"; 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1788 pinctrl-names = "default"; 1789 pinctrl-0 = <&qup_uart15_default>; 1790 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1791 power-domains = <&rpmhpd SDM845_CX>; 1792 operating-points-v2 = <&qup_opp_table>; 1793 status = "disabled"; 1794 }; 1795 }; 1796 1797 system-cache-controller@1100000 { 1798 compatible = "qcom,sdm845-llcc"; 1799 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1800 reg-names = "llcc_base", "llcc_broadcast_base"; 1801 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1802 }; 1803 1804 pcie0: pci@1c00000 { 1805 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1806 reg = <0 0x01c00000 0 0x2000>, 1807 <0 0x60000000 0 0xf1d>, 1808 <0 0x60000f20 0 0xa8>, 1809 <0 0x60100000 0 0x100000>; 1810 reg-names = "parf", "dbi", "elbi", "config"; 1811 device_type = "pci"; 1812 linux,pci-domain = <0>; 1813 bus-range = <0x00 0xff>; 1814 num-lanes = <1>; 1815 1816 #address-cells = <3>; 1817 #size-cells = <2>; 1818 1819 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1820 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 1821 1822 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1823 interrupt-names = "msi"; 1824 #interrupt-cells = <1>; 1825 interrupt-map-mask = <0 0 0 0x7>; 1826 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1827 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1828 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1829 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1830 1831 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1832 <&gcc GCC_PCIE_0_AUX_CLK>, 1833 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1834 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1835 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1836 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1837 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1838 clock-names = "pipe", 1839 "aux", 1840 "cfg", 1841 "bus_master", 1842 "bus_slave", 1843 "slave_q2a", 1844 "tbu"; 1845 1846 iommus = <&apps_smmu 0x1c10 0xf>; 1847 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 1848 <0x100 &apps_smmu 0x1c11 0x1>, 1849 <0x200 &apps_smmu 0x1c12 0x1>, 1850 <0x300 &apps_smmu 0x1c13 0x1>, 1851 <0x400 &apps_smmu 0x1c14 0x1>, 1852 <0x500 &apps_smmu 0x1c15 0x1>, 1853 <0x600 &apps_smmu 0x1c16 0x1>, 1854 <0x700 &apps_smmu 0x1c17 0x1>, 1855 <0x800 &apps_smmu 0x1c18 0x1>, 1856 <0x900 &apps_smmu 0x1c19 0x1>, 1857 <0xa00 &apps_smmu 0x1c1a 0x1>, 1858 <0xb00 &apps_smmu 0x1c1b 0x1>, 1859 <0xc00 &apps_smmu 0x1c1c 0x1>, 1860 <0xd00 &apps_smmu 0x1c1d 0x1>, 1861 <0xe00 &apps_smmu 0x1c1e 0x1>, 1862 <0xf00 &apps_smmu 0x1c1f 0x1>; 1863 1864 resets = <&gcc GCC_PCIE_0_BCR>; 1865 reset-names = "pci"; 1866 1867 power-domains = <&gcc PCIE_0_GDSC>; 1868 1869 phys = <&pcie0_lane>; 1870 phy-names = "pciephy"; 1871 1872 status = "disabled"; 1873 }; 1874 1875 pcie0_phy: phy@1c06000 { 1876 compatible = "qcom,sdm845-qmp-pcie-phy"; 1877 reg = <0 0x01c06000 0 0x18c>; 1878 #address-cells = <2>; 1879 #size-cells = <2>; 1880 ranges; 1881 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1882 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1883 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1884 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1885 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1886 1887 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1888 reset-names = "phy"; 1889 1890 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1891 assigned-clock-rates = <100000000>; 1892 1893 status = "disabled"; 1894 1895 pcie0_lane: lanes@1c06200 { 1896 reg = <0 0x01c06200 0 0x128>, 1897 <0 0x01c06400 0 0x1fc>, 1898 <0 0x01c06800 0 0x218>, 1899 <0 0x01c06600 0 0x70>; 1900 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1901 clock-names = "pipe0"; 1902 1903 #phy-cells = <0>; 1904 clock-output-names = "pcie_0_pipe_clk"; 1905 }; 1906 }; 1907 1908 pcie1: pci@1c08000 { 1909 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1910 reg = <0 0x01c08000 0 0x2000>, 1911 <0 0x40000000 0 0xf1d>, 1912 <0 0x40000f20 0 0xa8>, 1913 <0 0x40100000 0 0x100000>; 1914 reg-names = "parf", "dbi", "elbi", "config"; 1915 device_type = "pci"; 1916 linux,pci-domain = <1>; 1917 bus-range = <0x00 0xff>; 1918 num-lanes = <1>; 1919 1920 #address-cells = <3>; 1921 #size-cells = <2>; 1922 1923 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1924 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1925 1926 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1927 interrupt-names = "msi"; 1928 #interrupt-cells = <1>; 1929 interrupt-map-mask = <0 0 0 0x7>; 1930 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1931 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1932 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1933 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1934 1935 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1936 <&gcc GCC_PCIE_1_AUX_CLK>, 1937 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1938 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1939 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1940 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1941 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1942 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1943 clock-names = "pipe", 1944 "aux", 1945 "cfg", 1946 "bus_master", 1947 "bus_slave", 1948 "slave_q2a", 1949 "ref", 1950 "tbu"; 1951 1952 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1953 assigned-clock-rates = <19200000>; 1954 1955 iommus = <&apps_smmu 0x1c00 0xf>; 1956 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1957 <0x100 &apps_smmu 0x1c01 0x1>, 1958 <0x200 &apps_smmu 0x1c02 0x1>, 1959 <0x300 &apps_smmu 0x1c03 0x1>, 1960 <0x400 &apps_smmu 0x1c04 0x1>, 1961 <0x500 &apps_smmu 0x1c05 0x1>, 1962 <0x600 &apps_smmu 0x1c06 0x1>, 1963 <0x700 &apps_smmu 0x1c07 0x1>, 1964 <0x800 &apps_smmu 0x1c08 0x1>, 1965 <0x900 &apps_smmu 0x1c09 0x1>, 1966 <0xa00 &apps_smmu 0x1c0a 0x1>, 1967 <0xb00 &apps_smmu 0x1c0b 0x1>, 1968 <0xc00 &apps_smmu 0x1c0c 0x1>, 1969 <0xd00 &apps_smmu 0x1c0d 0x1>, 1970 <0xe00 &apps_smmu 0x1c0e 0x1>, 1971 <0xf00 &apps_smmu 0x1c0f 0x1>; 1972 1973 resets = <&gcc GCC_PCIE_1_BCR>; 1974 reset-names = "pci"; 1975 1976 power-domains = <&gcc PCIE_1_GDSC>; 1977 1978 phys = <&pcie1_lane>; 1979 phy-names = "pciephy"; 1980 1981 status = "disabled"; 1982 }; 1983 1984 pcie1_phy: phy@1c0a000 { 1985 compatible = "qcom,sdm845-qhp-pcie-phy"; 1986 reg = <0 0x01c0a000 0 0x800>; 1987 #address-cells = <2>; 1988 #size-cells = <2>; 1989 ranges; 1990 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1991 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1992 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1993 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1994 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1995 1996 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1997 reset-names = "phy"; 1998 1999 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2000 assigned-clock-rates = <100000000>; 2001 2002 status = "disabled"; 2003 2004 pcie1_lane: lanes@1c06200 { 2005 reg = <0 0x01c0a800 0 0x800>, 2006 <0 0x01c0a800 0 0x800>, 2007 <0 0x01c0b800 0 0x400>; 2008 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2009 clock-names = "pipe0"; 2010 2011 #phy-cells = <0>; 2012 clock-output-names = "pcie_1_pipe_clk"; 2013 }; 2014 }; 2015 2016 mem_noc: interconnect@1380000 { 2017 compatible = "qcom,sdm845-mem-noc"; 2018 reg = <0 0x01380000 0 0x27200>; 2019 #interconnect-cells = <2>; 2020 qcom,bcm-voters = <&apps_bcm_voter>; 2021 }; 2022 2023 dc_noc: interconnect@14e0000 { 2024 compatible = "qcom,sdm845-dc-noc"; 2025 reg = <0 0x014e0000 0 0x400>; 2026 #interconnect-cells = <2>; 2027 qcom,bcm-voters = <&apps_bcm_voter>; 2028 }; 2029 2030 config_noc: interconnect@1500000 { 2031 compatible = "qcom,sdm845-config-noc"; 2032 reg = <0 0x01500000 0 0x5080>; 2033 #interconnect-cells = <2>; 2034 qcom,bcm-voters = <&apps_bcm_voter>; 2035 }; 2036 2037 system_noc: interconnect@1620000 { 2038 compatible = "qcom,sdm845-system-noc"; 2039 reg = <0 0x01620000 0 0x18080>; 2040 #interconnect-cells = <2>; 2041 qcom,bcm-voters = <&apps_bcm_voter>; 2042 }; 2043 2044 aggre1_noc: interconnect@16e0000 { 2045 compatible = "qcom,sdm845-aggre1-noc"; 2046 reg = <0 0x016e0000 0 0x15080>; 2047 #interconnect-cells = <2>; 2048 qcom,bcm-voters = <&apps_bcm_voter>; 2049 }; 2050 2051 aggre2_noc: interconnect@1700000 { 2052 compatible = "qcom,sdm845-aggre2-noc"; 2053 reg = <0 0x01700000 0 0x1f300>; 2054 #interconnect-cells = <2>; 2055 qcom,bcm-voters = <&apps_bcm_voter>; 2056 }; 2057 2058 mmss_noc: interconnect@1740000 { 2059 compatible = "qcom,sdm845-mmss-noc"; 2060 reg = <0 0x01740000 0 0x1c100>; 2061 #interconnect-cells = <2>; 2062 qcom,bcm-voters = <&apps_bcm_voter>; 2063 }; 2064 2065 ufs_mem_hc: ufshc@1d84000 { 2066 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2067 "jedec,ufs-2.0"; 2068 reg = <0 0x01d84000 0 0x2500>, 2069 <0 0x01d90000 0 0x8000>; 2070 reg-names = "std", "ice"; 2071 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2072 phys = <&ufs_mem_phy_lanes>; 2073 phy-names = "ufsphy"; 2074 lanes-per-direction = <2>; 2075 power-domains = <&gcc UFS_PHY_GDSC>; 2076 #reset-cells = <1>; 2077 resets = <&gcc GCC_UFS_PHY_BCR>; 2078 reset-names = "rst"; 2079 2080 iommus = <&apps_smmu 0x100 0xf>; 2081 2082 clock-names = 2083 "core_clk", 2084 "bus_aggr_clk", 2085 "iface_clk", 2086 "core_clk_unipro", 2087 "ref_clk", 2088 "tx_lane0_sync_clk", 2089 "rx_lane0_sync_clk", 2090 "rx_lane1_sync_clk", 2091 "ice_core_clk"; 2092 clocks = 2093 <&gcc GCC_UFS_PHY_AXI_CLK>, 2094 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2095 <&gcc GCC_UFS_PHY_AHB_CLK>, 2096 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2097 <&rpmhcc RPMH_CXO_CLK>, 2098 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2099 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2100 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2101 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2102 freq-table-hz = 2103 <50000000 200000000>, 2104 <0 0>, 2105 <0 0>, 2106 <37500000 150000000>, 2107 <0 0>, 2108 <0 0>, 2109 <0 0>, 2110 <0 0>, 2111 <0 300000000>; 2112 2113 status = "disabled"; 2114 }; 2115 2116 ufs_mem_phy: phy@1d87000 { 2117 compatible = "qcom,sdm845-qmp-ufs-phy"; 2118 reg = <0 0x01d87000 0 0x18c>; 2119 #address-cells = <2>; 2120 #size-cells = <2>; 2121 ranges; 2122 clock-names = "ref", 2123 "ref_aux"; 2124 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2125 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2126 2127 resets = <&ufs_mem_hc 0>; 2128 reset-names = "ufsphy"; 2129 status = "disabled"; 2130 2131 ufs_mem_phy_lanes: lanes@1d87400 { 2132 reg = <0 0x01d87400 0 0x108>, 2133 <0 0x01d87600 0 0x1e0>, 2134 <0 0x01d87c00 0 0x1dc>, 2135 <0 0x01d87800 0 0x108>, 2136 <0 0x01d87a00 0 0x1e0>; 2137 #phy-cells = <0>; 2138 }; 2139 }; 2140 2141 ipa: ipa@1e40000 { 2142 compatible = "qcom,sdm845-ipa"; 2143 2144 iommus = <&apps_smmu 0x720 0x3>; 2145 reg = <0 0x1e40000 0 0x7000>, 2146 <0 0x1e47000 0 0x2000>, 2147 <0 0x1e04000 0 0x2c000>; 2148 reg-names = "ipa-reg", 2149 "ipa-shared", 2150 "gsi"; 2151 2152 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, 2153 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 2154 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2155 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2156 interrupt-names = "ipa", 2157 "gsi", 2158 "ipa-clock-query", 2159 "ipa-setup-ready"; 2160 2161 clocks = <&rpmhcc RPMH_IPA_CLK>; 2162 clock-names = "core"; 2163 2164 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2165 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2166 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2167 interconnect-names = "memory", 2168 "imem", 2169 "config"; 2170 2171 qcom,smem-states = <&ipa_smp2p_out 0>, 2172 <&ipa_smp2p_out 1>; 2173 qcom,smem-state-names = "ipa-clock-enabled-valid", 2174 "ipa-clock-enabled"; 2175 2176 modem-remoteproc = <&mss_pil>; 2177 2178 status = "disabled"; 2179 }; 2180 2181 tcsr_mutex_regs: syscon@1f40000 { 2182 compatible = "syscon"; 2183 reg = <0 0x01f40000 0 0x40000>; 2184 }; 2185 2186 tlmm: pinctrl@3400000 { 2187 compatible = "qcom,sdm845-pinctrl"; 2188 reg = <0 0x03400000 0 0xc00000>; 2189 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2190 gpio-controller; 2191 #gpio-cells = <2>; 2192 interrupt-controller; 2193 #interrupt-cells = <2>; 2194 gpio-ranges = <&tlmm 0 0 150>; 2195 wakeup-parent = <&pdc_intc>; 2196 2197 cci0_default: cci0-default { 2198 /* SDA, SCL */ 2199 pins = "gpio17", "gpio18"; 2200 function = "cci_i2c"; 2201 2202 bias-pull-up; 2203 drive-strength = <2>; /* 2 mA */ 2204 }; 2205 2206 cci0_sleep: cci0-sleep { 2207 /* SDA, SCL */ 2208 pins = "gpio17", "gpio18"; 2209 function = "cci_i2c"; 2210 2211 drive-strength = <2>; /* 2 mA */ 2212 bias-pull-down; 2213 }; 2214 2215 cci1_default: cci1-default { 2216 /* SDA, SCL */ 2217 pins = "gpio19", "gpio20"; 2218 function = "cci_i2c"; 2219 2220 bias-pull-up; 2221 drive-strength = <2>; /* 2 mA */ 2222 }; 2223 2224 cci1_sleep: cci1-sleep { 2225 /* SDA, SCL */ 2226 pins = "gpio19", "gpio20"; 2227 function = "cci_i2c"; 2228 2229 drive-strength = <2>; /* 2 mA */ 2230 bias-pull-down; 2231 }; 2232 2233 qspi_clk: qspi-clk { 2234 pinmux { 2235 pins = "gpio95"; 2236 function = "qspi_clk"; 2237 }; 2238 }; 2239 2240 qspi_cs0: qspi-cs0 { 2241 pinmux { 2242 pins = "gpio90"; 2243 function = "qspi_cs"; 2244 }; 2245 }; 2246 2247 qspi_cs1: qspi-cs1 { 2248 pinmux { 2249 pins = "gpio89"; 2250 function = "qspi_cs"; 2251 }; 2252 }; 2253 2254 qspi_data01: qspi-data01 { 2255 pinmux-data { 2256 pins = "gpio91", "gpio92"; 2257 function = "qspi_data"; 2258 }; 2259 }; 2260 2261 qspi_data12: qspi-data12 { 2262 pinmux-data { 2263 pins = "gpio93", "gpio94"; 2264 function = "qspi_data"; 2265 }; 2266 }; 2267 2268 qup_i2c0_default: qup-i2c0-default { 2269 pinmux { 2270 pins = "gpio0", "gpio1"; 2271 function = "qup0"; 2272 }; 2273 }; 2274 2275 qup_i2c1_default: qup-i2c1-default { 2276 pinmux { 2277 pins = "gpio17", "gpio18"; 2278 function = "qup1"; 2279 }; 2280 }; 2281 2282 qup_i2c2_default: qup-i2c2-default { 2283 pinmux { 2284 pins = "gpio27", "gpio28"; 2285 function = "qup2"; 2286 }; 2287 }; 2288 2289 qup_i2c3_default: qup-i2c3-default { 2290 pinmux { 2291 pins = "gpio41", "gpio42"; 2292 function = "qup3"; 2293 }; 2294 }; 2295 2296 qup_i2c4_default: qup-i2c4-default { 2297 pinmux { 2298 pins = "gpio89", "gpio90"; 2299 function = "qup4"; 2300 }; 2301 }; 2302 2303 qup_i2c5_default: qup-i2c5-default { 2304 pinmux { 2305 pins = "gpio85", "gpio86"; 2306 function = "qup5"; 2307 }; 2308 }; 2309 2310 qup_i2c6_default: qup-i2c6-default { 2311 pinmux { 2312 pins = "gpio45", "gpio46"; 2313 function = "qup6"; 2314 }; 2315 }; 2316 2317 qup_i2c7_default: qup-i2c7-default { 2318 pinmux { 2319 pins = "gpio93", "gpio94"; 2320 function = "qup7"; 2321 }; 2322 }; 2323 2324 qup_i2c8_default: qup-i2c8-default { 2325 pinmux { 2326 pins = "gpio65", "gpio66"; 2327 function = "qup8"; 2328 }; 2329 }; 2330 2331 qup_i2c9_default: qup-i2c9-default { 2332 pinmux { 2333 pins = "gpio6", "gpio7"; 2334 function = "qup9"; 2335 }; 2336 }; 2337 2338 qup_i2c10_default: qup-i2c10-default { 2339 pinmux { 2340 pins = "gpio55", "gpio56"; 2341 function = "qup10"; 2342 }; 2343 }; 2344 2345 qup_i2c11_default: qup-i2c11-default { 2346 pinmux { 2347 pins = "gpio31", "gpio32"; 2348 function = "qup11"; 2349 }; 2350 }; 2351 2352 qup_i2c12_default: qup-i2c12-default { 2353 pinmux { 2354 pins = "gpio49", "gpio50"; 2355 function = "qup12"; 2356 }; 2357 }; 2358 2359 qup_i2c13_default: qup-i2c13-default { 2360 pinmux { 2361 pins = "gpio105", "gpio106"; 2362 function = "qup13"; 2363 }; 2364 }; 2365 2366 qup_i2c14_default: qup-i2c14-default { 2367 pinmux { 2368 pins = "gpio33", "gpio34"; 2369 function = "qup14"; 2370 }; 2371 }; 2372 2373 qup_i2c15_default: qup-i2c15-default { 2374 pinmux { 2375 pins = "gpio81", "gpio82"; 2376 function = "qup15"; 2377 }; 2378 }; 2379 2380 qup_spi0_default: qup-spi0-default { 2381 pinmux { 2382 pins = "gpio0", "gpio1", 2383 "gpio2", "gpio3"; 2384 function = "qup0"; 2385 }; 2386 }; 2387 2388 qup_spi1_default: qup-spi1-default { 2389 pinmux { 2390 pins = "gpio17", "gpio18", 2391 "gpio19", "gpio20"; 2392 function = "qup1"; 2393 }; 2394 }; 2395 2396 qup_spi2_default: qup-spi2-default { 2397 pinmux { 2398 pins = "gpio27", "gpio28", 2399 "gpio29", "gpio30"; 2400 function = "qup2"; 2401 }; 2402 }; 2403 2404 qup_spi3_default: qup-spi3-default { 2405 pinmux { 2406 pins = "gpio41", "gpio42", 2407 "gpio43", "gpio44"; 2408 function = "qup3"; 2409 }; 2410 }; 2411 2412 qup_spi4_default: qup-spi4-default { 2413 pinmux { 2414 pins = "gpio89", "gpio90", 2415 "gpio91", "gpio92"; 2416 function = "qup4"; 2417 }; 2418 }; 2419 2420 qup_spi5_default: qup-spi5-default { 2421 pinmux { 2422 pins = "gpio85", "gpio86", 2423 "gpio87", "gpio88"; 2424 function = "qup5"; 2425 }; 2426 }; 2427 2428 qup_spi6_default: qup-spi6-default { 2429 pinmux { 2430 pins = "gpio45", "gpio46", 2431 "gpio47", "gpio48"; 2432 function = "qup6"; 2433 }; 2434 }; 2435 2436 qup_spi7_default: qup-spi7-default { 2437 pinmux { 2438 pins = "gpio93", "gpio94", 2439 "gpio95", "gpio96"; 2440 function = "qup7"; 2441 }; 2442 }; 2443 2444 qup_spi8_default: qup-spi8-default { 2445 pinmux { 2446 pins = "gpio65", "gpio66", 2447 "gpio67", "gpio68"; 2448 function = "qup8"; 2449 }; 2450 }; 2451 2452 qup_spi9_default: qup-spi9-default { 2453 pinmux { 2454 pins = "gpio6", "gpio7", 2455 "gpio4", "gpio5"; 2456 function = "qup9"; 2457 }; 2458 }; 2459 2460 qup_spi10_default: qup-spi10-default { 2461 pinmux { 2462 pins = "gpio55", "gpio56", 2463 "gpio53", "gpio54"; 2464 function = "qup10"; 2465 }; 2466 }; 2467 2468 qup_spi11_default: qup-spi11-default { 2469 pinmux { 2470 pins = "gpio31", "gpio32", 2471 "gpio33", "gpio34"; 2472 function = "qup11"; 2473 }; 2474 }; 2475 2476 qup_spi12_default: qup-spi12-default { 2477 pinmux { 2478 pins = "gpio49", "gpio50", 2479 "gpio51", "gpio52"; 2480 function = "qup12"; 2481 }; 2482 }; 2483 2484 qup_spi13_default: qup-spi13-default { 2485 pinmux { 2486 pins = "gpio105", "gpio106", 2487 "gpio107", "gpio108"; 2488 function = "qup13"; 2489 }; 2490 }; 2491 2492 qup_spi14_default: qup-spi14-default { 2493 pinmux { 2494 pins = "gpio33", "gpio34", 2495 "gpio31", "gpio32"; 2496 function = "qup14"; 2497 }; 2498 }; 2499 2500 qup_spi15_default: qup-spi15-default { 2501 pinmux { 2502 pins = "gpio81", "gpio82", 2503 "gpio83", "gpio84"; 2504 function = "qup15"; 2505 }; 2506 }; 2507 2508 qup_uart0_default: qup-uart0-default { 2509 pinmux { 2510 pins = "gpio2", "gpio3"; 2511 function = "qup0"; 2512 }; 2513 }; 2514 2515 qup_uart1_default: qup-uart1-default { 2516 pinmux { 2517 pins = "gpio19", "gpio20"; 2518 function = "qup1"; 2519 }; 2520 }; 2521 2522 qup_uart2_default: qup-uart2-default { 2523 pinmux { 2524 pins = "gpio29", "gpio30"; 2525 function = "qup2"; 2526 }; 2527 }; 2528 2529 qup_uart3_default: qup-uart3-default { 2530 pinmux { 2531 pins = "gpio43", "gpio44"; 2532 function = "qup3"; 2533 }; 2534 }; 2535 2536 qup_uart4_default: qup-uart4-default { 2537 pinmux { 2538 pins = "gpio91", "gpio92"; 2539 function = "qup4"; 2540 }; 2541 }; 2542 2543 qup_uart5_default: qup-uart5-default { 2544 pinmux { 2545 pins = "gpio87", "gpio88"; 2546 function = "qup5"; 2547 }; 2548 }; 2549 2550 qup_uart6_default: qup-uart6-default { 2551 pinmux { 2552 pins = "gpio47", "gpio48"; 2553 function = "qup6"; 2554 }; 2555 }; 2556 2557 qup_uart7_default: qup-uart7-default { 2558 pinmux { 2559 pins = "gpio95", "gpio96"; 2560 function = "qup7"; 2561 }; 2562 }; 2563 2564 qup_uart8_default: qup-uart8-default { 2565 pinmux { 2566 pins = "gpio67", "gpio68"; 2567 function = "qup8"; 2568 }; 2569 }; 2570 2571 qup_uart9_default: qup-uart9-default { 2572 pinmux { 2573 pins = "gpio4", "gpio5"; 2574 function = "qup9"; 2575 }; 2576 }; 2577 2578 qup_uart10_default: qup-uart10-default { 2579 pinmux { 2580 pins = "gpio53", "gpio54"; 2581 function = "qup10"; 2582 }; 2583 }; 2584 2585 qup_uart11_default: qup-uart11-default { 2586 pinmux { 2587 pins = "gpio33", "gpio34"; 2588 function = "qup11"; 2589 }; 2590 }; 2591 2592 qup_uart12_default: qup-uart12-default { 2593 pinmux { 2594 pins = "gpio51", "gpio52"; 2595 function = "qup12"; 2596 }; 2597 }; 2598 2599 qup_uart13_default: qup-uart13-default { 2600 pinmux { 2601 pins = "gpio107", "gpio108"; 2602 function = "qup13"; 2603 }; 2604 }; 2605 2606 qup_uart14_default: qup-uart14-default { 2607 pinmux { 2608 pins = "gpio31", "gpio32"; 2609 function = "qup14"; 2610 }; 2611 }; 2612 2613 qup_uart15_default: qup-uart15-default { 2614 pinmux { 2615 pins = "gpio83", "gpio84"; 2616 function = "qup15"; 2617 }; 2618 }; 2619 2620 quat_mi2s_sleep: quat_mi2s_sleep { 2621 mux { 2622 pins = "gpio58", "gpio59"; 2623 function = "gpio"; 2624 }; 2625 2626 config { 2627 pins = "gpio58", "gpio59"; 2628 drive-strength = <2>; 2629 bias-pull-down; 2630 input-enable; 2631 }; 2632 }; 2633 2634 quat_mi2s_active: quat_mi2s_active { 2635 mux { 2636 pins = "gpio58", "gpio59"; 2637 function = "qua_mi2s"; 2638 }; 2639 2640 config { 2641 pins = "gpio58", "gpio59"; 2642 drive-strength = <8>; 2643 bias-disable; 2644 output-high; 2645 }; 2646 }; 2647 2648 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { 2649 mux { 2650 pins = "gpio60"; 2651 function = "gpio"; 2652 }; 2653 2654 config { 2655 pins = "gpio60"; 2656 drive-strength = <2>; 2657 bias-pull-down; 2658 input-enable; 2659 }; 2660 }; 2661 2662 quat_mi2s_sd0_active: quat_mi2s_sd0_active { 2663 mux { 2664 pins = "gpio60"; 2665 function = "qua_mi2s"; 2666 }; 2667 2668 config { 2669 pins = "gpio60"; 2670 drive-strength = <8>; 2671 bias-disable; 2672 }; 2673 }; 2674 2675 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { 2676 mux { 2677 pins = "gpio61"; 2678 function = "gpio"; 2679 }; 2680 2681 config { 2682 pins = "gpio61"; 2683 drive-strength = <2>; 2684 bias-pull-down; 2685 input-enable; 2686 }; 2687 }; 2688 2689 quat_mi2s_sd1_active: quat_mi2s_sd1_active { 2690 mux { 2691 pins = "gpio61"; 2692 function = "qua_mi2s"; 2693 }; 2694 2695 config { 2696 pins = "gpio61"; 2697 drive-strength = <8>; 2698 bias-disable; 2699 }; 2700 }; 2701 2702 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { 2703 mux { 2704 pins = "gpio62"; 2705 function = "gpio"; 2706 }; 2707 2708 config { 2709 pins = "gpio62"; 2710 drive-strength = <2>; 2711 bias-pull-down; 2712 input-enable; 2713 }; 2714 }; 2715 2716 quat_mi2s_sd2_active: quat_mi2s_sd2_active { 2717 mux { 2718 pins = "gpio62"; 2719 function = "qua_mi2s"; 2720 }; 2721 2722 config { 2723 pins = "gpio62"; 2724 drive-strength = <8>; 2725 bias-disable; 2726 }; 2727 }; 2728 2729 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { 2730 mux { 2731 pins = "gpio63"; 2732 function = "gpio"; 2733 }; 2734 2735 config { 2736 pins = "gpio63"; 2737 drive-strength = <2>; 2738 bias-pull-down; 2739 input-enable; 2740 }; 2741 }; 2742 2743 quat_mi2s_sd3_active: quat_mi2s_sd3_active { 2744 mux { 2745 pins = "gpio63"; 2746 function = "qua_mi2s"; 2747 }; 2748 2749 config { 2750 pins = "gpio63"; 2751 drive-strength = <8>; 2752 bias-disable; 2753 }; 2754 }; 2755 }; 2756 2757 mss_pil: remoteproc@4080000 { 2758 compatible = "qcom,sdm845-mss-pil"; 2759 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2760 reg-names = "qdsp6", "rmb"; 2761 2762 interrupts-extended = 2763 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2764 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2765 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2766 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2767 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2768 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2769 interrupt-names = "wdog", "fatal", "ready", 2770 "handover", "stop-ack", 2771 "shutdown-ack"; 2772 2773 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2774 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2775 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2776 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2777 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2778 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2779 <&gcc GCC_PRNG_AHB_CLK>, 2780 <&rpmhcc RPMH_CXO_CLK>; 2781 clock-names = "iface", "bus", "mem", "gpll0_mss", 2782 "snoc_axi", "mnoc_axi", "prng", "xo"; 2783 2784 qcom,smem-states = <&modem_smp2p_out 0>; 2785 qcom,smem-state-names = "stop"; 2786 2787 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2788 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2789 reset-names = "mss_restart", "pdc_reset"; 2790 2791 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2792 2793 power-domains = <&aoss_qmp 2>, 2794 <&rpmhpd SDM845_CX>, 2795 <&rpmhpd SDM845_MX>, 2796 <&rpmhpd SDM845_MSS>; 2797 power-domain-names = "load_state", "cx", "mx", "mss"; 2798 2799 mba { 2800 memory-region = <&mba_region>; 2801 }; 2802 2803 mpss { 2804 memory-region = <&mpss_region>; 2805 }; 2806 2807 glink-edge { 2808 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2809 label = "modem"; 2810 qcom,remote-pid = <1>; 2811 mboxes = <&apss_shared 12>; 2812 }; 2813 }; 2814 2815 gpucc: clock-controller@5090000 { 2816 compatible = "qcom,sdm845-gpucc"; 2817 reg = <0 0x05090000 0 0x9000>; 2818 #clock-cells = <1>; 2819 #reset-cells = <1>; 2820 #power-domain-cells = <1>; 2821 clocks = <&rpmhcc RPMH_CXO_CLK>, 2822 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2823 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2824 clock-names = "bi_tcxo", 2825 "gcc_gpu_gpll0_clk_src", 2826 "gcc_gpu_gpll0_div_clk_src"; 2827 }; 2828 2829 stm@6002000 { 2830 compatible = "arm,coresight-stm", "arm,primecell"; 2831 reg = <0 0x06002000 0 0x1000>, 2832 <0 0x16280000 0 0x180000>; 2833 reg-names = "stm-base", "stm-stimulus-base"; 2834 2835 clocks = <&aoss_qmp>; 2836 clock-names = "apb_pclk"; 2837 2838 out-ports { 2839 port { 2840 stm_out: endpoint { 2841 remote-endpoint = 2842 <&funnel0_in7>; 2843 }; 2844 }; 2845 }; 2846 }; 2847 2848 funnel@6041000 { 2849 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2850 reg = <0 0x06041000 0 0x1000>; 2851 2852 clocks = <&aoss_qmp>; 2853 clock-names = "apb_pclk"; 2854 2855 out-ports { 2856 port { 2857 funnel0_out: endpoint { 2858 remote-endpoint = 2859 <&merge_funnel_in0>; 2860 }; 2861 }; 2862 }; 2863 2864 in-ports { 2865 #address-cells = <1>; 2866 #size-cells = <0>; 2867 2868 port@7 { 2869 reg = <7>; 2870 funnel0_in7: endpoint { 2871 remote-endpoint = <&stm_out>; 2872 }; 2873 }; 2874 }; 2875 }; 2876 2877 funnel@6043000 { 2878 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2879 reg = <0 0x06043000 0 0x1000>; 2880 2881 clocks = <&aoss_qmp>; 2882 clock-names = "apb_pclk"; 2883 2884 out-ports { 2885 port { 2886 funnel2_out: endpoint { 2887 remote-endpoint = 2888 <&merge_funnel_in2>; 2889 }; 2890 }; 2891 }; 2892 2893 in-ports { 2894 #address-cells = <1>; 2895 #size-cells = <0>; 2896 2897 port@5 { 2898 reg = <5>; 2899 funnel2_in5: endpoint { 2900 remote-endpoint = 2901 <&apss_merge_funnel_out>; 2902 }; 2903 }; 2904 }; 2905 }; 2906 2907 funnel@6045000 { 2908 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2909 reg = <0 0x06045000 0 0x1000>; 2910 2911 clocks = <&aoss_qmp>; 2912 clock-names = "apb_pclk"; 2913 2914 out-ports { 2915 port { 2916 merge_funnel_out: endpoint { 2917 remote-endpoint = <&etf_in>; 2918 }; 2919 }; 2920 }; 2921 2922 in-ports { 2923 #address-cells = <1>; 2924 #size-cells = <0>; 2925 2926 port@0 { 2927 reg = <0>; 2928 merge_funnel_in0: endpoint { 2929 remote-endpoint = 2930 <&funnel0_out>; 2931 }; 2932 }; 2933 2934 port@2 { 2935 reg = <2>; 2936 merge_funnel_in2: endpoint { 2937 remote-endpoint = 2938 <&funnel2_out>; 2939 }; 2940 }; 2941 }; 2942 }; 2943 2944 replicator@6046000 { 2945 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2946 reg = <0 0x06046000 0 0x1000>; 2947 2948 clocks = <&aoss_qmp>; 2949 clock-names = "apb_pclk"; 2950 2951 out-ports { 2952 port { 2953 replicator_out: endpoint { 2954 remote-endpoint = <&etr_in>; 2955 }; 2956 }; 2957 }; 2958 2959 in-ports { 2960 port { 2961 replicator_in: endpoint { 2962 remote-endpoint = <&etf_out>; 2963 }; 2964 }; 2965 }; 2966 }; 2967 2968 etf@6047000 { 2969 compatible = "arm,coresight-tmc", "arm,primecell"; 2970 reg = <0 0x06047000 0 0x1000>; 2971 2972 clocks = <&aoss_qmp>; 2973 clock-names = "apb_pclk"; 2974 2975 out-ports { 2976 port { 2977 etf_out: endpoint { 2978 remote-endpoint = 2979 <&replicator_in>; 2980 }; 2981 }; 2982 }; 2983 2984 in-ports { 2985 #address-cells = <1>; 2986 #size-cells = <0>; 2987 2988 port@1 { 2989 reg = <1>; 2990 etf_in: endpoint { 2991 remote-endpoint = 2992 <&merge_funnel_out>; 2993 }; 2994 }; 2995 }; 2996 }; 2997 2998 etr@6048000 { 2999 compatible = "arm,coresight-tmc", "arm,primecell"; 3000 reg = <0 0x06048000 0 0x1000>; 3001 3002 clocks = <&aoss_qmp>; 3003 clock-names = "apb_pclk"; 3004 arm,scatter-gather; 3005 3006 in-ports { 3007 port { 3008 etr_in: endpoint { 3009 remote-endpoint = 3010 <&replicator_out>; 3011 }; 3012 }; 3013 }; 3014 }; 3015 3016 etm@7040000 { 3017 compatible = "arm,coresight-etm4x", "arm,primecell"; 3018 reg = <0 0x07040000 0 0x1000>; 3019 3020 cpu = <&CPU0>; 3021 3022 clocks = <&aoss_qmp>; 3023 clock-names = "apb_pclk"; 3024 arm,coresight-loses-context-with-cpu; 3025 3026 out-ports { 3027 port { 3028 etm0_out: endpoint { 3029 remote-endpoint = 3030 <&apss_funnel_in0>; 3031 }; 3032 }; 3033 }; 3034 }; 3035 3036 etm@7140000 { 3037 compatible = "arm,coresight-etm4x", "arm,primecell"; 3038 reg = <0 0x07140000 0 0x1000>; 3039 3040 cpu = <&CPU1>; 3041 3042 clocks = <&aoss_qmp>; 3043 clock-names = "apb_pclk"; 3044 arm,coresight-loses-context-with-cpu; 3045 3046 out-ports { 3047 port { 3048 etm1_out: endpoint { 3049 remote-endpoint = 3050 <&apss_funnel_in1>; 3051 }; 3052 }; 3053 }; 3054 }; 3055 3056 etm@7240000 { 3057 compatible = "arm,coresight-etm4x", "arm,primecell"; 3058 reg = <0 0x07240000 0 0x1000>; 3059 3060 cpu = <&CPU2>; 3061 3062 clocks = <&aoss_qmp>; 3063 clock-names = "apb_pclk"; 3064 arm,coresight-loses-context-with-cpu; 3065 3066 out-ports { 3067 port { 3068 etm2_out: endpoint { 3069 remote-endpoint = 3070 <&apss_funnel_in2>; 3071 }; 3072 }; 3073 }; 3074 }; 3075 3076 etm@7340000 { 3077 compatible = "arm,coresight-etm4x", "arm,primecell"; 3078 reg = <0 0x07340000 0 0x1000>; 3079 3080 cpu = <&CPU3>; 3081 3082 clocks = <&aoss_qmp>; 3083 clock-names = "apb_pclk"; 3084 arm,coresight-loses-context-with-cpu; 3085 3086 out-ports { 3087 port { 3088 etm3_out: endpoint { 3089 remote-endpoint = 3090 <&apss_funnel_in3>; 3091 }; 3092 }; 3093 }; 3094 }; 3095 3096 etm@7440000 { 3097 compatible = "arm,coresight-etm4x", "arm,primecell"; 3098 reg = <0 0x07440000 0 0x1000>; 3099 3100 cpu = <&CPU4>; 3101 3102 clocks = <&aoss_qmp>; 3103 clock-names = "apb_pclk"; 3104 arm,coresight-loses-context-with-cpu; 3105 3106 out-ports { 3107 port { 3108 etm4_out: endpoint { 3109 remote-endpoint = 3110 <&apss_funnel_in4>; 3111 }; 3112 }; 3113 }; 3114 }; 3115 3116 etm@7540000 { 3117 compatible = "arm,coresight-etm4x", "arm,primecell"; 3118 reg = <0 0x07540000 0 0x1000>; 3119 3120 cpu = <&CPU5>; 3121 3122 clocks = <&aoss_qmp>; 3123 clock-names = "apb_pclk"; 3124 arm,coresight-loses-context-with-cpu; 3125 3126 out-ports { 3127 port { 3128 etm5_out: endpoint { 3129 remote-endpoint = 3130 <&apss_funnel_in5>; 3131 }; 3132 }; 3133 }; 3134 }; 3135 3136 etm@7640000 { 3137 compatible = "arm,coresight-etm4x", "arm,primecell"; 3138 reg = <0 0x07640000 0 0x1000>; 3139 3140 cpu = <&CPU6>; 3141 3142 clocks = <&aoss_qmp>; 3143 clock-names = "apb_pclk"; 3144 arm,coresight-loses-context-with-cpu; 3145 3146 out-ports { 3147 port { 3148 etm6_out: endpoint { 3149 remote-endpoint = 3150 <&apss_funnel_in6>; 3151 }; 3152 }; 3153 }; 3154 }; 3155 3156 etm@7740000 { 3157 compatible = "arm,coresight-etm4x", "arm,primecell"; 3158 reg = <0 0x07740000 0 0x1000>; 3159 3160 cpu = <&CPU7>; 3161 3162 clocks = <&aoss_qmp>; 3163 clock-names = "apb_pclk"; 3164 arm,coresight-loses-context-with-cpu; 3165 3166 out-ports { 3167 port { 3168 etm7_out: endpoint { 3169 remote-endpoint = 3170 <&apss_funnel_in7>; 3171 }; 3172 }; 3173 }; 3174 }; 3175 3176 funnel@7800000 { /* APSS Funnel */ 3177 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3178 reg = <0 0x07800000 0 0x1000>; 3179 3180 clocks = <&aoss_qmp>; 3181 clock-names = "apb_pclk"; 3182 3183 out-ports { 3184 port { 3185 apss_funnel_out: endpoint { 3186 remote-endpoint = 3187 <&apss_merge_funnel_in>; 3188 }; 3189 }; 3190 }; 3191 3192 in-ports { 3193 #address-cells = <1>; 3194 #size-cells = <0>; 3195 3196 port@0 { 3197 reg = <0>; 3198 apss_funnel_in0: endpoint { 3199 remote-endpoint = 3200 <&etm0_out>; 3201 }; 3202 }; 3203 3204 port@1 { 3205 reg = <1>; 3206 apss_funnel_in1: endpoint { 3207 remote-endpoint = 3208 <&etm1_out>; 3209 }; 3210 }; 3211 3212 port@2 { 3213 reg = <2>; 3214 apss_funnel_in2: endpoint { 3215 remote-endpoint = 3216 <&etm2_out>; 3217 }; 3218 }; 3219 3220 port@3 { 3221 reg = <3>; 3222 apss_funnel_in3: endpoint { 3223 remote-endpoint = 3224 <&etm3_out>; 3225 }; 3226 }; 3227 3228 port@4 { 3229 reg = <4>; 3230 apss_funnel_in4: endpoint { 3231 remote-endpoint = 3232 <&etm4_out>; 3233 }; 3234 }; 3235 3236 port@5 { 3237 reg = <5>; 3238 apss_funnel_in5: endpoint { 3239 remote-endpoint = 3240 <&etm5_out>; 3241 }; 3242 }; 3243 3244 port@6 { 3245 reg = <6>; 3246 apss_funnel_in6: endpoint { 3247 remote-endpoint = 3248 <&etm6_out>; 3249 }; 3250 }; 3251 3252 port@7 { 3253 reg = <7>; 3254 apss_funnel_in7: endpoint { 3255 remote-endpoint = 3256 <&etm7_out>; 3257 }; 3258 }; 3259 }; 3260 }; 3261 3262 funnel@7810000 { 3263 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3264 reg = <0 0x07810000 0 0x1000>; 3265 3266 clocks = <&aoss_qmp>; 3267 clock-names = "apb_pclk"; 3268 3269 out-ports { 3270 port { 3271 apss_merge_funnel_out: endpoint { 3272 remote-endpoint = 3273 <&funnel2_in5>; 3274 }; 3275 }; 3276 }; 3277 3278 in-ports { 3279 port { 3280 apss_merge_funnel_in: endpoint { 3281 remote-endpoint = 3282 <&apss_funnel_out>; 3283 }; 3284 }; 3285 }; 3286 }; 3287 3288 sdhc_2: sdhci@8804000 { 3289 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3290 reg = <0 0x08804000 0 0x1000>; 3291 3292 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3294 interrupt-names = "hc_irq", "pwr_irq"; 3295 3296 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3297 <&gcc GCC_SDCC2_APPS_CLK>; 3298 clock-names = "iface", "core"; 3299 iommus = <&apps_smmu 0xa0 0xf>; 3300 power-domains = <&rpmhpd SDM845_CX>; 3301 operating-points-v2 = <&sdhc2_opp_table>; 3302 3303 status = "disabled"; 3304 3305 sdhc2_opp_table: sdhc2-opp-table { 3306 compatible = "operating-points-v2"; 3307 3308 opp-9600000 { 3309 opp-hz = /bits/ 64 <9600000>; 3310 required-opps = <&rpmhpd_opp_min_svs>; 3311 }; 3312 3313 opp-19200000 { 3314 opp-hz = /bits/ 64 <19200000>; 3315 required-opps = <&rpmhpd_opp_low_svs>; 3316 }; 3317 3318 opp-100000000 { 3319 opp-hz = /bits/ 64 <100000000>; 3320 required-opps = <&rpmhpd_opp_svs>; 3321 }; 3322 3323 opp-201500000 { 3324 opp-hz = /bits/ 64 <201500000>; 3325 required-opps = <&rpmhpd_opp_svs_l1>; 3326 }; 3327 }; 3328 }; 3329 3330 qspi_opp_table: qspi-opp-table { 3331 compatible = "operating-points-v2"; 3332 3333 opp-19200000 { 3334 opp-hz = /bits/ 64 <19200000>; 3335 required-opps = <&rpmhpd_opp_min_svs>; 3336 }; 3337 3338 opp-100000000 { 3339 opp-hz = /bits/ 64 <100000000>; 3340 required-opps = <&rpmhpd_opp_low_svs>; 3341 }; 3342 3343 opp-150000000 { 3344 opp-hz = /bits/ 64 <150000000>; 3345 required-opps = <&rpmhpd_opp_svs>; 3346 }; 3347 3348 opp-300000000 { 3349 opp-hz = /bits/ 64 <300000000>; 3350 required-opps = <&rpmhpd_opp_nom>; 3351 }; 3352 }; 3353 3354 qspi: spi@88df000 { 3355 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3356 reg = <0 0x088df000 0 0x600>; 3357 #address-cells = <1>; 3358 #size-cells = <0>; 3359 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3360 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3361 <&gcc GCC_QSPI_CORE_CLK>; 3362 clock-names = "iface", "core"; 3363 power-domains = <&rpmhpd SDM845_CX>; 3364 operating-points-v2 = <&qspi_opp_table>; 3365 status = "disabled"; 3366 }; 3367 3368 slim: slim@171c0000 { 3369 compatible = "qcom,slim-ngd-v2.1.0"; 3370 reg = <0 0x171c0000 0 0x2c000>; 3371 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3372 3373 qcom,apps-ch-pipes = <0x780000>; 3374 qcom,ea-pc = <0x270>; 3375 status = "okay"; 3376 dmas = <&slimbam 3>, <&slimbam 4>, 3377 <&slimbam 5>, <&slimbam 6>; 3378 dma-names = "rx", "tx", "tx2", "rx2"; 3379 3380 iommus = <&apps_smmu 0x1806 0x0>; 3381 #address-cells = <1>; 3382 #size-cells = <0>; 3383 3384 ngd@1 { 3385 reg = <1>; 3386 #address-cells = <2>; 3387 #size-cells = <0>; 3388 3389 wcd9340_ifd: ifd@0{ 3390 compatible = "slim217,250"; 3391 reg = <0 0>; 3392 }; 3393 3394 wcd9340: codec@1{ 3395 compatible = "slim217,250"; 3396 reg = <1 0>; 3397 slim-ifc-dev = <&wcd9340_ifd>; 3398 3399 #sound-dai-cells = <1>; 3400 3401 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; 3402 interrupt-controller; 3403 #interrupt-cells = <1>; 3404 3405 #clock-cells = <0>; 3406 clock-frequency = <9600000>; 3407 clock-output-names = "mclk"; 3408 qcom,micbias1-millivolt = <1800>; 3409 qcom,micbias2-millivolt = <1800>; 3410 qcom,micbias3-millivolt = <1800>; 3411 qcom,micbias4-millivolt = <1800>; 3412 3413 #address-cells = <1>; 3414 #size-cells = <1>; 3415 3416 wcdgpio: gpio-controller@42 { 3417 compatible = "qcom,wcd9340-gpio"; 3418 gpio-controller; 3419 #gpio-cells = <2>; 3420 reg = <0x42 0x2>; 3421 }; 3422 3423 swm: swm@c85 { 3424 compatible = "qcom,soundwire-v1.3.0"; 3425 reg = <0xc85 0x40>; 3426 interrupts-extended = <&wcd9340 20>; 3427 3428 qcom,dout-ports = <6>; 3429 qcom,din-ports = <2>; 3430 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 3431 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 3432 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; 3433 3434 #sound-dai-cells = <1>; 3435 clocks = <&wcd9340>; 3436 clock-names = "iface"; 3437 #address-cells = <2>; 3438 #size-cells = <0>; 3439 3440 3441 }; 3442 }; 3443 }; 3444 }; 3445 3446 sound: sound { 3447 }; 3448 3449 usb_1_hsphy: phy@88e2000 { 3450 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3451 reg = <0 0x088e2000 0 0x400>; 3452 status = "disabled"; 3453 #phy-cells = <0>; 3454 3455 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3456 <&rpmhcc RPMH_CXO_CLK>; 3457 clock-names = "cfg_ahb", "ref"; 3458 3459 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3460 3461 nvmem-cells = <&qusb2p_hstx_trim>; 3462 }; 3463 3464 usb_2_hsphy: phy@88e3000 { 3465 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3466 reg = <0 0x088e3000 0 0x400>; 3467 status = "disabled"; 3468 #phy-cells = <0>; 3469 3470 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3471 <&rpmhcc RPMH_CXO_CLK>; 3472 clock-names = "cfg_ahb", "ref"; 3473 3474 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3475 3476 nvmem-cells = <&qusb2s_hstx_trim>; 3477 }; 3478 3479 usb_1_qmpphy: phy@88e9000 { 3480 compatible = "qcom,sdm845-qmp-usb3-phy"; 3481 reg = <0 0x088e9000 0 0x18c>, 3482 <0 0x088e8000 0 0x10>; 3483 reg-names = "reg-base", "dp_com"; 3484 status = "disabled"; 3485 #clock-cells = <1>; 3486 #address-cells = <2>; 3487 #size-cells = <2>; 3488 ranges; 3489 3490 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3491 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3492 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3493 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3494 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3495 3496 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3497 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3498 reset-names = "phy", "common"; 3499 3500 usb_1_ssphy: lanes@88e9200 { 3501 reg = <0 0x088e9200 0 0x128>, 3502 <0 0x088e9400 0 0x200>, 3503 <0 0x088e9c00 0 0x218>, 3504 <0 0x088e9600 0 0x128>, 3505 <0 0x088e9800 0 0x200>, 3506 <0 0x088e9a00 0 0x100>; 3507 #phy-cells = <0>; 3508 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3509 clock-names = "pipe0"; 3510 clock-output-names = "usb3_phy_pipe_clk_src"; 3511 }; 3512 }; 3513 3514 usb_2_qmpphy: phy@88eb000 { 3515 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 3516 reg = <0 0x088eb000 0 0x18c>; 3517 status = "disabled"; 3518 #clock-cells = <1>; 3519 #address-cells = <2>; 3520 #size-cells = <2>; 3521 ranges; 3522 3523 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3524 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3525 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3526 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3527 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3528 3529 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3530 <&gcc GCC_USB3_PHY_SEC_BCR>; 3531 reset-names = "phy", "common"; 3532 3533 usb_2_ssphy: lane@88eb200 { 3534 reg = <0 0x088eb200 0 0x128>, 3535 <0 0x088eb400 0 0x1fc>, 3536 <0 0x088eb800 0 0x218>, 3537 <0 0x088eb600 0 0x70>; 3538 #phy-cells = <0>; 3539 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3540 clock-names = "pipe0"; 3541 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3542 }; 3543 }; 3544 3545 usb_1: usb@a6f8800 { 3546 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3547 reg = <0 0x0a6f8800 0 0x400>; 3548 status = "disabled"; 3549 #address-cells = <2>; 3550 #size-cells = <2>; 3551 ranges; 3552 dma-ranges; 3553 3554 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3555 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3556 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3557 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3558 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3559 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3560 "sleep"; 3561 3562 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3563 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3564 assigned-clock-rates = <19200000>, <150000000>; 3565 3566 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 3570 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3571 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3572 3573 power-domains = <&gcc USB30_PRIM_GDSC>; 3574 3575 resets = <&gcc GCC_USB30_PRIM_BCR>; 3576 3577 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 3578 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3579 interconnect-names = "usb-ddr", "apps-usb"; 3580 3581 usb_1_dwc3: dwc3@a600000 { 3582 compatible = "snps,dwc3"; 3583 reg = <0 0x0a600000 0 0xcd00>; 3584 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3585 iommus = <&apps_smmu 0x740 0>; 3586 snps,dis_u2_susphy_quirk; 3587 snps,dis_enblslpm_quirk; 3588 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3589 phy-names = "usb2-phy", "usb3-phy"; 3590 }; 3591 }; 3592 3593 usb_2: usb@a8f8800 { 3594 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3595 reg = <0 0x0a8f8800 0 0x400>; 3596 status = "disabled"; 3597 #address-cells = <2>; 3598 #size-cells = <2>; 3599 ranges; 3600 dma-ranges; 3601 3602 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3603 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3604 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3605 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3606 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 3607 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3608 "sleep"; 3609 3610 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3611 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3612 assigned-clock-rates = <19200000>, <150000000>; 3613 3614 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 3618 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3619 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3620 3621 power-domains = <&gcc USB30_SEC_GDSC>; 3622 3623 resets = <&gcc GCC_USB30_SEC_BCR>; 3624 3625 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 3626 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3627 interconnect-names = "usb-ddr", "apps-usb"; 3628 3629 usb_2_dwc3: dwc3@a800000 { 3630 compatible = "snps,dwc3"; 3631 reg = <0 0x0a800000 0 0xcd00>; 3632 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3633 iommus = <&apps_smmu 0x760 0>; 3634 snps,dis_u2_susphy_quirk; 3635 snps,dis_enblslpm_quirk; 3636 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3637 phy-names = "usb2-phy", "usb3-phy"; 3638 }; 3639 }; 3640 3641 venus: video-codec@aa00000 { 3642 compatible = "qcom,sdm845-venus-v2"; 3643 reg = <0 0x0aa00000 0 0xff000>; 3644 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3645 power-domains = <&videocc VENUS_GDSC>, 3646 <&videocc VCODEC0_GDSC>, 3647 <&videocc VCODEC1_GDSC>, 3648 <&rpmhpd SDM845_CX>; 3649 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 3650 operating-points-v2 = <&venus_opp_table>; 3651 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3652 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3653 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3654 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3655 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 3656 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 3657 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 3658 clock-names = "core", "iface", "bus", 3659 "vcodec0_core", "vcodec0_bus", 3660 "vcodec1_core", "vcodec1_bus"; 3661 iommus = <&apps_smmu 0x10a0 0x8>, 3662 <&apps_smmu 0x10b0 0x0>; 3663 memory-region = <&venus_mem>; 3664 3665 video-core0 { 3666 compatible = "venus-decoder"; 3667 }; 3668 3669 video-core1 { 3670 compatible = "venus-encoder"; 3671 }; 3672 3673 venus_opp_table: venus-opp-table { 3674 compatible = "operating-points-v2"; 3675 3676 opp-100000000 { 3677 opp-hz = /bits/ 64 <100000000>; 3678 required-opps = <&rpmhpd_opp_min_svs>; 3679 }; 3680 3681 opp-200000000 { 3682 opp-hz = /bits/ 64 <200000000>; 3683 required-opps = <&rpmhpd_opp_low_svs>; 3684 }; 3685 3686 opp-320000000 { 3687 opp-hz = /bits/ 64 <320000000>; 3688 required-opps = <&rpmhpd_opp_svs>; 3689 }; 3690 3691 opp-380000000 { 3692 opp-hz = /bits/ 64 <380000000>; 3693 required-opps = <&rpmhpd_opp_svs_l1>; 3694 }; 3695 3696 opp-444000000 { 3697 opp-hz = /bits/ 64 <444000000>; 3698 required-opps = <&rpmhpd_opp_nom>; 3699 }; 3700 3701 opp-533000097 { 3702 opp-hz = /bits/ 64 <533000097>; 3703 required-opps = <&rpmhpd_opp_turbo>; 3704 }; 3705 }; 3706 }; 3707 3708 videocc: clock-controller@ab00000 { 3709 compatible = "qcom,sdm845-videocc"; 3710 reg = <0 0x0ab00000 0 0x10000>; 3711 clocks = <&rpmhcc RPMH_CXO_CLK>; 3712 clock-names = "bi_tcxo"; 3713 #clock-cells = <1>; 3714 #power-domain-cells = <1>; 3715 #reset-cells = <1>; 3716 }; 3717 3718 cci: cci@ac4a000 { 3719 compatible = "qcom,sdm845-cci"; 3720 #address-cells = <1>; 3721 #size-cells = <0>; 3722 3723 reg = <0 0x0ac4a000 0 0x4000>; 3724 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3725 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 3726 3727 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3728 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 3729 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3730 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 3731 <&clock_camcc CAM_CC_CCI_CLK>, 3732 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 3733 clock-names = "camnoc_axi", 3734 "soc_ahb", 3735 "slow_ahb_src", 3736 "cpas_ahb", 3737 "cci", 3738 "cci_src"; 3739 3740 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3741 <&clock_camcc CAM_CC_CCI_CLK>; 3742 assigned-clock-rates = <80000000>, <37500000>; 3743 3744 pinctrl-names = "default", "sleep"; 3745 pinctrl-0 = <&cci0_default &cci1_default>; 3746 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 3747 3748 status = "disabled"; 3749 3750 cci_i2c0: i2c-bus@0 { 3751 reg = <0>; 3752 clock-frequency = <1000000>; 3753 #address-cells = <1>; 3754 #size-cells = <0>; 3755 }; 3756 3757 cci_i2c1: i2c-bus@1 { 3758 reg = <1>; 3759 clock-frequency = <1000000>; 3760 #address-cells = <1>; 3761 #size-cells = <0>; 3762 }; 3763 }; 3764 3765 clock_camcc: clock-controller@ad00000 { 3766 compatible = "qcom,sdm845-camcc"; 3767 reg = <0 0x0ad00000 0 0x10000>; 3768 #clock-cells = <1>; 3769 #reset-cells = <1>; 3770 #power-domain-cells = <1>; 3771 }; 3772 3773 dsi_opp_table: dsi-opp-table { 3774 compatible = "operating-points-v2"; 3775 3776 opp-19200000 { 3777 opp-hz = /bits/ 64 <19200000>; 3778 required-opps = <&rpmhpd_opp_min_svs>; 3779 }; 3780 3781 opp-180000000 { 3782 opp-hz = /bits/ 64 <180000000>; 3783 required-opps = <&rpmhpd_opp_low_svs>; 3784 }; 3785 3786 opp-275000000 { 3787 opp-hz = /bits/ 64 <275000000>; 3788 required-opps = <&rpmhpd_opp_svs>; 3789 }; 3790 3791 opp-328580000 { 3792 opp-hz = /bits/ 64 <328580000>; 3793 required-opps = <&rpmhpd_opp_svs_l1>; 3794 }; 3795 3796 opp-358000000 { 3797 opp-hz = /bits/ 64 <358000000>; 3798 required-opps = <&rpmhpd_opp_nom>; 3799 }; 3800 }; 3801 3802 mdss: mdss@ae00000 { 3803 compatible = "qcom,sdm845-mdss"; 3804 reg = <0 0x0ae00000 0 0x1000>; 3805 reg-names = "mdss"; 3806 3807 power-domains = <&dispcc MDSS_GDSC>; 3808 3809 clocks = <&gcc GCC_DISP_AHB_CLK>, 3810 <&gcc GCC_DISP_AXI_CLK>, 3811 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3812 clock-names = "iface", "bus", "core"; 3813 3814 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 3815 assigned-clock-rates = <300000000>; 3816 3817 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3818 interrupt-controller; 3819 #interrupt-cells = <1>; 3820 3821 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 3822 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 3823 interconnect-names = "mdp0-mem", "mdp1-mem"; 3824 3825 iommus = <&apps_smmu 0x880 0x8>, 3826 <&apps_smmu 0xc80 0x8>; 3827 3828 status = "disabled"; 3829 3830 #address-cells = <2>; 3831 #size-cells = <2>; 3832 ranges; 3833 3834 mdss_mdp: mdp@ae01000 { 3835 compatible = "qcom,sdm845-dpu"; 3836 reg = <0 0x0ae01000 0 0x8f000>, 3837 <0 0x0aeb0000 0 0x2008>; 3838 reg-names = "mdp", "vbif"; 3839 3840 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3841 <&dispcc DISP_CC_MDSS_AXI_CLK>, 3842 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3843 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3844 clock-names = "iface", "bus", "core", "vsync"; 3845 3846 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3847 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3848 assigned-clock-rates = <300000000>, 3849 <19200000>; 3850 operating-points-v2 = <&mdp_opp_table>; 3851 power-domains = <&rpmhpd SDM845_CX>; 3852 3853 interrupt-parent = <&mdss>; 3854 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 3855 3856 status = "disabled"; 3857 3858 ports { 3859 #address-cells = <1>; 3860 #size-cells = <0>; 3861 3862 port@0 { 3863 reg = <0>; 3864 dpu_intf1_out: endpoint { 3865 remote-endpoint = <&dsi0_in>; 3866 }; 3867 }; 3868 3869 port@1 { 3870 reg = <1>; 3871 dpu_intf2_out: endpoint { 3872 remote-endpoint = <&dsi1_in>; 3873 }; 3874 }; 3875 }; 3876 3877 mdp_opp_table: mdp-opp-table { 3878 compatible = "operating-points-v2"; 3879 3880 opp-19200000 { 3881 opp-hz = /bits/ 64 <19200000>; 3882 required-opps = <&rpmhpd_opp_min_svs>; 3883 }; 3884 3885 opp-171428571 { 3886 opp-hz = /bits/ 64 <171428571>; 3887 required-opps = <&rpmhpd_opp_low_svs>; 3888 }; 3889 3890 opp-344000000 { 3891 opp-hz = /bits/ 64 <344000000>; 3892 required-opps = <&rpmhpd_opp_svs_l1>; 3893 }; 3894 3895 opp-430000000 { 3896 opp-hz = /bits/ 64 <430000000>; 3897 required-opps = <&rpmhpd_opp_nom>; 3898 }; 3899 }; 3900 }; 3901 3902 dsi0: dsi@ae94000 { 3903 compatible = "qcom,mdss-dsi-ctrl"; 3904 reg = <0 0x0ae94000 0 0x400>; 3905 reg-names = "dsi_ctrl"; 3906 3907 interrupt-parent = <&mdss>; 3908 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 3909 3910 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3911 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3912 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3913 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3914 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3915 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3916 clock-names = "byte", 3917 "byte_intf", 3918 "pixel", 3919 "core", 3920 "iface", 3921 "bus"; 3922 operating-points-v2 = <&dsi_opp_table>; 3923 power-domains = <&rpmhpd SDM845_CX>; 3924 3925 phys = <&dsi0_phy>; 3926 phy-names = "dsi"; 3927 3928 status = "disabled"; 3929 3930 ports { 3931 #address-cells = <1>; 3932 #size-cells = <0>; 3933 3934 port@0 { 3935 reg = <0>; 3936 dsi0_in: endpoint { 3937 remote-endpoint = <&dpu_intf1_out>; 3938 }; 3939 }; 3940 3941 port@1 { 3942 reg = <1>; 3943 dsi0_out: endpoint { 3944 }; 3945 }; 3946 }; 3947 }; 3948 3949 dsi0_phy: dsi-phy@ae94400 { 3950 compatible = "qcom,dsi-phy-10nm"; 3951 reg = <0 0x0ae94400 0 0x200>, 3952 <0 0x0ae94600 0 0x280>, 3953 <0 0x0ae94a00 0 0x1e0>; 3954 reg-names = "dsi_phy", 3955 "dsi_phy_lane", 3956 "dsi_pll"; 3957 3958 #clock-cells = <1>; 3959 #phy-cells = <0>; 3960 3961 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3962 <&rpmhcc RPMH_CXO_CLK>; 3963 clock-names = "iface", "ref"; 3964 3965 status = "disabled"; 3966 }; 3967 3968 dsi1: dsi@ae96000 { 3969 compatible = "qcom,mdss-dsi-ctrl"; 3970 reg = <0 0x0ae96000 0 0x400>; 3971 reg-names = "dsi_ctrl"; 3972 3973 interrupt-parent = <&mdss>; 3974 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 3975 3976 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3977 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3978 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3979 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3980 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3981 <&dispcc DISP_CC_MDSS_AXI_CLK>; 3982 clock-names = "byte", 3983 "byte_intf", 3984 "pixel", 3985 "core", 3986 "iface", 3987 "bus"; 3988 operating-points-v2 = <&dsi_opp_table>; 3989 power-domains = <&rpmhpd SDM845_CX>; 3990 3991 phys = <&dsi1_phy>; 3992 phy-names = "dsi"; 3993 3994 status = "disabled"; 3995 3996 ports { 3997 #address-cells = <1>; 3998 #size-cells = <0>; 3999 4000 port@0 { 4001 reg = <0>; 4002 dsi1_in: endpoint { 4003 remote-endpoint = <&dpu_intf2_out>; 4004 }; 4005 }; 4006 4007 port@1 { 4008 reg = <1>; 4009 dsi1_out: endpoint { 4010 }; 4011 }; 4012 }; 4013 }; 4014 4015 dsi1_phy: dsi-phy@ae96400 { 4016 compatible = "qcom,dsi-phy-10nm"; 4017 reg = <0 0x0ae96400 0 0x200>, 4018 <0 0x0ae96600 0 0x280>, 4019 <0 0x0ae96a00 0 0x10e>; 4020 reg-names = "dsi_phy", 4021 "dsi_phy_lane", 4022 "dsi_pll"; 4023 4024 #clock-cells = <1>; 4025 #phy-cells = <0>; 4026 4027 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4028 <&rpmhcc RPMH_CXO_CLK>; 4029 clock-names = "iface", "ref"; 4030 4031 status = "disabled"; 4032 }; 4033 }; 4034 4035 gpu: gpu@5000000 { 4036 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4037 #stream-id-cells = <16>; 4038 4039 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 4040 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4041 4042 /* 4043 * Look ma, no clocks! The GPU clocks and power are 4044 * controlled entirely by the GMU 4045 */ 4046 4047 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4048 4049 iommus = <&adreno_smmu 0>; 4050 4051 operating-points-v2 = <&gpu_opp_table>; 4052 4053 qcom,gmu = <&gmu>; 4054 4055 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4056 interconnect-names = "gfx-mem"; 4057 4058 gpu_opp_table: opp-table { 4059 compatible = "operating-points-v2"; 4060 4061 opp-710000000 { 4062 opp-hz = /bits/ 64 <710000000>; 4063 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4064 opp-peak-kBps = <7216000>; 4065 }; 4066 4067 opp-675000000 { 4068 opp-hz = /bits/ 64 <675000000>; 4069 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4070 opp-peak-kBps = <7216000>; 4071 }; 4072 4073 opp-596000000 { 4074 opp-hz = /bits/ 64 <596000000>; 4075 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4076 opp-peak-kBps = <6220000>; 4077 }; 4078 4079 opp-520000000 { 4080 opp-hz = /bits/ 64 <520000000>; 4081 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4082 opp-peak-kBps = <6220000>; 4083 }; 4084 4085 opp-414000000 { 4086 opp-hz = /bits/ 64 <414000000>; 4087 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4088 opp-peak-kBps = <4068000>; 4089 }; 4090 4091 opp-342000000 { 4092 opp-hz = /bits/ 64 <342000000>; 4093 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4094 opp-peak-kBps = <2724000>; 4095 }; 4096 4097 opp-257000000 { 4098 opp-hz = /bits/ 64 <257000000>; 4099 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4100 opp-peak-kBps = <1648000>; 4101 }; 4102 }; 4103 }; 4104 4105 adreno_smmu: iommu@5040000 { 4106 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 4107 reg = <0 0x5040000 0 0x10000>; 4108 #iommu-cells = <1>; 4109 #global-interrupts = <2>; 4110 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4113 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4114 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4115 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4116 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4117 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4118 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4119 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4120 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4121 <&gcc GCC_GPU_CFG_AHB_CLK>; 4122 clock-names = "bus", "iface"; 4123 4124 power-domains = <&gpucc GPU_CX_GDSC>; 4125 }; 4126 4127 gmu: gmu@506a000 { 4128 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4129 4130 reg = <0 0x506a000 0 0x30000>, 4131 <0 0xb280000 0 0x10000>, 4132 <0 0xb480000 0 0x10000>; 4133 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4134 4135 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4137 interrupt-names = "hfi", "gmu"; 4138 4139 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4140 <&gpucc GPU_CC_CXO_CLK>, 4141 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4142 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4143 clock-names = "gmu", "cxo", "axi", "memnoc"; 4144 4145 power-domains = <&gpucc GPU_CX_GDSC>, 4146 <&gpucc GPU_GX_GDSC>; 4147 power-domain-names = "cx", "gx"; 4148 4149 iommus = <&adreno_smmu 5>; 4150 4151 operating-points-v2 = <&gmu_opp_table>; 4152 4153 gmu_opp_table: opp-table { 4154 compatible = "operating-points-v2"; 4155 4156 opp-400000000 { 4157 opp-hz = /bits/ 64 <400000000>; 4158 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4159 }; 4160 4161 opp-200000000 { 4162 opp-hz = /bits/ 64 <200000000>; 4163 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4164 }; 4165 }; 4166 }; 4167 4168 dispcc: clock-controller@af00000 { 4169 compatible = "qcom,sdm845-dispcc"; 4170 reg = <0 0x0af00000 0 0x10000>; 4171 clocks = <&rpmhcc RPMH_CXO_CLK>, 4172 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4173 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4174 <&dsi0_phy 0>, 4175 <&dsi0_phy 1>, 4176 <&dsi1_phy 0>, 4177 <&dsi1_phy 1>, 4178 <0>, 4179 <0>; 4180 clock-names = "bi_tcxo", 4181 "gcc_disp_gpll0_clk_src", 4182 "gcc_disp_gpll0_div_clk_src", 4183 "dsi0_phy_pll_out_byteclk", 4184 "dsi0_phy_pll_out_dsiclk", 4185 "dsi1_phy_pll_out_byteclk", 4186 "dsi1_phy_pll_out_dsiclk", 4187 "dp_link_clk_divsel_ten", 4188 "dp_vco_divided_clk_src_mux"; 4189 #clock-cells = <1>; 4190 #reset-cells = <1>; 4191 #power-domain-cells = <1>; 4192 }; 4193 4194 pdc_intc: interrupt-controller@b220000 { 4195 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4196 reg = <0 0x0b220000 0 0x30000>; 4197 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4198 #interrupt-cells = <2>; 4199 interrupt-parent = <&intc>; 4200 interrupt-controller; 4201 }; 4202 4203 pdc_reset: reset-controller@b2e0000 { 4204 compatible = "qcom,sdm845-pdc-global"; 4205 reg = <0 0x0b2e0000 0 0x20000>; 4206 #reset-cells = <1>; 4207 }; 4208 4209 tsens0: thermal-sensor@c263000 { 4210 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4211 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4212 <0 0x0c222000 0 0x1ff>; /* SROT */ 4213 #qcom,sensors = <13>; 4214 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4216 interrupt-names = "uplow", "critical"; 4217 #thermal-sensor-cells = <1>; 4218 }; 4219 4220 tsens1: thermal-sensor@c265000 { 4221 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4222 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4223 <0 0x0c223000 0 0x1ff>; /* SROT */ 4224 #qcom,sensors = <8>; 4225 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4227 interrupt-names = "uplow", "critical"; 4228 #thermal-sensor-cells = <1>; 4229 }; 4230 4231 aoss_reset: reset-controller@c2a0000 { 4232 compatible = "qcom,sdm845-aoss-cc"; 4233 reg = <0 0x0c2a0000 0 0x31000>; 4234 #reset-cells = <1>; 4235 }; 4236 4237 aoss_qmp: qmp@c300000 { 4238 compatible = "qcom,sdm845-aoss-qmp"; 4239 reg = <0 0x0c300000 0 0x100000>; 4240 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4241 mboxes = <&apss_shared 0>; 4242 4243 #clock-cells = <0>; 4244 #power-domain-cells = <1>; 4245 4246 cx_cdev: cx { 4247 #cooling-cells = <2>; 4248 }; 4249 4250 ebi_cdev: ebi { 4251 #cooling-cells = <2>; 4252 }; 4253 }; 4254 4255 spmi_bus: spmi@c440000 { 4256 compatible = "qcom,spmi-pmic-arb"; 4257 reg = <0 0x0c440000 0 0x1100>, 4258 <0 0x0c600000 0 0x2000000>, 4259 <0 0x0e600000 0 0x100000>, 4260 <0 0x0e700000 0 0xa0000>, 4261 <0 0x0c40a000 0 0x26000>; 4262 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4263 interrupt-names = "periph_irq"; 4264 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4265 qcom,ee = <0>; 4266 qcom,channel = <0>; 4267 #address-cells = <2>; 4268 #size-cells = <0>; 4269 interrupt-controller; 4270 #interrupt-cells = <4>; 4271 cell-index = <0>; 4272 }; 4273 4274 imem@146bf000 { 4275 compatible = "simple-mfd"; 4276 reg = <0 0x146bf000 0 0x1000>; 4277 4278 #address-cells = <1>; 4279 #size-cells = <1>; 4280 4281 ranges = <0 0 0x146bf000 0x1000>; 4282 4283 pil-reloc@94c { 4284 compatible = "qcom,pil-reloc-info"; 4285 reg = <0x94c 0xc8>; 4286 }; 4287 }; 4288 4289 apps_smmu: iommu@15000000 { 4290 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 4291 reg = <0 0x15000000 0 0x80000>; 4292 #iommu-cells = <2>; 4293 #global-interrupts = <1>; 4294 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 4359 }; 4360 4361 lpasscc: clock-controller@17014000 { 4362 compatible = "qcom,sdm845-lpasscc"; 4363 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 4364 reg-names = "cc", "qdsp6ss"; 4365 #clock-cells = <1>; 4366 status = "disabled"; 4367 }; 4368 4369 gladiator_noc: interconnect@17900000 { 4370 compatible = "qcom,sdm845-gladiator-noc"; 4371 reg = <0 0x17900000 0 0xd080>; 4372 #interconnect-cells = <2>; 4373 qcom,bcm-voters = <&apps_bcm_voter>; 4374 }; 4375 4376 watchdog@17980000 { 4377 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 4378 reg = <0 0x17980000 0 0x1000>; 4379 clocks = <&sleep_clk>; 4380 }; 4381 4382 apss_shared: mailbox@17990000 { 4383 compatible = "qcom,sdm845-apss-shared"; 4384 reg = <0 0x17990000 0 0x1000>; 4385 #mbox-cells = <1>; 4386 }; 4387 4388 apps_rsc: rsc@179c0000 { 4389 label = "apps_rsc"; 4390 compatible = "qcom,rpmh-rsc"; 4391 reg = <0 0x179c0000 0 0x10000>, 4392 <0 0x179d0000 0 0x10000>, 4393 <0 0x179e0000 0 0x10000>; 4394 reg-names = "drv-0", "drv-1", "drv-2"; 4395 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4396 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4397 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4398 qcom,tcs-offset = <0xd00>; 4399 qcom,drv-id = <2>; 4400 qcom,tcs-config = <ACTIVE_TCS 2>, 4401 <SLEEP_TCS 3>, 4402 <WAKE_TCS 3>, 4403 <CONTROL_TCS 1>; 4404 4405 apps_bcm_voter: bcm-voter { 4406 compatible = "qcom,bcm-voter"; 4407 }; 4408 4409 rpmhcc: clock-controller { 4410 compatible = "qcom,sdm845-rpmh-clk"; 4411 #clock-cells = <1>; 4412 clock-names = "xo"; 4413 clocks = <&xo_board>; 4414 }; 4415 4416 rpmhpd: power-controller { 4417 compatible = "qcom,sdm845-rpmhpd"; 4418 #power-domain-cells = <1>; 4419 operating-points-v2 = <&rpmhpd_opp_table>; 4420 4421 rpmhpd_opp_table: opp-table { 4422 compatible = "operating-points-v2"; 4423 4424 rpmhpd_opp_ret: opp1 { 4425 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4426 }; 4427 4428 rpmhpd_opp_min_svs: opp2 { 4429 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4430 }; 4431 4432 rpmhpd_opp_low_svs: opp3 { 4433 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4434 }; 4435 4436 rpmhpd_opp_svs: opp4 { 4437 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4438 }; 4439 4440 rpmhpd_opp_svs_l1: opp5 { 4441 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4442 }; 4443 4444 rpmhpd_opp_nom: opp6 { 4445 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4446 }; 4447 4448 rpmhpd_opp_nom_l1: opp7 { 4449 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4450 }; 4451 4452 rpmhpd_opp_nom_l2: opp8 { 4453 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4454 }; 4455 4456 rpmhpd_opp_turbo: opp9 { 4457 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4458 }; 4459 4460 rpmhpd_opp_turbo_l1: opp10 { 4461 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4462 }; 4463 }; 4464 }; 4465 }; 4466 4467 intc: interrupt-controller@17a00000 { 4468 compatible = "arm,gic-v3"; 4469 #address-cells = <2>; 4470 #size-cells = <2>; 4471 ranges; 4472 #interrupt-cells = <3>; 4473 interrupt-controller; 4474 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4475 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4476 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4477 4478 msi-controller@17a40000 { 4479 compatible = "arm,gic-v3-its"; 4480 msi-controller; 4481 #msi-cells = <1>; 4482 reg = <0 0x17a40000 0 0x20000>; 4483 status = "disabled"; 4484 }; 4485 }; 4486 4487 slimbam: dma@17184000 { 4488 compatible = "qcom,bam-v1.7.0"; 4489 qcom,controlled-remotely; 4490 reg = <0 0x17184000 0 0x2a000>; 4491 num-channels = <31>; 4492 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 4493 #dma-cells = <1>; 4494 qcom,ee = <1>; 4495 qcom,num-ees = <2>; 4496 iommus = <&apps_smmu 0x1806 0x0>; 4497 }; 4498 4499 timer@17c90000 { 4500 #address-cells = <2>; 4501 #size-cells = <2>; 4502 ranges; 4503 compatible = "arm,armv7-timer-mem"; 4504 reg = <0 0x17c90000 0 0x1000>; 4505 4506 frame@17ca0000 { 4507 frame-number = <0>; 4508 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 4509 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4510 reg = <0 0x17ca0000 0 0x1000>, 4511 <0 0x17cb0000 0 0x1000>; 4512 }; 4513 4514 frame@17cc0000 { 4515 frame-number = <1>; 4516 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 4517 reg = <0 0x17cc0000 0 0x1000>; 4518 status = "disabled"; 4519 }; 4520 4521 frame@17cd0000 { 4522 frame-number = <2>; 4523 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4524 reg = <0 0x17cd0000 0 0x1000>; 4525 status = "disabled"; 4526 }; 4527 4528 frame@17ce0000 { 4529 frame-number = <3>; 4530 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4531 reg = <0 0x17ce0000 0 0x1000>; 4532 status = "disabled"; 4533 }; 4534 4535 frame@17cf0000 { 4536 frame-number = <4>; 4537 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4538 reg = <0 0x17cf0000 0 0x1000>; 4539 status = "disabled"; 4540 }; 4541 4542 frame@17d00000 { 4543 frame-number = <5>; 4544 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4545 reg = <0 0x17d00000 0 0x1000>; 4546 status = "disabled"; 4547 }; 4548 4549 frame@17d10000 { 4550 frame-number = <6>; 4551 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4552 reg = <0 0x17d10000 0 0x1000>; 4553 status = "disabled"; 4554 }; 4555 }; 4556 4557 osm_l3: interconnect@17d41000 { 4558 compatible = "qcom,sdm845-osm-l3"; 4559 reg = <0 0x17d41000 0 0x1400>; 4560 4561 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4562 clock-names = "xo", "alternate"; 4563 4564 #interconnect-cells = <1>; 4565 }; 4566 4567 cpufreq_hw: cpufreq@17d43000 { 4568 compatible = "qcom,cpufreq-hw"; 4569 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 4570 reg-names = "freq-domain0", "freq-domain1"; 4571 4572 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4573 clock-names = "xo", "alternate"; 4574 4575 #freq-domain-cells = <1>; 4576 }; 4577 4578 wifi: wifi@18800000 { 4579 compatible = "qcom,wcn3990-wifi"; 4580 status = "disabled"; 4581 reg = <0 0x18800000 0 0x800000>; 4582 reg-names = "membase"; 4583 memory-region = <&wlan_msa_mem>; 4584 clock-names = "cxo_ref_clk_pin"; 4585 clocks = <&rpmhcc RPMH_RF_CLK2>; 4586 interrupts = 4587 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4588 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4589 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4590 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4591 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4592 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4594 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4595 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4596 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4598 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4599 iommus = <&apps_smmu 0x0040 0x1>; 4600 }; 4601 }; 4602 4603 thermal-zones { 4604 cpu0-thermal { 4605 polling-delay-passive = <250>; 4606 polling-delay = <1000>; 4607 4608 thermal-sensors = <&tsens0 1>; 4609 4610 trips { 4611 cpu0_alert0: trip-point0 { 4612 temperature = <90000>; 4613 hysteresis = <2000>; 4614 type = "passive"; 4615 }; 4616 4617 cpu0_alert1: trip-point1 { 4618 temperature = <95000>; 4619 hysteresis = <2000>; 4620 type = "passive"; 4621 }; 4622 4623 cpu0_crit: cpu_crit { 4624 temperature = <110000>; 4625 hysteresis = <1000>; 4626 type = "critical"; 4627 }; 4628 }; 4629 4630 cooling-maps { 4631 map0 { 4632 trip = <&cpu0_alert0>; 4633 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4634 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4635 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4636 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4637 }; 4638 map1 { 4639 trip = <&cpu0_alert1>; 4640 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4641 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4642 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4644 }; 4645 }; 4646 }; 4647 4648 cpu1-thermal { 4649 polling-delay-passive = <250>; 4650 polling-delay = <1000>; 4651 4652 thermal-sensors = <&tsens0 2>; 4653 4654 trips { 4655 cpu1_alert0: trip-point0 { 4656 temperature = <90000>; 4657 hysteresis = <2000>; 4658 type = "passive"; 4659 }; 4660 4661 cpu1_alert1: trip-point1 { 4662 temperature = <95000>; 4663 hysteresis = <2000>; 4664 type = "passive"; 4665 }; 4666 4667 cpu1_crit: cpu_crit { 4668 temperature = <110000>; 4669 hysteresis = <1000>; 4670 type = "critical"; 4671 }; 4672 }; 4673 4674 cooling-maps { 4675 map0 { 4676 trip = <&cpu1_alert0>; 4677 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4678 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4679 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4680 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4681 }; 4682 map1 { 4683 trip = <&cpu1_alert1>; 4684 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4686 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4687 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4688 }; 4689 }; 4690 }; 4691 4692 cpu2-thermal { 4693 polling-delay-passive = <250>; 4694 polling-delay = <1000>; 4695 4696 thermal-sensors = <&tsens0 3>; 4697 4698 trips { 4699 cpu2_alert0: trip-point0 { 4700 temperature = <90000>; 4701 hysteresis = <2000>; 4702 type = "passive"; 4703 }; 4704 4705 cpu2_alert1: trip-point1 { 4706 temperature = <95000>; 4707 hysteresis = <2000>; 4708 type = "passive"; 4709 }; 4710 4711 cpu2_crit: cpu_crit { 4712 temperature = <110000>; 4713 hysteresis = <1000>; 4714 type = "critical"; 4715 }; 4716 }; 4717 4718 cooling-maps { 4719 map0 { 4720 trip = <&cpu2_alert0>; 4721 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4722 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4723 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4724 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4725 }; 4726 map1 { 4727 trip = <&cpu2_alert1>; 4728 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4729 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4730 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4731 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4732 }; 4733 }; 4734 }; 4735 4736 cpu3-thermal { 4737 polling-delay-passive = <250>; 4738 polling-delay = <1000>; 4739 4740 thermal-sensors = <&tsens0 4>; 4741 4742 trips { 4743 cpu3_alert0: trip-point0 { 4744 temperature = <90000>; 4745 hysteresis = <2000>; 4746 type = "passive"; 4747 }; 4748 4749 cpu3_alert1: trip-point1 { 4750 temperature = <95000>; 4751 hysteresis = <2000>; 4752 type = "passive"; 4753 }; 4754 4755 cpu3_crit: cpu_crit { 4756 temperature = <110000>; 4757 hysteresis = <1000>; 4758 type = "critical"; 4759 }; 4760 }; 4761 4762 cooling-maps { 4763 map0 { 4764 trip = <&cpu3_alert0>; 4765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4766 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4767 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4768 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4769 }; 4770 map1 { 4771 trip = <&cpu3_alert1>; 4772 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4773 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4774 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4776 }; 4777 }; 4778 }; 4779 4780 cpu4-thermal { 4781 polling-delay-passive = <250>; 4782 polling-delay = <1000>; 4783 4784 thermal-sensors = <&tsens0 7>; 4785 4786 trips { 4787 cpu4_alert0: trip-point0 { 4788 temperature = <90000>; 4789 hysteresis = <2000>; 4790 type = "passive"; 4791 }; 4792 4793 cpu4_alert1: trip-point1 { 4794 temperature = <95000>; 4795 hysteresis = <2000>; 4796 type = "passive"; 4797 }; 4798 4799 cpu4_crit: cpu_crit { 4800 temperature = <110000>; 4801 hysteresis = <1000>; 4802 type = "critical"; 4803 }; 4804 }; 4805 4806 cooling-maps { 4807 map0 { 4808 trip = <&cpu4_alert0>; 4809 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4811 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4812 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4813 }; 4814 map1 { 4815 trip = <&cpu4_alert1>; 4816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4820 }; 4821 }; 4822 }; 4823 4824 cpu5-thermal { 4825 polling-delay-passive = <250>; 4826 polling-delay = <1000>; 4827 4828 thermal-sensors = <&tsens0 8>; 4829 4830 trips { 4831 cpu5_alert0: trip-point0 { 4832 temperature = <90000>; 4833 hysteresis = <2000>; 4834 type = "passive"; 4835 }; 4836 4837 cpu5_alert1: trip-point1 { 4838 temperature = <95000>; 4839 hysteresis = <2000>; 4840 type = "passive"; 4841 }; 4842 4843 cpu5_crit: cpu_crit { 4844 temperature = <110000>; 4845 hysteresis = <1000>; 4846 type = "critical"; 4847 }; 4848 }; 4849 4850 cooling-maps { 4851 map0 { 4852 trip = <&cpu5_alert0>; 4853 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4855 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4856 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4857 }; 4858 map1 { 4859 trip = <&cpu5_alert1>; 4860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4861 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4862 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4863 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4864 }; 4865 }; 4866 }; 4867 4868 cpu6-thermal { 4869 polling-delay-passive = <250>; 4870 polling-delay = <1000>; 4871 4872 thermal-sensors = <&tsens0 9>; 4873 4874 trips { 4875 cpu6_alert0: trip-point0 { 4876 temperature = <90000>; 4877 hysteresis = <2000>; 4878 type = "passive"; 4879 }; 4880 4881 cpu6_alert1: trip-point1 { 4882 temperature = <95000>; 4883 hysteresis = <2000>; 4884 type = "passive"; 4885 }; 4886 4887 cpu6_crit: cpu_crit { 4888 temperature = <110000>; 4889 hysteresis = <1000>; 4890 type = "critical"; 4891 }; 4892 }; 4893 4894 cooling-maps { 4895 map0 { 4896 trip = <&cpu6_alert0>; 4897 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4898 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4899 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4900 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4901 }; 4902 map1 { 4903 trip = <&cpu6_alert1>; 4904 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4906 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4907 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4908 }; 4909 }; 4910 }; 4911 4912 cpu7-thermal { 4913 polling-delay-passive = <250>; 4914 polling-delay = <1000>; 4915 4916 thermal-sensors = <&tsens0 10>; 4917 4918 trips { 4919 cpu7_alert0: trip-point0 { 4920 temperature = <90000>; 4921 hysteresis = <2000>; 4922 type = "passive"; 4923 }; 4924 4925 cpu7_alert1: trip-point1 { 4926 temperature = <95000>; 4927 hysteresis = <2000>; 4928 type = "passive"; 4929 }; 4930 4931 cpu7_crit: cpu_crit { 4932 temperature = <110000>; 4933 hysteresis = <1000>; 4934 type = "critical"; 4935 }; 4936 }; 4937 4938 cooling-maps { 4939 map0 { 4940 trip = <&cpu7_alert0>; 4941 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4942 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4943 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4944 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4945 }; 4946 map1 { 4947 trip = <&cpu7_alert1>; 4948 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4949 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4950 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4951 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4952 }; 4953 }; 4954 }; 4955 4956 aoss0-thermal { 4957 polling-delay-passive = <250>; 4958 polling-delay = <1000>; 4959 4960 thermal-sensors = <&tsens0 0>; 4961 4962 trips { 4963 aoss0_alert0: trip-point0 { 4964 temperature = <90000>; 4965 hysteresis = <2000>; 4966 type = "hot"; 4967 }; 4968 }; 4969 }; 4970 4971 cluster0-thermal { 4972 polling-delay-passive = <250>; 4973 polling-delay = <1000>; 4974 4975 thermal-sensors = <&tsens0 5>; 4976 4977 trips { 4978 cluster0_alert0: trip-point0 { 4979 temperature = <90000>; 4980 hysteresis = <2000>; 4981 type = "hot"; 4982 }; 4983 cluster0_crit: cluster0_crit { 4984 temperature = <110000>; 4985 hysteresis = <2000>; 4986 type = "critical"; 4987 }; 4988 }; 4989 }; 4990 4991 cluster1-thermal { 4992 polling-delay-passive = <250>; 4993 polling-delay = <1000>; 4994 4995 thermal-sensors = <&tsens0 6>; 4996 4997 trips { 4998 cluster1_alert0: trip-point0 { 4999 temperature = <90000>; 5000 hysteresis = <2000>; 5001 type = "hot"; 5002 }; 5003 cluster1_crit: cluster1_crit { 5004 temperature = <110000>; 5005 hysteresis = <2000>; 5006 type = "critical"; 5007 }; 5008 }; 5009 }; 5010 5011 gpu-thermal-top { 5012 polling-delay-passive = <250>; 5013 polling-delay = <1000>; 5014 5015 thermal-sensors = <&tsens0 11>; 5016 5017 trips { 5018 gpu1_alert0: trip-point0 { 5019 temperature = <90000>; 5020 hysteresis = <2000>; 5021 type = "hot"; 5022 }; 5023 }; 5024 }; 5025 5026 gpu-thermal-bottom { 5027 polling-delay-passive = <250>; 5028 polling-delay = <1000>; 5029 5030 thermal-sensors = <&tsens0 12>; 5031 5032 trips { 5033 gpu2_alert0: trip-point0 { 5034 temperature = <90000>; 5035 hysteresis = <2000>; 5036 type = "hot"; 5037 }; 5038 }; 5039 }; 5040 5041 aoss1-thermal { 5042 polling-delay-passive = <250>; 5043 polling-delay = <1000>; 5044 5045 thermal-sensors = <&tsens1 0>; 5046 5047 trips { 5048 aoss1_alert0: trip-point0 { 5049 temperature = <90000>; 5050 hysteresis = <2000>; 5051 type = "hot"; 5052 }; 5053 }; 5054 }; 5055 5056 q6-modem-thermal { 5057 polling-delay-passive = <250>; 5058 polling-delay = <1000>; 5059 5060 thermal-sensors = <&tsens1 1>; 5061 5062 trips { 5063 q6_modem_alert0: trip-point0 { 5064 temperature = <90000>; 5065 hysteresis = <2000>; 5066 type = "hot"; 5067 }; 5068 }; 5069 }; 5070 5071 mem-thermal { 5072 polling-delay-passive = <250>; 5073 polling-delay = <1000>; 5074 5075 thermal-sensors = <&tsens1 2>; 5076 5077 trips { 5078 mem_alert0: trip-point0 { 5079 temperature = <90000>; 5080 hysteresis = <2000>; 5081 type = "hot"; 5082 }; 5083 }; 5084 }; 5085 5086 wlan-thermal { 5087 polling-delay-passive = <250>; 5088 polling-delay = <1000>; 5089 5090 thermal-sensors = <&tsens1 3>; 5091 5092 trips { 5093 wlan_alert0: trip-point0 { 5094 temperature = <90000>; 5095 hysteresis = <2000>; 5096 type = "hot"; 5097 }; 5098 }; 5099 }; 5100 5101 q6-hvx-thermal { 5102 polling-delay-passive = <250>; 5103 polling-delay = <1000>; 5104 5105 thermal-sensors = <&tsens1 4>; 5106 5107 trips { 5108 q6_hvx_alert0: trip-point0 { 5109 temperature = <90000>; 5110 hysteresis = <2000>; 5111 type = "hot"; 5112 }; 5113 }; 5114 }; 5115 5116 camera-thermal { 5117 polling-delay-passive = <250>; 5118 polling-delay = <1000>; 5119 5120 thermal-sensors = <&tsens1 5>; 5121 5122 trips { 5123 camera_alert0: trip-point0 { 5124 temperature = <90000>; 5125 hysteresis = <2000>; 5126 type = "hot"; 5127 }; 5128 }; 5129 }; 5130 5131 video-thermal { 5132 polling-delay-passive = <250>; 5133 polling-delay = <1000>; 5134 5135 thermal-sensors = <&tsens1 6>; 5136 5137 trips { 5138 video_alert0: trip-point0 { 5139 temperature = <90000>; 5140 hysteresis = <2000>; 5141 type = "hot"; 5142 }; 5143 }; 5144 }; 5145 5146 modem-thermal { 5147 polling-delay-passive = <250>; 5148 polling-delay = <1000>; 5149 5150 thermal-sensors = <&tsens1 7>; 5151 5152 trips { 5153 modem_alert0: trip-point0 { 5154 temperature = <90000>; 5155 hysteresis = <2000>; 5156 type = "hot"; 5157 }; 5158 }; 5159 }; 5160 }; 5161}; 5162