1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Cheza device tree source (common between revisions) 4 * 5 * Copyright 2018 Google LLC. 6 */ 7 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 10#include "sdm845.dtsi" 11 12/* PMICs depend on spmi_bus label and so must come after SoC */ 13#include "pm8005.dtsi" 14#include "pm8998.dtsi" 15 16/ { 17 aliases { 18 bluetooth0 = &bluetooth; 19 hsuart0 = &uart6; 20 serial0 = &uart9; 21 wifi0 = &wifi; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 backlight: backlight { 29 compatible = "pwm-backlight"; 30 pwms = <&cros_ec_pwm 0>; 31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 32 power-supply = <&ppvar_sys>; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&ap_edp_bklten>; 35 }; 36 37 /* FIXED REGULATORS - parents above children */ 38 39 /* This is the top level supply and variable voltage */ 40 ppvar_sys: ppvar-sys-regulator { 41 compatible = "regulator-fixed"; 42 regulator-name = "ppvar_sys"; 43 regulator-always-on; 44 regulator-boot-on; 45 }; 46 47 /* This divides ppvar_sys by 2, so voltage is variable */ 48 src_vph_pwr: src-vph-pwr-regulator { 49 compatible = "regulator-fixed"; 50 regulator-name = "src_vph_pwr"; 51 52 /* EC turns on with switchcap_on_l; always on for AP */ 53 regulator-always-on; 54 regulator-boot-on; 55 56 vin-supply = <&ppvar_sys>; 57 }; 58 59 pp5000_a: pp5000-a-regulator { 60 compatible = "regulator-fixed"; 61 regulator-name = "pp5000_a"; 62 63 /* EC turns on with en_pp5000_a; always on for AP */ 64 regulator-always-on; 65 regulator-boot-on; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 69 vin-supply = <&ppvar_sys>; 70 }; 71 72 src_vreg_bob: src-vreg-bob-regulator { 73 compatible = "regulator-fixed"; 74 regulator-name = "src_vreg_bob"; 75 76 /* EC turns on with vbob_en; always on for AP */ 77 regulator-always-on; 78 regulator-boot-on; 79 regulator-min-microvolt = <3600000>; 80 regulator-max-microvolt = <3600000>; 81 82 vin-supply = <&ppvar_sys>; 83 }; 84 85 pp3300_dx_edp: pp3300-dx-edp-regulator { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp3300_dx_edp"; 88 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 92 gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&en_pp3300_dx_edp>; 96 }; 97 98 /* 99 * Apparently RPMh does not provide support for PM8998 S4 because it 100 * is always-on; model it as a fixed regulator. 101 */ 102 src_pp1800_s4a: pm8998-smps4 { 103 compatible = "regulator-fixed"; 104 regulator-name = "src_pp1800_s4a"; 105 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 109 regulator-always-on; 110 regulator-boot-on; 111 112 vin-supply = <&src_vph_pwr>; 113 }; 114 115 /* BOARD-SPECIFIC TOP LEVEL NODES */ 116 117 gpio-keys { 118 compatible = "gpio-keys"; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pen_eject_odl>; 121 122 pen-insert { 123 label = "Pen Insert"; 124 /* Insert = low, eject = high */ 125 gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; 126 linux,code = <SW_PEN_INSERTED>; 127 linux,input-type = <EV_SW>; 128 wakeup-source; 129 }; 130 }; 131 132 panel: panel { 133 compatible ="innolux,p120zdg-bf1"; 134 power-supply = <&pp3300_dx_edp>; 135 backlight = <&backlight>; 136 no-hpd; 137 138 ports { 139 panel_in: port { 140 panel_in_edp: endpoint { 141 remote-endpoint = <&sn65dsi86_out>; 142 }; 143 }; 144 }; 145 }; 146}; 147 148/* 149 * Reserved memory changes 150 * 151 * Putting this all together (out of order with the rest of the file) to keep 152 * all modifications to the memory map (from sdm845.dtsi) in one place. 153 */ 154 155/* 156 * Our mpss_region is 8MB bigger than the default one and that conflicts 157 * with venus_mem and cdsp_mem. 158 * 159 * For venus_mem we'll delete and re-create at a different address. 160 * 161 * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but 162 * that also means we need to delete cdsp_pas. 163 */ 164/delete-node/ &venus_mem; 165/delete-node/ &cdsp_mem; 166/delete-node/ &cdsp_pas; 167/delete-node/ &gpu_mem; 168 169/* Increase the size from 120 MB to 128 MB */ 170&mpss_region { 171 reg = <0 0x8e000000 0 0x8000000>; 172}; 173 174/* Increase the size from 2MB to 8MB */ 175&rmtfs_mem { 176 reg = <0 0x88f00000 0 0x800000>; 177}; 178 179/ { 180 reserved-memory { 181 venus_mem: memory@96000000 { 182 reg = <0 0x96000000 0 0x500000>; 183 no-map; 184 }; 185 }; 186}; 187 188&qspi { 189 status = "okay"; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; 192 193 flash@0 { 194 compatible = "jedec,spi-nor"; 195 reg = <0>; 196 197 /* 198 * In theory chip supports up to 104 MHz and controller up 199 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use 200 * that for now. b:117440651 201 */ 202 spi-max-frequency = <25000000>; 203 spi-tx-bus-width = <2>; 204 spi-rx-bus-width = <2>; 205 }; 206}; 207 208 209&apps_rsc { 210 pm8998-rpmh-regulators { 211 compatible = "qcom,pm8998-rpmh-regulators"; 212 qcom,pmic-id = "a"; 213 214 vdd-s1-supply = <&src_vph_pwr>; 215 vdd-s2-supply = <&src_vph_pwr>; 216 vdd-s3-supply = <&src_vph_pwr>; 217 vdd-s4-supply = <&src_vph_pwr>; 218 vdd-s5-supply = <&src_vph_pwr>; 219 vdd-s6-supply = <&src_vph_pwr>; 220 vdd-s7-supply = <&src_vph_pwr>; 221 vdd-s8-supply = <&src_vph_pwr>; 222 vdd-s9-supply = <&src_vph_pwr>; 223 vdd-s10-supply = <&src_vph_pwr>; 224 vdd-s11-supply = <&src_vph_pwr>; 225 vdd-s12-supply = <&src_vph_pwr>; 226 vdd-s13-supply = <&src_vph_pwr>; 227 vdd-l1-l27-supply = <&src_pp1025_s7a>; 228 vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; 229 vdd-l3-l11-supply = <&src_pp1025_s7a>; 230 vdd-l4-l5-supply = <&src_pp1025_s7a>; 231 vdd-l6-supply = <&src_vph_pwr>; 232 vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; 233 vdd-l9-supply = <&src_pp2040_s5a>; 234 vdd-l10-l23-l25-supply = <&src_vreg_bob>; 235 vdd-l13-l19-l21-supply = <&src_vreg_bob>; 236 vdd-l16-l28-supply = <&src_vreg_bob>; 237 vdd-l18-l22-supply = <&src_vreg_bob>; 238 vdd-l20-l24-supply = <&src_vreg_bob>; 239 vdd-l26-supply = <&src_pp1350_s3a>; 240 vin-lvs-1-2-supply = <&src_pp1800_s4a>; 241 242 src_pp1125_s2a: smps2 { 243 regulator-min-microvolt = <1100000>; 244 regulator-max-microvolt = <1100000>; 245 }; 246 247 src_pp1350_s3a: smps3 { 248 regulator-min-microvolt = <1352000>; 249 regulator-max-microvolt = <1352000>; 250 }; 251 252 src_pp2040_s5a: smps5 { 253 regulator-min-microvolt = <1904000>; 254 regulator-max-microvolt = <2040000>; 255 }; 256 257 src_pp1025_s7a: smps7 { 258 regulator-min-microvolt = <900000>; 259 regulator-max-microvolt = <1028000>; 260 }; 261 262 vdd_qusb_hs0: 263 vdda_hp_pcie_core: 264 vdda_mipi_csi0_0p9: 265 vdda_mipi_csi1_0p9: 266 vdda_mipi_csi2_0p9: 267 vdda_mipi_dsi0_pll: 268 vdda_mipi_dsi1_pll: 269 vdda_qlink_lv: 270 vdda_qlink_lv_ck: 271 vdda_qrefs_0p875: 272 vdda_pcie_core: 273 vdda_pll_cc_ebi01: 274 vdda_pll_cc_ebi23: 275 vdda_sp_sensor: 276 vdda_ufs1_core: 277 vdda_ufs2_core: 278 vdda_usb1_ss_core: 279 vdda_usb2_ss_core: 280 src_pp875_l1a: ldo1 { 281 regulator-min-microvolt = <880000>; 282 regulator-max-microvolt = <880000>; 283 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 284 }; 285 286 vddpx_10: 287 src_pp1200_l2a: ldo2 { 288 regulator-min-microvolt = <1200000>; 289 regulator-max-microvolt = <1200000>; 290 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 291 292 /* TODO: why??? */ 293 regulator-always-on; 294 }; 295 296 pp1000_l3a_sdr845: ldo3 { 297 regulator-min-microvolt = <1000000>; 298 regulator-max-microvolt = <1000000>; 299 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 300 }; 301 302 vdd_wcss_cx: 303 vdd_wcss_mx: 304 vdda_wcss_pll: 305 src_pp800_l5a: ldo5 { 306 regulator-min-microvolt = <800000>; 307 regulator-max-microvolt = <800000>; 308 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 309 }; 310 311 vddpx_13: 312 src_pp1800_l6a: ldo6 { 313 regulator-min-microvolt = <1856000>; 314 regulator-max-microvolt = <1856000>; 315 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 316 }; 317 318 pp1800_l7a_wcn3990: ldo7 { 319 regulator-min-microvolt = <1800000>; 320 regulator-max-microvolt = <1800000>; 321 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 322 }; 323 324 src_pp1200_l8a: ldo8 { 325 regulator-min-microvolt = <1200000>; 326 regulator-max-microvolt = <1248000>; 327 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 328 }; 329 330 pp1800_dx_pen: 331 src_pp1800_l9a: ldo9 { 332 regulator-min-microvolt = <1800000>; 333 regulator-max-microvolt = <1800000>; 334 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 335 }; 336 337 src_pp1800_l10a: ldo10 { 338 regulator-min-microvolt = <1800000>; 339 regulator-max-microvolt = <1800000>; 340 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 341 }; 342 343 pp1000_l11a_sdr845: ldo11 { 344 regulator-min-microvolt = <1000000>; 345 regulator-max-microvolt = <1048000>; 346 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 347 }; 348 349 vdd_qfprom: 350 vdd_qfprom_sp: 351 vdda_apc1_cs_1p8: 352 vdda_gfx_cs_1p8: 353 vdda_qrefs_1p8: 354 vdda_qusb_hs0_1p8: 355 vddpx_11: 356 src_pp1800_l12a: ldo12 { 357 regulator-min-microvolt = <1800000>; 358 regulator-max-microvolt = <1800000>; 359 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 360 }; 361 362 vddpx_2: 363 src_pp2950_l13a: ldo13 { 364 regulator-min-microvolt = <1800000>; 365 regulator-max-microvolt = <2960000>; 366 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 367 }; 368 369 src_pp1800_l14a: ldo14 { 370 regulator-min-microvolt = <1800000>; 371 regulator-max-microvolt = <1800000>; 372 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 373 }; 374 375 src_pp1800_l15a: ldo15 { 376 regulator-min-microvolt = <1800000>; 377 regulator-max-microvolt = <1800000>; 378 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 379 }; 380 381 pp2700_l16a: ldo16 { 382 regulator-min-microvolt = <2704000>; 383 regulator-max-microvolt = <2704000>; 384 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 385 }; 386 387 src_pp1300_l17a: ldo17 { 388 regulator-min-microvolt = <1304000>; 389 regulator-max-microvolt = <1304000>; 390 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 391 }; 392 393 pp2700_l18a: ldo18 { 394 regulator-min-microvolt = <2704000>; 395 regulator-max-microvolt = <2960000>; 396 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 397 }; 398 399 /* 400 * NOTE: this rail should have been called 401 * src_pp3300_l19a in the schematic 402 */ 403 src_pp3000_l19a: ldo19 { 404 regulator-min-microvolt = <3304000>; 405 regulator-max-microvolt = <3304000>; 406 407 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 408 }; 409 410 src_pp2950_l20a: ldo20 { 411 regulator-min-microvolt = <2704000>; 412 regulator-max-microvolt = <2960000>; 413 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 414 }; 415 416 src_pp2950_l21a: ldo21 { 417 regulator-min-microvolt = <2704000>; 418 regulator-max-microvolt = <2960000>; 419 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 420 }; 421 422 pp3300_hub: 423 src_pp3300_l22a: ldo22 { 424 regulator-min-microvolt = <3304000>; 425 regulator-max-microvolt = <3304000>; 426 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 427 /* 428 * HACK: Should add a usb hub node and driver 429 * to turn this on and off at suspend/resume time 430 */ 431 regulator-boot-on; 432 regulator-always-on; 433 }; 434 435 pp3300_l23a_ch1_wcn3990: ldo23 { 436 regulator-min-microvolt = <3000000>; 437 regulator-max-microvolt = <3312000>; 438 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 439 }; 440 441 vdda_qusb_hs0_3p1: 442 src_pp3075_l24a: ldo24 { 443 regulator-min-microvolt = <3088000>; 444 regulator-max-microvolt = <3088000>; 445 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 446 }; 447 448 pp3300_l25a_ch0_wcn3990: ldo25 { 449 regulator-min-microvolt = <3304000>; 450 regulator-max-microvolt = <3304000>; 451 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 452 }; 453 454 pp1200_hub: 455 vdda_hp_pcie_1p2: 456 vdda_hv_ebi0: 457 vdda_hv_ebi1: 458 vdda_hv_ebi2: 459 vdda_hv_ebi3: 460 vdda_mipi_csi_1p25: 461 vdda_mipi_dsi0_1p2: 462 vdda_mipi_dsi1_1p2: 463 vdda_pcie_1p2: 464 vdda_ufs1_1p2: 465 vdda_ufs2_1p2: 466 vdda_usb1_ss_1p2: 467 vdda_usb2_ss_1p2: 468 src_pp1200_l26a: ldo26 { 469 regulator-min-microvolt = <1200000>; 470 regulator-max-microvolt = <1200000>; 471 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 472 }; 473 474 pp3300_dx_pen: 475 src_pp3300_l28a: ldo28 { 476 regulator-min-microvolt = <3304000>; 477 regulator-max-microvolt = <3304000>; 478 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 479 }; 480 481 src_pp1800_lvs1: lvs1 { 482 regulator-min-microvolt = <1800000>; 483 regulator-max-microvolt = <1800000>; 484 }; 485 486 src_pp1800_lvs2: lvs2 { 487 regulator-min-microvolt = <1800000>; 488 regulator-max-microvolt = <1800000>; 489 }; 490 }; 491 492 pm8005-rpmh-regulators { 493 compatible = "qcom,pm8005-rpmh-regulators"; 494 qcom,pmic-id = "c"; 495 496 vdd-s1-supply = <&src_vph_pwr>; 497 vdd-s2-supply = <&src_vph_pwr>; 498 vdd-s3-supply = <&src_vph_pwr>; 499 vdd-s4-supply = <&src_vph_pwr>; 500 501 src_pp600_s3c: smps3 { 502 regulator-min-microvolt = <600000>; 503 regulator-max-microvolt = <600000>; 504 }; 505 }; 506}; 507 508&dsi0 { 509 status = "okay"; 510 vdda-supply = <&vdda_mipi_dsi0_1p2>; 511 512 ports { 513 port@1 { 514 endpoint { 515 remote-endpoint = <&sn65dsi86_in>; 516 data-lanes = <0 1 2 3>; 517 }; 518 }; 519 }; 520}; 521 522&dsi0_phy { 523 status = "okay"; 524 vdds-supply = <&vdda_mipi_dsi0_pll>; 525}; 526 527edp_brij_i2c: &i2c3 { 528 status = "okay"; 529 clock-frequency = <400000>; 530 531 sn65dsi86_bridge: bridge@2d { 532 compatible = "ti,sn65dsi86"; 533 reg = <0x2d>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&edp_brij_en &edp_brij_irq>; 536 537 interrupt-parent = <&tlmm>; 538 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 539 540 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 541 542 vpll-supply = <&src_pp1800_s4a>; 543 vccio-supply = <&src_pp1800_s4a>; 544 vcca-supply = <&src_pp1200_l2a>; 545 vcc-supply = <&src_pp1200_l2a>; 546 547 clocks = <&rpmhcc RPMH_LN_BB_CLK2>; 548 clock-names = "refclk"; 549 550 no-hpd; 551 552 ports { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 556 port@0 { 557 reg = <0>; 558 sn65dsi86_in: endpoint { 559 remote-endpoint = <&dsi0_out>; 560 }; 561 }; 562 563 port@1 { 564 reg = <1>; 565 sn65dsi86_out: endpoint { 566 remote-endpoint = <&panel_in_edp>; 567 }; 568 }; 569 }; 570 }; 571}; 572 573ap_pen_1v8: &i2c11 { 574 status = "okay"; 575 clock-frequency = <400000>; 576 577 digitizer@9 { 578 compatible = "wacom,w9013", "hid-over-i2c"; 579 reg = <0x9>; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; 582 583 vdd-supply = <&pp3300_dx_pen>; 584 vddl-supply = <&pp1800_dx_pen>; 585 post-power-on-delay-ms = <100>; 586 587 interrupt-parent = <&tlmm>; 588 interrupts = <24 IRQ_TYPE_LEVEL_LOW>; 589 590 hid-descr-addr = <0x1>; 591 }; 592}; 593 594amp_i2c: &i2c12 { 595 status = "okay"; 596 clock-frequency = <400000>; 597}; 598 599ap_ts_i2c: &i2c14 { 600 status = "okay"; 601 clock-frequency = <400000>; 602 603 touchscreen@10 { 604 compatible = "elan,ekth3500"; 605 reg = <0x10>; 606 pinctrl-names = "default"; 607 pinctrl-0 = <&ts_int_l &ts_reset_l>; 608 609 interrupt-parent = <&tlmm>; 610 interrupts = <125 IRQ_TYPE_LEVEL_LOW>; 611 612 vcc33-supply = <&src_pp3300_l28a>; 613 614 reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; 615 }; 616}; 617 618&gmu { 619 status = "okay"; 620}; 621 622&gpu { 623 status = "okay"; 624}; 625 626&ipa { 627 status = "okay"; 628 modem-init; 629}; 630 631&lpasscc { 632 status = "okay"; 633}; 634 635&mdss { 636 status = "okay"; 637}; 638 639/* 640 * Cheza fw does not properly program the GPU aperture to allow the 641 * GPU to update the SMMU pagetables for context switches. Work 642 * around this by dropping the "qcom,adreno-smmu" compat string. 643 */ 644&adreno_smmu { 645 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 646}; 647 648&mss_pil { 649 status = "okay"; 650 651 iommus = <&apps_smmu 0x781 0x0>, 652 <&apps_smmu 0x724 0x3>; 653}; 654 655&pm8998_pwrkey { 656 status = "disabled"; 657}; 658 659&qupv3_id_0 { 660 status = "okay"; 661 iommus = <&apps_smmu 0x0 0x3>; 662}; 663 664&qupv3_id_1 { 665 status = "okay"; 666 iommus = <&apps_smmu 0x6c0 0x3>; 667}; 668 669&sdhc_2 { 670 status = "okay"; 671 672 pinctrl-names = "default"; 673 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; 674 675 vmmc-supply = <&src_pp2950_l21a>; 676 vqmmc-supply = <&vddpx_2>; 677 678 cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; 679}; 680 681&spi0 { 682 status = "okay"; 683}; 684 685&spi5 { 686 status = "okay"; 687 688 tpm@0 { 689 compatible = "google,cr50"; 690 reg = <0>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&h1_ap_int_odl>; 693 spi-max-frequency = <800000>; 694 interrupt-parent = <&tlmm>; 695 interrupts = <129 IRQ_TYPE_EDGE_RISING>; 696 }; 697}; 698 699&spi10 { 700 status = "okay"; 701 702 cros_ec: ec@0 { 703 compatible = "google,cros-ec-spi"; 704 reg = <0>; 705 interrupt-parent = <&tlmm>; 706 interrupts = <122 IRQ_TYPE_LEVEL_LOW>; 707 pinctrl-names = "default"; 708 pinctrl-0 = <&ec_ap_int_l>; 709 spi-max-frequency = <3000000>; 710 711 cros_ec_pwm: pwm { 712 compatible = "google,cros-ec-pwm"; 713 #pwm-cells = <1>; 714 }; 715 716 i2c_tunnel: i2c-tunnel { 717 compatible = "google,cros-ec-i2c-tunnel"; 718 google,remote-bus = <0>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 }; 722 }; 723}; 724 725#include <arm/cros-ec-keyboard.dtsi> 726#include <arm/cros-ec-sbs.dtsi> 727 728&uart6 { 729 status = "okay"; 730 731 bluetooth: wcn3990-bt { 732 compatible = "qcom,wcn3990-bt"; 733 vddio-supply = <&src_pp1800_s4a>; 734 vddxo-supply = <&pp1800_l7a_wcn3990>; 735 vddrf-supply = <&src_pp1300_l17a>; 736 vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; 737 max-speed = <3200000>; 738 }; 739}; 740 741&uart9 { 742 status = "okay"; 743}; 744 745&ufs_mem_hc { 746 status = "okay"; 747 748 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; 749 750 vcc-supply = <&src_pp2950_l20a>; 751 vcc-max-microamp = <600000>; 752}; 753 754&ufs_mem_phy { 755 status = "okay"; 756 757 vdda-phy-supply = <&vdda_ufs1_core>; 758 vdda-pll-supply = <&vdda_ufs1_1p2>; 759}; 760 761&usb_1 { 762 status = "okay"; 763 764 /* We'll use this as USB 2.0 only */ 765 qcom,select-utmi-as-pipe-clk; 766}; 767 768&usb_1_dwc3 { 769 /* 770 * The hardware design intends this port to be hooked up in peripheral 771 * mode, so we'll hardcode it here. Some details: 772 * - SDM845 expects only a single Type C connector so it has only one 773 * native Type C port but cheza has two Type C connectors. 774 * - The only source of DP is the single native Type C port. 775 * - On cheza we want to be able to hook DP up to _either_ of the 776 * two Type C connectors and want to be able to achieve 4 lanes of DP. 777 * - When you configure a Type C port for 4 lanes of DP you lose USB3. 778 * - In order to make everything work, the native Type C port is always 779 * configured as 4-lanes DP so it's always available. 780 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then 781 * sent to the two Type C connectors. 782 * - The extra USB2 lines from the native Type C port are always 783 * setup as "peripheral" so that we can mux them over to one connector 784 * or the other if someone needs the connector configured as a gadget 785 * (but they only get USB2 speeds). 786 * 787 * All the hardware muxes would allow us to hook things up in different 788 * ways to some potential benefit for static configurations (you could 789 * achieve extra USB2 bandwidth by using two different ports for the 790 * two connectors or possibly even get USB3 peripheral mode), but in 791 * each case you end up forcing to disconnect/reconnect an in-use 792 * USB session in some cases depending on what you hotplug into the 793 * other connector. Thus hardcoding this as peripheral makes sense. 794 */ 795 dr_mode = "peripheral"; 796 797 /* 798 * We always need the high speed pins as 4-lanes DP in case someone 799 * hotplugs a DP peripheral. Thus limit this port to a max of high 800 * speed. 801 */ 802 maximum-speed = "high-speed"; 803 804 /* 805 * We don't need the usb3-phy since we run in highspeed mode always, so 806 * re-define these properties removing the superspeed USB PHY reference. 807 */ 808 phys = <&usb_1_hsphy>; 809 phy-names = "usb2-phy"; 810}; 811 812&usb_1_hsphy { 813 status = "okay"; 814 815 vdd-supply = <&vdda_usb1_ss_core>; 816 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 817 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 818 819 qcom,imp-res-offset-value = <8>; 820 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 821 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; 822 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; 823}; 824 825&usb_2 { 826 status = "okay"; 827}; 828 829&usb_2_dwc3 { 830 /* We have this hooked up to a hub and we always use in host mode */ 831 dr_mode = "host"; 832}; 833 834&usb_2_hsphy { 835 status = "okay"; 836 837 vdd-supply = <&vdda_usb2_ss_core>; 838 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 839 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 840 841 qcom,imp-res-offset-value = <8>; 842 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; 843}; 844 845&usb_2_qmpphy { 846 status = "okay"; 847 848 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 849 vdda-pll-supply = <&vdda_usb2_ss_core>; 850}; 851 852&wifi { 853 status = "okay"; 854 855 vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; 856 vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; 857 vdd-1.3-rfa-supply = <&src_pp1300_l17a>; 858 vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; 859}; 860 861/* PINCTRL - additions to nodes defined in sdm845.dtsi */ 862 863&qspi_cs0 { 864 pinconf { 865 pins = "gpio90"; 866 bias-disable; 867 }; 868}; 869 870&qspi_clk { 871 pinconf { 872 pins = "gpio95"; 873 bias-disable; 874 }; 875}; 876 877&qspi_data01 { 878 pinconf { 879 pins = "gpio91", "gpio92"; 880 881 /* High-Z when no transfers; nice to park the lines */ 882 bias-pull-up; 883 }; 884}; 885 886&qup_i2c3_default { 887 pinconf { 888 pins = "gpio41", "gpio42"; 889 drive-strength = <2>; 890 891 /* Has external pullup */ 892 bias-disable; 893 }; 894}; 895 896&qup_i2c11_default { 897 pinconf { 898 pins = "gpio31", "gpio32"; 899 drive-strength = <2>; 900 901 /* Has external pullup */ 902 bias-disable; 903 }; 904}; 905 906&qup_i2c12_default { 907 pinconf { 908 pins = "gpio49", "gpio50"; 909 drive-strength = <2>; 910 911 /* Has external pullup */ 912 bias-disable; 913 }; 914}; 915 916&qup_i2c14_default { 917 pinconf { 918 pins = "gpio33", "gpio34"; 919 drive-strength = <2>; 920 921 /* Has external pullup */ 922 bias-disable; 923 }; 924}; 925 926&qup_spi0_default { 927 pinconf { 928 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 929 drive-strength = <2>; 930 bias-disable; 931 }; 932}; 933 934&qup_spi5_default { 935 pinconf { 936 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 937 drive-strength = <2>; 938 bias-disable; 939 }; 940}; 941 942&qup_spi10_default { 943 pinconf { 944 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 945 drive-strength = <2>; 946 bias-disable; 947 }; 948}; 949 950&qup_uart6_default { 951 /* Change pinmux to all 4 pins since CTS and RTS are connected */ 952 pinmux { 953 pins = "gpio45", "gpio46", 954 "gpio47", "gpio48"; 955 }; 956 957 pinconf-cts { 958 /* 959 * Configure a pull-down on 45 (CTS) to match the pull of 960 * the Bluetooth module. 961 */ 962 pins = "gpio45"; 963 bias-pull-down; 964 }; 965 966 pinconf-rts-tx { 967 /* We'll drive 46 (RTS) and 47 (TX), so no pull */ 968 pins = "gpio46", "gpio47"; 969 drive-strength = <2>; 970 bias-disable; 971 }; 972 973 pinconf-rx { 974 /* 975 * Configure a pull-up on 48 (RX). This is needed to avoid 976 * garbage data when the TX pin of the Bluetooth module is 977 * in tri-state (module powered off or not driving the 978 * signal yet). 979 */ 980 pins = "gpio48"; 981 bias-pull-up; 982 }; 983}; 984 985&qup_uart9_default { 986 pinconf-tx { 987 pins = "gpio4"; 988 drive-strength = <2>; 989 bias-disable; 990 }; 991 992 pinconf-rx { 993 pins = "gpio5"; 994 drive-strength = <2>; 995 bias-pull-up; 996 }; 997}; 998 999/* PINCTRL - board-specific pinctrl */ 1000&pm8005_gpio { 1001 gpio-line-names = "", 1002 "", 1003 "SLB", 1004 ""; 1005}; 1006 1007&pm8998_adc { 1008 adc-chan@4d { 1009 reg = <ADC5_AMUX_THM1_100K_PU>; 1010 label = "sdm_temp"; 1011 }; 1012 1013 adc-chan@4e { 1014 reg = <ADC5_AMUX_THM2_100K_PU>; 1015 label = "quiet_temp"; 1016 }; 1017 1018 adc-chan@4f { 1019 reg = <ADC5_AMUX_THM3_100K_PU>; 1020 label = "lte_temp_1"; 1021 }; 1022 1023 adc-chan@50 { 1024 reg = <ADC5_AMUX_THM4_100K_PU>; 1025 label = "lte_temp_2"; 1026 }; 1027 1028 adc-chan@51 { 1029 reg = <ADC5_AMUX_THM5_100K_PU>; 1030 label = "charger_temp"; 1031 }; 1032}; 1033 1034&pm8998_gpio { 1035 gpio-line-names = "", 1036 "", 1037 "SW_CTRL", 1038 "", 1039 "", 1040 "", 1041 "", 1042 "", 1043 "", 1044 "", 1045 "", 1046 "", 1047 "", 1048 "", 1049 "", 1050 "", 1051 "", 1052 "", 1053 "", 1054 "", 1055 "", 1056 "CFG_OPT1", 1057 "WCSS_PWR_REQ", 1058 "", 1059 "CFG_OPT2", 1060 "SLB"; 1061}; 1062 1063&tlmm { 1064 /* 1065 * pinctrl settings for pins that have no real owners. 1066 */ 1067 pinctrl-names = "default", "sleep"; 1068 pinctrl-0 = <&bios_flash_wp_r_l>, 1069 <&ap_suspend_l_deassert>; 1070 1071 pinctrl-1 = <&bios_flash_wp_r_l>, 1072 <&ap_suspend_l_assert>; 1073 1074 /* 1075 * Hogs prevent usermode from changing the value. A GPIO can be both 1076 * here and in the pinctrl section. 1077 */ 1078 ap-suspend-l-hog { 1079 gpio-hog; 1080 gpios = <126 GPIO_ACTIVE_LOW>; 1081 output-low; 1082 }; 1083 1084 ap_edp_bklten: ap-edp-bklten { 1085 pinmux { 1086 pins = "gpio37"; 1087 function = "gpio"; 1088 }; 1089 1090 pinconf { 1091 pins = "gpio37"; 1092 drive-strength = <2>; 1093 bias-disable; 1094 }; 1095 }; 1096 1097 bios_flash_wp_r_l: bios-flash-wp-r-l { 1098 pinmux { 1099 pins = "gpio128"; 1100 function = "gpio"; 1101 input-enable; 1102 }; 1103 1104 pinconf { 1105 pins = "gpio128"; 1106 bias-disable; 1107 }; 1108 }; 1109 1110 ec_ap_int_l: ec-ap-int-l { 1111 pinmux { 1112 pins = "gpio122"; 1113 function = "gpio"; 1114 input-enable; 1115 }; 1116 1117 pinconf { 1118 pins = "gpio122"; 1119 bias-pull-up; 1120 }; 1121 }; 1122 1123 edp_brij_en: edp-brij-en { 1124 pinmux { 1125 pins = "gpio102"; 1126 function = "gpio"; 1127 }; 1128 1129 pinconf { 1130 pins = "gpio102"; 1131 drive-strength = <2>; 1132 bias-disable; 1133 }; 1134 }; 1135 1136 edp_brij_irq: edp-brij-irq { 1137 pinmux { 1138 pins = "gpio10"; 1139 function = "gpio"; 1140 }; 1141 1142 pinconf { 1143 pins = "gpio10"; 1144 drive-strength = <2>; 1145 bias-pull-down; 1146 }; 1147 }; 1148 1149 en_pp3300_dx_edp: en-pp3300-dx-edp { 1150 pinmux { 1151 pins = "gpio43"; 1152 function = "gpio"; 1153 }; 1154 1155 pinconf { 1156 pins = "gpio43"; 1157 drive-strength = <2>; 1158 bias-disable; 1159 }; 1160 }; 1161 1162 h1_ap_int_odl: h1-ap-int-odl { 1163 pinmux { 1164 pins = "gpio129"; 1165 function = "gpio"; 1166 input-enable; 1167 }; 1168 1169 pinconf { 1170 pins = "gpio129"; 1171 bias-pull-up; 1172 }; 1173 }; 1174 1175 pen_eject_odl: pen-eject-odl { 1176 pinmux { 1177 pins = "gpio119"; 1178 function = "gpio"; 1179 bias-pull-up; 1180 }; 1181 }; 1182 1183 pen_irq_l: pen-irq-l { 1184 pinmux { 1185 pins = "gpio24"; 1186 function = "gpio"; 1187 }; 1188 1189 pinconf { 1190 pins = "gpio24"; 1191 1192 /* Has external pullup */ 1193 bias-disable; 1194 }; 1195 }; 1196 1197 pen_pdct_l: pen-pdct-l { 1198 pinmux { 1199 pins = "gpio63"; 1200 function = "gpio"; 1201 }; 1202 1203 pinconf { 1204 pins = "gpio63"; 1205 1206 /* Has external pullup */ 1207 bias-disable; 1208 }; 1209 }; 1210 1211 pen_rst_l: pen-rst-l { 1212 pinmux { 1213 pins = "gpio23"; 1214 function = "gpio"; 1215 }; 1216 1217 pinconf { 1218 pins = "gpio23"; 1219 bias-disable; 1220 drive-strength = <2>; 1221 1222 /* 1223 * The pen driver doesn't currently support 1224 * driving this reset line. By specifying 1225 * output-high here we're relying on the fact 1226 * that this pin has a default pulldown at boot 1227 * (which makes sure the pen was in reset if it 1228 * was powered) and then we set it high here to 1229 * take it out of reset. Better would be if the 1230 * pen driver could control this and we could 1231 * remove "output-high" here. 1232 */ 1233 output-high; 1234 }; 1235 }; 1236 1237 sdc2_clk: sdc2-clk { 1238 pinconf { 1239 pins = "sdc2_clk"; 1240 bias-disable; 1241 1242 /* 1243 * It seems that mmc_test reports errors if drive 1244 * strength is not 16. 1245 */ 1246 drive-strength = <16>; 1247 }; 1248 }; 1249 1250 sdc2_cmd: sdc2-cmd { 1251 pinconf { 1252 pins = "sdc2_cmd"; 1253 bias-pull-up; 1254 drive-strength = <16>; 1255 }; 1256 }; 1257 1258 sdc2_data: sdc2-data { 1259 pinconf { 1260 pins = "sdc2_data"; 1261 bias-pull-up; 1262 drive-strength = <16>; 1263 }; 1264 }; 1265 1266 sd_cd_odl: sd-cd-odl { 1267 pinmux { 1268 pins = "gpio44"; 1269 function = "gpio"; 1270 }; 1271 1272 pinconf { 1273 pins = "gpio44"; 1274 bias-pull-up; 1275 }; 1276 }; 1277 1278 ts_int_l: ts-int-l { 1279 pinmux { 1280 pins = "gpio125"; 1281 function = "gpio"; 1282 }; 1283 1284 pinconf { 1285 pins = "gpio125"; 1286 bias-pull-up; 1287 }; 1288 }; 1289 1290 ts_reset_l: ts-reset-l { 1291 pinmux { 1292 pins = "gpio118"; 1293 function = "gpio"; 1294 }; 1295 1296 pinconf { 1297 pins = "gpio118"; 1298 bias-disable; 1299 drive-strength = <2>; 1300 }; 1301 }; 1302 1303 ap_suspend_l_assert: ap_suspend_l_assert { 1304 config { 1305 pins = "gpio126"; 1306 function = "gpio"; 1307 bias-no-pull; 1308 drive-strength = <2>; 1309 output-low; 1310 }; 1311 }; 1312 1313 ap_suspend_l_deassert: ap_suspend_l_deassert { 1314 config { 1315 pins = "gpio126"; 1316 function = "gpio"; 1317 bias-no-pull; 1318 drive-strength = <2>; 1319 output-high; 1320 }; 1321 }; 1322}; 1323 1324&venus { 1325 status = "okay"; 1326 1327 video-firmware { 1328 iommus = <&apps_smmu 0x10b2 0x0>; 1329 }; 1330}; 1331