xref: /freebsd/sys/contrib/device-tree/src/arm64/qcom/sdm670.dtsi (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022, Richard Acayan. All rights reserved.
7 */
8
9#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10#include <dt-bindings/clock/qcom,gcc-sdm845.h>
11#include <dt-bindings/clock/qcom,rpmh.h>
12#include <dt-bindings/dma/qcom-gpi.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interconnect/qcom,osm-l3.h>
15#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/phy/phy-qcom-qusb2.h>
18#include <dt-bindings/power/qcom-rpmpd.h>
19#include <dt-bindings/soc/qcom,rpmh-rsc.h>
20
21/ {
22	interrupt-parent = <&intc>;
23
24	#address-cells = <2>;
25	#size-cells = <2>;
26
27	aliases { };
28
29	chosen { };
30
31	cpus {
32		#address-cells = <2>;
33		#size-cells = <0>;
34
35		CPU0: cpu@0 {
36			device_type = "cpu";
37			compatible = "qcom,kryo360";
38			reg = <0x0 0x0>;
39			enable-method = "psci";
40			capacity-dmips-mhz = <610>;
41			dynamic-power-coefficient = <203>;
42			qcom,freq-domain = <&cpufreq_hw 0>;
43			operating-points-v2 = <&cpu0_opp_table>;
44			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
45					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
46			power-domains = <&CPU_PD0>;
47			power-domain-names = "psci";
48			next-level-cache = <&L2_0>;
49			L2_0: l2-cache {
50				compatible = "cache";
51				next-level-cache = <&L3_0>;
52				cache-level = <2>;
53				cache-unified;
54				L3_0: l3-cache {
55					compatible = "cache";
56					cache-level = <3>;
57					cache-unified;
58				};
59			};
60		};
61
62		CPU1: cpu@100 {
63			device_type = "cpu";
64			compatible = "qcom,kryo360";
65			reg = <0x0 0x100>;
66			enable-method = "psci";
67			capacity-dmips-mhz = <610>;
68			dynamic-power-coefficient = <203>;
69			qcom,freq-domain = <&cpufreq_hw 0>;
70			operating-points-v2 = <&cpu0_opp_table>;
71			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
72					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
73			power-domains = <&CPU_PD1>;
74			power-domain-names = "psci";
75			next-level-cache = <&L2_100>;
76			L2_100: l2-cache {
77				compatible = "cache";
78				cache-level = <2>;
79				cache-unified;
80				next-level-cache = <&L3_0>;
81			};
82		};
83
84		CPU2: cpu@200 {
85			device_type = "cpu";
86			compatible = "qcom,kryo360";
87			reg = <0x0 0x200>;
88			enable-method = "psci";
89			capacity-dmips-mhz = <610>;
90			dynamic-power-coefficient = <203>;
91			qcom,freq-domain = <&cpufreq_hw 0>;
92			operating-points-v2 = <&cpu0_opp_table>;
93			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
94					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
95			power-domains = <&CPU_PD2>;
96			power-domain-names = "psci";
97			next-level-cache = <&L2_200>;
98			L2_200: l2-cache {
99				compatible = "cache";
100				cache-level = <2>;
101				cache-unified;
102				next-level-cache = <&L3_0>;
103			};
104		};
105
106		CPU3: cpu@300 {
107			device_type = "cpu";
108			compatible = "qcom,kryo360";
109			reg = <0x0 0x300>;
110			enable-method = "psci";
111			capacity-dmips-mhz = <610>;
112			dynamic-power-coefficient = <203>;
113			qcom,freq-domain = <&cpufreq_hw 0>;
114			operating-points-v2 = <&cpu0_opp_table>;
115			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
116					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117			power-domains = <&CPU_PD3>;
118			power-domain-names = "psci";
119			next-level-cache = <&L2_300>;
120			L2_300: l2-cache {
121				compatible = "cache";
122				cache-level = <2>;
123				cache-unified;
124				next-level-cache = <&L3_0>;
125			};
126		};
127
128		CPU4: cpu@400 {
129			device_type = "cpu";
130			compatible = "qcom,kryo360";
131			reg = <0x0 0x400>;
132			enable-method = "psci";
133			capacity-dmips-mhz = <610>;
134			dynamic-power-coefficient = <203>;
135			qcom,freq-domain = <&cpufreq_hw 0>;
136			operating-points-v2 = <&cpu0_opp_table>;
137			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
138					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
139			power-domains = <&CPU_PD4>;
140			power-domain-names = "psci";
141			next-level-cache = <&L2_400>;
142			L2_400: l2-cache {
143				compatible = "cache";
144				cache-level = <2>;
145				cache-unified;
146				next-level-cache = <&L3_0>;
147			};
148		};
149
150		CPU5: cpu@500 {
151			device_type = "cpu";
152			compatible = "qcom,kryo360";
153			reg = <0x0 0x500>;
154			enable-method = "psci";
155			capacity-dmips-mhz = <610>;
156			dynamic-power-coefficient = <203>;
157			qcom,freq-domain = <&cpufreq_hw 0>;
158			operating-points-v2 = <&cpu0_opp_table>;
159			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
160					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
161			power-domains = <&CPU_PD5>;
162			power-domain-names = "psci";
163			next-level-cache = <&L2_500>;
164			L2_500: l2-cache {
165				compatible = "cache";
166				cache-level = <2>;
167				cache-unified;
168				next-level-cache = <&L3_0>;
169			};
170		};
171
172		CPU6: cpu@600 {
173			device_type = "cpu";
174			compatible = "qcom,kryo360";
175			reg = <0x0 0x600>;
176			enable-method = "psci";
177			capacity-dmips-mhz = <1024>;
178			dynamic-power-coefficient = <393>;
179			qcom,freq-domain = <&cpufreq_hw 1>;
180			operating-points-v2 = <&cpu6_opp_table>;
181			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
182					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183			power-domains = <&CPU_PD6>;
184			power-domain-names = "psci";
185			next-level-cache = <&L2_600>;
186			L2_600: l2-cache {
187				compatible = "cache";
188				cache-level = <2>;
189				cache-unified;
190				next-level-cache = <&L3_0>;
191			};
192		};
193
194		CPU7: cpu@700 {
195			device_type = "cpu";
196			compatible = "qcom,kryo360";
197			reg = <0x0 0x700>;
198			enable-method = "psci";
199			capacity-dmips-mhz = <1024>;
200			dynamic-power-coefficient = <393>;
201			qcom,freq-domain = <&cpufreq_hw 1>;
202			operating-points-v2 = <&cpu6_opp_table>;
203			interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
204					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
205			power-domains = <&CPU_PD7>;
206			power-domain-names = "psci";
207			next-level-cache = <&L2_700>;
208			L2_700: l2-cache {
209				compatible = "cache";
210				cache-level = <2>;
211				cache-unified;
212				next-level-cache = <&L3_0>;
213			};
214		};
215
216		cpu-map {
217			cluster0 {
218				core0 {
219					cpu = <&CPU0>;
220				};
221
222				core1 {
223					cpu = <&CPU1>;
224				};
225
226				core2 {
227					cpu = <&CPU2>;
228				};
229
230				core3 {
231					cpu = <&CPU3>;
232				};
233
234				core4 {
235					cpu = <&CPU4>;
236				};
237
238				core5 {
239					cpu = <&CPU5>;
240				};
241
242				core6 {
243					cpu = <&CPU6>;
244				};
245
246				core7 {
247					cpu = <&CPU7>;
248				};
249			};
250		};
251
252		idle-states {
253			entry-method = "psci";
254
255			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
256				compatible = "arm,idle-state";
257				idle-state-name = "little-rail-power-collapse";
258				arm,psci-suspend-param = <0x40000004>;
259				entry-latency-us = <702>;
260				exit-latency-us = <915>;
261				min-residency-us = <1617>;
262				local-timer-stop;
263			};
264
265			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
266				compatible = "arm,idle-state";
267				idle-state-name = "big-rail-power-collapse";
268				arm,psci-suspend-param = <0x40000004>;
269				entry-latency-us = <526>;
270				exit-latency-us = <1854>;
271				min-residency-us = <2380>;
272				local-timer-stop;
273			};
274		};
275
276		domain-idle-states {
277			CLUSTER_SLEEP_0: cluster-sleep-0 {
278				compatible = "domain-idle-state";
279				arm,psci-suspend-param = <0x4100c244>;
280				entry-latency-us = <3263>;
281				exit-latency-us = <6562>;
282				min-residency-us = <9825>;
283			};
284		};
285	};
286
287	firmware {
288		scm {
289			compatible = "qcom,scm-sdm670", "qcom,scm";
290		};
291	};
292
293	memory@80000000 {
294		device_type = "memory";
295		/* We expect the bootloader to fill in the size */
296		reg = <0x0 0x80000000 0x0 0x0>;
297	};
298
299	cpu0_opp_table: opp-table-cpu0 {
300		compatible = "operating-points-v2";
301		opp-shared;
302
303		cpu0_opp1: opp-300000000 {
304			opp-hz = /bits/ 64 <300000000>;
305			opp-peak-kBps = <400000 4800000>;
306		};
307
308		cpu0_opp2: opp-576000000 {
309			opp-hz = /bits/ 64 <576000000>;
310			opp-peak-kBps = <400000 4800000>;
311		};
312
313		cpu0_opp3: opp-748800000 {
314			opp-hz = /bits/ 64 <748800000>;
315			opp-peak-kBps = <1200000 4800000>;
316		};
317
318		cpu0_opp4: opp-998400000 {
319			opp-hz = /bits/ 64 <998400000>;
320			opp-peak-kBps = <1804000 8908800>;
321		};
322
323		cpu0_opp5: opp-1209600000 {
324			opp-hz = /bits/ 64 <1209600000>;
325			opp-peak-kBps = <2188000 8908800>;
326		};
327
328		cpu0_opp6: opp-1324800000 {
329			opp-hz = /bits/ 64 <1324800000>;
330			opp-peak-kBps = <2188000 13516800>;
331		};
332
333		cpu0_opp7: opp-1516800000 {
334			opp-hz = /bits/ 64 <1516800000>;
335			opp-peak-kBps = <3072000 15052800>;
336		};
337
338		cpu0_opp8: opp-1612800000 {
339			opp-hz = /bits/ 64 <1612800000>;
340			opp-peak-kBps = <3072000 22118400>;
341		};
342
343		cpu0_opp9: opp-1708800000 {
344			opp-hz = /bits/ 64 <1708800000>;
345			opp-peak-kBps = <4068000 23040000>;
346		};
347	};
348
349	cpu6_opp_table: opp-table-cpu6 {
350		compatible = "operating-points-v2";
351		opp-shared;
352
353		cpu6_opp1: opp-300000000 {
354			opp-hz = /bits/ 64 <300000000>;
355			opp-peak-kBps = <400000 4800000>;
356		};
357
358		cpu6_opp2: opp-652800000 {
359			opp-hz = /bits/ 64 <652800000>;
360			opp-peak-kBps = <400000 4800000>;
361		};
362
363		cpu6_opp3: opp-825600000 {
364			opp-hz = /bits/ 64 <825600000>;
365			opp-peak-kBps = <1200000 4800000>;
366		};
367
368		cpu6_opp4: opp-979200000 {
369			opp-hz = /bits/ 64 <979200000>;
370			opp-peak-kBps = <1200000 4800000>;
371		};
372
373		cpu6_opp5: opp-1132800000 {
374			opp-hz = /bits/ 64 <1132800000>;
375			opp-peak-kBps = <2188000 8908800>;
376		};
377
378		cpu6_opp6: opp-1363200000 {
379			opp-hz = /bits/ 64 <1363200000>;
380			opp-peak-kBps = <4068000 12902400>;
381		};
382
383		cpu6_opp7: opp-1536000000 {
384			opp-hz = /bits/ 64 <1536000000>;
385			opp-peak-kBps = <4068000 12902400>;
386		};
387
388		cpu6_opp8: opp-1747200000 {
389			opp-hz = /bits/ 64 <1747200000>;
390			opp-peak-kBps = <4068000 15052800>;
391		};
392
393		cpu6_opp9: opp-1843200000 {
394			opp-hz = /bits/ 64 <1843200000>;
395			opp-peak-kBps = <4068000 15052800>;
396		};
397
398		cpu6_opp10: opp-1996800000 {
399			opp-hz = /bits/ 64 <1996800000>;
400			opp-peak-kBps = <6220000 19046400>;
401		};
402	};
403
404	dsi_opp_table: opp-table-dsi {
405		compatible = "operating-points-v2";
406
407		opp-19200000 {
408			opp-hz = /bits/ 64 <19200000>;
409			required-opps = <&rpmhpd_opp_min_svs>;
410		};
411
412		opp-180000000 {
413			opp-hz = /bits/ 64 <180000000>;
414			required-opps = <&rpmhpd_opp_low_svs>;
415		};
416
417		opp-275000000 {
418			opp-hz = /bits/ 64 <275000000>;
419			required-opps = <&rpmhpd_opp_svs>;
420		};
421
422		opp-358000000 {
423			opp-hz = /bits/ 64 <358000000>;
424			required-opps = <&rpmhpd_opp_svs_l1>;
425		};
426	};
427
428	psci {
429		compatible = "arm,psci-1.0";
430		method = "smc";
431
432		CPU_PD0: power-domain-cpu0 {
433			#power-domain-cells = <0>;
434			power-domains = <&CLUSTER_PD>;
435			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
436		};
437
438		CPU_PD1: power-domain-cpu1 {
439			#power-domain-cells = <0>;
440			power-domains = <&CLUSTER_PD>;
441			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
442		};
443
444		CPU_PD2: power-domain-cpu2 {
445			#power-domain-cells = <0>;
446			power-domains = <&CLUSTER_PD>;
447			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
448		};
449
450		CPU_PD3: power-domain-cpu3 {
451			#power-domain-cells = <0>;
452			power-domains = <&CLUSTER_PD>;
453			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
454		};
455
456		CPU_PD4: power-domain-cpu4 {
457			#power-domain-cells = <0>;
458			power-domains = <&CLUSTER_PD>;
459			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
460		};
461
462		CPU_PD5: power-domain-cpu5 {
463			#power-domain-cells = <0>;
464			power-domains = <&CLUSTER_PD>;
465			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
466		};
467
468		CPU_PD6: power-domain-cpu6 {
469			#power-domain-cells = <0>;
470			power-domains = <&CLUSTER_PD>;
471			domain-idle-states = <&BIG_CPU_SLEEP_0>;
472		};
473
474		CPU_PD7: power-domain-cpu7 {
475			#power-domain-cells = <0>;
476			power-domains = <&CLUSTER_PD>;
477			domain-idle-states = <&BIG_CPU_SLEEP_0>;
478		};
479
480		CLUSTER_PD: power-domain-cluster {
481			#power-domain-cells = <0>;
482			domain-idle-states = <&CLUSTER_SLEEP_0>;
483		};
484	};
485
486	reserved-memory {
487		#address-cells = <2>;
488		#size-cells = <2>;
489		ranges;
490
491		hyp_mem: hyp-mem@85700000 {
492			reg = <0 0x85700000 0 0x600000>;
493			no-map;
494		};
495
496		xbl_mem: xbl-mem@85e00000 {
497			reg = <0 0x85e00000 0 0x100000>;
498			no-map;
499		};
500
501		aop_mem: aop-mem@85fc0000 {
502			reg = <0 0x85fc0000 0 0x20000>;
503			no-map;
504		};
505
506		aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
507			compatible = "qcom,cmd-db";
508			reg = <0 0x85fe0000 0 0x20000>;
509			no-map;
510		};
511
512		camera_mem: camera-mem@8ab00000 {
513			reg = <0 0x8ab00000 0 0x500000>;
514			no-map;
515		};
516
517		mpss_region: mpss@8b000000 {
518			reg = <0 0x8b000000 0 0x7e00000>;
519			no-map;
520		};
521
522		venus_mem: venus@92e00000 {
523			reg = <0 0x92e00000 0 0x500000>;
524			no-map;
525		};
526
527		wlan_msa_mem: wlan-msa@93300000 {
528			reg = <0 0x93300000 0 0x100000>;
529			no-map;
530		};
531
532		cdsp_mem: cdsp@93400000 {
533			reg = <0 0x93400000 0 0x800000>;
534			no-map;
535		};
536
537		mba_region: mba@93c00000 {
538			reg = <0 0x93c00000 0 0x200000>;
539			no-map;
540		};
541
542		adsp_mem: adsp@93e00000 {
543			reg = <0 0x93e00000 0 0x1e00000>;
544			no-map;
545		};
546
547		ipa_fw_mem: ipa-fw@95c00000 {
548			reg = <0 0x95c00000 0 0x10000>;
549			no-map;
550		};
551
552		ipa_gsi_mem: ipa-gsi@95c10000 {
553			reg = <0 0x95c10000 0 0x5000>;
554			no-map;
555		};
556
557		gpu_mem: gpu@95c15000 {
558			reg = <0 0x95c15000 0 0x2000>;
559			no-map;
560		};
561
562		spss_mem: spss@97b00000 {
563			reg = <0 0x97b00000 0 0x100000>;
564			no-map;
565		};
566
567		qseecom_mem: qseecom@9e400000 {
568			reg = <0 0x9e400000 0 0x1400000>;
569			no-map;
570		};
571	};
572
573	timer {
574		compatible = "arm,armv8-timer";
575		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
576			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
577			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
578			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
579	};
580
581	soc: soc@0 {
582		#address-cells = <2>;
583		#size-cells = <2>;
584		ranges = <0 0 0 0 0x10 0>;
585		dma-ranges = <0 0 0 0 0x10 0>;
586		compatible = "simple-bus";
587
588		gcc: clock-controller@100000 {
589			compatible = "qcom,gcc-sdm670";
590			reg = <0 0x00100000 0 0x1f0000>;
591			clocks = <&rpmhcc RPMH_CXO_CLK>,
592				 <&rpmhcc RPMH_CXO_CLK_A>,
593				 <&sleep_clk>;
594			clock-names = "bi_tcxo",
595				      "bi_tcxo_ao",
596				      "sleep_clk";
597			#clock-cells = <1>;
598			#reset-cells = <1>;
599			#power-domain-cells = <1>;
600		};
601
602		qfprom: qfprom@784000 {
603			compatible = "qcom,sdm670-qfprom", "qcom,qfprom";
604			reg = <0 0x00784000 0 0x1000>;
605			#address-cells = <1>;
606			#size-cells = <1>;
607
608			qusb2_hstx_trim: hstx-trim@1eb {
609				reg = <0x1eb 0x1>;
610				bits = <1 4>;
611			};
612		};
613
614		sdhc_1: mmc@7c4000 {
615			compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
616			reg = <0 0x007c4000 0 0x1000>,
617			      <0 0x007c5000 0 0x1000>,
618			      <0 0x007c8000 0 0x8000>;
619			reg-names = "hc", "cqhci", "ice";
620
621			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
622				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
623			interrupt-names = "hc_irq", "pwr_irq";
624
625			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
626				 <&gcc GCC_SDCC1_APPS_CLK>,
627				 <&rpmhcc RPMH_CXO_CLK>,
628				 <&gcc GCC_SDCC1_ICE_CORE_CLK>,
629				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
630			clock-names = "iface", "core", "xo", "ice", "bus";
631			interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>,
632					<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>;
633			interconnect-names = "sdhc-ddr", "cpu-sdhc";
634			operating-points-v2 = <&sdhc1_opp_table>;
635
636			iommus = <&apps_smmu 0x140 0xf>;
637
638			pinctrl-names = "default", "sleep";
639			pinctrl-0 = <&sdc1_state_on>;
640			pinctrl-1 = <&sdc1_state_off>;
641			power-domains = <&rpmhpd SDM670_CX>;
642
643			bus-width = <8>;
644			non-removable;
645
646			status = "disabled";
647
648			sdhc1_opp_table: opp-table {
649				compatible = "operating-points-v2";
650
651				opp-20000000 {
652					opp-hz = /bits/ 64 <20000000>;
653					required-opps = <&rpmhpd_opp_min_svs>;
654					opp-peak-kBps = <80000 80000>;
655					opp-avg-kBps = <52286 80000>;
656				};
657
658				opp-50000000 {
659					opp-hz = /bits/ 64 <50000000>;
660					required-opps = <&rpmhpd_opp_low_svs>;
661					opp-peak-kBps = <200000 100000>;
662					opp-avg-kBps = <130718 100000>;
663				};
664
665				opp-100000000 {
666					opp-hz = /bits/ 64 <100000000>;
667					required-opps = <&rpmhpd_opp_svs>;
668					opp-peak-kBps = <200000 130000>;
669					opp-avg-kBps = <130718 130000>;
670				};
671
672				opp-384000000 {
673					opp-hz = /bits/ 64 <384000000>;
674					required-opps = <&rpmhpd_opp_nom>;
675					opp-peak-kBps = <4096000 4096000>;
676					opp-avg-kBps = <1338562 1338562>;
677				};
678			};
679		};
680
681		gpi_dma0: dma-controller@800000 {
682			#dma-cells = <3>;
683			compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
684			reg = <0 0x00800000 0 0x60000>;
685			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
686				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
687				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
688				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
689				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
690				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
691				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
692				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
693				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
694				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
695				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
696				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
697				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
698			dma-channels = <13>;
699			dma-channel-mask = <0xfa>;
700			iommus = <&apps_smmu 0x16 0x0>;
701			status = "disabled";
702		};
703
704		qupv3_id_0: geniqup@8c0000 {
705			compatible = "qcom,geni-se-qup";
706			reg = <0 0x008c0000 0 0x6000>;
707			clock-names = "m-ahb", "s-ahb";
708			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
709				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
710			iommus = <&apps_smmu 0x3 0x0>;
711			#address-cells = <2>;
712			#size-cells = <2>;
713			ranges;
714			interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>;
715			interconnect-names = "qup-core";
716			status = "disabled";
717
718			i2c0: i2c@880000 {
719				compatible = "qcom,geni-i2c";
720				reg = <0 0x00880000 0 0x4000>;
721				clock-names = "se";
722				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
723				pinctrl-names = "default";
724				pinctrl-0 = <&qup_i2c0_default>;
725				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
726				#address-cells = <1>;
727				#size-cells = <0>;
728				power-domains = <&rpmhpd SDM670_CX>;
729				interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
730						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
731						<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
732				interconnect-names = "qup-core", "qup-config", "qup-memory";
733				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
734				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
735				dma-names = "tx", "rx";
736				status = "disabled";
737			};
738
739			i2c1: i2c@884000 {
740				compatible = "qcom,geni-i2c";
741				reg = <0 0x00884000 0 0x4000>;
742				clock-names = "se";
743				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
744				pinctrl-names = "default";
745				pinctrl-0 = <&qup_i2c1_default>;
746				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
747				#address-cells = <1>;
748				#size-cells = <0>;
749				power-domains = <&rpmhpd SDM670_CX>;
750				interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
751						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
752						<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
753				interconnect-names = "qup-core", "qup-config", "qup-memory";
754				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
755				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
756				dma-names = "tx", "rx";
757				status = "disabled";
758			};
759
760			i2c2: i2c@888000 {
761				compatible = "qcom,geni-i2c";
762				reg = <0 0x00888000 0 0x4000>;
763				clock-names = "se";
764				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
765				pinctrl-names = "default";
766				pinctrl-0 = <&qup_i2c2_default>;
767				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
768				#address-cells = <1>;
769				#size-cells = <0>;
770				power-domains = <&rpmhpd SDM670_CX>;
771				interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
772						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
773						<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
774				interconnect-names = "qup-core", "qup-config", "qup-memory";
775				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
776				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
777				dma-names = "tx", "rx";
778				status = "disabled";
779			};
780
781			i2c3: i2c@88c000 {
782				compatible = "qcom,geni-i2c";
783				reg = <0 0x0088c000 0 0x4000>;
784				clock-names = "se";
785				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
786				pinctrl-names = "default";
787				pinctrl-0 = <&qup_i2c3_default>;
788				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
789				#address-cells = <1>;
790				#size-cells = <0>;
791				power-domains = <&rpmhpd SDM670_CX>;
792				interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
793						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
794						<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
795				interconnect-names = "qup-core", "qup-config", "qup-memory";
796				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
797				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
798				dma-names = "tx", "rx";
799				status = "disabled";
800			};
801
802			i2c4: i2c@890000 {
803				compatible = "qcom,geni-i2c";
804				reg = <0 0x00890000 0 0x4000>;
805				clock-names = "se";
806				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
807				pinctrl-names = "default";
808				pinctrl-0 = <&qup_i2c4_default>;
809				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
810				#address-cells = <1>;
811				#size-cells = <0>;
812				power-domains = <&rpmhpd SDM670_CX>;
813				interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
814						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
815						<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
816				interconnect-names = "qup-core", "qup-config", "qup-memory";
817				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
818				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
819				dma-names = "tx", "rx";
820				status = "disabled";
821			};
822
823			i2c5: i2c@894000 {
824				compatible = "qcom,geni-i2c";
825				reg = <0 0x00894000 0 0x4000>;
826				clock-names = "se";
827				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
828				pinctrl-names = "default";
829				pinctrl-0 = <&qup_i2c5_default>;
830				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
831				#address-cells = <1>;
832				#size-cells = <0>;
833				power-domains = <&rpmhpd SDM670_CX>;
834				interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
835						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
836						<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
837				interconnect-names = "qup-core", "qup-config", "qup-memory";
838				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
839				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
840				dma-names = "tx", "rx";
841				status = "disabled";
842			};
843
844			i2c6: i2c@898000 {
845				compatible = "qcom,geni-i2c";
846				reg = <0 0x00898000 0 0x4000>;
847				clock-names = "se";
848				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
849				pinctrl-names = "default";
850				pinctrl-0 = <&qup_i2c6_default>;
851				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
852				#address-cells = <1>;
853				#size-cells = <0>;
854				power-domains = <&rpmhpd SDM670_CX>;
855				interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
856						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
857						<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
858				interconnect-names = "qup-core", "qup-config", "qup-memory";
859				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
860				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
861				dma-names = "tx", "rx";
862				status = "disabled";
863			};
864
865			i2c7: i2c@89c000 {
866				compatible = "qcom,geni-i2c";
867				reg = <0 0x0089c000 0 0x4000>;
868				clock-names = "se";
869				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
870				pinctrl-names = "default";
871				pinctrl-0 = <&qup_i2c7_default>;
872				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
873				#address-cells = <1>;
874				#size-cells = <0>;
875				power-domains = <&rpmhpd SDM670_CX>;
876				interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
877						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
878						<&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
879				interconnect-names = "qup-core", "qup-config", "qup-memory";
880				dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
881				       <&gpi_dma0 1 7 QCOM_GPI_I2C>;
882				dma-names = "tx", "rx";
883				status = "disabled";
884			};
885		};
886
887		gpi_dma1: dma-controller@a00000 {
888			#dma-cells = <3>;
889			compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
890			reg = <0 0x00a00000 0 0x60000>;
891			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
892				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
893				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
894				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
895				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
896				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
897				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
898				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
899				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
900				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
901				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
902				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
903				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
904			dma-channels = <13>;
905			dma-channel-mask = <0xfa>;
906			iommus = <&apps_smmu 0x6d6 0x0>;
907			status = "disabled";
908		};
909
910		qupv3_id_1: geniqup@ac0000 {
911			compatible = "qcom,geni-se-qup";
912			reg = <0 0x00ac0000 0 0x6000>;
913			clock-names = "m-ahb", "s-ahb";
914			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
915				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
916			iommus = <&apps_smmu 0x6c3 0x0>;
917			#address-cells = <2>;
918			#size-cells = <2>;
919			ranges;
920			interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>;
921			interconnect-names = "qup-core";
922			status = "disabled";
923
924			i2c8: i2c@a80000 {
925				compatible = "qcom,geni-i2c";
926				reg = <0 0x00a80000 0 0x4000>;
927				clock-names = "se";
928				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
929				pinctrl-names = "default";
930				pinctrl-0 = <&qup_i2c8_default>;
931				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
932				#address-cells = <1>;
933				#size-cells = <0>;
934				power-domains = <&rpmhpd SDM670_CX>;
935				interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
936						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
937						<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
938				interconnect-names = "qup-core", "qup-config", "qup-memory";
939				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
940				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
941				dma-names = "tx", "rx";
942				status = "disabled";
943			};
944
945			i2c9: i2c@a84000 {
946				compatible = "qcom,geni-i2c";
947				reg = <0 0x00a84000 0 0x4000>;
948				clock-names = "se";
949				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
950				pinctrl-names = "default";
951				pinctrl-0 = <&qup_i2c9_default>;
952				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
953				#address-cells = <1>;
954				#size-cells = <0>;
955				power-domains = <&rpmhpd SDM670_CX>;
956				interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
957						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
958						<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
959				interconnect-names = "qup-core", "qup-config", "qup-memory";
960				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
961				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
962				dma-names = "tx", "rx";
963				status = "disabled";
964			};
965
966			i2c10: i2c@a88000 {
967				compatible = "qcom,geni-i2c";
968				reg = <0 0x00a88000 0 0x4000>;
969				clock-names = "se";
970				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
971				pinctrl-names = "default";
972				pinctrl-0 = <&qup_i2c10_default>;
973				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
974				#address-cells = <1>;
975				#size-cells = <0>;
976				power-domains = <&rpmhpd SDM670_CX>;
977				interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
978						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
979						<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
980				interconnect-names = "qup-core", "qup-config", "qup-memory";
981				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
982				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
983				dma-names = "tx", "rx";
984				status = "disabled";
985			};
986
987			i2c11: i2c@a8c000 {
988				compatible = "qcom,geni-i2c";
989				reg = <0 0x00a8c000 0 0x4000>;
990				clock-names = "se";
991				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
992				pinctrl-names = "default";
993				pinctrl-0 = <&qup_i2c11_default>;
994				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
995				#address-cells = <1>;
996				#size-cells = <0>;
997				power-domains = <&rpmhpd SDM670_CX>;
998				interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
999						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1000						<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1001				interconnect-names = "qup-core", "qup-config", "qup-memory";
1002				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1003				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1004				dma-names = "tx", "rx";
1005				status = "disabled";
1006			};
1007
1008			i2c12: i2c@a90000 {
1009				compatible = "qcom,geni-i2c";
1010				reg = <0 0x00a90000 0 0x4000>;
1011				clock-names = "se";
1012				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1013				pinctrl-names = "default";
1014				pinctrl-0 = <&qup_i2c12_default>;
1015				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1016				#address-cells = <1>;
1017				#size-cells = <0>;
1018				power-domains = <&rpmhpd SDM670_CX>;
1019				interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1020						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1021						<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1022				interconnect-names = "qup-core", "qup-config", "qup-memory";
1023				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1024				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1025				dma-names = "tx", "rx";
1026				status = "disabled";
1027			};
1028
1029			i2c13: i2c@a94000 {
1030				compatible = "qcom,geni-i2c";
1031				reg = <0 0x00a94000 0 0x4000>;
1032				clock-names = "se";
1033				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1034				pinctrl-names = "default";
1035				pinctrl-0 = <&qup_i2c13_default>;
1036				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1037				#address-cells = <1>;
1038				#size-cells = <0>;
1039				power-domains = <&rpmhpd SDM670_CX>;
1040				interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1041						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1042						<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1043				interconnect-names = "qup-core", "qup-config", "qup-memory";
1044				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1045				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1046				dma-names = "tx", "rx";
1047				status = "disabled";
1048			};
1049
1050			i2c14: i2c@a98000 {
1051				compatible = "qcom,geni-i2c";
1052				reg = <0 0x00a98000 0 0x4000>;
1053				clock-names = "se";
1054				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1055				pinctrl-names = "default";
1056				pinctrl-0 = <&qup_i2c14_default>;
1057				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1058				#address-cells = <1>;
1059				#size-cells = <0>;
1060				power-domains = <&rpmhpd SDM670_CX>;
1061				interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1062						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1063						<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1064				interconnect-names = "qup-core", "qup-config", "qup-memory";
1065				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1066				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1067				dma-names = "tx", "rx";
1068				status = "disabled";
1069			};
1070
1071			i2c15: i2c@a9c000 {
1072				compatible = "qcom,geni-i2c";
1073				reg = <0 0x00a9c000 0 0x4000>;
1074				clock-names = "se";
1075				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1076				pinctrl-names = "default";
1077				pinctrl-0 = <&qup_i2c15_default>;
1078				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1079				#address-cells = <1>;
1080				#size-cells = <0>;
1081				power-domains = <&rpmhpd SDM670_CX>;
1082				interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1083						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1084						<&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1085				interconnect-names = "qup-core", "qup-config", "qup-memory";
1086				dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1087				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1088				dma-names = "tx", "rx";
1089				status = "disabled";
1090			};
1091		};
1092
1093		mem_noc: interconnect@1380000 {
1094			compatible = "qcom,sdm670-mem-noc";
1095			reg = <0 0x01380000 0 0x27200>;
1096			#interconnect-cells = <2>;
1097			qcom,bcm-voters = <&apps_bcm_voter>;
1098		};
1099
1100		dc_noc: interconnect@14e0000 {
1101			compatible = "qcom,sdm670-dc-noc";
1102			reg = <0 0x014e0000 0 0x400>;
1103			#interconnect-cells = <2>;
1104			qcom,bcm-voters = <&apps_bcm_voter>;
1105		};
1106
1107		config_noc: interconnect@1500000 {
1108			compatible = "qcom,sdm670-config-noc";
1109			reg = <0 0x01500000 0 0x5080>;
1110			#interconnect-cells = <2>;
1111			qcom,bcm-voters = <&apps_bcm_voter>;
1112		};
1113
1114		system_noc: interconnect@1620000 {
1115			compatible = "qcom,sdm670-system-noc";
1116			reg = <0 0x01620000 0 0x18080>;
1117			#interconnect-cells = <2>;
1118			qcom,bcm-voters = <&apps_bcm_voter>;
1119		};
1120
1121		aggre1_noc: interconnect@16e0000 {
1122			compatible = "qcom,sdm670-aggre1-noc";
1123			reg = <0 0x016e0000 0 0x15080>;
1124			#interconnect-cells = <2>;
1125			qcom,bcm-voters = <&apps_bcm_voter>;
1126		};
1127
1128		aggre2_noc: interconnect@1700000 {
1129			compatible = "qcom,sdm670-aggre2-noc";
1130			reg = <0 0x01700000 0 0x1f300>;
1131			#interconnect-cells = <2>;
1132			qcom,bcm-voters = <&apps_bcm_voter>;
1133		};
1134
1135		mmss_noc: interconnect@1740000 {
1136			compatible = "qcom,sdm670-mmss-noc";
1137			reg = <0 0x01740000 0 0x1c100>;
1138			#interconnect-cells = <2>;
1139			qcom,bcm-voters = <&apps_bcm_voter>;
1140		};
1141
1142		tlmm: pinctrl@3400000 {
1143			compatible = "qcom,sdm670-tlmm";
1144			reg = <0 0x03400000 0 0xc00000>;
1145			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1146			gpio-controller;
1147			#gpio-cells = <2>;
1148			interrupt-controller;
1149			#interrupt-cells = <2>;
1150			gpio-ranges = <&tlmm 0 0 151>;
1151			wakeup-parent = <&pdc>;
1152
1153			qup_i2c0_default: qup-i2c0-default-state {
1154				pins = "gpio0", "gpio1";
1155				function = "qup0";
1156			};
1157
1158			qup_i2c1_default: qup-i2c1-default-state {
1159				pins = "gpio17", "gpio18";
1160				function = "qup1";
1161			};
1162
1163			qup_i2c2_default: qup-i2c2-default-state {
1164				pins = "gpio27", "gpio28";
1165				function = "qup2";
1166			};
1167
1168			qup_i2c3_default: qup-i2c3-default-state {
1169				pins = "gpio41", "gpio42";
1170				function = "qup3";
1171			};
1172
1173			qup_i2c4_default: qup-i2c4-default-state {
1174				pins = "gpio89", "gpio90";
1175				function = "qup4";
1176			};
1177
1178			qup_i2c5_default: qup-i2c5-default-state {
1179				pins = "gpio85", "gpio86";
1180				function = "qup5";
1181			};
1182
1183			qup_i2c6_default: qup-i2c6-default-state {
1184				pins = "gpio45", "gpio46";
1185				function = "qup6";
1186			};
1187
1188			qup_i2c7_default: qup-i2c7-default-state {
1189				pins = "gpio93", "gpio94";
1190				function = "qup7";
1191			};
1192
1193			qup_i2c8_default: qup-i2c8-default-state {
1194				pins = "gpio65", "gpio66";
1195				function = "qup8";
1196			};
1197
1198			qup_i2c9_default: qup-i2c9-default-state {
1199				pins = "gpio6", "gpio7";
1200				function = "qup9";
1201			};
1202
1203			qup_i2c10_default: qup-i2c10-default-state {
1204				pins = "gpio55", "gpio56";
1205				function = "qup10";
1206			};
1207
1208			qup_i2c11_default: qup-i2c11-default-state {
1209				pins = "gpio31", "gpio32";
1210				function = "qup11";
1211			};
1212
1213			qup_i2c12_default: qup-i2c12-default-state {
1214				pins = "gpio49", "gpio50";
1215				function = "qup12";
1216			};
1217
1218			qup_i2c13_default: qup-i2c13-default-state {
1219				pins = "gpio105", "gpio106";
1220				function = "qup13";
1221			};
1222
1223			qup_i2c14_default: qup-i2c14-default-state {
1224				pins = "gpio33", "gpio34";
1225				function = "qup14";
1226			};
1227
1228			qup_i2c15_default: qup-i2c15-default-state {
1229				pins = "gpio81", "gpio82";
1230				function = "qup15";
1231			};
1232
1233			sdc1_state_on: sdc1-on-state {
1234				clk-pins {
1235					pins = "sdc1_clk";
1236					bias-disable;
1237					drive-strength = <16>;
1238				};
1239
1240				cmd-pins {
1241					pins = "sdc1_cmd";
1242					bias-pull-up;
1243					drive-strength = <10>;
1244				};
1245
1246				data-pins {
1247					pins = "sdc1_data";
1248					bias-pull-up;
1249					drive-strength = <10>;
1250				};
1251
1252				rclk-pins {
1253					pins = "sdc1_rclk";
1254					bias-pull-down;
1255				};
1256			};
1257
1258			sdc1_state_off: sdc1-off-state {
1259				clk-pins {
1260					pins = "sdc1_clk";
1261					bias-disable;
1262					drive-strength = <2>;
1263				};
1264
1265				cmd-pins {
1266					pins = "sdc1_cmd";
1267					bias-pull-up;
1268					drive-strength = <2>;
1269				};
1270
1271				data-pins {
1272					pins = "sdc1_data";
1273					bias-pull-up;
1274					drive-strength = <2>;
1275				};
1276
1277				rclk-pins {
1278					pins = "sdc1_rclk";
1279					bias-pull-down;
1280				};
1281			};
1282		};
1283
1284		usb_1_hsphy: phy@88e2000 {
1285			compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
1286			reg = <0 0x088e2000 0 0x400>;
1287			#phy-cells = <0>;
1288
1289			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1290				 <&rpmhcc RPMH_CXO_CLK>;
1291			clock-names = "cfg_ahb", "ref";
1292
1293			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1294
1295			nvmem-cells = <&qusb2_hstx_trim>;
1296
1297			status = "disabled";
1298		};
1299
1300		usb_1: usb@a6f8800 {
1301			compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
1302			reg = <0 0x0a6f8800 0 0x400>;
1303			#address-cells = <2>;
1304			#size-cells = <2>;
1305			ranges;
1306			dma-ranges;
1307
1308			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1309				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1310				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1311				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1312				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1313			clock-names = "cfg_noc",
1314				      "core",
1315				      "iface",
1316				      "sleep",
1317				      "mock_utmi";
1318
1319			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1320					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1321			assigned-clock-rates = <19200000>, <150000000>;
1322
1323			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1324					      <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1325					      <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
1326					      <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
1327			interrupt-names = "hs_phy_irq", "ss_phy_irq",
1328					  "dm_hs_phy_irq", "dp_hs_phy_irq";
1329
1330			power-domains = <&gcc USB30_PRIM_GDSC>;
1331
1332			resets = <&gcc GCC_USB30_PRIM_BCR>;
1333
1334			interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>,
1335					<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1336			interconnect-names = "usb-ddr", "apps-usb";
1337
1338			status = "disabled";
1339
1340			usb_1_dwc3: usb@a600000 {
1341				compatible = "snps,dwc3";
1342				reg = <0 0x0a600000 0 0xcd00>;
1343				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1344				iommus = <&apps_smmu 0x740 0>;
1345				snps,dis_u2_susphy_quirk;
1346				snps,dis_enblslpm_quirk;
1347				phys = <&usb_1_hsphy>;
1348				phy-names = "usb2-phy";
1349			};
1350		};
1351
1352		pdc: interrupt-controller@b220000 {
1353			compatible = "qcom,sdm670-pdc", "qcom,pdc";
1354			reg = <0 0x0b220000 0 0x30000>;
1355			qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1356					  <54 534 24>, <79 559 15>, <94 609 15>,
1357					  <115 630 7>;
1358			#interrupt-cells = <2>;
1359			interrupt-parent = <&intc>;
1360			interrupt-controller;
1361		};
1362
1363		spmi_bus: spmi@c440000 {
1364			compatible = "qcom,spmi-pmic-arb";
1365			reg = <0 0x0c440000 0 0x1100>,
1366			      <0 0x0c600000 0 0x2000000>,
1367			      <0 0x0e600000 0 0x100000>,
1368			      <0 0x0e700000 0 0xa0000>,
1369			      <0 0x0c40a000 0 0x26000>;
1370			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1371			interrupt-names = "periph_irq";
1372			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
1373			qcom,ee = <0>;
1374			qcom,channel = <0>;
1375			#address-cells = <2>;
1376			#size-cells = <0>;
1377			interrupt-controller;
1378			#interrupt-cells = <4>;
1379		};
1380
1381		mdss: display-subsystem@ae00000 {
1382			compatible = "qcom,sdm670-mdss";
1383			reg = <0 0x0ae00000 0 0x1000>;
1384			reg-names = "mdss";
1385
1386			power-domains = <&dispcc MDSS_GDSC>;
1387
1388			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1389				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1390			clock-names = "iface", "core";
1391
1392			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1393			interrupt-controller;
1394			#interrupt-cells = <1>;
1395
1396			interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
1397					<&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
1398			interconnect-names = "mdp0-mem", "mdp1-mem";
1399
1400			iommus = <&apps_smmu 0x880 0x8>,
1401				 <&apps_smmu 0xc80 0x8>;
1402
1403			#address-cells = <2>;
1404			#size-cells = <2>;
1405			ranges;
1406
1407			status = "disabled";
1408
1409			mdss_mdp: display-controller@ae01000 {
1410				compatible = "qcom,sdm670-dpu";
1411				reg = <0 0x0ae01000 0 0x8f000>,
1412				      <0 0x0aeb0000 0 0x2008>;
1413				reg-names = "mdp", "vbif";
1414
1415				clocks = <&gcc GCC_DISP_AXI_CLK>,
1416					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1417					 <&dispcc DISP_CC_MDSS_AXI_CLK>,
1418					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1419					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1420				clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
1421
1422				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1423				assigned-clock-rates = <19200000>;
1424				operating-points-v2 = <&mdp_opp_table>;
1425				power-domains = <&rpmhpd SDM670_CX>;
1426
1427				interrupt-parent = <&mdss>;
1428				interrupts = <0>;
1429
1430				ports {
1431					#address-cells = <1>;
1432					#size-cells = <0>;
1433
1434					port@0 {
1435						reg = <0>;
1436						dpu_intf0_out: endpoint {
1437							remote-endpoint = <&mdss_dsi0_in>;
1438						};
1439					};
1440
1441					port@1 {
1442						reg = <1>;
1443						dpu_intf1_out: endpoint {
1444							remote-endpoint = <&mdss_dsi1_in>;
1445						};
1446					};
1447				};
1448
1449				mdp_opp_table: opp-table {
1450					compatible = "operating-points-v2";
1451
1452					opp-19200000 {
1453						opp-hz = /bits/ 64 <19200000>;
1454						required-opps = <&rpmhpd_opp_min_svs>;
1455					};
1456
1457					opp-171428571 {
1458						opp-hz = /bits/ 64 <171428571>;
1459						required-opps = <&rpmhpd_opp_low_svs>;
1460					};
1461
1462					opp-358000000 {
1463						opp-hz = /bits/ 64 <358000000>;
1464						required-opps = <&rpmhpd_opp_svs_l1>;
1465					};
1466
1467					opp-430000000 {
1468						opp-hz = /bits/ 64 <430000000>;
1469						required-opps = <&rpmhpd_opp_nom>;
1470					};
1471				};
1472			};
1473
1474			mdss_dsi0: dsi@ae94000 {
1475				compatible = "qcom,sdm670-dsi-ctrl",
1476					     "qcom,mdss-dsi-ctrl";
1477				reg = <0 0x0ae94000 0 0x400>;
1478				reg-names = "dsi_ctrl";
1479
1480				interrupt-parent = <&mdss>;
1481				interrupts = <4>;
1482
1483				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1484					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1485					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1486					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1487					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1488					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
1489				clock-names = "byte",
1490					      "byte_intf",
1491					      "pixel",
1492					      "core",
1493					      "iface",
1494					      "bus";
1495				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1496						  <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1497				assigned-clock-parents = <&mdss_dsi0_phy 0>,
1498							 <&mdss_dsi0_phy 1>;
1499
1500				operating-points-v2 = <&dsi_opp_table>;
1501				power-domains = <&rpmhpd SDM670_CX>;
1502
1503				phys = <&mdss_dsi0_phy>;
1504
1505				#address-cells = <1>;
1506				#size-cells = <0>;
1507
1508				status = "disabled";
1509
1510				ports {
1511					#address-cells = <1>;
1512					#size-cells = <0>;
1513
1514					port@0 {
1515						reg = <0>;
1516						mdss_dsi0_in: endpoint {
1517							remote-endpoint = <&dpu_intf0_out>;
1518						};
1519					};
1520
1521					port@1 {
1522						reg = <1>;
1523						mdss_dsi0_out: endpoint {
1524						};
1525					};
1526				};
1527			};
1528
1529			mdss_dsi0_phy: phy@ae94400 {
1530				compatible = "qcom,dsi-phy-10nm";
1531				reg = <0 0x0ae94400 0 0x200>,
1532				      <0 0x0ae94600 0 0x280>,
1533				      <0 0x0ae94a00 0 0x1e0>;
1534				reg-names = "dsi_phy",
1535					    "dsi_phy_lane",
1536					    "dsi_pll";
1537
1538				#clock-cells = <1>;
1539				#phy-cells = <0>;
1540
1541				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1542					 <&rpmhcc RPMH_CXO_CLK>;
1543				clock-names = "iface", "ref";
1544
1545				status = "disabled";
1546			};
1547
1548			mdss_dsi1: dsi@ae96000 {
1549				compatible = "qcom,sdm670-dsi-ctrl",
1550					     "qcom,mdss-dsi-ctrl";
1551				reg = <0 0x0ae96000 0 0x400>;
1552				reg-names = "dsi_ctrl";
1553
1554				interrupt-parent = <&mdss>;
1555				interrupts = <5>;
1556
1557				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
1558					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
1559					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
1560					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
1561					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1562					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
1563				clock-names = "byte",
1564					      "byte_intf",
1565					      "pixel",
1566					      "core",
1567					      "iface",
1568					      "bus";
1569				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
1570						  <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
1571				assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1572
1573				operating-points-v2 = <&dsi_opp_table>;
1574				power-domains = <&rpmhpd SDM670_CX>;
1575
1576				phys = <&mdss_dsi1_phy>;
1577
1578				#address-cells = <1>;
1579				#size-cells = <0>;
1580
1581				status = "disabled";
1582
1583				ports {
1584					#address-cells = <1>;
1585					#size-cells = <0>;
1586
1587					port@0 {
1588						reg = <0>;
1589						mdss_dsi1_in: endpoint {
1590							remote-endpoint = <&dpu_intf1_out>;
1591						};
1592					};
1593
1594					port@1 {
1595						reg = <1>;
1596						mdss_dsi1_out: endpoint {
1597						};
1598					};
1599				};
1600			};
1601
1602			mdss_dsi1_phy: phy@ae96400 {
1603				compatible = "qcom,dsi-phy-10nm";
1604				reg = <0 0x0ae96400 0 0x200>,
1605				      <0 0x0ae96600 0 0x280>,
1606				      <0 0x0ae96a00 0 0x10e>;
1607				reg-names = "dsi_phy",
1608					    "dsi_phy_lane",
1609					    "dsi_pll";
1610
1611				#clock-cells = <1>;
1612				#phy-cells = <0>;
1613
1614				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1615					 <&rpmhcc RPMH_CXO_CLK>;
1616				clock-names = "iface", "ref";
1617
1618				status = "disabled";
1619			};
1620		};
1621
1622		dispcc: clock-controller@af00000 {
1623			compatible = "qcom,sdm845-dispcc";
1624			reg = <0 0x0af00000 0 0x10000>;
1625			clocks = <&rpmhcc RPMH_CXO_CLK>,
1626				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1627				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
1628				 <&mdss_dsi0_phy 0>,
1629				 <&mdss_dsi0_phy 1>,
1630				 <&mdss_dsi1_phy 0>,
1631				 <&mdss_dsi1_phy 1>,
1632				 <0>,
1633				 <0>;
1634			clock-names = "bi_tcxo",
1635				      "gcc_disp_gpll0_clk_src",
1636				      "gcc_disp_gpll0_div_clk_src",
1637				      "dsi0_phy_pll_out_byteclk",
1638				      "dsi0_phy_pll_out_dsiclk",
1639				      "dsi1_phy_pll_out_byteclk",
1640				      "dsi1_phy_pll_out_dsiclk",
1641				      "dp_link_clk_divsel_ten",
1642				      "dp_vco_divided_clk_src_mux";
1643			#clock-cells = <1>;
1644			#reset-cells = <1>;
1645			#power-domain-cells = <1>;
1646		};
1647
1648		apps_smmu: iommu@15000000 {
1649			compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1650			reg = <0 0x15000000 0 0x80000>;
1651			#iommu-cells = <2>;
1652			#global-interrupts = <1>;
1653			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1654				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1655				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1656				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1657				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1658				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1659				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1660				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1661				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1662				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1663				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1664				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1665				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1666				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1667				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1668				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1669				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1670				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1671				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1672				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1673				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1674				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1675				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1676				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1677				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1678				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1679				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1680				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1681				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1682				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1683				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1684				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1685				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1686				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1687				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1688				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1689				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1690				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1691				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1692				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1693				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1694				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1695				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1696				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1697				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1698				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1699				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1700				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1701				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1702				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1703				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1704				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1705				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1706				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1707				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1708				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1709				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1710				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1711				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1712				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1713				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1714				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1715				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1716				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1717				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1718		};
1719
1720		gladiator_noc: interconnect@17900000 {
1721			compatible = "qcom,sdm670-gladiator-noc";
1722			reg = <0 0x17900000 0 0xd080>;
1723			#interconnect-cells = <2>;
1724			qcom,bcm-voters = <&apps_bcm_voter>;
1725		};
1726
1727		apps_rsc: rsc@179c0000 {
1728			compatible = "qcom,rpmh-rsc";
1729			reg = <0 0x179c0000 0 0x10000>,
1730			      <0 0x179d0000 0 0x10000>,
1731			      <0 0x179e0000 0 0x10000>;
1732			reg-names = "drv-0", "drv-1", "drv-2";
1733			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1734				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1735				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1736			label = "apps_rsc";
1737			qcom,tcs-offset = <0xd00>;
1738			qcom,drv-id = <2>;
1739			qcom,tcs-config = <ACTIVE_TCS  2>,
1740					  <SLEEP_TCS   3>,
1741					  <WAKE_TCS    3>,
1742					  <CONTROL_TCS 1>;
1743			power-domains = <&CLUSTER_PD>;
1744
1745			apps_bcm_voter: bcm-voter {
1746				compatible = "qcom,bcm-voter";
1747			};
1748
1749			rpmhcc: clock-controller {
1750				compatible = "qcom,sdm670-rpmh-clk";
1751				#clock-cells = <1>;
1752				clock-names = "xo";
1753				clocks = <&xo_board>;
1754			};
1755
1756			rpmhpd: power-controller {
1757				compatible = "qcom,sdm670-rpmhpd";
1758				#power-domain-cells = <1>;
1759				operating-points-v2 = <&rpmhpd_opp_table>;
1760
1761				rpmhpd_opp_table: opp-table {
1762					compatible = "operating-points-v2";
1763
1764					rpmhpd_opp_ret: opp1 {
1765						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1766					};
1767
1768					rpmhpd_opp_min_svs: opp2 {
1769						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1770					};
1771
1772					rpmhpd_opp_low_svs: opp3 {
1773						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1774					};
1775
1776					rpmhpd_opp_svs: opp4 {
1777						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1778					};
1779
1780					rpmhpd_opp_svs_l1: opp5 {
1781						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1782					};
1783
1784					rpmhpd_opp_nom: opp6 {
1785						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1786					};
1787
1788					rpmhpd_opp_nom_l1: opp7 {
1789						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1790					};
1791
1792					rpmhpd_opp_nom_l2: opp8 {
1793						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1794					};
1795
1796					rpmhpd_opp_turbo: opp9 {
1797						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1798					};
1799
1800					rpmhpd_opp_turbo_l1: opp10 {
1801						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1802					};
1803				};
1804			};
1805		};
1806
1807		intc: interrupt-controller@17a00000 {
1808			compatible = "arm,gic-v3";
1809			reg = <0 0x17a00000 0 0x10000>,     /* GICD */
1810			      <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
1811			interrupt-controller;
1812			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1813			#interrupt-cells = <3>;
1814		};
1815
1816		osm_l3: interconnect@17d41000 {
1817			compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
1818			reg = <0 0x17d41000 0 0x1400>;
1819
1820			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1821			clock-names = "xo", "alternate";
1822
1823			#interconnect-cells = <1>;
1824		};
1825
1826		cpufreq_hw: cpufreq@17d43000 {
1827			compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw";
1828			reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
1829			reg-names = "freq-domain0", "freq-domain1";
1830
1831			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1832			clock-names = "xo", "alternate";
1833
1834			#freq-domain-cells = <1>;
1835		};
1836	};
1837};
1838