1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/interconnect/qcom,sdm660.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/qcom,apr.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 mmc1 = &sdhc_1; 25 mmc2 = &sdhc_2; 26 }; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <19200000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 clock-output-names = "sleep_clk"; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 CPU0: cpu@100 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 cpu-idle-states = <&PERF_CPU_SLEEP_0 56 &PERF_CPU_SLEEP_1 57 &PERF_CLUSTER_SLEEP_0 58 &PERF_CLUSTER_SLEEP_1 59 &PERF_CLUSTER_SLEEP_2>; 60 capacity-dmips-mhz = <1126>; 61 #cooling-cells = <2>; 62 next-level-cache = <&L2_1>; 63 L2_1: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 }; 67 }; 68 69 CPU1: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x101>; 73 enable-method = "psci"; 74 cpu-idle-states = <&PERF_CPU_SLEEP_0 75 &PERF_CPU_SLEEP_1 76 &PERF_CLUSTER_SLEEP_0 77 &PERF_CLUSTER_SLEEP_1 78 &PERF_CLUSTER_SLEEP_2>; 79 capacity-dmips-mhz = <1126>; 80 #cooling-cells = <2>; 81 next-level-cache = <&L2_1>; 82 }; 83 84 CPU2: cpu@102 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x102>; 88 enable-method = "psci"; 89 cpu-idle-states = <&PERF_CPU_SLEEP_0 90 &PERF_CPU_SLEEP_1 91 &PERF_CLUSTER_SLEEP_0 92 &PERF_CLUSTER_SLEEP_1 93 &PERF_CLUSTER_SLEEP_2>; 94 capacity-dmips-mhz = <1126>; 95 #cooling-cells = <2>; 96 next-level-cache = <&L2_1>; 97 }; 98 99 CPU3: cpu@103 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x0 0x103>; 103 enable-method = "psci"; 104 cpu-idle-states = <&PERF_CPU_SLEEP_0 105 &PERF_CPU_SLEEP_1 106 &PERF_CLUSTER_SLEEP_0 107 &PERF_CLUSTER_SLEEP_1 108 &PERF_CLUSTER_SLEEP_2>; 109 capacity-dmips-mhz = <1126>; 110 #cooling-cells = <2>; 111 next-level-cache = <&L2_1>; 112 }; 113 114 CPU4: cpu@0 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x0 0x0>; 118 enable-method = "psci"; 119 cpu-idle-states = <&PWR_CPU_SLEEP_0 120 &PWR_CPU_SLEEP_1 121 &PWR_CLUSTER_SLEEP_0 122 &PWR_CLUSTER_SLEEP_1 123 &PWR_CLUSTER_SLEEP_2>; 124 capacity-dmips-mhz = <1024>; 125 #cooling-cells = <2>; 126 next-level-cache = <&L2_0>; 127 L2_0: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 }; 131 }; 132 133 CPU5: cpu@1 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53"; 136 reg = <0x0 0x1>; 137 enable-method = "psci"; 138 cpu-idle-states = <&PWR_CPU_SLEEP_0 139 &PWR_CPU_SLEEP_1 140 &PWR_CLUSTER_SLEEP_0 141 &PWR_CLUSTER_SLEEP_1 142 &PWR_CLUSTER_SLEEP_2>; 143 capacity-dmips-mhz = <1024>; 144 #cooling-cells = <2>; 145 next-level-cache = <&L2_0>; 146 }; 147 148 CPU6: cpu@2 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53"; 151 reg = <0x0 0x2>; 152 enable-method = "psci"; 153 cpu-idle-states = <&PWR_CPU_SLEEP_0 154 &PWR_CPU_SLEEP_1 155 &PWR_CLUSTER_SLEEP_0 156 &PWR_CLUSTER_SLEEP_1 157 &PWR_CLUSTER_SLEEP_2>; 158 capacity-dmips-mhz = <1024>; 159 #cooling-cells = <2>; 160 next-level-cache = <&L2_0>; 161 }; 162 163 CPU7: cpu@3 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a53"; 166 reg = <0x0 0x3>; 167 enable-method = "psci"; 168 cpu-idle-states = <&PWR_CPU_SLEEP_0 169 &PWR_CPU_SLEEP_1 170 &PWR_CLUSTER_SLEEP_0 171 &PWR_CLUSTER_SLEEP_1 172 &PWR_CLUSTER_SLEEP_2>; 173 capacity-dmips-mhz = <1024>; 174 #cooling-cells = <2>; 175 next-level-cache = <&L2_0>; 176 }; 177 178 cpu-map { 179 cluster0 { 180 core0 { 181 cpu = <&CPU4>; 182 }; 183 184 core1 { 185 cpu = <&CPU5>; 186 }; 187 188 core2 { 189 cpu = <&CPU6>; 190 }; 191 192 core3 { 193 cpu = <&CPU7>; 194 }; 195 }; 196 197 cluster1 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 }; 214 }; 215 216 idle-states { 217 entry-method = "psci"; 218 219 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 220 compatible = "arm,idle-state"; 221 idle-state-name = "pwr-retention"; 222 arm,psci-suspend-param = <0x40000002>; 223 entry-latency-us = <338>; 224 exit-latency-us = <423>; 225 min-residency-us = <200>; 226 }; 227 228 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 229 compatible = "arm,idle-state"; 230 idle-state-name = "pwr-power-collapse"; 231 arm,psci-suspend-param = <0x40000003>; 232 entry-latency-us = <515>; 233 exit-latency-us = <1821>; 234 min-residency-us = <1000>; 235 local-timer-stop; 236 }; 237 238 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 239 compatible = "arm,idle-state"; 240 idle-state-name = "perf-retention"; 241 arm,psci-suspend-param = <0x40000002>; 242 entry-latency-us = <154>; 243 exit-latency-us = <87>; 244 min-residency-us = <200>; 245 }; 246 247 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "perf-power-collapse"; 250 arm,psci-suspend-param = <0x40000003>; 251 entry-latency-us = <262>; 252 exit-latency-us = <301>; 253 min-residency-us = <1000>; 254 local-timer-stop; 255 }; 256 257 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "pwr-cluster-dynamic-retention"; 260 arm,psci-suspend-param = <0x400000F2>; 261 entry-latency-us = <284>; 262 exit-latency-us = <384>; 263 min-residency-us = <9987>; 264 local-timer-stop; 265 }; 266 267 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "pwr-cluster-retention"; 270 arm,psci-suspend-param = <0x400000F3>; 271 entry-latency-us = <338>; 272 exit-latency-us = <423>; 273 min-residency-us = <9987>; 274 local-timer-stop; 275 }; 276 277 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "pwr-cluster-retention"; 280 arm,psci-suspend-param = <0x400000F4>; 281 entry-latency-us = <515>; 282 exit-latency-us = <1821>; 283 min-residency-us = <9987>; 284 local-timer-stop; 285 }; 286 287 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 288 compatible = "arm,idle-state"; 289 idle-state-name = "perf-cluster-dynamic-retention"; 290 arm,psci-suspend-param = <0x400000F2>; 291 entry-latency-us = <272>; 292 exit-latency-us = <329>; 293 min-residency-us = <9987>; 294 local-timer-stop; 295 }; 296 297 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 298 compatible = "arm,idle-state"; 299 idle-state-name = "perf-cluster-retention"; 300 arm,psci-suspend-param = <0x400000F3>; 301 entry-latency-us = <332>; 302 exit-latency-us = <368>; 303 min-residency-us = <9987>; 304 local-timer-stop; 305 }; 306 307 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 308 compatible = "arm,idle-state"; 309 idle-state-name = "perf-cluster-retention"; 310 arm,psci-suspend-param = <0x400000F4>; 311 entry-latency-us = <545>; 312 exit-latency-us = <1609>; 313 min-residency-us = <9987>; 314 local-timer-stop; 315 }; 316 }; 317 }; 318 319 firmware { 320 scm { 321 compatible = "qcom,scm-msm8998", "qcom,scm"; 322 }; 323 }; 324 325 memory@80000000 { 326 device_type = "memory"; 327 /* We expect the bootloader to fill in the reg */ 328 reg = <0x0 0x80000000 0x0 0x0>; 329 }; 330 331 pmu { 332 compatible = "arm,armv8-pmuv3"; 333 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 334 }; 335 336 psci { 337 compatible = "arm,psci-1.0"; 338 method = "smc"; 339 }; 340 341 reserved-memory { 342 #address-cells = <2>; 343 #size-cells = <2>; 344 ranges; 345 346 wlan_msa_guard: wlan-msa-guard@85600000 { 347 reg = <0x0 0x85600000 0x0 0x100000>; 348 no-map; 349 }; 350 351 wlan_msa_mem: wlan-msa-mem@85700000 { 352 reg = <0x0 0x85700000 0x0 0x100000>; 353 no-map; 354 }; 355 356 qhee_code: qhee-code@85800000 { 357 reg = <0x0 0x85800000 0x0 0x600000>; 358 no-map; 359 }; 360 361 rmtfs_mem: memory@85e00000 { 362 compatible = "qcom,rmtfs-mem"; 363 reg = <0x0 0x85e00000 0x0 0x200000>; 364 no-map; 365 366 qcom,client-id = <1>; 367 qcom,vmid = <15>; 368 }; 369 370 smem_region: smem-mem@86000000 { 371 reg = <0 0x86000000 0 0x200000>; 372 no-map; 373 }; 374 375 tz_mem: memory@86200000 { 376 reg = <0x0 0x86200000 0x0 0x3300000>; 377 no-map; 378 }; 379 380 mpss_region: mpss@8ac00000 { 381 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 382 no-map; 383 }; 384 385 adsp_region: adsp@92a00000 { 386 reg = <0x0 0x92a00000 0x0 0x1e00000>; 387 no-map; 388 }; 389 390 mba_region: mba@94800000 { 391 reg = <0x0 0x94800000 0x0 0x200000>; 392 no-map; 393 }; 394 395 buffer_mem: tzbuffer@94a00000 { 396 reg = <0x0 0x94a00000 0x0 0x100000>; 397 no-map; 398 }; 399 400 venus_region: venus@9f800000 { 401 reg = <0x0 0x9f800000 0x0 0x800000>; 402 no-map; 403 }; 404 405 adsp_mem: adsp-region@f6000000 { 406 reg = <0x0 0xf6000000 0x0 0x800000>; 407 no-map; 408 }; 409 410 qseecom_mem: qseecom-region@f6800000 { 411 reg = <0x0 0xf6800000 0x0 0x1400000>; 412 no-map; 413 }; 414 415 zap_shader_region: gpu@fed00000 { 416 compatible = "shared-dma-pool"; 417 reg = <0x0 0xfed00000 0x0 0xa00000>; 418 no-map; 419 }; 420 }; 421 422 rpm-glink { 423 compatible = "qcom,glink-rpm"; 424 425 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 426 qcom,rpm-msg-ram = <&rpm_msg_ram>; 427 mboxes = <&apcs_glb 0>; 428 429 rpm_requests: rpm-requests { 430 compatible = "qcom,rpm-sdm660"; 431 qcom,glink-channels = "rpm_requests"; 432 433 rpmcc: clock-controller { 434 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 435 #clock-cells = <1>; 436 }; 437 438 rpmpd: power-controller { 439 compatible = "qcom,sdm660-rpmpd"; 440 #power-domain-cells = <1>; 441 operating-points-v2 = <&rpmpd_opp_table>; 442 443 rpmpd_opp_table: opp-table { 444 compatible = "operating-points-v2"; 445 446 rpmpd_opp_ret: opp1 { 447 opp-level = <RPM_SMD_LEVEL_RETENTION>; 448 }; 449 450 rpmpd_opp_ret_plus: opp2 { 451 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 452 }; 453 454 rpmpd_opp_min_svs: opp3 { 455 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 456 }; 457 458 rpmpd_opp_low_svs: opp4 { 459 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 460 }; 461 462 rpmpd_opp_svs: opp5 { 463 opp-level = <RPM_SMD_LEVEL_SVS>; 464 }; 465 466 rpmpd_opp_svs_plus: opp6 { 467 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 468 }; 469 470 rpmpd_opp_nom: opp7 { 471 opp-level = <RPM_SMD_LEVEL_NOM>; 472 }; 473 474 rpmpd_opp_nom_plus: opp8 { 475 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 476 }; 477 478 rpmpd_opp_turbo: opp9 { 479 opp-level = <RPM_SMD_LEVEL_TURBO>; 480 }; 481 }; 482 }; 483 }; 484 }; 485 486 smem: smem { 487 compatible = "qcom,smem"; 488 memory-region = <&smem_region>; 489 hwlocks = <&tcsr_mutex 3>; 490 }; 491 492 smp2p-adsp { 493 compatible = "qcom,smp2p"; 494 qcom,smem = <443>, <429>; 495 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 496 mboxes = <&apcs_glb 10>; 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <2>; 499 500 adsp_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 adsp_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 smp2p-mpss { 513 compatible = "qcom,smp2p"; 514 qcom,smem = <435>, <428>; 515 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 516 mboxes = <&apcs_glb 14>; 517 qcom,local-pid = <0>; 518 qcom,remote-pid = <1>; 519 520 modem_smp2p_out: master-kernel { 521 qcom,entry-name = "master-kernel"; 522 #qcom,smem-state-cells = <1>; 523 }; 524 525 modem_smp2p_in: slave-kernel { 526 qcom,entry-name = "slave-kernel"; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 }; 531 532 soc { 533 #address-cells = <1>; 534 #size-cells = <1>; 535 ranges = <0 0 0 0xffffffff>; 536 compatible = "simple-bus"; 537 538 gcc: clock-controller@100000 { 539 compatible = "qcom,gcc-sdm630"; 540 #clock-cells = <1>; 541 #reset-cells = <1>; 542 #power-domain-cells = <1>; 543 reg = <0x00100000 0x94000>; 544 545 clock-names = "xo", "sleep_clk"; 546 clocks = <&xo_board>, 547 <&sleep_clk>; 548 }; 549 550 rpm_msg_ram: sram@778000 { 551 compatible = "qcom,rpm-msg-ram"; 552 reg = <0x00778000 0x7000>; 553 }; 554 555 qfprom: qfprom@780000 { 556 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 557 reg = <0x00780000 0x621c>; 558 #address-cells = <1>; 559 #size-cells = <1>; 560 561 qusb2_hstx_trim: hstx-trim@240 { 562 reg = <0x243 0x1>; 563 bits = <1 3>; 564 }; 565 566 gpu_speed_bin: gpu-speed-bin@41a0 { 567 reg = <0x41a2 0x1>; 568 bits = <5 7>; 569 }; 570 }; 571 572 rng: rng@793000 { 573 compatible = "qcom,prng-ee"; 574 reg = <0x00793000 0x1000>; 575 clocks = <&gcc GCC_PRNG_AHB_CLK>; 576 clock-names = "core"; 577 }; 578 579 bimc: interconnect@1008000 { 580 compatible = "qcom,sdm660-bimc"; 581 reg = <0x01008000 0x78000>; 582 #interconnect-cells = <1>; 583 clock-names = "bus", "bus_a"; 584 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 585 <&rpmcc RPM_SMD_BIMC_A_CLK>; 586 }; 587 588 restart@10ac000 { 589 compatible = "qcom,pshold"; 590 reg = <0x010ac000 0x4>; 591 }; 592 593 cnoc: interconnect@1500000 { 594 compatible = "qcom,sdm660-cnoc"; 595 reg = <0x01500000 0x10000>; 596 #interconnect-cells = <1>; 597 clock-names = "bus", "bus_a"; 598 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 599 <&rpmcc RPM_SMD_CNOC_A_CLK>; 600 }; 601 602 snoc: interconnect@1626000 { 603 compatible = "qcom,sdm660-snoc"; 604 reg = <0x01626000 0x7090>; 605 #interconnect-cells = <1>; 606 clock-names = "bus", "bus_a"; 607 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 608 <&rpmcc RPM_SMD_SNOC_A_CLK>; 609 }; 610 611 anoc2_smmu: iommu@16c0000 { 612 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 613 reg = <0x016c0000 0x40000>; 614 615 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 616 assigned-clock-rates = <1000>; 617 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 618 clock-names = "bus"; 619 #global-interrupts = <2>; 620 #iommu-cells = <1>; 621 622 interrupts = 623 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 625 626 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 628 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 629 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 630 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 631 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 632 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 655 656 status = "disabled"; 657 }; 658 659 a2noc: interconnect@1704000 { 660 compatible = "qcom,sdm660-a2noc"; 661 reg = <0x01704000 0xc100>; 662 #interconnect-cells = <1>; 663 clock-names = "bus", 664 "bus_a", 665 "ipa", 666 "ufs_axi", 667 "aggre2_ufs_axi", 668 "aggre2_usb3_axi", 669 "cfg_noc_usb2_axi"; 670 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 671 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 672 <&rpmcc RPM_SMD_IPA_CLK>, 673 <&gcc GCC_UFS_AXI_CLK>, 674 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 675 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 676 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 677 }; 678 679 mnoc: interconnect@1745000 { 680 compatible = "qcom,sdm660-mnoc"; 681 reg = <0x01745000 0xA010>; 682 #interconnect-cells = <1>; 683 clock-names = "bus", "bus_a", "iface"; 684 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 685 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 686 <&mmcc AHB_CLK_SRC>; 687 }; 688 689 tsens: thermal-sensor@10ae000 { 690 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 691 reg = <0x010ae000 0x1000>, /* TM */ 692 <0x010ad000 0x1000>; /* SROT */ 693 #qcom,sensors = <12>; 694 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 696 interrupt-names = "uplow", "critical"; 697 #thermal-sensor-cells = <1>; 698 }; 699 700 tcsr_mutex_regs: syscon@1f40000 { 701 compatible = "syscon"; 702 reg = <0x01f40000 0x40000>; 703 }; 704 705 tlmm: pinctrl@3100000 { 706 compatible = "qcom,sdm630-pinctrl"; 707 reg = <0x03100000 0x400000>, 708 <0x03500000 0x400000>, 709 <0x03900000 0x400000>; 710 reg-names = "south", "center", "north"; 711 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 712 gpio-controller; 713 gpio-ranges = <&tlmm 0 0 114>; 714 #gpio-cells = <2>; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 718 blsp1_uart1_default: blsp1-uart1-default { 719 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 720 drive-strength = <2>; 721 bias-disable; 722 }; 723 724 blsp1_uart1_sleep: blsp1-uart1-sleep { 725 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 726 drive-strength = <2>; 727 bias-disable; 728 }; 729 730 blsp1_uart2_default: blsp1-uart2-default { 731 pins = "gpio4", "gpio5"; 732 drive-strength = <2>; 733 bias-disable; 734 }; 735 736 blsp2_uart1_default: blsp2-uart1-active { 737 tx-rts { 738 pins = "gpio16", "gpio19"; 739 function = "blsp_uart5"; 740 drive-strength = <2>; 741 bias-disable; 742 }; 743 744 rx { 745 /* 746 * Avoid garbage data while BT module 747 * is powered off or not driving signal 748 */ 749 pins = "gpio17"; 750 function = "blsp_uart5"; 751 drive-strength = <2>; 752 bias-pull-up; 753 }; 754 755 cts { 756 /* Match the pull of the BT module */ 757 pins = "gpio18"; 758 function = "blsp_uart5"; 759 drive-strength = <2>; 760 bias-pull-down; 761 }; 762 }; 763 764 blsp2_uart1_sleep: blsp2-uart1-sleep { 765 tx { 766 pins = "gpio16"; 767 function = "gpio"; 768 drive-strength = <2>; 769 bias-pull-up; 770 }; 771 772 rx-cts-rts { 773 pins = "gpio17", "gpio18", "gpio19"; 774 function = "gpio"; 775 drive-strength = <2>; 776 bias-no-pull; 777 }; 778 }; 779 780 i2c1_default: i2c1-default { 781 pins = "gpio2", "gpio3"; 782 function = "blsp_i2c1"; 783 drive-strength = <2>; 784 bias-disable; 785 }; 786 787 i2c1_sleep: i2c1-sleep { 788 pins = "gpio2", "gpio3"; 789 function = "blsp_i2c1"; 790 drive-strength = <2>; 791 bias-pull-up; 792 }; 793 794 i2c2_default: i2c2-default { 795 pins = "gpio6", "gpio7"; 796 function = "blsp_i2c2"; 797 drive-strength = <2>; 798 bias-disable; 799 }; 800 801 i2c2_sleep: i2c2-sleep { 802 pins = "gpio6", "gpio7"; 803 function = "blsp_i2c2"; 804 drive-strength = <2>; 805 bias-pull-up; 806 }; 807 808 i2c3_default: i2c3-default { 809 pins = "gpio10", "gpio11"; 810 function = "blsp_i2c3"; 811 drive-strength = <2>; 812 bias-disable; 813 }; 814 815 i2c3_sleep: i2c3-sleep { 816 pins = "gpio10", "gpio11"; 817 function = "blsp_i2c3"; 818 drive-strength = <2>; 819 bias-pull-up; 820 }; 821 822 i2c4_default: i2c4-default { 823 pins = "gpio14", "gpio15"; 824 function = "blsp_i2c4"; 825 drive-strength = <2>; 826 bias-disable; 827 }; 828 829 i2c4_sleep: i2c4-sleep { 830 pins = "gpio14", "gpio15"; 831 function = "blsp_i2c4"; 832 drive-strength = <2>; 833 bias-pull-up; 834 }; 835 836 i2c5_default: i2c5-default { 837 pins = "gpio18", "gpio19"; 838 function = "blsp_i2c5"; 839 drive-strength = <2>; 840 bias-disable; 841 }; 842 843 i2c5_sleep: i2c5-sleep { 844 pins = "gpio18", "gpio19"; 845 function = "blsp_i2c5"; 846 drive-strength = <2>; 847 bias-pull-up; 848 }; 849 850 i2c6_default: i2c6-default { 851 pins = "gpio22", "gpio23"; 852 function = "blsp_i2c6"; 853 drive-strength = <2>; 854 bias-disable; 855 }; 856 857 i2c6_sleep: i2c6-sleep { 858 pins = "gpio22", "gpio23"; 859 function = "blsp_i2c6"; 860 drive-strength = <2>; 861 bias-pull-up; 862 }; 863 864 i2c7_default: i2c7-default { 865 pins = "gpio26", "gpio27"; 866 function = "blsp_i2c7"; 867 drive-strength = <2>; 868 bias-disable; 869 }; 870 871 i2c7_sleep: i2c7-sleep { 872 pins = "gpio26", "gpio27"; 873 function = "blsp_i2c7"; 874 drive-strength = <2>; 875 bias-pull-up; 876 }; 877 878 i2c8_default: i2c8-default { 879 pins = "gpio30", "gpio31"; 880 function = "blsp_i2c8"; 881 drive-strength = <2>; 882 bias-disable; 883 }; 884 885 i2c8_sleep: i2c8-sleep { 886 pins = "gpio30", "gpio31"; 887 function = "blsp_i2c8"; 888 drive-strength = <2>; 889 bias-pull-up; 890 }; 891 892 cci0_default: cci0_default { 893 pinmux { 894 pins = "gpio36","gpio37"; 895 function = "cci_i2c"; 896 }; 897 898 pinconf { 899 pins = "gpio36","gpio37"; 900 bias-pull-up; 901 drive-strength = <2>; 902 }; 903 }; 904 905 cci1_default: cci1_default { 906 pinmux { 907 pins = "gpio38","gpio39"; 908 function = "cci_i2c"; 909 }; 910 911 pinconf { 912 pins = "gpio38","gpio39"; 913 bias-pull-up; 914 drive-strength = <2>; 915 }; 916 }; 917 918 sdc1_state_on: sdc1-on { 919 clk { 920 pins = "sdc1_clk"; 921 bias-disable; 922 drive-strength = <16>; 923 }; 924 925 cmd { 926 pins = "sdc1_cmd"; 927 bias-pull-up; 928 drive-strength = <10>; 929 }; 930 931 data { 932 pins = "sdc1_data"; 933 bias-pull-up; 934 drive-strength = <10>; 935 }; 936 937 rclk { 938 pins = "sdc1_rclk"; 939 bias-pull-down; 940 }; 941 }; 942 943 sdc1_state_off: sdc1-off { 944 clk { 945 pins = "sdc1_clk"; 946 bias-disable; 947 drive-strength = <2>; 948 }; 949 950 cmd { 951 pins = "sdc1_cmd"; 952 bias-pull-up; 953 drive-strength = <2>; 954 }; 955 956 data { 957 pins = "sdc1_data"; 958 bias-pull-up; 959 drive-strength = <2>; 960 }; 961 962 rclk { 963 pins = "sdc1_rclk"; 964 bias-pull-down; 965 }; 966 }; 967 968 sdc2_state_on: sdc2-on { 969 clk { 970 pins = "sdc2_clk"; 971 bias-disable; 972 drive-strength = <16>; 973 }; 974 975 cmd { 976 pins = "sdc2_cmd"; 977 bias-pull-up; 978 drive-strength = <10>; 979 }; 980 981 data { 982 pins = "sdc2_data"; 983 bias-pull-up; 984 drive-strength = <10>; 985 }; 986 }; 987 988 sdc2_state_off: sdc2-off { 989 clk { 990 pins = "sdc2_clk"; 991 bias-disable; 992 drive-strength = <2>; 993 }; 994 995 cmd { 996 pins = "sdc2_cmd"; 997 bias-pull-up; 998 drive-strength = <2>; 999 }; 1000 1001 data { 1002 pins = "sdc2_data"; 1003 bias-pull-up; 1004 drive-strength = <2>; 1005 }; 1006 }; 1007 }; 1008 1009 adreno_gpu: gpu@5000000 { 1010 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1011 1012 reg = <0x05000000 0x40000>; 1013 reg-names = "kgsl_3d0_reg_memory"; 1014 1015 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1016 1017 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1018 <&gpucc GPUCC_RBBMTIMER_CLK>, 1019 <&gcc GCC_BIMC_GFX_CLK>, 1020 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1021 <&gpucc GPUCC_RBCPR_CLK>, 1022 <&gpucc GPUCC_GFX3D_CLK>; 1023 1024 clock-names = "iface", 1025 "rbbmtimer", 1026 "mem", 1027 "mem_iface", 1028 "rbcpr", 1029 "core"; 1030 1031 power-domains = <&rpmpd SDM660_VDDMX>; 1032 iommus = <&kgsl_smmu 0>; 1033 1034 nvmem-cells = <&gpu_speed_bin>; 1035 nvmem-cell-names = "speed_bin"; 1036 1037 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1038 interconnect-names = "gfx-mem"; 1039 1040 operating-points-v2 = <&gpu_sdm630_opp_table>; 1041 1042 status = "disabled"; 1043 1044 gpu_sdm630_opp_table: opp-table { 1045 compatible = "operating-points-v2"; 1046 opp-775000000 { 1047 opp-hz = /bits/ 64 <775000000>; 1048 opp-level = <RPM_SMD_LEVEL_TURBO>; 1049 opp-peak-kBps = <5412000>; 1050 opp-supported-hw = <0xA2>; 1051 }; 1052 opp-647000000 { 1053 opp-hz = /bits/ 64 <647000000>; 1054 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1055 opp-peak-kBps = <4068000>; 1056 opp-supported-hw = <0xFF>; 1057 }; 1058 opp-588000000 { 1059 opp-hz = /bits/ 64 <588000000>; 1060 opp-level = <RPM_SMD_LEVEL_NOM>; 1061 opp-peak-kBps = <3072000>; 1062 opp-supported-hw = <0xFF>; 1063 }; 1064 opp-465000000 { 1065 opp-hz = /bits/ 64 <465000000>; 1066 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1067 opp-peak-kBps = <2724000>; 1068 opp-supported-hw = <0xFF>; 1069 }; 1070 opp-370000000 { 1071 opp-hz = /bits/ 64 <370000000>; 1072 opp-level = <RPM_SMD_LEVEL_SVS>; 1073 opp-peak-kBps = <2188000>; 1074 opp-supported-hw = <0xFF>; 1075 }; 1076 opp-240000000 { 1077 opp-hz = /bits/ 64 <240000000>; 1078 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1079 opp-peak-kBps = <1648000>; 1080 opp-supported-hw = <0xFF>; 1081 }; 1082 opp-160000000 { 1083 opp-hz = /bits/ 64 <160000000>; 1084 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1085 opp-peak-kBps = <1200000>; 1086 opp-supported-hw = <0xFF>; 1087 }; 1088 }; 1089 }; 1090 1091 kgsl_smmu: iommu@5040000 { 1092 compatible = "qcom,sdm630-smmu-v2", 1093 "qcom,adreno-smmu", "qcom,smmu-v2"; 1094 reg = <0x05040000 0x10000>; 1095 1096 /* 1097 * GX GDSC parent is CX. We need to bring up CX for SMMU 1098 * but we need both up for Adreno. On the other hand, we 1099 * need to manage the GX rpmpd domain in the adreno driver. 1100 * Enable CX/GX GDSCs here so that we can manage just the GX 1101 * RPM Power Domain in the Adreno driver. 1102 */ 1103 power-domains = <&gpucc GPU_GX_GDSC>; 1104 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1105 <&gcc GCC_BIMC_GFX_CLK>, 1106 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1107 clock-names = "iface", "mem", "mem_iface"; 1108 #global-interrupts = <2>; 1109 #iommu-cells = <1>; 1110 1111 interrupts = 1112 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1114 1115 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1123 1124 status = "disabled"; 1125 }; 1126 1127 gpucc: clock-controller@5065000 { 1128 compatible = "qcom,gpucc-sdm630"; 1129 #clock-cells = <1>; 1130 #reset-cells = <1>; 1131 #power-domain-cells = <1>; 1132 reg = <0x05065000 0x9038>; 1133 1134 clocks = <&xo_board>, 1135 <&gcc GCC_GPU_GPLL0_CLK>, 1136 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1137 clock-names = "xo", 1138 "gcc_gpu_gpll0_clk", 1139 "gcc_gpu_gpll0_div_clk"; 1140 status = "disabled"; 1141 }; 1142 1143 lpass_smmu: iommu@5100000 { 1144 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1145 reg = <0x05100000 0x40000>; 1146 #iommu-cells = <1>; 1147 1148 #global-interrupts = <2>; 1149 interrupts = 1150 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1152 1153 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1170 1171 status = "disabled"; 1172 }; 1173 1174 sram@290000 { 1175 compatible = "qcom,rpm-stats"; 1176 reg = <0x00290000 0x10000>; 1177 }; 1178 1179 spmi_bus: spmi@800f000 { 1180 compatible = "qcom,spmi-pmic-arb"; 1181 reg = <0x0800f000 0x1000>, 1182 <0x08400000 0x1000000>, 1183 <0x09400000 0x1000000>, 1184 <0x0a400000 0x220000>, 1185 <0x0800a000 0x3000>; 1186 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1187 interrupt-names = "periph_irq"; 1188 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1189 qcom,ee = <0>; 1190 qcom,channel = <0>; 1191 #address-cells = <2>; 1192 #size-cells = <0>; 1193 interrupt-controller; 1194 #interrupt-cells = <4>; 1195 cell-index = <0>; 1196 }; 1197 1198 usb3: usb@a8f8800 { 1199 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1200 reg = <0x0a8f8800 0x400>; 1201 status = "disabled"; 1202 #address-cells = <1>; 1203 #size-cells = <1>; 1204 ranges; 1205 1206 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1207 <&gcc GCC_USB30_MASTER_CLK>, 1208 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1209 <&gcc GCC_USB30_SLEEP_CLK>, 1210 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1211 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1212 clock-names = "cfg_noc", 1213 "core", 1214 "iface", 1215 "sleep", 1216 "mock_utmi", 1217 "bus"; 1218 1219 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1220 <&gcc GCC_USB30_MASTER_CLK>, 1221 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1222 assigned-clock-rates = <19200000>, <120000000>, 1223 <19200000>; 1224 1225 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1227 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1228 1229 power-domains = <&gcc USB_30_GDSC>; 1230 qcom,select-utmi-as-pipe-clk; 1231 1232 resets = <&gcc GCC_USB_30_BCR>; 1233 1234 usb3_dwc3: usb@a800000 { 1235 compatible = "snps,dwc3"; 1236 reg = <0x0a800000 0xc8d0>; 1237 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1238 snps,dis_u2_susphy_quirk; 1239 snps,dis_enblslpm_quirk; 1240 1241 /* 1242 * SDM630 technically supports USB3 but I 1243 * haven't seen any devices making use of it. 1244 */ 1245 maximum-speed = "high-speed"; 1246 phys = <&qusb2phy0>; 1247 phy-names = "usb2-phy"; 1248 snps,hird-threshold = /bits/ 8 <0>; 1249 }; 1250 }; 1251 1252 qusb2phy0: phy@c012000 { 1253 compatible = "qcom,sdm660-qusb2-phy"; 1254 reg = <0x0c012000 0x180>; 1255 #phy-cells = <0>; 1256 1257 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1258 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1259 clock-names = "cfg_ahb", "ref"; 1260 1261 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1262 nvmem-cells = <&qusb2_hstx_trim>; 1263 status = "disabled"; 1264 }; 1265 1266 qusb2phy1: phy@c014000 { 1267 compatible = "qcom,sdm660-qusb2-phy"; 1268 reg = <0x0c014000 0x180>; 1269 #phy-cells = <0>; 1270 1271 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1272 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1273 clock-names = "cfg_ahb", "ref"; 1274 1275 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1276 nvmem-cells = <&qusb2_hstx_trim>; 1277 status = "disabled"; 1278 }; 1279 1280 sdhc_2: mmc@c084000 { 1281 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1282 reg = <0x0c084000 0x1000>; 1283 reg-names = "hc"; 1284 1285 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1287 interrupt-names = "hc_irq", "pwr_irq"; 1288 1289 bus-width = <4>; 1290 1291 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1292 <&gcc GCC_SDCC2_APPS_CLK>, 1293 <&xo_board>; 1294 clock-names = "iface", "core", "xo"; 1295 1296 1297 interconnects = <&a2noc 3 &a2noc 10>, 1298 <&gnoc 0 &cnoc 28>; 1299 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1300 operating-points-v2 = <&sdhc2_opp_table>; 1301 1302 pinctrl-names = "default", "sleep"; 1303 pinctrl-0 = <&sdc2_state_on>; 1304 pinctrl-1 = <&sdc2_state_off>; 1305 power-domains = <&rpmpd SDM660_VDDCX>; 1306 1307 status = "disabled"; 1308 1309 sdhc2_opp_table: opp-table { 1310 compatible = "operating-points-v2"; 1311 1312 opp-50000000 { 1313 opp-hz = /bits/ 64 <50000000>; 1314 required-opps = <&rpmpd_opp_low_svs>; 1315 opp-peak-kBps = <200000 140000>; 1316 opp-avg-kBps = <130718 133320>; 1317 }; 1318 opp-100000000 { 1319 opp-hz = /bits/ 64 <100000000>; 1320 required-opps = <&rpmpd_opp_svs>; 1321 opp-peak-kBps = <250000 160000>; 1322 opp-avg-kBps = <196078 150000>; 1323 }; 1324 opp-200000000 { 1325 opp-hz = /bits/ 64 <200000000>; 1326 required-opps = <&rpmpd_opp_nom>; 1327 opp-peak-kBps = <4096000 4096000>; 1328 opp-avg-kBps = <1338562 1338562>; 1329 }; 1330 }; 1331 }; 1332 1333 sdhc_1: mmc@c0c4000 { 1334 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1335 reg = <0x0c0c4000 0x1000>, 1336 <0x0c0c5000 0x1000>, 1337 <0x0c0c8000 0x8000>; 1338 reg-names = "hc", "cqhci", "ice"; 1339 1340 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1342 interrupt-names = "hc_irq", "pwr_irq"; 1343 1344 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1345 <&gcc GCC_SDCC1_APPS_CLK>, 1346 <&xo_board>, 1347 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1348 clock-names = "iface", "core", "xo", "ice"; 1349 1350 interconnects = <&a2noc 2 &a2noc 10>, 1351 <&gnoc 0 &cnoc 27>; 1352 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1353 operating-points-v2 = <&sdhc1_opp_table>; 1354 pinctrl-names = "default", "sleep"; 1355 pinctrl-0 = <&sdc1_state_on>; 1356 pinctrl-1 = <&sdc1_state_off>; 1357 power-domains = <&rpmpd SDM660_VDDCX>; 1358 1359 bus-width = <8>; 1360 non-removable; 1361 1362 status = "disabled"; 1363 1364 sdhc1_opp_table: opp-table { 1365 compatible = "operating-points-v2"; 1366 1367 opp-50000000 { 1368 opp-hz = /bits/ 64 <50000000>; 1369 required-opps = <&rpmpd_opp_low_svs>; 1370 opp-peak-kBps = <200000 140000>; 1371 opp-avg-kBps = <130718 133320>; 1372 }; 1373 opp-100000000 { 1374 opp-hz = /bits/ 64 <100000000>; 1375 required-opps = <&rpmpd_opp_svs>; 1376 opp-peak-kBps = <250000 160000>; 1377 opp-avg-kBps = <196078 150000>; 1378 }; 1379 opp-384000000 { 1380 opp-hz = /bits/ 64 <384000000>; 1381 required-opps = <&rpmpd_opp_nom>; 1382 opp-peak-kBps = <4096000 4096000>; 1383 opp-avg-kBps = <1338562 1338562>; 1384 }; 1385 }; 1386 }; 1387 1388 usb2: usb@c2f8800 { 1389 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1390 reg = <0x0c2f8800 0x400>; 1391 status = "disabled"; 1392 #address-cells = <1>; 1393 #size-cells = <1>; 1394 ranges; 1395 1396 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1397 <&gcc GCC_USB20_MASTER_CLK>, 1398 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1399 <&gcc GCC_USB20_SLEEP_CLK>; 1400 clock-names = "cfg_noc", "core", 1401 "mock_utmi", "sleep"; 1402 1403 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1404 <&gcc GCC_USB20_MASTER_CLK>; 1405 assigned-clock-rates = <19200000>, <60000000>; 1406 1407 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1408 interrupt-names = "hs_phy_irq"; 1409 1410 qcom,select-utmi-as-pipe-clk; 1411 1412 resets = <&gcc GCC_USB_20_BCR>; 1413 1414 usb2_dwc3: usb@c200000 { 1415 compatible = "snps,dwc3"; 1416 reg = <0x0c200000 0xc8d0>; 1417 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1418 snps,dis_u2_susphy_quirk; 1419 snps,dis_enblslpm_quirk; 1420 1421 /* This is the HS-only host */ 1422 maximum-speed = "high-speed"; 1423 phys = <&qusb2phy1>; 1424 phy-names = "usb2-phy"; 1425 snps,hird-threshold = /bits/ 8 <0>; 1426 }; 1427 }; 1428 1429 mmcc: clock-controller@c8c0000 { 1430 compatible = "qcom,mmcc-sdm630"; 1431 reg = <0x0c8c0000 0x40000>; 1432 #clock-cells = <1>; 1433 #reset-cells = <1>; 1434 #power-domain-cells = <1>; 1435 clock-names = "xo", 1436 "sleep_clk", 1437 "gpll0", 1438 "gpll0_div", 1439 "dsi0pll", 1440 "dsi0pllbyte", 1441 "dsi1pll", 1442 "dsi1pllbyte", 1443 "dp_link_2x_clk_divsel_five", 1444 "dp_vco_divided_clk_src_mux"; 1445 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1446 <&sleep_clk>, 1447 <&gcc GCC_MMSS_GPLL0_CLK>, 1448 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1449 <&dsi0_phy 1>, 1450 <&dsi0_phy 0>, 1451 <0>, 1452 <0>, 1453 <0>, 1454 <0>; 1455 }; 1456 1457 dsi_opp_table: opp-table-dsi { 1458 compatible = "operating-points-v2"; 1459 1460 opp-131250000 { 1461 opp-hz = /bits/ 64 <131250000>; 1462 required-opps = <&rpmpd_opp_svs>; 1463 }; 1464 1465 opp-210000000 { 1466 opp-hz = /bits/ 64 <210000000>; 1467 required-opps = <&rpmpd_opp_svs_plus>; 1468 }; 1469 1470 opp-262500000 { 1471 opp-hz = /bits/ 64 <262500000>; 1472 required-opps = <&rpmpd_opp_nom>; 1473 }; 1474 }; 1475 1476 mdss: mdss@c900000 { 1477 compatible = "qcom,mdss"; 1478 reg = <0x0c900000 0x1000>, 1479 <0x0c9b0000 0x1040>; 1480 reg-names = "mdss_phys", "vbif_phys"; 1481 1482 power-domains = <&mmcc MDSS_GDSC>; 1483 1484 clocks = <&mmcc MDSS_AHB_CLK>, 1485 <&mmcc MDSS_AXI_CLK>, 1486 <&mmcc MDSS_VSYNC_CLK>, 1487 <&mmcc MDSS_MDP_CLK>; 1488 clock-names = "iface", 1489 "bus", 1490 "vsync", 1491 "core"; 1492 1493 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1494 1495 interrupt-controller; 1496 #interrupt-cells = <1>; 1497 1498 #address-cells = <1>; 1499 #size-cells = <1>; 1500 ranges; 1501 status = "disabled"; 1502 1503 mdp: mdp@c901000 { 1504 compatible = "qcom,mdp5"; 1505 reg = <0x0c901000 0x89000>; 1506 reg-names = "mdp_phys"; 1507 1508 interrupt-parent = <&mdss>; 1509 interrupts = <0>; 1510 1511 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1512 <&mmcc MDSS_VSYNC_CLK>; 1513 assigned-clock-rates = <300000000>, 1514 <19200000>; 1515 clocks = <&mmcc MDSS_AHB_CLK>, 1516 <&mmcc MDSS_AXI_CLK>, 1517 <&mmcc MDSS_MDP_CLK>, 1518 <&mmcc MDSS_VSYNC_CLK>; 1519 clock-names = "iface", 1520 "bus", 1521 "core", 1522 "vsync"; 1523 1524 interconnects = <&mnoc 2 &bimc 5>, 1525 <&mnoc 3 &bimc 5>, 1526 <&gnoc 0 &mnoc 17>; 1527 interconnect-names = "mdp0-mem", 1528 "mdp1-mem", 1529 "rotator-mem"; 1530 iommus = <&mmss_smmu 0>; 1531 operating-points-v2 = <&mdp_opp_table>; 1532 power-domains = <&rpmpd SDM660_VDDCX>; 1533 1534 ports { 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 1538 port@0 { 1539 reg = <0>; 1540 mdp5_intf1_out: endpoint { 1541 remote-endpoint = <&dsi0_in>; 1542 }; 1543 }; 1544 }; 1545 1546 mdp_opp_table: opp-table { 1547 compatible = "operating-points-v2"; 1548 1549 opp-150000000 { 1550 opp-hz = /bits/ 64 <150000000>; 1551 opp-peak-kBps = <320000 320000 76800>; 1552 required-opps = <&rpmpd_opp_low_svs>; 1553 }; 1554 opp-275000000 { 1555 opp-hz = /bits/ 64 <275000000>; 1556 opp-peak-kBps = <6400000 6400000 160000>; 1557 required-opps = <&rpmpd_opp_svs>; 1558 }; 1559 opp-300000000 { 1560 opp-hz = /bits/ 64 <300000000>; 1561 opp-peak-kBps = <6400000 6400000 190000>; 1562 required-opps = <&rpmpd_opp_svs_plus>; 1563 }; 1564 opp-330000000 { 1565 opp-hz = /bits/ 64 <330000000>; 1566 opp-peak-kBps = <6400000 6400000 240000>; 1567 required-opps = <&rpmpd_opp_nom>; 1568 }; 1569 opp-412500000 { 1570 opp-hz = /bits/ 64 <412500000>; 1571 opp-peak-kBps = <6400000 6400000 320000>; 1572 required-opps = <&rpmpd_opp_turbo>; 1573 }; 1574 }; 1575 }; 1576 1577 dsi0: dsi@c994000 { 1578 compatible = "qcom,mdss-dsi-ctrl"; 1579 reg = <0x0c994000 0x400>; 1580 reg-names = "dsi_ctrl"; 1581 1582 operating-points-v2 = <&dsi_opp_table>; 1583 power-domains = <&rpmpd SDM660_VDDCX>; 1584 1585 interrupt-parent = <&mdss>; 1586 interrupts = <4>; 1587 1588 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1589 <&mmcc PCLK0_CLK_SRC>; 1590 assigned-clock-parents = <&dsi0_phy 0>, 1591 <&dsi0_phy 1>; 1592 1593 clocks = <&mmcc MDSS_MDP_CLK>, 1594 <&mmcc MDSS_BYTE0_CLK>, 1595 <&mmcc MDSS_BYTE0_INTF_CLK>, 1596 <&mmcc MNOC_AHB_CLK>, 1597 <&mmcc MDSS_AHB_CLK>, 1598 <&mmcc MDSS_AXI_CLK>, 1599 <&mmcc MISC_AHB_CLK>, 1600 <&mmcc MDSS_PCLK0_CLK>, 1601 <&mmcc MDSS_ESC0_CLK>; 1602 clock-names = "mdp_core", 1603 "byte", 1604 "byte_intf", 1605 "mnoc", 1606 "iface", 1607 "bus", 1608 "core_mmss", 1609 "pixel", 1610 "core"; 1611 1612 phys = <&dsi0_phy>; 1613 phy-names = "dsi"; 1614 1615 status = "disabled"; 1616 1617 ports { 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 1621 port@0 { 1622 reg = <0>; 1623 dsi0_in: endpoint { 1624 remote-endpoint = <&mdp5_intf1_out>; 1625 }; 1626 }; 1627 1628 port@1 { 1629 reg = <1>; 1630 dsi0_out: endpoint { 1631 }; 1632 }; 1633 }; 1634 }; 1635 1636 dsi0_phy: dsi-phy@c994400 { 1637 compatible = "qcom,dsi-phy-14nm-660"; 1638 reg = <0x0c994400 0x100>, 1639 <0x0c994500 0x300>, 1640 <0x0c994800 0x188>; 1641 reg-names = "dsi_phy", 1642 "dsi_phy_lane", 1643 "dsi_pll"; 1644 1645 #clock-cells = <1>; 1646 #phy-cells = <0>; 1647 1648 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1649 clock-names = "iface", "ref"; 1650 status = "disabled"; 1651 }; 1652 }; 1653 1654 blsp1_dma: dma-controller@c144000 { 1655 compatible = "qcom,bam-v1.7.0"; 1656 reg = <0x0c144000 0x1f000>; 1657 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1658 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1659 clock-names = "bam_clk"; 1660 #dma-cells = <1>; 1661 qcom,ee = <0>; 1662 qcom,controlled-remotely; 1663 num-channels = <18>; 1664 qcom,num-ees = <4>; 1665 }; 1666 1667 blsp1_uart1: serial@c16f000 { 1668 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1669 reg = <0x0c16f000 0x200>; 1670 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1671 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1672 <&gcc GCC_BLSP1_AHB_CLK>; 1673 clock-names = "core", "iface"; 1674 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1675 dma-names = "tx", "rx"; 1676 pinctrl-names = "default", "sleep"; 1677 pinctrl-0 = <&blsp1_uart1_default>; 1678 pinctrl-1 = <&blsp1_uart1_sleep>; 1679 status = "disabled"; 1680 }; 1681 1682 blsp1_uart2: serial@c170000 { 1683 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1684 reg = <0x0c170000 0x1000>; 1685 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1686 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1687 <&gcc GCC_BLSP1_AHB_CLK>; 1688 clock-names = "core", "iface"; 1689 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1690 dma-names = "tx", "rx"; 1691 pinctrl-names = "default"; 1692 pinctrl-0 = <&blsp1_uart2_default>; 1693 status = "disabled"; 1694 }; 1695 1696 blsp_i2c1: i2c@c175000 { 1697 compatible = "qcom,i2c-qup-v2.2.1"; 1698 reg = <0x0c175000 0x600>; 1699 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1700 1701 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1702 <&gcc GCC_BLSP1_AHB_CLK>; 1703 clock-names = "core", "iface"; 1704 clock-frequency = <400000>; 1705 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1706 dma-names = "tx", "rx"; 1707 1708 pinctrl-names = "default", "sleep"; 1709 pinctrl-0 = <&i2c1_default>; 1710 pinctrl-1 = <&i2c1_sleep>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 1716 blsp_i2c2: i2c@c176000 { 1717 compatible = "qcom,i2c-qup-v2.2.1"; 1718 reg = <0x0c176000 0x600>; 1719 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1720 1721 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1722 <&gcc GCC_BLSP1_AHB_CLK>; 1723 clock-names = "core", "iface"; 1724 clock-frequency = <400000>; 1725 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1726 dma-names = "tx", "rx"; 1727 1728 pinctrl-names = "default", "sleep"; 1729 pinctrl-0 = <&i2c2_default>; 1730 pinctrl-1 = <&i2c2_sleep>; 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 status = "disabled"; 1734 }; 1735 1736 blsp_i2c3: i2c@c177000 { 1737 compatible = "qcom,i2c-qup-v2.2.1"; 1738 reg = <0x0c177000 0x600>; 1739 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1740 1741 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1742 <&gcc GCC_BLSP1_AHB_CLK>; 1743 clock-names = "core", "iface"; 1744 clock-frequency = <400000>; 1745 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1746 dma-names = "tx", "rx"; 1747 1748 pinctrl-names = "default", "sleep"; 1749 pinctrl-0 = <&i2c3_default>; 1750 pinctrl-1 = <&i2c3_sleep>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 status = "disabled"; 1754 }; 1755 1756 blsp_i2c4: i2c@c178000 { 1757 compatible = "qcom,i2c-qup-v2.2.1"; 1758 reg = <0x0c178000 0x600>; 1759 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1760 1761 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1762 <&gcc GCC_BLSP1_AHB_CLK>; 1763 clock-names = "core", "iface"; 1764 clock-frequency = <400000>; 1765 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1766 dma-names = "tx", "rx"; 1767 1768 pinctrl-names = "default", "sleep"; 1769 pinctrl-0 = <&i2c4_default>; 1770 pinctrl-1 = <&i2c4_sleep>; 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 status = "disabled"; 1774 }; 1775 1776 blsp2_dma: dma-controller@c184000 { 1777 compatible = "qcom,bam-v1.7.0"; 1778 reg = <0x0c184000 0x1f000>; 1779 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1780 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1781 clock-names = "bam_clk"; 1782 #dma-cells = <1>; 1783 qcom,ee = <0>; 1784 qcom,controlled-remotely; 1785 num-channels = <18>; 1786 qcom,num-ees = <4>; 1787 }; 1788 1789 blsp2_uart1: serial@c1af000 { 1790 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1791 reg = <0x0c1af000 0x200>; 1792 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1793 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1794 <&gcc GCC_BLSP2_AHB_CLK>; 1795 clock-names = "core", "iface"; 1796 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1797 dma-names = "tx", "rx"; 1798 pinctrl-names = "default", "sleep"; 1799 pinctrl-0 = <&blsp2_uart1_default>; 1800 pinctrl-1 = <&blsp2_uart1_sleep>; 1801 status = "disabled"; 1802 }; 1803 1804 blsp_i2c5: i2c@c1b5000 { 1805 compatible = "qcom,i2c-qup-v2.2.1"; 1806 reg = <0x0c1b5000 0x600>; 1807 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1808 1809 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1810 <&gcc GCC_BLSP2_AHB_CLK>; 1811 clock-names = "core", "iface"; 1812 clock-frequency = <400000>; 1813 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1814 dma-names = "tx", "rx"; 1815 1816 pinctrl-names = "default", "sleep"; 1817 pinctrl-0 = <&i2c5_default>; 1818 pinctrl-1 = <&i2c5_sleep>; 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 status = "disabled"; 1822 }; 1823 1824 blsp_i2c6: i2c@c1b6000 { 1825 compatible = "qcom,i2c-qup-v2.2.1"; 1826 reg = <0x0c1b6000 0x600>; 1827 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1828 1829 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1830 <&gcc GCC_BLSP2_AHB_CLK>; 1831 clock-names = "core", "iface"; 1832 clock-frequency = <400000>; 1833 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1834 dma-names = "tx", "rx"; 1835 1836 pinctrl-names = "default", "sleep"; 1837 pinctrl-0 = <&i2c6_default>; 1838 pinctrl-1 = <&i2c6_sleep>; 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 status = "disabled"; 1842 }; 1843 1844 blsp_i2c7: i2c@c1b7000 { 1845 compatible = "qcom,i2c-qup-v2.2.1"; 1846 reg = <0x0c1b7000 0x600>; 1847 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1848 1849 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1850 <&gcc GCC_BLSP2_AHB_CLK>; 1851 clock-names = "core", "iface"; 1852 clock-frequency = <400000>; 1853 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1854 dma-names = "tx", "rx"; 1855 1856 pinctrl-names = "default", "sleep"; 1857 pinctrl-0 = <&i2c7_default>; 1858 pinctrl-1 = <&i2c7_sleep>; 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 status = "disabled"; 1862 }; 1863 1864 blsp_i2c8: i2c@c1b8000 { 1865 compatible = "qcom,i2c-qup-v2.2.1"; 1866 reg = <0x0c1b8000 0x600>; 1867 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1868 1869 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1870 <&gcc GCC_BLSP2_AHB_CLK>; 1871 clock-names = "core", "iface"; 1872 clock-frequency = <400000>; 1873 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1874 dma-names = "tx", "rx"; 1875 1876 pinctrl-names = "default", "sleep"; 1877 pinctrl-0 = <&i2c8_default>; 1878 pinctrl-1 = <&i2c8_sleep>; 1879 #address-cells = <1>; 1880 #size-cells = <0>; 1881 status = "disabled"; 1882 }; 1883 1884 sram@146bf000 { 1885 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1886 reg = <0x146bf000 0x1000>; 1887 1888 #address-cells = <1>; 1889 #size-cells = <1>; 1890 1891 ranges = <0 0x146bf000 0x1000>; 1892 1893 pil-reloc@94c { 1894 compatible = "qcom,pil-reloc-info"; 1895 reg = <0x94c 0xc8>; 1896 }; 1897 }; 1898 1899 camss: camss@ca00000 { 1900 compatible = "qcom,sdm660-camss"; 1901 reg = <0x0ca00020 0x10>, 1902 <0x0ca30000 0x100>, 1903 <0x0ca30400 0x100>, 1904 <0x0ca30800 0x100>, 1905 <0x0ca30c00 0x100>, 1906 <0x0c824000 0x1000>, 1907 <0x0ca00120 0x4>, 1908 <0x0c825000 0x1000>, 1909 <0x0ca00124 0x4>, 1910 <0x0c826000 0x1000>, 1911 <0x0ca00128 0x4>, 1912 <0x0ca31000 0x500>, 1913 <0x0ca10000 0x1000>, 1914 <0x0ca14000 0x1000>; 1915 reg-names = "csi_clk_mux", 1916 "csid0", 1917 "csid1", 1918 "csid2", 1919 "csid3", 1920 "csiphy0", 1921 "csiphy0_clk_mux", 1922 "csiphy1", 1923 "csiphy1_clk_mux", 1924 "csiphy2", 1925 "csiphy2_clk_mux", 1926 "ispif", 1927 "vfe0", 1928 "vfe1"; 1929 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1930 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1931 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1932 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1933 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1934 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1935 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1936 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1937 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1938 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1939 interrupt-names = "csid0", 1940 "csid1", 1941 "csid2", 1942 "csid3", 1943 "csiphy0", 1944 "csiphy1", 1945 "csiphy2", 1946 "ispif", 1947 "vfe0", 1948 "vfe1"; 1949 clocks = <&mmcc CAMSS_AHB_CLK>, 1950 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1951 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1952 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1953 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1954 <&mmcc CAMSS_CSI0_AHB_CLK>, 1955 <&mmcc CAMSS_CSI0_CLK>, 1956 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1957 <&mmcc CAMSS_CSI0PIX_CLK>, 1958 <&mmcc CAMSS_CSI0RDI_CLK>, 1959 <&mmcc CAMSS_CSI1_AHB_CLK>, 1960 <&mmcc CAMSS_CSI1_CLK>, 1961 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1962 <&mmcc CAMSS_CSI1PIX_CLK>, 1963 <&mmcc CAMSS_CSI1RDI_CLK>, 1964 <&mmcc CAMSS_CSI2_AHB_CLK>, 1965 <&mmcc CAMSS_CSI2_CLK>, 1966 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1967 <&mmcc CAMSS_CSI2PIX_CLK>, 1968 <&mmcc CAMSS_CSI2RDI_CLK>, 1969 <&mmcc CAMSS_CSI3_AHB_CLK>, 1970 <&mmcc CAMSS_CSI3_CLK>, 1971 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1972 <&mmcc CAMSS_CSI3PIX_CLK>, 1973 <&mmcc CAMSS_CSI3RDI_CLK>, 1974 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1975 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1976 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1977 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1978 <&mmcc CAMSS_CSI_VFE0_CLK>, 1979 <&mmcc CAMSS_CSI_VFE1_CLK>, 1980 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1981 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1982 <&mmcc CAMSS_TOP_AHB_CLK>, 1983 <&mmcc CAMSS_VFE0_AHB_CLK>, 1984 <&mmcc CAMSS_VFE0_CLK>, 1985 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1986 <&mmcc CAMSS_VFE1_AHB_CLK>, 1987 <&mmcc CAMSS_VFE1_CLK>, 1988 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1989 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1990 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 1991 clock-names = "ahb", 1992 "cphy_csid0", 1993 "cphy_csid1", 1994 "cphy_csid2", 1995 "cphy_csid3", 1996 "csi0_ahb", 1997 "csi0", 1998 "csi0_phy", 1999 "csi0_pix", 2000 "csi0_rdi", 2001 "csi1_ahb", 2002 "csi1", 2003 "csi1_phy", 2004 "csi1_pix", 2005 "csi1_rdi", 2006 "csi2_ahb", 2007 "csi2", 2008 "csi2_phy", 2009 "csi2_pix", 2010 "csi2_rdi", 2011 "csi3_ahb", 2012 "csi3", 2013 "csi3_phy", 2014 "csi3_pix", 2015 "csi3_rdi", 2016 "csiphy0_timer", 2017 "csiphy1_timer", 2018 "csiphy2_timer", 2019 "csiphy_ahb2crif", 2020 "csi_vfe0", 2021 "csi_vfe1", 2022 "ispif_ahb", 2023 "throttle_axi", 2024 "top_ahb", 2025 "vfe0_ahb", 2026 "vfe0", 2027 "vfe0_stream", 2028 "vfe1_ahb", 2029 "vfe1", 2030 "vfe1_stream", 2031 "vfe_ahb", 2032 "vfe_axi"; 2033 interconnects = <&mnoc 5 &bimc 5>; 2034 interconnect-names = "vfe-mem"; 2035 iommus = <&mmss_smmu 0xc00>, 2036 <&mmss_smmu 0xc01>, 2037 <&mmss_smmu 0xc02>, 2038 <&mmss_smmu 0xc03>; 2039 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2040 <&mmcc CAMSS_VFE1_GDSC>; 2041 status = "disabled"; 2042 2043 ports { 2044 #address-cells = <1>; 2045 #size-cells = <0>; 2046 }; 2047 }; 2048 2049 cci: cci@ca0c000 { 2050 compatible = "qcom,msm8996-cci"; 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 reg = <0x0ca0c000 0x1000>; 2054 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2055 2056 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2057 <&mmcc CAMSS_CCI_CLK>; 2058 assigned-clock-rates = <80800000>, <37500000>; 2059 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2060 <&mmcc CAMSS_CCI_AHB_CLK>, 2061 <&mmcc CAMSS_CCI_CLK>, 2062 <&mmcc CAMSS_AHB_CLK>; 2063 clock-names = "camss_top_ahb", 2064 "cci_ahb", 2065 "cci", 2066 "camss_ahb"; 2067 2068 pinctrl-names = "default"; 2069 pinctrl-0 = <&cci0_default &cci1_default>; 2070 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2071 status = "disabled"; 2072 2073 cci_i2c0: i2c-bus@0 { 2074 reg = <0>; 2075 clock-frequency = <400000>; 2076 #address-cells = <1>; 2077 #size-cells = <0>; 2078 }; 2079 2080 cci_i2c1: i2c-bus@1 { 2081 reg = <1>; 2082 clock-frequency = <400000>; 2083 #address-cells = <1>; 2084 #size-cells = <0>; 2085 }; 2086 }; 2087 2088 venus: video-codec@cc00000 { 2089 compatible = "qcom,sdm660-venus"; 2090 reg = <0x0cc00000 0xff000>; 2091 clocks = <&mmcc VIDEO_CORE_CLK>, 2092 <&mmcc VIDEO_AHB_CLK>, 2093 <&mmcc VIDEO_AXI_CLK>, 2094 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2095 clock-names = "core", "iface", "bus", "bus_throttle"; 2096 interconnects = <&gnoc 0 &mnoc 13>, 2097 <&mnoc 4 &bimc 5>; 2098 interconnect-names = "cpu-cfg", "video-mem"; 2099 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2100 iommus = <&mmss_smmu 0x400>, 2101 <&mmss_smmu 0x401>, 2102 <&mmss_smmu 0x40a>, 2103 <&mmss_smmu 0x407>, 2104 <&mmss_smmu 0x40e>, 2105 <&mmss_smmu 0x40f>, 2106 <&mmss_smmu 0x408>, 2107 <&mmss_smmu 0x409>, 2108 <&mmss_smmu 0x40b>, 2109 <&mmss_smmu 0x40c>, 2110 <&mmss_smmu 0x40d>, 2111 <&mmss_smmu 0x410>, 2112 <&mmss_smmu 0x421>, 2113 <&mmss_smmu 0x428>, 2114 <&mmss_smmu 0x429>, 2115 <&mmss_smmu 0x42b>, 2116 <&mmss_smmu 0x42c>, 2117 <&mmss_smmu 0x42d>, 2118 <&mmss_smmu 0x411>, 2119 <&mmss_smmu 0x431>; 2120 memory-region = <&venus_region>; 2121 power-domains = <&mmcc VENUS_GDSC>; 2122 status = "disabled"; 2123 2124 video-decoder { 2125 compatible = "venus-decoder"; 2126 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2127 clock-names = "vcodec0_core"; 2128 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2129 }; 2130 2131 video-encoder { 2132 compatible = "venus-encoder"; 2133 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2134 clock-names = "vcodec0_core"; 2135 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2136 }; 2137 }; 2138 2139 mmss_smmu: iommu@cd00000 { 2140 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2141 reg = <0x0cd00000 0x40000>; 2142 2143 clocks = <&mmcc MNOC_AHB_CLK>, 2144 <&mmcc BIMC_SMMU_AHB_CLK>, 2145 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2146 <&mmcc BIMC_SMMU_AXI_CLK>; 2147 clock-names = "iface-mm", "iface-smmu", 2148 "bus-mm", "bus-smmu"; 2149 #global-interrupts = <2>; 2150 #iommu-cells = <1>; 2151 2152 interrupts = 2153 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2155 2156 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2180 2181 status = "disabled"; 2182 }; 2183 2184 adsp_pil: remoteproc@15700000 { 2185 compatible = "qcom,sdm660-adsp-pas"; 2186 reg = <0x15700000 0x4040>; 2187 2188 interrupts-extended = 2189 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2190 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2191 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2192 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2193 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2194 interrupt-names = "wdog", "fatal", "ready", 2195 "handover", "stop-ack"; 2196 2197 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2198 clock-names = "xo"; 2199 2200 memory-region = <&adsp_region>; 2201 power-domains = <&rpmpd SDM660_VDDCX>; 2202 power-domain-names = "cx"; 2203 2204 qcom,smem-states = <&adsp_smp2p_out 0>; 2205 qcom,smem-state-names = "stop"; 2206 2207 glink-edge { 2208 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2209 2210 label = "lpass"; 2211 mboxes = <&apcs_glb 9>; 2212 qcom,remote-pid = <2>; 2213 2214 apr { 2215 compatible = "qcom,apr-v2"; 2216 qcom,glink-channels = "apr_audio_svc"; 2217 qcom,domain = <APR_DOMAIN_ADSP>; 2218 #address-cells = <1>; 2219 #size-cells = <0>; 2220 2221 q6core { 2222 reg = <APR_SVC_ADSP_CORE>; 2223 compatible = "qcom,q6core"; 2224 }; 2225 2226 q6afe: apr-service@4 { 2227 compatible = "qcom,q6afe"; 2228 reg = <APR_SVC_AFE>; 2229 q6afedai: dais { 2230 compatible = "qcom,q6afe-dais"; 2231 #address-cells = <1>; 2232 #size-cells = <0>; 2233 #sound-dai-cells = <1>; 2234 }; 2235 }; 2236 2237 q6asm: apr-service@7 { 2238 compatible = "qcom,q6asm"; 2239 reg = <APR_SVC_ASM>; 2240 q6asmdai: dais { 2241 compatible = "qcom,q6asm-dais"; 2242 #address-cells = <1>; 2243 #size-cells = <0>; 2244 #sound-dai-cells = <1>; 2245 iommus = <&lpass_smmu 1>; 2246 }; 2247 }; 2248 2249 q6adm: apr-service@8 { 2250 compatible = "qcom,q6adm"; 2251 reg = <APR_SVC_ADM>; 2252 q6routing: routing { 2253 compatible = "qcom,q6adm-routing"; 2254 #sound-dai-cells = <0>; 2255 }; 2256 }; 2257 }; 2258 }; 2259 }; 2260 2261 gnoc: interconnect@17900000 { 2262 compatible = "qcom,sdm660-gnoc"; 2263 reg = <0x17900000 0xe000>; 2264 #interconnect-cells = <1>; 2265 /* 2266 * This one apparently features no clocks, 2267 * so let's not mess with the driver needlessly 2268 */ 2269 clock-names = "bus", "bus_a"; 2270 clocks = <&xo_board>, <&xo_board>; 2271 }; 2272 2273 apcs_glb: mailbox@17911000 { 2274 compatible = "qcom,sdm660-apcs-hmss-global"; 2275 reg = <0x17911000 0x1000>; 2276 2277 #mbox-cells = <1>; 2278 }; 2279 2280 timer@17920000 { 2281 #address-cells = <1>; 2282 #size-cells = <1>; 2283 ranges; 2284 compatible = "arm,armv7-timer-mem"; 2285 reg = <0x17920000 0x1000>; 2286 clock-frequency = <19200000>; 2287 2288 frame@17921000 { 2289 frame-number = <0>; 2290 interrupts = <0 8 0x4>, 2291 <0 7 0x4>; 2292 reg = <0x17921000 0x1000>, 2293 <0x17922000 0x1000>; 2294 }; 2295 2296 frame@17923000 { 2297 frame-number = <1>; 2298 interrupts = <0 9 0x4>; 2299 reg = <0x17923000 0x1000>; 2300 status = "disabled"; 2301 }; 2302 2303 frame@17924000 { 2304 frame-number = <2>; 2305 interrupts = <0 10 0x4>; 2306 reg = <0x17924000 0x1000>; 2307 status = "disabled"; 2308 }; 2309 2310 frame@17925000 { 2311 frame-number = <3>; 2312 interrupts = <0 11 0x4>; 2313 reg = <0x17925000 0x1000>; 2314 status = "disabled"; 2315 }; 2316 2317 frame@17926000 { 2318 frame-number = <4>; 2319 interrupts = <0 12 0x4>; 2320 reg = <0x17926000 0x1000>; 2321 status = "disabled"; 2322 }; 2323 2324 frame@17927000 { 2325 frame-number = <5>; 2326 interrupts = <0 13 0x4>; 2327 reg = <0x17927000 0x1000>; 2328 status = "disabled"; 2329 }; 2330 2331 frame@17928000 { 2332 frame-number = <6>; 2333 interrupts = <0 14 0x4>; 2334 reg = <0x17928000 0x1000>; 2335 status = "disabled"; 2336 }; 2337 }; 2338 2339 intc: interrupt-controller@17a00000 { 2340 compatible = "arm,gic-v3"; 2341 reg = <0x17a00000 0x10000>, /* GICD */ 2342 <0x17b00000 0x100000>; /* GICR * 8 */ 2343 #interrupt-cells = <3>; 2344 #address-cells = <1>; 2345 #size-cells = <1>; 2346 ranges; 2347 interrupt-controller; 2348 #redistributor-regions = <1>; 2349 redistributor-stride = <0x0 0x20000>; 2350 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2351 }; 2352 }; 2353 2354 tcsr_mutex: hwlock { 2355 compatible = "qcom,tcsr-mutex"; 2356 syscon = <&tcsr_mutex_regs 0 0x1000>; 2357 #hwlock-cells = <1>; 2358 }; 2359 2360 sound: sound { 2361 }; 2362 2363 thermal-zones { 2364 aoss-thermal { 2365 polling-delay-passive = <250>; 2366 polling-delay = <1000>; 2367 2368 thermal-sensors = <&tsens 0>; 2369 2370 trips { 2371 aoss_alert0: trip-point0 { 2372 temperature = <105000>; 2373 hysteresis = <1000>; 2374 type = "hot"; 2375 }; 2376 }; 2377 }; 2378 2379 cpuss0-thermal { 2380 polling-delay-passive = <250>; 2381 polling-delay = <1000>; 2382 2383 thermal-sensors = <&tsens 1>; 2384 2385 trips { 2386 cpuss0_alert0: trip-point0 { 2387 temperature = <125000>; 2388 hysteresis = <1000>; 2389 type = "hot"; 2390 }; 2391 }; 2392 }; 2393 2394 cpuss1-thermal { 2395 polling-delay-passive = <250>; 2396 polling-delay = <1000>; 2397 2398 thermal-sensors = <&tsens 2>; 2399 2400 trips { 2401 cpuss1_alert0: trip-point0 { 2402 temperature = <125000>; 2403 hysteresis = <1000>; 2404 type = "hot"; 2405 }; 2406 }; 2407 }; 2408 2409 cpu0-thermal { 2410 polling-delay-passive = <250>; 2411 polling-delay = <1000>; 2412 2413 thermal-sensors = <&tsens 3>; 2414 2415 trips { 2416 cpu0_alert0: trip-point0 { 2417 temperature = <70000>; 2418 hysteresis = <1000>; 2419 type = "passive"; 2420 }; 2421 2422 cpu0_crit: cpu_crit { 2423 temperature = <110000>; 2424 hysteresis = <1000>; 2425 type = "critical"; 2426 }; 2427 }; 2428 }; 2429 2430 cpu1-thermal { 2431 polling-delay-passive = <250>; 2432 polling-delay = <1000>; 2433 2434 thermal-sensors = <&tsens 4>; 2435 2436 trips { 2437 cpu1_alert0: trip-point0 { 2438 temperature = <70000>; 2439 hysteresis = <1000>; 2440 type = "passive"; 2441 }; 2442 2443 cpu1_crit: cpu_crit { 2444 temperature = <110000>; 2445 hysteresis = <1000>; 2446 type = "critical"; 2447 }; 2448 }; 2449 }; 2450 2451 cpu2-thermal { 2452 polling-delay-passive = <250>; 2453 polling-delay = <1000>; 2454 2455 thermal-sensors = <&tsens 5>; 2456 2457 trips { 2458 cpu2_alert0: trip-point0 { 2459 temperature = <70000>; 2460 hysteresis = <1000>; 2461 type = "passive"; 2462 }; 2463 2464 cpu2_crit: cpu_crit { 2465 temperature = <110000>; 2466 hysteresis = <1000>; 2467 type = "critical"; 2468 }; 2469 }; 2470 }; 2471 2472 cpu3-thermal { 2473 polling-delay-passive = <250>; 2474 polling-delay = <1000>; 2475 2476 thermal-sensors = <&tsens 6>; 2477 2478 trips { 2479 cpu3_alert0: trip-point0 { 2480 temperature = <70000>; 2481 hysteresis = <1000>; 2482 type = "passive"; 2483 }; 2484 2485 cpu3_crit: cpu_crit { 2486 temperature = <110000>; 2487 hysteresis = <1000>; 2488 type = "critical"; 2489 }; 2490 }; 2491 }; 2492 2493 /* 2494 * According to what downstream DTS says, 2495 * the entire power efficient cluster has 2496 * only a single thermal sensor. 2497 */ 2498 2499 pwr-cluster-thermal { 2500 polling-delay-passive = <250>; 2501 polling-delay = <1000>; 2502 2503 thermal-sensors = <&tsens 7>; 2504 2505 trips { 2506 pwr_cluster_alert0: trip-point0 { 2507 temperature = <70000>; 2508 hysteresis = <1000>; 2509 type = "passive"; 2510 }; 2511 2512 pwr_cluster_crit: cpu_crit { 2513 temperature = <110000>; 2514 hysteresis = <1000>; 2515 type = "critical"; 2516 }; 2517 }; 2518 }; 2519 2520 gpu-thermal { 2521 polling-delay-passive = <250>; 2522 polling-delay = <1000>; 2523 2524 thermal-sensors = <&tsens 8>; 2525 2526 trips { 2527 gpu_alert0: trip-point0 { 2528 temperature = <90000>; 2529 hysteresis = <1000>; 2530 type = "hot"; 2531 }; 2532 }; 2533 }; 2534 }; 2535 2536 timer { 2537 compatible = "arm,armv8-timer"; 2538 interrupts = <GIC_PPI 1 0xf08>, 2539 <GIC_PPI 2 0xf08>, 2540 <GIC_PPI 3 0xf08>, 2541 <GIC_PPI 0 0xf08>; 2542 }; 2543}; 2544 2545