1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,osm-l3.h> 11#include <dt-bindings/interconnect/qcom,sc8280xp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/phy/phy-qcom-qmp.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6afe.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 clocks { 28 xo_board_clk: xo-board-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32764>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a78c"; 47 reg = <0x0 0x0>; 48 clocks = <&cpufreq_hw 0>; 49 enable-method = "psci"; 50 capacity-dmips-mhz = <602>; 51 next-level-cache = <&L2_0>; 52 power-domains = <&CPU_PD0>; 53 power-domain-names = "psci"; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 operating-points-v2 = <&cpu0_opp_table>; 56 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 57 #cooling-cells = <2>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 next-level-cache = <&L3_0>; 63 L3_0: l3-cache { 64 compatible = "cache"; 65 cache-level = <3>; 66 cache-unified; 67 }; 68 }; 69 }; 70 71 CPU1: cpu@100 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a78c"; 74 reg = <0x0 0x100>; 75 clocks = <&cpufreq_hw 0>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <602>; 78 next-level-cache = <&L2_100>; 79 power-domains = <&CPU_PD1>; 80 power-domain-names = "psci"; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 operating-points-v2 = <&cpu0_opp_table>; 83 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 84 #cooling-cells = <2>; 85 L2_100: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 next-level-cache = <&L3_0>; 90 }; 91 }; 92 93 CPU2: cpu@200 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a78c"; 96 reg = <0x0 0x200>; 97 clocks = <&cpufreq_hw 0>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <602>; 100 next-level-cache = <&L2_200>; 101 power-domains = <&CPU_PD2>; 102 power-domain-names = "psci"; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 operating-points-v2 = <&cpu0_opp_table>; 105 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a78c"; 118 reg = <0x0 0x300>; 119 clocks = <&cpufreq_hw 0>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <602>; 122 next-level-cache = <&L2_300>; 123 power-domains = <&CPU_PD3>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 operating-points-v2 = <&cpu0_opp_table>; 127 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 128 #cooling-cells = <2>; 129 L2_300: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&L3_0>; 134 }; 135 }; 136 137 CPU4: cpu@400 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-x1c"; 140 reg = <0x0 0x400>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 next-level-cache = <&L2_400>; 145 power-domains = <&CPU_PD4>; 146 power-domain-names = "psci"; 147 qcom,freq-domain = <&cpufreq_hw 1>; 148 operating-points-v2 = <&cpu4_opp_table>; 149 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 150 #cooling-cells = <2>; 151 L2_400: l2-cache { 152 compatible = "cache"; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU5: cpu@500 { 160 device_type = "cpu"; 161 compatible = "arm,cortex-x1c"; 162 reg = <0x0 0x500>; 163 clocks = <&cpufreq_hw 1>; 164 enable-method = "psci"; 165 capacity-dmips-mhz = <1024>; 166 next-level-cache = <&L2_500>; 167 power-domains = <&CPU_PD5>; 168 power-domain-names = "psci"; 169 qcom,freq-domain = <&cpufreq_hw 1>; 170 operating-points-v2 = <&cpu4_opp_table>; 171 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 172 #cooling-cells = <2>; 173 L2_500: l2-cache { 174 compatible = "cache"; 175 cache-level = <2>; 176 cache-unified; 177 next-level-cache = <&L3_0>; 178 }; 179 }; 180 181 CPU6: cpu@600 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-x1c"; 184 reg = <0x0 0x600>; 185 clocks = <&cpufreq_hw 1>; 186 enable-method = "psci"; 187 capacity-dmips-mhz = <1024>; 188 next-level-cache = <&L2_600>; 189 power-domains = <&CPU_PD6>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 operating-points-v2 = <&cpu4_opp_table>; 193 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 194 #cooling-cells = <2>; 195 L2_600: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 cache-unified; 199 next-level-cache = <&L3_0>; 200 }; 201 }; 202 203 CPU7: cpu@700 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-x1c"; 206 reg = <0x0 0x700>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1024>; 210 next-level-cache = <&L2_700>; 211 power-domains = <&CPU_PD7>; 212 power-domain-names = "psci"; 213 qcom,freq-domain = <&cpufreq_hw 1>; 214 operating-points-v2 = <&cpu4_opp_table>; 215 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 216 #cooling-cells = <2>; 217 L2_700: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&CPU0>; 229 }; 230 231 core1 { 232 cpu = <&CPU1>; 233 }; 234 235 core2 { 236 cpu = <&CPU2>; 237 }; 238 239 core3 { 240 cpu = <&CPU3>; 241 }; 242 243 core4 { 244 cpu = <&CPU4>; 245 }; 246 247 core5 { 248 cpu = <&CPU5>; 249 }; 250 251 core6 { 252 cpu = <&CPU6>; 253 }; 254 255 core7 { 256 cpu = <&CPU7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "little-rail-power-collapse"; 267 arm,psci-suspend-param = <0x40000004>; 268 entry-latency-us = <355>; 269 exit-latency-us = <909>; 270 min-residency-us = <3934>; 271 local-timer-stop; 272 }; 273 274 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "big-rail-power-collapse"; 277 arm,psci-suspend-param = <0x40000004>; 278 entry-latency-us = <241>; 279 exit-latency-us = <1461>; 280 min-residency-us = <4488>; 281 local-timer-stop; 282 }; 283 }; 284 285 domain-idle-states { 286 CLUSTER_SLEEP_0: cluster-sleep-0 { 287 compatible = "domain-idle-state"; 288 arm,psci-suspend-param = <0x4100c344>; 289 entry-latency-us = <3263>; 290 exit-latency-us = <6562>; 291 min-residency-us = <9987>; 292 }; 293 }; 294 }; 295 296 firmware { 297 scm: scm { 298 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 299 }; 300 }; 301 302 aggre1_noc: interconnect-aggre1-noc { 303 compatible = "qcom,sc8280xp-aggre1-noc"; 304 #interconnect-cells = <2>; 305 qcom,bcm-voters = <&apps_bcm_voter>; 306 }; 307 308 aggre2_noc: interconnect-aggre2-noc { 309 compatible = "qcom,sc8280xp-aggre2-noc"; 310 #interconnect-cells = <2>; 311 qcom,bcm-voters = <&apps_bcm_voter>; 312 }; 313 314 clk_virt: interconnect-clk-virt { 315 compatible = "qcom,sc8280xp-clk-virt"; 316 #interconnect-cells = <2>; 317 qcom,bcm-voters = <&apps_bcm_voter>; 318 }; 319 320 config_noc: interconnect-config-noc { 321 compatible = "qcom,sc8280xp-config-noc"; 322 #interconnect-cells = <2>; 323 qcom,bcm-voters = <&apps_bcm_voter>; 324 }; 325 326 dc_noc: interconnect-dc-noc { 327 compatible = "qcom,sc8280xp-dc-noc"; 328 #interconnect-cells = <2>; 329 qcom,bcm-voters = <&apps_bcm_voter>; 330 }; 331 332 gem_noc: interconnect-gem-noc { 333 compatible = "qcom,sc8280xp-gem-noc"; 334 #interconnect-cells = <2>; 335 qcom,bcm-voters = <&apps_bcm_voter>; 336 }; 337 338 lpass_noc: interconnect-lpass-ag-noc { 339 compatible = "qcom,sc8280xp-lpass-ag-noc"; 340 #interconnect-cells = <2>; 341 qcom,bcm-voters = <&apps_bcm_voter>; 342 }; 343 344 mc_virt: interconnect-mc-virt { 345 compatible = "qcom,sc8280xp-mc-virt"; 346 #interconnect-cells = <2>; 347 qcom,bcm-voters = <&apps_bcm_voter>; 348 }; 349 350 mmss_noc: interconnect-mmss-noc { 351 compatible = "qcom,sc8280xp-mmss-noc"; 352 #interconnect-cells = <2>; 353 qcom,bcm-voters = <&apps_bcm_voter>; 354 }; 355 356 nspa_noc: interconnect-nspa-noc { 357 compatible = "qcom,sc8280xp-nspa-noc"; 358 #interconnect-cells = <2>; 359 qcom,bcm-voters = <&apps_bcm_voter>; 360 }; 361 362 nspb_noc: interconnect-nspb-noc { 363 compatible = "qcom,sc8280xp-nspb-noc"; 364 #interconnect-cells = <2>; 365 qcom,bcm-voters = <&apps_bcm_voter>; 366 }; 367 368 system_noc: interconnect-system-noc { 369 compatible = "qcom,sc8280xp-system-noc"; 370 #interconnect-cells = <2>; 371 qcom,bcm-voters = <&apps_bcm_voter>; 372 }; 373 374 memory@80000000 { 375 device_type = "memory"; 376 /* We expect the bootloader to fill in the size */ 377 reg = <0x0 0x80000000 0x0 0x0>; 378 }; 379 380 cpu0_opp_table: opp-table-cpu0 { 381 compatible = "operating-points-v2"; 382 opp-shared; 383 384 opp-300000000 { 385 opp-hz = /bits/ 64 <300000000>; 386 opp-peak-kBps = <(300000 * 32)>; 387 }; 388 opp-403200000 { 389 opp-hz = /bits/ 64 <403200000>; 390 opp-peak-kBps = <(384000 * 32)>; 391 }; 392 opp-499200000 { 393 opp-hz = /bits/ 64 <499200000>; 394 opp-peak-kBps = <(480000 * 32)>; 395 }; 396 opp-595200000 { 397 opp-hz = /bits/ 64 <595200000>; 398 opp-peak-kBps = <(576000 * 32)>; 399 }; 400 opp-691200000 { 401 opp-hz = /bits/ 64 <691200000>; 402 opp-peak-kBps = <(672000 * 32)>; 403 }; 404 opp-806400000 { 405 opp-hz = /bits/ 64 <806400000>; 406 opp-peak-kBps = <(768000 * 32)>; 407 }; 408 opp-902400000 { 409 opp-hz = /bits/ 64 <902400000>; 410 opp-peak-kBps = <(864000 * 32)>; 411 }; 412 opp-1017600000 { 413 opp-hz = /bits/ 64 <1017600000>; 414 opp-peak-kBps = <(960000 * 32)>; 415 }; 416 opp-1113600000 { 417 opp-hz = /bits/ 64 <1113600000>; 418 opp-peak-kBps = <(1075200 * 32)>; 419 }; 420 opp-1209600000 { 421 opp-hz = /bits/ 64 <1209600000>; 422 opp-peak-kBps = <(1171200 * 32)>; 423 }; 424 opp-1324800000 { 425 opp-hz = /bits/ 64 <1324800000>; 426 opp-peak-kBps = <(1267200 * 32)>; 427 }; 428 opp-1440000000 { 429 opp-hz = /bits/ 64 <1440000000>; 430 opp-peak-kBps = <(1363200 * 32)>; 431 }; 432 opp-1555200000 { 433 opp-hz = /bits/ 64 <1555200000>; 434 opp-peak-kBps = <(1536000 * 32)>; 435 }; 436 opp-1670400000 { 437 opp-hz = /bits/ 64 <1670400000>; 438 opp-peak-kBps = <(1612800 * 32)>; 439 }; 440 opp-1785600000 { 441 opp-hz = /bits/ 64 <1785600000>; 442 opp-peak-kBps = <(1689600 * 32)>; 443 }; 444 opp-1881600000 { 445 opp-hz = /bits/ 64 <1881600000>; 446 opp-peak-kBps = <(1689600 * 32)>; 447 }; 448 opp-1996800000 { 449 opp-hz = /bits/ 64 <1996800000>; 450 opp-peak-kBps = <(1689600 * 32)>; 451 }; 452 opp-2112000000 { 453 opp-hz = /bits/ 64 <2112000000>; 454 opp-peak-kBps = <(1689600 * 32)>; 455 }; 456 opp-2227200000 { 457 opp-hz = /bits/ 64 <2227200000>; 458 opp-peak-kBps = <(1689600 * 32)>; 459 }; 460 opp-2342400000 { 461 opp-hz = /bits/ 64 <2342400000>; 462 opp-peak-kBps = <(1689600 * 32)>; 463 }; 464 opp-2438400000 { 465 opp-hz = /bits/ 64 <2438400000>; 466 opp-peak-kBps = <(1689600 * 32)>; 467 }; 468 }; 469 470 cpu4_opp_table: opp-table-cpu4 { 471 compatible = "operating-points-v2"; 472 opp-shared; 473 474 opp-825600000 { 475 opp-hz = /bits/ 64 <825600000>; 476 opp-peak-kBps = <(768000 * 32)>; 477 }; 478 opp-940800000 { 479 opp-hz = /bits/ 64 <940800000>; 480 opp-peak-kBps = <(864000 * 32)>; 481 }; 482 opp-1056000000 { 483 opp-hz = /bits/ 64 <1056000000>; 484 opp-peak-kBps = <(960000 * 32)>; 485 }; 486 opp-1171200000 { 487 opp-hz = /bits/ 64 <1171200000>; 488 opp-peak-kBps = <(1171200 * 32)>; 489 }; 490 opp-1286400000 { 491 opp-hz = /bits/ 64 <1286400000>; 492 opp-peak-kBps = <(1267200 * 32)>; 493 }; 494 opp-1401600000 { 495 opp-hz = /bits/ 64 <1401600000>; 496 opp-peak-kBps = <(1363200 * 32)>; 497 }; 498 opp-1516800000 { 499 opp-hz = /bits/ 64 <1516800000>; 500 opp-peak-kBps = <(1459200 * 32)>; 501 }; 502 opp-1632000000 { 503 opp-hz = /bits/ 64 <1632000000>; 504 opp-peak-kBps = <(1612800 * 32)>; 505 }; 506 opp-1747200000 { 507 opp-hz = /bits/ 64 <1747200000>; 508 opp-peak-kBps = <(1689600 * 32)>; 509 }; 510 opp-1862400000 { 511 opp-hz = /bits/ 64 <1862400000>; 512 opp-peak-kBps = <(1689600 * 32)>; 513 }; 514 opp-1977600000 { 515 opp-hz = /bits/ 64 <1977600000>; 516 opp-peak-kBps = <(1689600 * 32)>; 517 }; 518 opp-2073600000 { 519 opp-hz = /bits/ 64 <2073600000>; 520 opp-peak-kBps = <(1689600 * 32)>; 521 }; 522 opp-2169600000 { 523 opp-hz = /bits/ 64 <2169600000>; 524 opp-peak-kBps = <(1689600 * 32)>; 525 }; 526 opp-2284800000 { 527 opp-hz = /bits/ 64 <2284800000>; 528 opp-peak-kBps = <(1689600 * 32)>; 529 }; 530 opp-2400000000 { 531 opp-hz = /bits/ 64 <2400000000>; 532 opp-peak-kBps = <(1689600 * 32)>; 533 }; 534 opp-2496000000 { 535 opp-hz = /bits/ 64 <2496000000>; 536 opp-peak-kBps = <(1689600 * 32)>; 537 }; 538 opp-2592000000 { 539 opp-hz = /bits/ 64 <2592000000>; 540 opp-peak-kBps = <(1689600 * 32)>; 541 }; 542 opp-2688000000 { 543 opp-hz = /bits/ 64 <2688000000>; 544 opp-peak-kBps = <(1689600 * 32)>; 545 }; 546 opp-2803200000 { 547 opp-hz = /bits/ 64 <2803200000>; 548 opp-peak-kBps = <(1689600 * 32)>; 549 }; 550 opp-2899200000 { 551 opp-hz = /bits/ 64 <2899200000>; 552 opp-peak-kBps = <(1689600 * 32)>; 553 }; 554 opp-2995200000 { 555 opp-hz = /bits/ 64 <2995200000>; 556 opp-peak-kBps = <(1689600 * 32)>; 557 }; 558 }; 559 560 qup_opp_table_100mhz: opp-table-qup100mhz { 561 compatible = "operating-points-v2"; 562 563 opp-75000000 { 564 opp-hz = /bits/ 64 <75000000>; 565 required-opps = <&rpmhpd_opp_low_svs>; 566 }; 567 568 opp-100000000 { 569 opp-hz = /bits/ 64 <100000000>; 570 required-opps = <&rpmhpd_opp_svs>; 571 }; 572 }; 573 574 pmu { 575 compatible = "arm,armv8-pmuv3"; 576 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 577 }; 578 579 psci { 580 compatible = "arm,psci-1.0"; 581 method = "smc"; 582 583 CPU_PD0: power-domain-cpu0 { 584 #power-domain-cells = <0>; 585 power-domains = <&CLUSTER_PD>; 586 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 587 }; 588 589 CPU_PD1: power-domain-cpu1 { 590 #power-domain-cells = <0>; 591 power-domains = <&CLUSTER_PD>; 592 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 593 }; 594 595 CPU_PD2: power-domain-cpu2 { 596 #power-domain-cells = <0>; 597 power-domains = <&CLUSTER_PD>; 598 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 599 }; 600 601 CPU_PD3: power-domain-cpu3 { 602 #power-domain-cells = <0>; 603 power-domains = <&CLUSTER_PD>; 604 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 605 }; 606 607 CPU_PD4: power-domain-cpu4 { 608 #power-domain-cells = <0>; 609 power-domains = <&CLUSTER_PD>; 610 domain-idle-states = <&BIG_CPU_SLEEP_0>; 611 }; 612 613 CPU_PD5: power-domain-cpu5 { 614 #power-domain-cells = <0>; 615 power-domains = <&CLUSTER_PD>; 616 domain-idle-states = <&BIG_CPU_SLEEP_0>; 617 }; 618 619 CPU_PD6: power-domain-cpu6 { 620 #power-domain-cells = <0>; 621 power-domains = <&CLUSTER_PD>; 622 domain-idle-states = <&BIG_CPU_SLEEP_0>; 623 }; 624 625 CPU_PD7: power-domain-cpu7 { 626 #power-domain-cells = <0>; 627 power-domains = <&CLUSTER_PD>; 628 domain-idle-states = <&BIG_CPU_SLEEP_0>; 629 }; 630 631 CLUSTER_PD: power-domain-cpu-cluster0 { 632 #power-domain-cells = <0>; 633 domain-idle-states = <&CLUSTER_SLEEP_0>; 634 }; 635 }; 636 637 reserved-memory { 638 #address-cells = <2>; 639 #size-cells = <2>; 640 ranges; 641 642 reserved-region@80000000 { 643 reg = <0 0x80000000 0 0x860000>; 644 no-map; 645 }; 646 647 cmd_db: cmd-db-region@80860000 { 648 compatible = "qcom,cmd-db"; 649 reg = <0 0x80860000 0 0x20000>; 650 no-map; 651 }; 652 653 reserved-region@80880000 { 654 reg = <0 0x80880000 0 0x80000>; 655 no-map; 656 }; 657 658 smem_mem: smem-region@80900000 { 659 compatible = "qcom,smem"; 660 reg = <0 0x80900000 0 0x200000>; 661 no-map; 662 hwlocks = <&tcsr_mutex 3>; 663 }; 664 665 reserved-region@80b00000 { 666 reg = <0 0x80b00000 0 0x100000>; 667 no-map; 668 }; 669 670 reserved-region@83b00000 { 671 reg = <0 0x83b00000 0 0x1700000>; 672 no-map; 673 }; 674 675 reserved-region@85b00000 { 676 reg = <0 0x85b00000 0 0xc00000>; 677 no-map; 678 }; 679 680 pil_adsp_mem: adsp-region@86c00000 { 681 reg = <0 0x86c00000 0 0x2000000>; 682 no-map; 683 }; 684 685 pil_nsp0_mem: cdsp0-region@8a100000 { 686 reg = <0 0x8a100000 0 0x1e00000>; 687 no-map; 688 }; 689 690 pil_nsp1_mem: cdsp1-region@8c600000 { 691 reg = <0 0x8c600000 0 0x1e00000>; 692 no-map; 693 }; 694 695 reserved-region@aeb00000 { 696 reg = <0 0xaeb00000 0 0x16600000>; 697 no-map; 698 }; 699 }; 700 701 smp2p-adsp { 702 compatible = "qcom,smp2p"; 703 qcom,smem = <443>, <429>; 704 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 705 IPCC_MPROC_SIGNAL_SMP2P 706 IRQ_TYPE_EDGE_RISING>; 707 mboxes = <&ipcc IPCC_CLIENT_LPASS 708 IPCC_MPROC_SIGNAL_SMP2P>; 709 710 qcom,local-pid = <0>; 711 qcom,remote-pid = <2>; 712 713 smp2p_adsp_out: master-kernel { 714 qcom,entry-name = "master-kernel"; 715 #qcom,smem-state-cells = <1>; 716 }; 717 718 smp2p_adsp_in: slave-kernel { 719 qcom,entry-name = "slave-kernel"; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 }; 724 725 smp2p-nsp0 { 726 compatible = "qcom,smp2p"; 727 qcom,smem = <94>, <432>; 728 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 729 IPCC_MPROC_SIGNAL_SMP2P 730 IRQ_TYPE_EDGE_RISING>; 731 mboxes = <&ipcc IPCC_CLIENT_CDSP 732 IPCC_MPROC_SIGNAL_SMP2P>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <5>; 736 737 smp2p_nsp0_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 smp2p_nsp0_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 smp2p-nsp1 { 750 compatible = "qcom,smp2p"; 751 qcom,smem = <617>, <616>; 752 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 753 IPCC_MPROC_SIGNAL_SMP2P 754 IRQ_TYPE_EDGE_RISING>; 755 mboxes = <&ipcc IPCC_CLIENT_NSP1 756 IPCC_MPROC_SIGNAL_SMP2P>; 757 758 qcom,local-pid = <0>; 759 qcom,remote-pid = <12>; 760 761 smp2p_nsp1_out: master-kernel { 762 qcom,entry-name = "master-kernel"; 763 #qcom,smem-state-cells = <1>; 764 }; 765 766 smp2p_nsp1_in: slave-kernel { 767 qcom,entry-name = "slave-kernel"; 768 interrupt-controller; 769 #interrupt-cells = <2>; 770 }; 771 }; 772 773 soc: soc@0 { 774 compatible = "simple-bus"; 775 #address-cells = <2>; 776 #size-cells = <2>; 777 ranges = <0 0 0 0 0x10 0>; 778 dma-ranges = <0 0 0 0 0x10 0>; 779 780 gcc: clock-controller@100000 { 781 compatible = "qcom,gcc-sc8280xp"; 782 reg = <0x0 0x00100000 0x0 0x1f0000>; 783 #clock-cells = <1>; 784 #reset-cells = <1>; 785 #power-domain-cells = <1>; 786 clocks = <&rpmhcc RPMH_CXO_CLK>, 787 <&sleep_clk>, 788 <0>, 789 <0>, 790 <0>, 791 <0>, 792 <0>, 793 <0>, 794 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 795 <0>, 796 <0>, 797 <0>, 798 <0>, 799 <0>, 800 <0>, 801 <0>, 802 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 803 <0>, 804 <0>, 805 <0>, 806 <0>, 807 <0>, 808 <0>, 809 <0>, 810 <0>, 811 <0>, 812 <&pcie2a_phy>, 813 <&pcie2b_phy>, 814 <&pcie3a_phy>, 815 <&pcie3b_phy>, 816 <&pcie4_phy>, 817 <0>, 818 <0>; 819 power-domains = <&rpmhpd SC8280XP_CX>; 820 }; 821 822 ipcc: mailbox@408000 { 823 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 824 reg = <0 0x00408000 0 0x1000>; 825 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 826 interrupt-controller; 827 #interrupt-cells = <3>; 828 #mbox-cells = <2>; 829 }; 830 831 qup2: geniqup@8c0000 { 832 compatible = "qcom,geni-se-qup"; 833 reg = <0 0x008c0000 0 0x2000>; 834 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 835 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 836 clock-names = "m-ahb", "s-ahb"; 837 iommus = <&apps_smmu 0xa3 0>; 838 839 #address-cells = <2>; 840 #size-cells = <2>; 841 ranges; 842 843 status = "disabled"; 844 845 i2c16: i2c@880000 { 846 compatible = "qcom,geni-i2c"; 847 reg = <0 0x00880000 0 0x4000>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 851 clock-names = "se"; 852 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 853 power-domains = <&rpmhpd SC8280XP_CX>; 854 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 855 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 856 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 857 interconnect-names = "qup-core", "qup-config", "qup-memory"; 858 status = "disabled"; 859 }; 860 861 spi16: spi@880000 { 862 compatible = "qcom,geni-spi"; 863 reg = <0 0x00880000 0 0x4000>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 867 clock-names = "se"; 868 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 869 power-domains = <&rpmhpd SC8280XP_CX>; 870 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 871 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 872 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 873 interconnect-names = "qup-core", "qup-config", "qup-memory"; 874 status = "disabled"; 875 }; 876 877 i2c17: i2c@884000 { 878 compatible = "qcom,geni-i2c"; 879 reg = <0 0x00884000 0 0x4000>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 883 clock-names = "se"; 884 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 885 power-domains = <&rpmhpd SC8280XP_CX>; 886 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 887 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 888 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 889 interconnect-names = "qup-core", "qup-config", "qup-memory"; 890 status = "disabled"; 891 }; 892 893 spi17: spi@884000 { 894 compatible = "qcom,geni-spi"; 895 reg = <0 0x00884000 0 0x4000>; 896 #address-cells = <1>; 897 #size-cells = <0>; 898 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 899 clock-names = "se"; 900 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 901 power-domains = <&rpmhpd SC8280XP_CX>; 902 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 903 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 904 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 905 interconnect-names = "qup-core", "qup-config", "qup-memory"; 906 status = "disabled"; 907 }; 908 909 uart17: serial@884000 { 910 compatible = "qcom,geni-uart"; 911 reg = <0 0x00884000 0 0x4000>; 912 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 913 clock-names = "se"; 914 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 915 operating-points-v2 = <&qup_opp_table_100mhz>; 916 power-domains = <&rpmhpd SC8280XP_CX>; 917 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 919 interconnect-names = "qup-core", "qup-config"; 920 status = "disabled"; 921 }; 922 923 i2c18: i2c@888000 { 924 compatible = "qcom,geni-i2c"; 925 reg = <0 0x00888000 0 0x4000>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 929 clock-names = "se"; 930 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 931 power-domains = <&rpmhpd SC8280XP_CX>; 932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 934 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 935 interconnect-names = "qup-core", "qup-config", "qup-memory"; 936 status = "disabled"; 937 }; 938 939 spi18: spi@888000 { 940 compatible = "qcom,geni-spi"; 941 reg = <0 0x00888000 0 0x4000>; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 945 clock-names = "se"; 946 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 947 power-domains = <&rpmhpd SC8280XP_CX>; 948 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 949 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 950 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 951 interconnect-names = "qup-core", "qup-config", "qup-memory"; 952 status = "disabled"; 953 }; 954 955 i2c19: i2c@88c000 { 956 compatible = "qcom,geni-i2c"; 957 reg = <0 0x0088c000 0 0x4000>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 961 clock-names = "se"; 962 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 963 power-domains = <&rpmhpd SC8280XP_CX>; 964 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 965 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 966 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 967 interconnect-names = "qup-core", "qup-config", "qup-memory"; 968 status = "disabled"; 969 }; 970 971 spi19: spi@88c000 { 972 compatible = "qcom,geni-spi"; 973 reg = <0 0x0088c000 0 0x4000>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 977 clock-names = "se"; 978 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 979 power-domains = <&rpmhpd SC8280XP_CX>; 980 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 981 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 982 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 983 interconnect-names = "qup-core", "qup-config", "qup-memory"; 984 status = "disabled"; 985 }; 986 987 i2c20: i2c@890000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00890000 0 0x4000>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 993 clock-names = "se"; 994 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 995 power-domains = <&rpmhpd SC8280XP_CX>; 996 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 997 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 998 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 999 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1000 status = "disabled"; 1001 }; 1002 1003 spi20: spi@890000 { 1004 compatible = "qcom,geni-spi"; 1005 reg = <0 0x00890000 0 0x4000>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1009 clock-names = "se"; 1010 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1011 power-domains = <&rpmhpd SC8280XP_CX>; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1013 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1014 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1015 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1016 status = "disabled"; 1017 }; 1018 1019 i2c21: i2c@894000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0 0x00894000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1024 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 power-domains = <&rpmhpd SC8280XP_CX>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1029 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1030 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1031 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1032 status = "disabled"; 1033 }; 1034 1035 spi21: spi@894000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0 0x00894000 0 0x4000>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1041 clock-names = "se"; 1042 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1043 power-domains = <&rpmhpd SC8280XP_CX>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1045 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1046 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1047 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1048 status = "disabled"; 1049 }; 1050 1051 i2c22: i2c@898000 { 1052 compatible = "qcom,geni-i2c"; 1053 reg = <0 0x00898000 0 0x4000>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1058 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1059 power-domains = <&rpmhpd SC8280XP_CX>; 1060 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1062 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1063 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1064 status = "disabled"; 1065 }; 1066 1067 spi22: spi@898000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0 0x00898000 0 0x4000>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1073 clock-names = "se"; 1074 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1075 power-domains = <&rpmhpd SC8280XP_CX>; 1076 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1077 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1078 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1079 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1080 status = "disabled"; 1081 }; 1082 1083 i2c23: i2c@89c000 { 1084 compatible = "qcom,geni-i2c"; 1085 reg = <0 0x0089c000 0 0x4000>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1090 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1091 power-domains = <&rpmhpd SC8280XP_CX>; 1092 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1093 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1094 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1095 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1096 status = "disabled"; 1097 }; 1098 1099 spi23: spi@89c000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0 0x0089c000 0 0x4000>; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1105 clock-names = "se"; 1106 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1107 power-domains = <&rpmhpd SC8280XP_CX>; 1108 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1109 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1110 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1111 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1112 status = "disabled"; 1113 }; 1114 }; 1115 1116 qup0: geniqup@9c0000 { 1117 compatible = "qcom,geni-se-qup"; 1118 reg = <0 0x009c0000 0 0x6000>; 1119 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1120 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1121 clock-names = "m-ahb", "s-ahb"; 1122 iommus = <&apps_smmu 0x563 0>; 1123 1124 #address-cells = <2>; 1125 #size-cells = <2>; 1126 ranges; 1127 1128 status = "disabled"; 1129 1130 i2c0: i2c@980000 { 1131 compatible = "qcom,geni-i2c"; 1132 reg = <0 0x00980000 0 0x4000>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1137 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmhpd SC8280XP_CX>; 1139 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1140 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1141 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1142 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1143 status = "disabled"; 1144 }; 1145 1146 spi0: spi@980000 { 1147 compatible = "qcom,geni-spi"; 1148 reg = <0 0x00980000 0 0x4000>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1152 clock-names = "se"; 1153 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1154 power-domains = <&rpmhpd SC8280XP_CX>; 1155 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1156 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1157 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1158 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1159 status = "disabled"; 1160 }; 1161 1162 i2c1: i2c@984000 { 1163 compatible = "qcom,geni-i2c"; 1164 reg = <0 0x00984000 0 0x4000>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1169 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1170 power-domains = <&rpmhpd SC8280XP_CX>; 1171 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1172 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1173 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1174 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1175 status = "disabled"; 1176 }; 1177 1178 spi1: spi@984000 { 1179 compatible = "qcom,geni-spi"; 1180 reg = <0 0x00984000 0 0x4000>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1184 clock-names = "se"; 1185 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1186 power-domains = <&rpmhpd SC8280XP_CX>; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1188 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1189 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1190 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1191 status = "disabled"; 1192 }; 1193 1194 i2c2: i2c@988000 { 1195 compatible = "qcom,geni-i2c"; 1196 reg = <0 0x00988000 0 0x4000>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 clock-names = "se"; 1200 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1201 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1202 power-domains = <&rpmhpd SC8280XP_CX>; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1205 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1206 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1207 status = "disabled"; 1208 }; 1209 1210 spi2: spi@988000 { 1211 compatible = "qcom,geni-spi"; 1212 reg = <0 0x00988000 0 0x4000>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1216 clock-names = "se"; 1217 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1218 power-domains = <&rpmhpd SC8280XP_CX>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1221 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1222 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1223 status = "disabled"; 1224 }; 1225 1226 uart2: serial@988000 { 1227 compatible = "qcom,geni-uart"; 1228 reg = <0 0x00988000 0 0x4000>; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1230 clock-names = "se"; 1231 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1232 operating-points-v2 = <&qup_opp_table_100mhz>; 1233 power-domains = <&rpmhpd SC8280XP_CX>; 1234 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1235 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1236 interconnect-names = "qup-core", "qup-config"; 1237 status = "disabled"; 1238 }; 1239 1240 i2c3: i2c@98c000 { 1241 compatible = "qcom,geni-i2c"; 1242 reg = <0 0x0098c000 0 0x4000>; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 clock-names = "se"; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1247 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1248 power-domains = <&rpmhpd SC8280XP_CX>; 1249 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1250 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1251 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1252 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1253 status = "disabled"; 1254 }; 1255 1256 spi3: spi@98c000 { 1257 compatible = "qcom,geni-spi"; 1258 reg = <0 0x0098c000 0 0x4000>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1262 clock-names = "se"; 1263 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1264 power-domains = <&rpmhpd SC8280XP_CX>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1266 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1267 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1268 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1269 status = "disabled"; 1270 }; 1271 1272 i2c4: i2c@990000 { 1273 compatible = "qcom,geni-i2c"; 1274 reg = <0 0x00990000 0 0x4000>; 1275 clock-names = "se"; 1276 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1277 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 power-domains = <&rpmhpd SC8280XP_CX>; 1281 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1282 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1283 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1284 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1285 status = "disabled"; 1286 }; 1287 1288 spi4: spi@990000 { 1289 compatible = "qcom,geni-spi"; 1290 reg = <0 0x00990000 0 0x4000>; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1294 clock-names = "se"; 1295 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1296 power-domains = <&rpmhpd SC8280XP_CX>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1299 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1300 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1301 status = "disabled"; 1302 }; 1303 1304 i2c5: i2c@994000 { 1305 compatible = "qcom,geni-i2c"; 1306 reg = <0 0x00994000 0 0x4000>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1311 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1312 power-domains = <&rpmhpd SC8280XP_CX>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1315 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1316 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1317 status = "disabled"; 1318 }; 1319 1320 spi5: spi@994000 { 1321 compatible = "qcom,geni-spi"; 1322 reg = <0 0x00994000 0 0x4000>; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1326 clock-names = "se"; 1327 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1328 power-domains = <&rpmhpd SC8280XP_CX>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1330 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1331 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1332 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1333 status = "disabled"; 1334 }; 1335 1336 i2c6: i2c@998000 { 1337 compatible = "qcom,geni-i2c"; 1338 reg = <0 0x00998000 0 0x4000>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 clock-names = "se"; 1342 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1343 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1344 power-domains = <&rpmhpd SC8280XP_CX>; 1345 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1346 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1347 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1348 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1349 status = "disabled"; 1350 }; 1351 1352 spi6: spi@998000 { 1353 compatible = "qcom,geni-spi"; 1354 reg = <0 0x00998000 0 0x4000>; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1358 clock-names = "se"; 1359 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1360 power-domains = <&rpmhpd SC8280XP_CX>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1363 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1364 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1365 status = "disabled"; 1366 }; 1367 1368 i2c7: i2c@99c000 { 1369 compatible = "qcom,geni-i2c"; 1370 reg = <0 0x0099c000 0 0x4000>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 clock-names = "se"; 1374 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1375 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1376 power-domains = <&rpmhpd SC8280XP_CX>; 1377 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1378 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1379 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1380 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1381 status = "disabled"; 1382 }; 1383 1384 spi7: spi@99c000 { 1385 compatible = "qcom,geni-spi"; 1386 reg = <0 0x0099c000 0 0x4000>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1390 clock-names = "se"; 1391 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1392 power-domains = <&rpmhpd SC8280XP_CX>; 1393 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1394 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1395 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1396 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1397 status = "disabled"; 1398 }; 1399 }; 1400 1401 qup1: geniqup@ac0000 { 1402 compatible = "qcom,geni-se-qup"; 1403 reg = <0 0x00ac0000 0 0x6000>; 1404 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1405 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1406 clock-names = "m-ahb", "s-ahb"; 1407 iommus = <&apps_smmu 0x83 0>; 1408 1409 #address-cells = <2>; 1410 #size-cells = <2>; 1411 ranges; 1412 1413 status = "disabled"; 1414 1415 i2c8: i2c@a80000 { 1416 compatible = "qcom,geni-i2c"; 1417 reg = <0 0x00a80000 0 0x4000>; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1421 clock-names = "se"; 1422 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1423 power-domains = <&rpmhpd SC8280XP_CX>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1425 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1426 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1427 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1428 status = "disabled"; 1429 }; 1430 1431 spi8: spi@a80000 { 1432 compatible = "qcom,geni-spi"; 1433 reg = <0 0x00a80000 0 0x4000>; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1437 clock-names = "se"; 1438 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1439 power-domains = <&rpmhpd SC8280XP_CX>; 1440 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1441 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1442 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1443 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1444 status = "disabled"; 1445 }; 1446 1447 i2c9: i2c@a84000 { 1448 compatible = "qcom,geni-i2c"; 1449 reg = <0 0x00a84000 0 0x4000>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1453 clock-names = "se"; 1454 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1455 power-domains = <&rpmhpd SC8280XP_CX>; 1456 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1457 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1458 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1459 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1460 status = "disabled"; 1461 }; 1462 1463 spi9: spi@a84000 { 1464 compatible = "qcom,geni-spi"; 1465 reg = <0 0x00a84000 0 0x4000>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1469 clock-names = "se"; 1470 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1471 power-domains = <&rpmhpd SC8280XP_CX>; 1472 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1473 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1474 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1475 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1476 status = "disabled"; 1477 }; 1478 1479 i2c10: i2c@a88000 { 1480 compatible = "qcom,geni-i2c"; 1481 reg = <0 0x00a88000 0 0x4000>; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1485 clock-names = "se"; 1486 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1487 power-domains = <&rpmhpd SC8280XP_CX>; 1488 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1489 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1490 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1491 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1492 status = "disabled"; 1493 }; 1494 1495 spi10: spi@a88000 { 1496 compatible = "qcom,geni-spi"; 1497 reg = <0 0x00a88000 0 0x4000>; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1501 clock-names = "se"; 1502 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1503 power-domains = <&rpmhpd SC8280XP_CX>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1506 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1507 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1508 status = "disabled"; 1509 }; 1510 1511 i2c11: i2c@a8c000 { 1512 compatible = "qcom,geni-i2c"; 1513 reg = <0 0x00a8c000 0 0x4000>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1517 clock-names = "se"; 1518 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1519 power-domains = <&rpmhpd SC8280XP_CX>; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1521 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1522 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1523 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1524 status = "disabled"; 1525 }; 1526 1527 spi11: spi@a8c000 { 1528 compatible = "qcom,geni-spi"; 1529 reg = <0 0x00a8c000 0 0x4000>; 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1533 clock-names = "se"; 1534 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1535 power-domains = <&rpmhpd SC8280XP_CX>; 1536 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1537 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1538 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1539 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1540 status = "disabled"; 1541 }; 1542 1543 i2c12: i2c@a90000 { 1544 compatible = "qcom,geni-i2c"; 1545 reg = <0 0x00a90000 0 0x4000>; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1549 clock-names = "se"; 1550 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1551 power-domains = <&rpmhpd SC8280XP_CX>; 1552 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1553 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1554 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1555 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1556 status = "disabled"; 1557 }; 1558 1559 spi12: spi@a90000 { 1560 compatible = "qcom,geni-spi"; 1561 reg = <0 0x00a90000 0 0x4000>; 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1565 clock-names = "se"; 1566 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1567 power-domains = <&rpmhpd SC8280XP_CX>; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1569 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1570 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1571 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1572 status = "disabled"; 1573 }; 1574 1575 i2c13: i2c@a94000 { 1576 compatible = "qcom,geni-i2c"; 1577 reg = <0 0x00a94000 0 0x4000>; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1581 clock-names = "se"; 1582 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1583 power-domains = <&rpmhpd SC8280XP_CX>; 1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1585 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1586 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1587 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1588 status = "disabled"; 1589 }; 1590 1591 spi13: spi@a94000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a94000 0 0x4000>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1597 clock-names = "se"; 1598 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1599 power-domains = <&rpmhpd SC8280XP_CX>; 1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1601 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1602 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1603 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1604 status = "disabled"; 1605 }; 1606 1607 i2c14: i2c@a98000 { 1608 compatible = "qcom,geni-i2c"; 1609 reg = <0 0x00a98000 0 0x4000>; 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1613 clock-names = "se"; 1614 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1615 power-domains = <&rpmhpd SC8280XP_CX>; 1616 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1617 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1618 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1619 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1620 status = "disabled"; 1621 }; 1622 1623 spi14: spi@a98000 { 1624 compatible = "qcom,geni-spi"; 1625 reg = <0 0x00a98000 0 0x4000>; 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1629 clock-names = "se"; 1630 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1631 power-domains = <&rpmhpd SC8280XP_CX>; 1632 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1633 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1634 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1635 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1636 status = "disabled"; 1637 }; 1638 1639 i2c15: i2c@a9c000 { 1640 compatible = "qcom,geni-i2c"; 1641 reg = <0 0x00a9c000 0 0x4000>; 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1645 clock-names = "se"; 1646 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1647 power-domains = <&rpmhpd SC8280XP_CX>; 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1649 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1650 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1651 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1652 status = "disabled"; 1653 }; 1654 1655 spi15: spi@a9c000 { 1656 compatible = "qcom,geni-spi"; 1657 reg = <0 0x00a9c000 0 0x4000>; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1661 clock-names = "se"; 1662 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1663 power-domains = <&rpmhpd SC8280XP_CX>; 1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1665 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1666 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1667 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1668 status = "disabled"; 1669 }; 1670 }; 1671 1672 rng: rng@10d3000 { 1673 compatible = "qcom,prng-ee"; 1674 reg = <0 0x010d3000 0 0x1000>; 1675 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1676 clock-names = "core"; 1677 }; 1678 1679 pcie4: pcie@1c00000 { 1680 device_type = "pci"; 1681 compatible = "qcom,pcie-sc8280xp"; 1682 reg = <0x0 0x01c00000 0x0 0x3000>, 1683 <0x0 0x30000000 0x0 0xf1d>, 1684 <0x0 0x30000f20 0x0 0xa8>, 1685 <0x0 0x30001000 0x0 0x1000>, 1686 <0x0 0x30100000 0x0 0x100000>, 1687 <0x0 0x01c03000 0x0 0x1000>; 1688 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1689 #address-cells = <3>; 1690 #size-cells = <2>; 1691 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1692 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1693 bus-range = <0x00 0xff>; 1694 1695 dma-coherent; 1696 1697 linux,pci-domain = <6>; 1698 num-lanes = <1>; 1699 1700 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1704 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1705 1706 #interrupt-cells = <1>; 1707 interrupt-map-mask = <0 0 0 0x7>; 1708 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1709 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1710 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1711 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1712 1713 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1714 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1715 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1716 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1717 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1718 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1719 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1720 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1721 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1722 clock-names = "aux", 1723 "cfg", 1724 "bus_master", 1725 "bus_slave", 1726 "slave_q2a", 1727 "ddrss_sf_tbu", 1728 "noc_aggr_4", 1729 "noc_aggr_south_sf", 1730 "cnoc_qx"; 1731 1732 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1733 assigned-clock-rates = <19200000>; 1734 1735 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1736 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1737 interconnect-names = "pcie-mem", "cpu-pcie"; 1738 1739 resets = <&gcc GCC_PCIE_4_BCR>; 1740 reset-names = "pci"; 1741 1742 power-domains = <&gcc PCIE_4_GDSC>; 1743 1744 phys = <&pcie4_phy>; 1745 phy-names = "pciephy"; 1746 1747 status = "disabled"; 1748 }; 1749 1750 pcie4_phy: phy@1c06000 { 1751 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1752 reg = <0x0 0x01c06000 0x0 0x2000>; 1753 1754 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1755 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1756 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1757 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1758 <&gcc GCC_PCIE_4_PIPE_CLK>, 1759 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1760 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1761 "pipe", "pipediv2"; 1762 1763 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1764 assigned-clock-rates = <100000000>; 1765 1766 power-domains = <&gcc PCIE_4_GDSC>; 1767 1768 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1769 reset-names = "phy"; 1770 1771 #clock-cells = <0>; 1772 clock-output-names = "pcie_4_pipe_clk"; 1773 1774 #phy-cells = <0>; 1775 1776 status = "disabled"; 1777 }; 1778 1779 pcie3b: pcie@1c08000 { 1780 device_type = "pci"; 1781 compatible = "qcom,pcie-sc8280xp"; 1782 reg = <0x0 0x01c08000 0x0 0x3000>, 1783 <0x0 0x32000000 0x0 0xf1d>, 1784 <0x0 0x32000f20 0x0 0xa8>, 1785 <0x0 0x32001000 0x0 0x1000>, 1786 <0x0 0x32100000 0x0 0x100000>, 1787 <0x0 0x01c0b000 0x0 0x1000>; 1788 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1789 #address-cells = <3>; 1790 #size-cells = <2>; 1791 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1792 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1793 bus-range = <0x00 0xff>; 1794 1795 dma-coherent; 1796 1797 linux,pci-domain = <5>; 1798 num-lanes = <2>; 1799 1800 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1804 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1805 1806 #interrupt-cells = <1>; 1807 interrupt-map-mask = <0 0 0 0x7>; 1808 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1809 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1810 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1811 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1812 1813 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1814 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1815 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1816 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1817 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1818 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1819 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1820 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1821 clock-names = "aux", 1822 "cfg", 1823 "bus_master", 1824 "bus_slave", 1825 "slave_q2a", 1826 "ddrss_sf_tbu", 1827 "noc_aggr_4", 1828 "noc_aggr_south_sf"; 1829 1830 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1831 assigned-clock-rates = <19200000>; 1832 1833 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1834 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1835 interconnect-names = "pcie-mem", "cpu-pcie"; 1836 1837 resets = <&gcc GCC_PCIE_3B_BCR>; 1838 reset-names = "pci"; 1839 1840 power-domains = <&gcc PCIE_3B_GDSC>; 1841 1842 phys = <&pcie3b_phy>; 1843 phy-names = "pciephy"; 1844 1845 status = "disabled"; 1846 }; 1847 1848 pcie3b_phy: phy@1c0e000 { 1849 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1850 reg = <0x0 0x01c0e000 0x0 0x2000>; 1851 1852 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1853 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1854 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1855 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1856 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1857 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1858 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1859 "pipe", "pipediv2"; 1860 1861 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1862 assigned-clock-rates = <100000000>; 1863 1864 power-domains = <&gcc PCIE_3B_GDSC>; 1865 1866 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1867 reset-names = "phy"; 1868 1869 #clock-cells = <0>; 1870 clock-output-names = "pcie_3b_pipe_clk"; 1871 1872 #phy-cells = <0>; 1873 1874 status = "disabled"; 1875 }; 1876 1877 pcie3a: pcie@1c10000 { 1878 device_type = "pci"; 1879 compatible = "qcom,pcie-sc8280xp"; 1880 reg = <0x0 0x01c10000 0x0 0x3000>, 1881 <0x0 0x34000000 0x0 0xf1d>, 1882 <0x0 0x34000f20 0x0 0xa8>, 1883 <0x0 0x34001000 0x0 0x1000>, 1884 <0x0 0x34100000 0x0 0x100000>, 1885 <0x0 0x01c13000 0x0 0x1000>; 1886 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1887 #address-cells = <3>; 1888 #size-cells = <2>; 1889 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1890 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1891 bus-range = <0x00 0xff>; 1892 1893 dma-coherent; 1894 1895 linux,pci-domain = <4>; 1896 num-lanes = <4>; 1897 1898 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1902 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1903 1904 #interrupt-cells = <1>; 1905 interrupt-map-mask = <0 0 0 0x7>; 1906 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1907 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1908 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1909 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1910 1911 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1912 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1913 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1914 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1915 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1916 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1917 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1918 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1919 clock-names = "aux", 1920 "cfg", 1921 "bus_master", 1922 "bus_slave", 1923 "slave_q2a", 1924 "ddrss_sf_tbu", 1925 "noc_aggr_4", 1926 "noc_aggr_south_sf"; 1927 1928 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1929 assigned-clock-rates = <19200000>; 1930 1931 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1932 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1933 interconnect-names = "pcie-mem", "cpu-pcie"; 1934 1935 resets = <&gcc GCC_PCIE_3A_BCR>; 1936 reset-names = "pci"; 1937 1938 power-domains = <&gcc PCIE_3A_GDSC>; 1939 1940 phys = <&pcie3a_phy>; 1941 phy-names = "pciephy"; 1942 1943 status = "disabled"; 1944 }; 1945 1946 pcie3a_phy: phy@1c14000 { 1947 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1948 reg = <0x0 0x01c14000 0x0 0x2000>, 1949 <0x0 0x01c16000 0x0 0x2000>; 1950 1951 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1952 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1953 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1954 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1955 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1956 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1957 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1958 "pipe", "pipediv2"; 1959 1960 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1961 assigned-clock-rates = <100000000>; 1962 1963 power-domains = <&gcc PCIE_3A_GDSC>; 1964 1965 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 1966 reset-names = "phy"; 1967 1968 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 1969 1970 #clock-cells = <0>; 1971 clock-output-names = "pcie_3a_pipe_clk"; 1972 1973 #phy-cells = <0>; 1974 1975 status = "disabled"; 1976 }; 1977 1978 pcie2b: pcie@1c18000 { 1979 device_type = "pci"; 1980 compatible = "qcom,pcie-sc8280xp"; 1981 reg = <0x0 0x01c18000 0x0 0x3000>, 1982 <0x0 0x38000000 0x0 0xf1d>, 1983 <0x0 0x38000f20 0x0 0xa8>, 1984 <0x0 0x38001000 0x0 0x1000>, 1985 <0x0 0x38100000 0x0 0x100000>, 1986 <0x0 0x01c1b000 0x0 0x1000>; 1987 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1988 #address-cells = <3>; 1989 #size-cells = <2>; 1990 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 1991 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 1992 bus-range = <0x00 0xff>; 1993 1994 dma-coherent; 1995 1996 linux,pci-domain = <3>; 1997 num-lanes = <2>; 1998 1999 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2003 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2004 2005 #interrupt-cells = <1>; 2006 interrupt-map-mask = <0 0 0 0x7>; 2007 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2008 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2009 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2010 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2011 2012 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2013 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2014 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2015 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2016 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2017 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2018 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2019 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2020 clock-names = "aux", 2021 "cfg", 2022 "bus_master", 2023 "bus_slave", 2024 "slave_q2a", 2025 "ddrss_sf_tbu", 2026 "noc_aggr_4", 2027 "noc_aggr_south_sf"; 2028 2029 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2030 assigned-clock-rates = <19200000>; 2031 2032 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2033 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2034 interconnect-names = "pcie-mem", "cpu-pcie"; 2035 2036 resets = <&gcc GCC_PCIE_2B_BCR>; 2037 reset-names = "pci"; 2038 2039 power-domains = <&gcc PCIE_2B_GDSC>; 2040 2041 phys = <&pcie2b_phy>; 2042 phy-names = "pciephy"; 2043 2044 status = "disabled"; 2045 }; 2046 2047 pcie2b_phy: phy@1c1e000 { 2048 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2049 reg = <0x0 0x01c1e000 0x0 0x2000>; 2050 2051 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2052 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2053 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2054 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2055 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2056 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2057 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2058 "pipe", "pipediv2"; 2059 2060 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2061 assigned-clock-rates = <100000000>; 2062 2063 power-domains = <&gcc PCIE_2B_GDSC>; 2064 2065 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2066 reset-names = "phy"; 2067 2068 #clock-cells = <0>; 2069 clock-output-names = "pcie_2b_pipe_clk"; 2070 2071 #phy-cells = <0>; 2072 2073 status = "disabled"; 2074 }; 2075 2076 pcie2a: pcie@1c20000 { 2077 device_type = "pci"; 2078 compatible = "qcom,pcie-sc8280xp"; 2079 reg = <0x0 0x01c20000 0x0 0x3000>, 2080 <0x0 0x3c000000 0x0 0xf1d>, 2081 <0x0 0x3c000f20 0x0 0xa8>, 2082 <0x0 0x3c001000 0x0 0x1000>, 2083 <0x0 0x3c100000 0x0 0x100000>, 2084 <0x0 0x01c23000 0x0 0x1000>; 2085 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2086 #address-cells = <3>; 2087 #size-cells = <2>; 2088 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2089 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2090 bus-range = <0x00 0xff>; 2091 2092 dma-coherent; 2093 2094 linux,pci-domain = <2>; 2095 num-lanes = <4>; 2096 2097 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2101 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2102 2103 #interrupt-cells = <1>; 2104 interrupt-map-mask = <0 0 0 0x7>; 2105 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2106 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2107 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2108 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2109 2110 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2111 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2112 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2113 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2114 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2115 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2116 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2117 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2118 clock-names = "aux", 2119 "cfg", 2120 "bus_master", 2121 "bus_slave", 2122 "slave_q2a", 2123 "ddrss_sf_tbu", 2124 "noc_aggr_4", 2125 "noc_aggr_south_sf"; 2126 2127 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2128 assigned-clock-rates = <19200000>; 2129 2130 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2132 interconnect-names = "pcie-mem", "cpu-pcie"; 2133 2134 resets = <&gcc GCC_PCIE_2A_BCR>; 2135 reset-names = "pci"; 2136 2137 power-domains = <&gcc PCIE_2A_GDSC>; 2138 2139 phys = <&pcie2a_phy>; 2140 phy-names = "pciephy"; 2141 2142 status = "disabled"; 2143 }; 2144 2145 pcie2a_phy: phy@1c24000 { 2146 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2147 reg = <0x0 0x01c24000 0x0 0x2000>, 2148 <0x0 0x01c26000 0x0 0x2000>; 2149 2150 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2151 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2152 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2153 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2154 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2155 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2156 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2157 "pipe", "pipediv2"; 2158 2159 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2160 assigned-clock-rates = <100000000>; 2161 2162 power-domains = <&gcc PCIE_2A_GDSC>; 2163 2164 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2165 reset-names = "phy"; 2166 2167 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2168 2169 #clock-cells = <0>; 2170 clock-output-names = "pcie_2a_pipe_clk"; 2171 2172 #phy-cells = <0>; 2173 2174 status = "disabled"; 2175 }; 2176 2177 ufs_mem_hc: ufs@1d84000 { 2178 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2179 "jedec,ufs-2.0"; 2180 reg = <0 0x01d84000 0 0x3000>; 2181 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2182 phys = <&ufs_mem_phy>; 2183 phy-names = "ufsphy"; 2184 lanes-per-direction = <2>; 2185 #reset-cells = <1>; 2186 resets = <&gcc GCC_UFS_PHY_BCR>; 2187 reset-names = "rst"; 2188 2189 power-domains = <&gcc UFS_PHY_GDSC>; 2190 required-opps = <&rpmhpd_opp_nom>; 2191 2192 iommus = <&apps_smmu 0xe0 0x0>; 2193 dma-coherent; 2194 2195 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2196 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2197 <&gcc GCC_UFS_PHY_AHB_CLK>, 2198 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2199 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2200 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2201 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2202 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2203 clock-names = "core_clk", 2204 "bus_aggr_clk", 2205 "iface_clk", 2206 "core_clk_unipro", 2207 "ref_clk", 2208 "tx_lane0_sync_clk", 2209 "rx_lane0_sync_clk", 2210 "rx_lane1_sync_clk"; 2211 freq-table-hz = <75000000 300000000>, 2212 <0 0>, 2213 <0 0>, 2214 <75000000 300000000>, 2215 <0 0>, 2216 <0 0>, 2217 <0 0>, 2218 <0 0>; 2219 status = "disabled"; 2220 }; 2221 2222 ufs_mem_phy: phy@1d87000 { 2223 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2224 reg = <0 0x01d87000 0 0x1000>; 2225 2226 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, 2227 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2228 clock-names = "ref", "ref_aux"; 2229 2230 power-domains = <&gcc UFS_PHY_GDSC>; 2231 2232 resets = <&ufs_mem_hc 0>; 2233 reset-names = "ufsphy"; 2234 2235 #phy-cells = <0>; 2236 2237 status = "disabled"; 2238 }; 2239 2240 ufs_card_hc: ufs@1da4000 { 2241 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2242 "jedec,ufs-2.0"; 2243 reg = <0 0x01da4000 0 0x3000>; 2244 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2245 phys = <&ufs_card_phy>; 2246 phy-names = "ufsphy"; 2247 lanes-per-direction = <2>; 2248 #reset-cells = <1>; 2249 resets = <&gcc GCC_UFS_CARD_BCR>; 2250 reset-names = "rst"; 2251 2252 power-domains = <&gcc UFS_CARD_GDSC>; 2253 2254 iommus = <&apps_smmu 0x4a0 0x0>; 2255 dma-coherent; 2256 2257 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2258 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2259 <&gcc GCC_UFS_CARD_AHB_CLK>, 2260 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2261 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2262 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2263 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2264 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2265 clock-names = "core_clk", 2266 "bus_aggr_clk", 2267 "iface_clk", 2268 "core_clk_unipro", 2269 "ref_clk", 2270 "tx_lane0_sync_clk", 2271 "rx_lane0_sync_clk", 2272 "rx_lane1_sync_clk"; 2273 freq-table-hz = <75000000 300000000>, 2274 <0 0>, 2275 <0 0>, 2276 <75000000 300000000>, 2277 <0 0>, 2278 <0 0>, 2279 <0 0>, 2280 <0 0>; 2281 status = "disabled"; 2282 }; 2283 2284 ufs_card_phy: phy@1da7000 { 2285 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2286 reg = <0 0x01da7000 0 0x1000>; 2287 2288 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, 2289 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>; 2290 clock-names = "ref", "ref_aux"; 2291 2292 power-domains = <&gcc UFS_CARD_GDSC>; 2293 2294 resets = <&ufs_card_hc 0>; 2295 reset-names = "ufsphy"; 2296 2297 #phy-cells = <0>; 2298 2299 status = "disabled"; 2300 }; 2301 2302 tcsr_mutex: hwlock@1f40000 { 2303 compatible = "qcom,tcsr-mutex"; 2304 reg = <0x0 0x01f40000 0x0 0x20000>; 2305 #hwlock-cells = <1>; 2306 }; 2307 2308 tcsr: syscon@1fc0000 { 2309 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2310 reg = <0x0 0x01fc0000 0x0 0x30000>; 2311 }; 2312 2313 usb_0_hsphy: phy@88e5000 { 2314 compatible = "qcom,sc8280xp-usb-hs-phy", 2315 "qcom,usb-snps-hs-5nm-phy"; 2316 reg = <0 0x088e5000 0 0x400>; 2317 clocks = <&rpmhcc RPMH_CXO_CLK>; 2318 clock-names = "ref"; 2319 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2320 2321 #phy-cells = <0>; 2322 2323 status = "disabled"; 2324 }; 2325 2326 usb_2_hsphy0: phy@88e7000 { 2327 compatible = "qcom,sc8280xp-usb-hs-phy", 2328 "qcom,usb-snps-hs-5nm-phy"; 2329 reg = <0 0x088e7000 0 0x400>; 2330 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2331 clock-names = "ref"; 2332 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2333 2334 #phy-cells = <0>; 2335 2336 status = "disabled"; 2337 }; 2338 2339 usb_2_hsphy1: phy@88e8000 { 2340 compatible = "qcom,sc8280xp-usb-hs-phy", 2341 "qcom,usb-snps-hs-5nm-phy"; 2342 reg = <0 0x088e8000 0 0x400>; 2343 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2344 clock-names = "ref"; 2345 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2346 2347 #phy-cells = <0>; 2348 2349 status = "disabled"; 2350 }; 2351 2352 usb_2_hsphy2: phy@88e9000 { 2353 compatible = "qcom,sc8280xp-usb-hs-phy", 2354 "qcom,usb-snps-hs-5nm-phy"; 2355 reg = <0 0x088e9000 0 0x400>; 2356 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2357 clock-names = "ref"; 2358 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2359 2360 #phy-cells = <0>; 2361 2362 status = "disabled"; 2363 }; 2364 2365 usb_2_hsphy3: phy@88ea000 { 2366 compatible = "qcom,sc8280xp-usb-hs-phy", 2367 "qcom,usb-snps-hs-5nm-phy"; 2368 reg = <0 0x088ea000 0 0x400>; 2369 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2370 clock-names = "ref"; 2371 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2372 2373 #phy-cells = <0>; 2374 2375 status = "disabled"; 2376 }; 2377 2378 usb_2_qmpphy0: phy@88ef000 { 2379 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2380 reg = <0 0x088ef000 0 0x2000>; 2381 2382 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2383 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2384 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2385 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2386 clock-names = "aux", "ref", "com_aux", "pipe"; 2387 2388 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2389 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2390 reset-names = "phy", "phy_phy"; 2391 2392 power-domains = <&gcc USB30_MP_GDSC>; 2393 2394 #clock-cells = <0>; 2395 clock-output-names = "usb2_phy0_pipe_clk"; 2396 2397 #phy-cells = <0>; 2398 2399 status = "disabled"; 2400 }; 2401 2402 usb_2_qmpphy1: phy@88f1000 { 2403 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2404 reg = <0 0x088f1000 0 0x2000>; 2405 2406 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2407 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2408 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2409 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2410 clock-names = "aux", "ref", "com_aux", "pipe"; 2411 2412 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2413 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2414 reset-names = "phy", "phy_phy"; 2415 2416 power-domains = <&gcc USB30_MP_GDSC>; 2417 2418 #clock-cells = <0>; 2419 clock-output-names = "usb2_phy1_pipe_clk"; 2420 2421 #phy-cells = <0>; 2422 2423 status = "disabled"; 2424 }; 2425 2426 remoteproc_adsp: remoteproc@3000000 { 2427 compatible = "qcom,sc8280xp-adsp-pas"; 2428 reg = <0 0x03000000 0 0x100>; 2429 2430 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2431 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2432 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2433 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2434 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2435 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2436 interrupt-names = "wdog", "fatal", "ready", 2437 "handover", "stop-ack", "shutdown-ack"; 2438 2439 clocks = <&rpmhcc RPMH_CXO_CLK>; 2440 clock-names = "xo"; 2441 2442 power-domains = <&rpmhpd SC8280XP_LCX>, 2443 <&rpmhpd SC8280XP_LMX>; 2444 power-domain-names = "lcx", "lmx"; 2445 2446 memory-region = <&pil_adsp_mem>; 2447 2448 qcom,qmp = <&aoss_qmp>; 2449 2450 qcom,smem-states = <&smp2p_adsp_out 0>; 2451 qcom,smem-state-names = "stop"; 2452 2453 status = "disabled"; 2454 2455 remoteproc_adsp_glink: glink-edge { 2456 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2457 IPCC_MPROC_SIGNAL_GLINK_QMP 2458 IRQ_TYPE_EDGE_RISING>; 2459 mboxes = <&ipcc IPCC_CLIENT_LPASS 2460 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2461 2462 label = "lpass"; 2463 qcom,remote-pid = <2>; 2464 2465 gpr { 2466 compatible = "qcom,gpr"; 2467 qcom,glink-channels = "adsp_apps"; 2468 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2469 qcom,intents = <512 20>; 2470 #address-cells = <1>; 2471 #size-cells = <0>; 2472 2473 q6apm: service@1 { 2474 compatible = "qcom,q6apm"; 2475 reg = <GPR_APM_MODULE_IID>; 2476 #sound-dai-cells = <0>; 2477 qcom,protection-domain = "avs/audio", 2478 "msm/adsp/audio_pd"; 2479 q6apmdai: dais { 2480 compatible = "qcom,q6apm-dais"; 2481 iommus = <&apps_smmu 0x0c01 0x0>; 2482 }; 2483 2484 q6apmbedai: bedais { 2485 compatible = "qcom,q6apm-lpass-dais"; 2486 #sound-dai-cells = <1>; 2487 }; 2488 }; 2489 2490 q6prm: service@2 { 2491 compatible = "qcom,q6prm"; 2492 reg = <GPR_PRM_MODULE_IID>; 2493 qcom,protection-domain = "avs/audio", 2494 "msm/adsp/audio_pd"; 2495 q6prmcc: clock-controller { 2496 compatible = "qcom,q6prm-lpass-clocks"; 2497 #clock-cells = <2>; 2498 }; 2499 }; 2500 }; 2501 }; 2502 }; 2503 2504 rxmacro: rxmacro@3200000 { 2505 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2506 reg = <0 0x03200000 0 0x1000>; 2507 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2508 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2509 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2510 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2511 <&vamacro>; 2512 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2513 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2514 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2515 assigned-clock-rates = <19200000>, <19200000>; 2516 2517 clock-output-names = "mclk"; 2518 #clock-cells = <0>; 2519 #sound-dai-cells = <1>; 2520 2521 pinctrl-names = "default"; 2522 pinctrl-0 = <&rx_swr_default>; 2523 2524 status = "disabled"; 2525 }; 2526 2527 swr1: soundwire-controller@3210000 { 2528 compatible = "qcom,soundwire-v1.6.0"; 2529 reg = <0 0x03210000 0 0x2000>; 2530 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2531 clocks = <&rxmacro>; 2532 clock-names = "iface"; 2533 label = "RX"; 2534 2535 qcom,din-ports = <0>; 2536 qcom,dout-ports = <5>; 2537 2538 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2539 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2540 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2541 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2542 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2543 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2544 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2545 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2546 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2547 2548 #sound-dai-cells = <1>; 2549 #address-cells = <2>; 2550 #size-cells = <0>; 2551 2552 status = "disabled"; 2553 }; 2554 2555 txmacro: txmacro@3220000 { 2556 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2557 reg = <0 0x03220000 0 0x1000>; 2558 pinctrl-names = "default"; 2559 pinctrl-0 = <&tx_swr_default>; 2560 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2561 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2562 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2563 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2564 <&vamacro>; 2565 2566 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2567 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2568 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2569 assigned-clock-rates = <19200000>, <19200000>; 2570 clock-output-names = "mclk"; 2571 2572 #clock-cells = <0>; 2573 #sound-dai-cells = <1>; 2574 2575 status = "disabled"; 2576 }; 2577 2578 wsamacro: codec@3240000 { 2579 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2580 reg = <0 0x03240000 0 0x1000>; 2581 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2582 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2583 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2584 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2585 <&vamacro>; 2586 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2587 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2588 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2589 assigned-clock-rates = <19200000>, <19200000>; 2590 2591 #clock-cells = <0>; 2592 clock-output-names = "mclk"; 2593 #sound-dai-cells = <1>; 2594 2595 pinctrl-names = "default"; 2596 pinctrl-0 = <&wsa_swr_default>; 2597 2598 status = "disabled"; 2599 }; 2600 2601 swr0: soundwire-controller@3250000 { 2602 reg = <0 0x03250000 0 0x2000>; 2603 compatible = "qcom,soundwire-v1.6.0"; 2604 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2605 clocks = <&wsamacro>; 2606 clock-names = "iface"; 2607 label = "WSA"; 2608 2609 qcom,din-ports = <2>; 2610 qcom,dout-ports = <6>; 2611 2612 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2613 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2614 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2615 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2616 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2617 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2618 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2619 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2620 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2621 2622 #sound-dai-cells = <1>; 2623 #address-cells = <2>; 2624 #size-cells = <0>; 2625 2626 status = "disabled"; 2627 }; 2628 2629 swr2: soundwire-controller@3330000 { 2630 compatible = "qcom,soundwire-v1.6.0"; 2631 reg = <0 0x03330000 0 0x2000>; 2632 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2633 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2634 interrupt-names = "core", "wakeup"; 2635 2636 clocks = <&txmacro>; 2637 clock-names = "iface"; 2638 label = "TX"; 2639 #sound-dai-cells = <1>; 2640 #address-cells = <2>; 2641 #size-cells = <0>; 2642 2643 qcom,din-ports = <4>; 2644 qcom,dout-ports = <0>; 2645 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2646 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2647 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2648 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2649 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2650 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2651 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2652 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2653 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2654 2655 status = "disabled"; 2656 }; 2657 2658 vamacro: codec@3370000 { 2659 compatible = "qcom,sc8280xp-lpass-va-macro"; 2660 reg = <0 0x03370000 0 0x1000>; 2661 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2662 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2663 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2664 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2665 clock-names = "mclk", "macro", "dcodec", "npl"; 2666 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2667 assigned-clock-rates = <19200000>; 2668 2669 #clock-cells = <0>; 2670 clock-output-names = "fsgen"; 2671 #sound-dai-cells = <1>; 2672 2673 status = "disabled"; 2674 }; 2675 2676 lpass_tlmm: pinctrl@33c0000 { 2677 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2678 reg = <0 0x33c0000 0x0 0x20000>, 2679 <0 0x3550000 0x0 0x10000>; 2680 gpio-controller; 2681 #gpio-cells = <2>; 2682 gpio-ranges = <&lpass_tlmm 0 0 19>; 2683 2684 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2685 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2686 clock-names = "core", "audio"; 2687 2688 status = "disabled"; 2689 2690 tx_swr_default: tx-swr-default-state { 2691 clk-pins { 2692 pins = "gpio0"; 2693 function = "swr_tx_clk"; 2694 drive-strength = <2>; 2695 slew-rate = <1>; 2696 bias-disable; 2697 }; 2698 2699 data-pins { 2700 pins = "gpio1", "gpio2"; 2701 function = "swr_tx_data"; 2702 drive-strength = <2>; 2703 slew-rate = <1>; 2704 bias-bus-hold; 2705 }; 2706 }; 2707 2708 rx_swr_default: rx-swr-default-state { 2709 clk-pins { 2710 pins = "gpio3"; 2711 function = "swr_rx_clk"; 2712 drive-strength = <2>; 2713 slew-rate = <1>; 2714 bias-disable; 2715 }; 2716 2717 data-pins { 2718 pins = "gpio4", "gpio5"; 2719 function = "swr_rx_data"; 2720 drive-strength = <2>; 2721 slew-rate = <1>; 2722 bias-bus-hold; 2723 }; 2724 }; 2725 2726 dmic01_default: dmic01-default-state { 2727 clk-pins { 2728 pins = "gpio6"; 2729 function = "dmic1_clk"; 2730 drive-strength = <8>; 2731 output-high; 2732 }; 2733 2734 data-pins { 2735 pins = "gpio7"; 2736 function = "dmic1_data"; 2737 drive-strength = <8>; 2738 input-enable; 2739 }; 2740 }; 2741 2742 dmic01_sleep: dmic01-sleep-state { 2743 clk-pins { 2744 pins = "gpio6"; 2745 function = "dmic1_clk"; 2746 drive-strength = <2>; 2747 bias-disable; 2748 output-low; 2749 }; 2750 2751 data-pins { 2752 pins = "gpio7"; 2753 function = "dmic1_data"; 2754 drive-strength = <2>; 2755 bias-pull-down; 2756 input-enable; 2757 }; 2758 }; 2759 2760 dmic02_default: dmic02-default-state { 2761 clk-pins { 2762 pins = "gpio8"; 2763 function = "dmic2_clk"; 2764 drive-strength = <8>; 2765 output-high; 2766 }; 2767 2768 data-pins { 2769 pins = "gpio9"; 2770 function = "dmic2_data"; 2771 drive-strength = <8>; 2772 input-enable; 2773 }; 2774 }; 2775 2776 dmic02_sleep: dmic02-sleep-state { 2777 clk-pins { 2778 pins = "gpio8"; 2779 function = "dmic2_clk"; 2780 drive-strength = <2>; 2781 bias-disable; 2782 output-low; 2783 }; 2784 2785 data-pins { 2786 pins = "gpio9"; 2787 function = "dmic2_data"; 2788 drive-strength = <2>; 2789 bias-pull-down; 2790 input-enable; 2791 }; 2792 }; 2793 2794 wsa_swr_default: wsa-swr-default-state { 2795 clk-pins { 2796 pins = "gpio10"; 2797 function = "wsa_swr_clk"; 2798 drive-strength = <2>; 2799 slew-rate = <1>; 2800 bias-disable; 2801 }; 2802 2803 data-pins { 2804 pins = "gpio11"; 2805 function = "wsa_swr_data"; 2806 drive-strength = <2>; 2807 slew-rate = <1>; 2808 bias-bus-hold; 2809 }; 2810 }; 2811 2812 wsa2_swr_default: wsa2-swr-default-state { 2813 clk-pins { 2814 pins = "gpio15"; 2815 function = "wsa2_swr_clk"; 2816 drive-strength = <2>; 2817 slew-rate = <1>; 2818 bias-disable; 2819 }; 2820 2821 data-pins { 2822 pins = "gpio16"; 2823 function = "wsa2_swr_data"; 2824 drive-strength = <2>; 2825 slew-rate = <1>; 2826 bias-bus-hold; 2827 }; 2828 }; 2829 }; 2830 2831 usb_0_qmpphy: phy@88eb000 { 2832 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 2833 reg = <0 0x088eb000 0 0x4000>; 2834 2835 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2836 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 2837 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2838 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2839 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2840 2841 power-domains = <&gcc USB30_PRIM_GDSC>; 2842 2843 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2844 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 2845 reset-names = "phy", "common"; 2846 2847 #clock-cells = <1>; 2848 #phy-cells = <1>; 2849 2850 status = "disabled"; 2851 }; 2852 2853 usb_1_hsphy: phy@8902000 { 2854 compatible = "qcom,sc8280xp-usb-hs-phy", 2855 "qcom,usb-snps-hs-5nm-phy"; 2856 reg = <0 0x08902000 0 0x400>; 2857 #phy-cells = <0>; 2858 2859 clocks = <&rpmhcc RPMH_CXO_CLK>; 2860 clock-names = "ref"; 2861 2862 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2863 2864 status = "disabled"; 2865 }; 2866 2867 usb_1_qmpphy: phy@8903000 { 2868 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 2869 reg = <0 0x08903000 0 0x4000>; 2870 2871 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2872 <&gcc GCC_USB4_CLKREF_CLK>, 2873 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2874 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2875 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2876 2877 power-domains = <&gcc USB30_SEC_GDSC>; 2878 2879 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2880 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 2881 reset-names = "phy", "common"; 2882 2883 #clock-cells = <1>; 2884 #phy-cells = <1>; 2885 2886 status = "disabled"; 2887 }; 2888 2889 mdss1_dp0_phy: phy@8909a00 { 2890 compatible = "qcom,sc8280xp-dp-phy"; 2891 reg = <0 0x08909a00 0 0x19c>, 2892 <0 0x08909200 0 0xec>, 2893 <0 0x08909600 0 0xec>, 2894 <0 0x08909000 0 0x1c8>; 2895 2896 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 2897 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 2898 clock-names = "aux", "cfg_ahb"; 2899 power-domains = <&rpmhpd SC8280XP_MX>; 2900 2901 #clock-cells = <1>; 2902 #phy-cells = <0>; 2903 2904 status = "disabled"; 2905 }; 2906 2907 mdss1_dp1_phy: phy@890ca00 { 2908 compatible = "qcom,sc8280xp-dp-phy"; 2909 reg = <0 0x0890ca00 0 0x19c>, 2910 <0 0x0890c200 0 0xec>, 2911 <0 0x0890c600 0 0xec>, 2912 <0 0x0890c000 0 0x1c8>; 2913 2914 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 2915 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 2916 clock-names = "aux", "cfg_ahb"; 2917 power-domains = <&rpmhpd SC8280XP_MX>; 2918 2919 #clock-cells = <1>; 2920 #phy-cells = <0>; 2921 2922 status = "disabled"; 2923 }; 2924 2925 pmu@9091000 { 2926 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2927 reg = <0 0x09091000 0 0x1000>; 2928 2929 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2930 2931 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 2932 2933 operating-points-v2 = <&llcc_bwmon_opp_table>; 2934 2935 llcc_bwmon_opp_table: opp-table { 2936 compatible = "operating-points-v2"; 2937 2938 opp-0 { 2939 opp-peak-kBps = <762000>; 2940 }; 2941 opp-1 { 2942 opp-peak-kBps = <1720000>; 2943 }; 2944 opp-2 { 2945 opp-peak-kBps = <2086000>; 2946 }; 2947 opp-3 { 2948 opp-peak-kBps = <2597000>; 2949 }; 2950 opp-4 { 2951 opp-peak-kBps = <2929000>; 2952 }; 2953 opp-5 { 2954 opp-peak-kBps = <3879000>; 2955 }; 2956 opp-6 { 2957 opp-peak-kBps = <5161000>; 2958 }; 2959 opp-7 { 2960 opp-peak-kBps = <5931000>; 2961 }; 2962 opp-8 { 2963 opp-peak-kBps = <6515000>; 2964 }; 2965 opp-9 { 2966 opp-peak-kBps = <7980000>; 2967 }; 2968 opp-10 { 2969 opp-peak-kBps = <8136000>; 2970 }; 2971 opp-11 { 2972 opp-peak-kBps = <10437000>; 2973 }; 2974 opp-12 { 2975 opp-peak-kBps = <12191000>; 2976 }; 2977 }; 2978 }; 2979 2980 pmu@90b6400 { 2981 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 2982 reg = <0 0x090b6400 0 0x600>; 2983 2984 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2985 2986 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 2987 operating-points-v2 = <&cpu_bwmon_opp_table>; 2988 2989 cpu_bwmon_opp_table: opp-table { 2990 compatible = "operating-points-v2"; 2991 2992 opp-0 { 2993 opp-peak-kBps = <2288000>; 2994 }; 2995 opp-1 { 2996 opp-peak-kBps = <4577000>; 2997 }; 2998 opp-2 { 2999 opp-peak-kBps = <7110000>; 3000 }; 3001 opp-3 { 3002 opp-peak-kBps = <9155000>; 3003 }; 3004 opp-4 { 3005 opp-peak-kBps = <12298000>; 3006 }; 3007 opp-5 { 3008 opp-peak-kBps = <14236000>; 3009 }; 3010 opp-6 { 3011 opp-peak-kBps = <15258001>; 3012 }; 3013 }; 3014 }; 3015 3016 system-cache-controller@9200000 { 3017 compatible = "qcom,sc8280xp-llcc"; 3018 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3019 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3020 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3021 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3022 <0 0x09600000 0 0x58000>; 3023 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3024 "llcc3_base", "llcc4_base", "llcc5_base", 3025 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3026 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3027 }; 3028 3029 usb_0: usb@a6f8800 { 3030 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3031 reg = <0 0x0a6f8800 0 0x400>; 3032 #address-cells = <2>; 3033 #size-cells = <2>; 3034 ranges; 3035 3036 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3037 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3038 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3039 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3040 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3041 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3042 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3043 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3044 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3045 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3046 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3047 3048 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3049 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3050 assigned-clock-rates = <19200000>, <200000000>; 3051 3052 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3053 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3054 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3055 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3056 interrupt-names = "pwr_event", 3057 "dp_hs_phy_irq", 3058 "dm_hs_phy_irq", 3059 "ss_phy_irq"; 3060 3061 power-domains = <&gcc USB30_PRIM_GDSC>; 3062 required-opps = <&rpmhpd_opp_nom>; 3063 3064 resets = <&gcc GCC_USB30_PRIM_BCR>; 3065 3066 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3067 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3068 interconnect-names = "usb-ddr", "apps-usb"; 3069 3070 wakeup-source; 3071 3072 status = "disabled"; 3073 3074 usb_0_dwc3: usb@a600000 { 3075 compatible = "snps,dwc3"; 3076 reg = <0 0x0a600000 0 0xcd00>; 3077 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3078 iommus = <&apps_smmu 0x820 0x0>; 3079 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3080 phy-names = "usb2-phy", "usb3-phy"; 3081 3082 port { 3083 usb_0_role_switch: endpoint { 3084 }; 3085 }; 3086 }; 3087 }; 3088 3089 usb_1: usb@a8f8800 { 3090 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3091 reg = <0 0x0a8f8800 0 0x400>; 3092 #address-cells = <2>; 3093 #size-cells = <2>; 3094 ranges; 3095 3096 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3097 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3098 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3099 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3100 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3101 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3102 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3103 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3104 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3105 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3106 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3107 3108 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3109 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3110 assigned-clock-rates = <19200000>, <200000000>; 3111 3112 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3113 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3114 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3115 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3116 interrupt-names = "pwr_event", 3117 "dp_hs_phy_irq", 3118 "dm_hs_phy_irq", 3119 "ss_phy_irq"; 3120 3121 power-domains = <&gcc USB30_SEC_GDSC>; 3122 required-opps = <&rpmhpd_opp_nom>; 3123 3124 resets = <&gcc GCC_USB30_SEC_BCR>; 3125 3126 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3127 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3128 interconnect-names = "usb-ddr", "apps-usb"; 3129 3130 wakeup-source; 3131 3132 status = "disabled"; 3133 3134 usb_1_dwc3: usb@a800000 { 3135 compatible = "snps,dwc3"; 3136 reg = <0 0x0a800000 0 0xcd00>; 3137 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3138 iommus = <&apps_smmu 0x860 0x0>; 3139 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3140 phy-names = "usb2-phy", "usb3-phy"; 3141 3142 port { 3143 usb_1_role_switch: endpoint { 3144 }; 3145 }; 3146 }; 3147 }; 3148 3149 mdss0: display-subsystem@ae00000 { 3150 compatible = "qcom,sc8280xp-mdss"; 3151 reg = <0 0x0ae00000 0 0x1000>; 3152 reg-names = "mdss"; 3153 3154 clocks = <&gcc GCC_DISP_AHB_CLK>, 3155 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3156 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3157 clock-names = "iface", 3158 "ahb", 3159 "core"; 3160 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3161 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3162 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3163 interconnect-names = "mdp0-mem", "mdp1-mem"; 3164 iommus = <&apps_smmu 0x1000 0x402>; 3165 power-domains = <&dispcc0 MDSS_GDSC>; 3166 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3167 3168 interrupt-controller; 3169 #interrupt-cells = <1>; 3170 #address-cells = <2>; 3171 #size-cells = <2>; 3172 ranges; 3173 3174 status = "disabled"; 3175 3176 mdss0_mdp: display-controller@ae01000 { 3177 compatible = "qcom,sc8280xp-dpu"; 3178 reg = <0 0x0ae01000 0 0x8f000>, 3179 <0 0x0aeb0000 0 0x2008>; 3180 reg-names = "mdp", "vbif"; 3181 3182 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3183 <&gcc GCC_DISP_SF_AXI_CLK>, 3184 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3185 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3186 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3187 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3188 clock-names = "bus", 3189 "nrt_bus", 3190 "iface", 3191 "lut", 3192 "core", 3193 "vsync"; 3194 interrupt-parent = <&mdss0>; 3195 interrupts = <0>; 3196 power-domains = <&rpmhpd SC8280XP_MMCX>; 3197 3198 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3199 assigned-clock-rates = <19200000>; 3200 operating-points-v2 = <&mdss0_mdp_opp_table>; 3201 3202 ports { 3203 #address-cells = <1>; 3204 #size-cells = <0>; 3205 3206 port@0 { 3207 reg = <0>; 3208 mdss0_intf0_out: endpoint { 3209 remote-endpoint = <&mdss0_dp0_in>; 3210 }; 3211 }; 3212 3213 port@4 { 3214 reg = <4>; 3215 mdss0_intf4_out: endpoint { 3216 remote-endpoint = <&mdss0_dp1_in>; 3217 }; 3218 }; 3219 3220 port@5 { 3221 reg = <5>; 3222 mdss0_intf5_out: endpoint { 3223 remote-endpoint = <&mdss0_dp3_in>; 3224 }; 3225 }; 3226 3227 port@6 { 3228 reg = <6>; 3229 mdss0_intf6_out: endpoint { 3230 remote-endpoint = <&mdss0_dp2_in>; 3231 }; 3232 }; 3233 }; 3234 3235 mdss0_mdp_opp_table: opp-table { 3236 compatible = "operating-points-v2"; 3237 3238 opp-200000000 { 3239 opp-hz = /bits/ 64 <200000000>; 3240 required-opps = <&rpmhpd_opp_low_svs>; 3241 }; 3242 3243 opp-300000000 { 3244 opp-hz = /bits/ 64 <300000000>; 3245 required-opps = <&rpmhpd_opp_svs>; 3246 }; 3247 3248 opp-375000000 { 3249 opp-hz = /bits/ 64 <375000000>; 3250 required-opps = <&rpmhpd_opp_svs_l1>; 3251 }; 3252 3253 opp-500000000 { 3254 opp-hz = /bits/ 64 <500000000>; 3255 required-opps = <&rpmhpd_opp_nom>; 3256 }; 3257 opp-600000000 { 3258 opp-hz = /bits/ 64 <600000000>; 3259 required-opps = <&rpmhpd_opp_turbo_l1>; 3260 }; 3261 }; 3262 }; 3263 3264 mdss0_dp0: displayport-controller@ae90000 { 3265 compatible = "qcom,sc8280xp-dp"; 3266 reg = <0 0xae90000 0 0x200>, 3267 <0 0xae90200 0 0x200>, 3268 <0 0xae90400 0 0x600>, 3269 <0 0xae91000 0 0x400>, 3270 <0 0xae91400 0 0x400>; 3271 interrupt-parent = <&mdss0>; 3272 interrupts = <12>; 3273 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3274 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3275 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 3276 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3277 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3278 clock-names = "core_iface", "core_aux", 3279 "ctrl_link", 3280 "ctrl_link_iface", 3281 "stream_pixel"; 3282 3283 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3284 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3285 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3286 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3287 3288 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 3289 phy-names = "dp"; 3290 3291 #sound-dai-cells = <0>; 3292 3293 operating-points-v2 = <&mdss0_dp0_opp_table>; 3294 power-domains = <&rpmhpd SC8280XP_MMCX>; 3295 3296 status = "disabled"; 3297 3298 ports { 3299 #address-cells = <1>; 3300 #size-cells = <0>; 3301 3302 port@0 { 3303 reg = <0>; 3304 3305 mdss0_dp0_in: endpoint { 3306 remote-endpoint = <&mdss0_intf0_out>; 3307 }; 3308 }; 3309 3310 port@1 { 3311 reg = <1>; 3312 3313 mdss0_dp0_out: endpoint { 3314 }; 3315 }; 3316 }; 3317 3318 mdss0_dp0_opp_table: opp-table { 3319 compatible = "operating-points-v2"; 3320 3321 opp-160000000 { 3322 opp-hz = /bits/ 64 <160000000>; 3323 required-opps = <&rpmhpd_opp_low_svs>; 3324 }; 3325 3326 opp-270000000 { 3327 opp-hz = /bits/ 64 <270000000>; 3328 required-opps = <&rpmhpd_opp_svs>; 3329 }; 3330 3331 opp-540000000 { 3332 opp-hz = /bits/ 64 <540000000>; 3333 required-opps = <&rpmhpd_opp_svs_l1>; 3334 }; 3335 3336 opp-810000000 { 3337 opp-hz = /bits/ 64 <810000000>; 3338 required-opps = <&rpmhpd_opp_nom>; 3339 }; 3340 }; 3341 }; 3342 3343 mdss0_dp1: displayport-controller@ae98000 { 3344 compatible = "qcom,sc8280xp-dp"; 3345 reg = <0 0xae98000 0 0x200>, 3346 <0 0xae98200 0 0x200>, 3347 <0 0xae98400 0 0x600>, 3348 <0 0xae99000 0 0x400>, 3349 <0 0xae99400 0 0x400>; 3350 interrupt-parent = <&mdss0>; 3351 interrupts = <13>; 3352 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3353 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3354 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 3355 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3356 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3357 clock-names = "core_iface", "core_aux", 3358 "ctrl_link", 3359 "ctrl_link_iface", "stream_pixel"; 3360 3361 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3362 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3363 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3364 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3365 3366 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3367 phy-names = "dp"; 3368 3369 #sound-dai-cells = <0>; 3370 3371 operating-points-v2 = <&mdss0_dp1_opp_table>; 3372 power-domains = <&rpmhpd SC8280XP_MMCX>; 3373 3374 status = "disabled"; 3375 3376 ports { 3377 #address-cells = <1>; 3378 #size-cells = <0>; 3379 3380 port@0 { 3381 reg = <0>; 3382 3383 mdss0_dp1_in: endpoint { 3384 remote-endpoint = <&mdss0_intf4_out>; 3385 }; 3386 }; 3387 3388 port@1 { 3389 reg = <1>; 3390 3391 mdss0_dp1_out: endpoint { 3392 }; 3393 }; 3394 }; 3395 3396 mdss0_dp1_opp_table: opp-table { 3397 compatible = "operating-points-v2"; 3398 3399 opp-160000000 { 3400 opp-hz = /bits/ 64 <160000000>; 3401 required-opps = <&rpmhpd_opp_low_svs>; 3402 }; 3403 3404 opp-270000000 { 3405 opp-hz = /bits/ 64 <270000000>; 3406 required-opps = <&rpmhpd_opp_svs>; 3407 }; 3408 3409 opp-540000000 { 3410 opp-hz = /bits/ 64 <540000000>; 3411 required-opps = <&rpmhpd_opp_svs_l1>; 3412 }; 3413 3414 opp-810000000 { 3415 opp-hz = /bits/ 64 <810000000>; 3416 required-opps = <&rpmhpd_opp_nom>; 3417 }; 3418 }; 3419 }; 3420 3421 mdss0_dp2: displayport-controller@ae9a000 { 3422 compatible = "qcom,sc8280xp-dp"; 3423 reg = <0 0xae9a000 0 0x200>, 3424 <0 0xae9a200 0 0x200>, 3425 <0 0xae9a400 0 0x600>, 3426 <0 0xae9b000 0 0x400>, 3427 <0 0xae9b400 0 0x400>; 3428 3429 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3430 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3431 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 3432 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3433 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3434 clock-names = "core_iface", "core_aux", 3435 "ctrl_link", 3436 "ctrl_link_iface", "stream_pixel"; 3437 interrupt-parent = <&mdss0>; 3438 interrupts = <14>; 3439 phys = <&mdss0_dp2_phy>; 3440 phy-names = "dp"; 3441 power-domains = <&rpmhpd SC8280XP_MMCX>; 3442 3443 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3444 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3445 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 3446 operating-points-v2 = <&mdss0_dp2_opp_table>; 3447 3448 #sound-dai-cells = <0>; 3449 3450 status = "disabled"; 3451 3452 ports { 3453 #address-cells = <1>; 3454 #size-cells = <0>; 3455 3456 port@0 { 3457 reg = <0>; 3458 mdss0_dp2_in: endpoint { 3459 remote-endpoint = <&mdss0_intf6_out>; 3460 }; 3461 }; 3462 3463 port@1 { 3464 reg = <1>; 3465 }; 3466 }; 3467 3468 mdss0_dp2_opp_table: opp-table { 3469 compatible = "operating-points-v2"; 3470 3471 opp-160000000 { 3472 opp-hz = /bits/ 64 <160000000>; 3473 required-opps = <&rpmhpd_opp_low_svs>; 3474 }; 3475 3476 opp-270000000 { 3477 opp-hz = /bits/ 64 <270000000>; 3478 required-opps = <&rpmhpd_opp_svs>; 3479 }; 3480 3481 opp-540000000 { 3482 opp-hz = /bits/ 64 <540000000>; 3483 required-opps = <&rpmhpd_opp_svs_l1>; 3484 }; 3485 3486 opp-810000000 { 3487 opp-hz = /bits/ 64 <810000000>; 3488 required-opps = <&rpmhpd_opp_nom>; 3489 }; 3490 }; 3491 }; 3492 3493 mdss0_dp3: displayport-controller@aea0000 { 3494 compatible = "qcom,sc8280xp-dp"; 3495 reg = <0 0xaea0000 0 0x200>, 3496 <0 0xaea0200 0 0x200>, 3497 <0 0xaea0400 0 0x600>, 3498 <0 0xaea1000 0 0x400>, 3499 <0 0xaea1400 0 0x400>; 3500 3501 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3502 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3503 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 3504 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 3505 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 3506 clock-names = "core_iface", "core_aux", 3507 "ctrl_link", 3508 "ctrl_link_iface", "stream_pixel"; 3509 interrupt-parent = <&mdss0>; 3510 interrupts = <15>; 3511 phys = <&mdss0_dp3_phy>; 3512 phy-names = "dp"; 3513 power-domains = <&rpmhpd SC8280XP_MMCX>; 3514 3515 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 3516 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 3517 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 3518 operating-points-v2 = <&mdss0_dp3_opp_table>; 3519 3520 #sound-dai-cells = <0>; 3521 3522 status = "disabled"; 3523 3524 ports { 3525 #address-cells = <1>; 3526 #size-cells = <0>; 3527 3528 port@0 { 3529 reg = <0>; 3530 mdss0_dp3_in: endpoint { 3531 remote-endpoint = <&mdss0_intf5_out>; 3532 }; 3533 }; 3534 3535 port@1 { 3536 reg = <1>; 3537 }; 3538 }; 3539 3540 mdss0_dp3_opp_table: opp-table { 3541 compatible = "operating-points-v2"; 3542 3543 opp-160000000 { 3544 opp-hz = /bits/ 64 <160000000>; 3545 required-opps = <&rpmhpd_opp_low_svs>; 3546 }; 3547 3548 opp-270000000 { 3549 opp-hz = /bits/ 64 <270000000>; 3550 required-opps = <&rpmhpd_opp_svs>; 3551 }; 3552 3553 opp-540000000 { 3554 opp-hz = /bits/ 64 <540000000>; 3555 required-opps = <&rpmhpd_opp_svs_l1>; 3556 }; 3557 3558 opp-810000000 { 3559 opp-hz = /bits/ 64 <810000000>; 3560 required-opps = <&rpmhpd_opp_nom>; 3561 }; 3562 }; 3563 }; 3564 }; 3565 3566 mdss0_dp2_phy: phy@aec2a00 { 3567 compatible = "qcom,sc8280xp-dp-phy"; 3568 reg = <0 0x0aec2a00 0 0x19c>, 3569 <0 0x0aec2200 0 0xec>, 3570 <0 0x0aec2600 0 0xec>, 3571 <0 0x0aec2000 0 0x1c8>; 3572 3573 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 3574 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3575 clock-names = "aux", "cfg_ahb"; 3576 power-domains = <&rpmhpd SC8280XP_MX>; 3577 3578 #clock-cells = <1>; 3579 #phy-cells = <0>; 3580 3581 status = "disabled"; 3582 }; 3583 3584 mdss0_dp3_phy: phy@aec5a00 { 3585 compatible = "qcom,sc8280xp-dp-phy"; 3586 reg = <0 0x0aec5a00 0 0x19c>, 3587 <0 0x0aec5200 0 0xec>, 3588 <0 0x0aec5600 0 0xec>, 3589 <0 0x0aec5000 0 0x1c8>; 3590 3591 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 3592 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 3593 clock-names = "aux", "cfg_ahb"; 3594 power-domains = <&rpmhpd SC8280XP_MX>; 3595 3596 #clock-cells = <1>; 3597 #phy-cells = <0>; 3598 3599 status = "disabled"; 3600 }; 3601 3602 dispcc0: clock-controller@af00000 { 3603 compatible = "qcom,sc8280xp-dispcc0"; 3604 reg = <0 0x0af00000 0 0x20000>; 3605 3606 clocks = <&gcc GCC_DISP_AHB_CLK>, 3607 <&rpmhcc RPMH_CXO_CLK>, 3608 <&sleep_clk>, 3609 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3610 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3611 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3612 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3613 <&mdss0_dp2_phy 0>, 3614 <&mdss0_dp2_phy 1>, 3615 <&mdss0_dp3_phy 0>, 3616 <&mdss0_dp3_phy 1>, 3617 <0>, 3618 <0>, 3619 <0>, 3620 <0>; 3621 power-domains = <&rpmhpd SC8280XP_MMCX>; 3622 3623 #clock-cells = <1>; 3624 #power-domain-cells = <1>; 3625 #reset-cells = <1>; 3626 3627 status = "disabled"; 3628 }; 3629 3630 pdc: interrupt-controller@b220000 { 3631 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 3632 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3633 qcom,pdc-ranges = <0 480 40>, 3634 <40 140 14>, 3635 <54 263 1>, 3636 <55 306 4>, 3637 <59 312 3>, 3638 <62 374 2>, 3639 <64 434 2>, 3640 <66 438 3>, 3641 <69 86 1>, 3642 <70 520 54>, 3643 <124 609 28>, 3644 <159 638 1>, 3645 <160 720 8>, 3646 <168 801 1>, 3647 <169 728 30>, 3648 <199 416 2>, 3649 <201 449 1>, 3650 <202 89 1>, 3651 <203 451 1>, 3652 <204 462 1>, 3653 <205 264 1>, 3654 <206 579 1>, 3655 <207 653 1>, 3656 <208 656 1>, 3657 <209 659 1>, 3658 <210 122 1>, 3659 <211 699 1>, 3660 <212 705 1>, 3661 <213 450 1>, 3662 <214 643 1>, 3663 <216 646 5>, 3664 <221 390 5>, 3665 <226 700 3>, 3666 <229 240 3>, 3667 <232 269 1>, 3668 <233 377 1>, 3669 <234 372 1>, 3670 <235 138 1>, 3671 <236 857 1>, 3672 <237 860 1>, 3673 <238 137 1>, 3674 <239 668 1>, 3675 <240 366 1>, 3676 <241 949 1>, 3677 <242 815 5>, 3678 <247 769 1>, 3679 <248 768 1>, 3680 <249 663 1>, 3681 <250 799 2>, 3682 <252 798 1>, 3683 <253 765 1>, 3684 <254 763 1>, 3685 <255 454 1>, 3686 <258 139 1>, 3687 <259 786 2>, 3688 <261 370 2>, 3689 <263 158 2>; 3690 #interrupt-cells = <2>; 3691 interrupt-parent = <&intc>; 3692 interrupt-controller; 3693 }; 3694 3695 tsens0: thermal-sensor@c263000 { 3696 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3697 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3698 <0 0x0c222000 0 0x8>; /* SROT */ 3699 #qcom,sensors = <14>; 3700 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3701 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3702 interrupt-names = "uplow", "critical"; 3703 #thermal-sensor-cells = <1>; 3704 }; 3705 3706 tsens1: thermal-sensor@c265000 { 3707 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 3708 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3709 <0 0x0c223000 0 0x8>; /* SROT */ 3710 #qcom,sensors = <16>; 3711 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 3712 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 3713 interrupt-names = "uplow", "critical"; 3714 #thermal-sensor-cells = <1>; 3715 }; 3716 3717 aoss_qmp: power-management@c300000 { 3718 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 3719 reg = <0 0x0c300000 0 0x400>; 3720 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 3721 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3722 3723 #clock-cells = <0>; 3724 }; 3725 3726 sram@c3f0000 { 3727 compatible = "qcom,rpmh-stats"; 3728 reg = <0 0x0c3f0000 0 0x400>; 3729 }; 3730 3731 spmi_bus: spmi@c440000 { 3732 compatible = "qcom,spmi-pmic-arb"; 3733 reg = <0 0x0c440000 0 0x1100>, 3734 <0 0x0c600000 0 0x2000000>, 3735 <0 0x0e600000 0 0x100000>, 3736 <0 0x0e700000 0 0xa0000>, 3737 <0 0x0c40a000 0 0x26000>; 3738 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3739 interrupt-names = "periph_irq"; 3740 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3741 qcom,ee = <0>; 3742 qcom,channel = <0>; 3743 #address-cells = <2>; 3744 #size-cells = <0>; 3745 interrupt-controller; 3746 #interrupt-cells = <4>; 3747 }; 3748 3749 tlmm: pinctrl@f100000 { 3750 compatible = "qcom,sc8280xp-tlmm"; 3751 reg = <0 0x0f100000 0 0x300000>; 3752 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3753 gpio-controller; 3754 #gpio-cells = <2>; 3755 interrupt-controller; 3756 #interrupt-cells = <2>; 3757 gpio-ranges = <&tlmm 0 0 230>; 3758 }; 3759 3760 apps_smmu: iommu@15000000 { 3761 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 3762 reg = <0 0x15000000 0 0x100000>; 3763 #iommu-cells = <2>; 3764 #global-interrupts = <2>; 3765 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 3895 }; 3896 3897 intc: interrupt-controller@17a00000 { 3898 compatible = "arm,gic-v3"; 3899 interrupt-controller; 3900 #interrupt-cells = <3>; 3901 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3902 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3903 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3904 #redistributor-regions = <1>; 3905 redistributor-stride = <0 0x20000>; 3906 3907 #address-cells = <2>; 3908 #size-cells = <2>; 3909 ranges; 3910 3911 gic-its@17a40000 { 3912 compatible = "arm,gic-v3-its"; 3913 reg = <0 0x17a40000 0 0x20000>; 3914 msi-controller; 3915 #msi-cells = <1>; 3916 }; 3917 }; 3918 3919 watchdog@17c10000 { 3920 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 3921 reg = <0 0x17c10000 0 0x1000>; 3922 clocks = <&sleep_clk>; 3923 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3924 }; 3925 3926 timer@17c20000 { 3927 compatible = "arm,armv7-timer-mem"; 3928 reg = <0x0 0x17c20000 0x0 0x1000>; 3929 #address-cells = <1>; 3930 #size-cells = <1>; 3931 ranges = <0x0 0x0 0x0 0x20000000>; 3932 3933 frame@17c21000 { 3934 frame-number = <0>; 3935 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3937 reg = <0x17c21000 0x1000>, 3938 <0x17c22000 0x1000>; 3939 }; 3940 3941 frame@17c23000 { 3942 frame-number = <1>; 3943 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3944 reg = <0x17c23000 0x1000>; 3945 status = "disabled"; 3946 }; 3947 3948 frame@17c25000 { 3949 frame-number = <2>; 3950 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3951 reg = <0x17c25000 0x1000>; 3952 status = "disabled"; 3953 }; 3954 3955 frame@17c27000 { 3956 frame-number = <3>; 3957 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3958 reg = <0x17c26000 0x1000>; 3959 status = "disabled"; 3960 }; 3961 3962 frame@17c29000 { 3963 frame-number = <4>; 3964 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3965 reg = <0x17c29000 0x1000>; 3966 status = "disabled"; 3967 }; 3968 3969 frame@17c2b000 { 3970 frame-number = <5>; 3971 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3972 reg = <0x17c2b000 0x1000>; 3973 status = "disabled"; 3974 }; 3975 3976 frame@17c2d000 { 3977 frame-number = <6>; 3978 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3979 reg = <0x17c2d000 0x1000>; 3980 status = "disabled"; 3981 }; 3982 }; 3983 3984 apps_rsc: rsc@18200000 { 3985 compatible = "qcom,rpmh-rsc"; 3986 reg = <0x0 0x18200000 0x0 0x10000>, 3987 <0x0 0x18210000 0x0 0x10000>, 3988 <0x0 0x18220000 0x0 0x10000>; 3989 reg-names = "drv-0", "drv-1", "drv-2"; 3990 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3991 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3992 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3993 qcom,tcs-offset = <0xd00>; 3994 qcom,drv-id = <2>; 3995 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3996 <WAKE_TCS 3>, <CONTROL_TCS 1>; 3997 label = "apps_rsc"; 3998 power-domains = <&CLUSTER_PD>; 3999 4000 apps_bcm_voter: bcm-voter { 4001 compatible = "qcom,bcm-voter"; 4002 }; 4003 4004 rpmhcc: clock-controller { 4005 compatible = "qcom,sc8280xp-rpmh-clk"; 4006 #clock-cells = <1>; 4007 clock-names = "xo"; 4008 clocks = <&xo_board_clk>; 4009 }; 4010 4011 rpmhpd: power-controller { 4012 compatible = "qcom,sc8280xp-rpmhpd"; 4013 #power-domain-cells = <1>; 4014 operating-points-v2 = <&rpmhpd_opp_table>; 4015 4016 rpmhpd_opp_table: opp-table { 4017 compatible = "operating-points-v2"; 4018 4019 rpmhpd_opp_ret: opp1 { 4020 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4021 }; 4022 4023 rpmhpd_opp_min_svs: opp2 { 4024 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4025 }; 4026 4027 rpmhpd_opp_low_svs: opp3 { 4028 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4029 }; 4030 4031 rpmhpd_opp_svs: opp4 { 4032 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4033 }; 4034 4035 rpmhpd_opp_svs_l1: opp5 { 4036 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4037 }; 4038 4039 rpmhpd_opp_nom: opp6 { 4040 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4041 }; 4042 4043 rpmhpd_opp_nom_l1: opp7 { 4044 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4045 }; 4046 4047 rpmhpd_opp_nom_l2: opp8 { 4048 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4049 }; 4050 4051 rpmhpd_opp_turbo: opp9 { 4052 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4053 }; 4054 4055 rpmhpd_opp_turbo_l1: opp10 { 4056 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4057 }; 4058 }; 4059 }; 4060 }; 4061 4062 epss_l3: interconnect@18590000 { 4063 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4064 reg = <0 0x18590000 0 0x1000>; 4065 4066 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4067 clock-names = "xo", "alternate"; 4068 4069 #interconnect-cells = <1>; 4070 }; 4071 4072 cpufreq_hw: cpufreq@18591000 { 4073 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4074 reg = <0 0x18591000 0 0x1000>, 4075 <0 0x18592000 0 0x1000>; 4076 reg-names = "freq-domain0", "freq-domain1"; 4077 4078 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4079 clock-names = "xo", "alternate"; 4080 4081 #freq-domain-cells = <1>; 4082 #clock-cells = <1>; 4083 }; 4084 4085 remoteproc_nsp0: remoteproc@1b300000 { 4086 compatible = "qcom,sc8280xp-nsp0-pas"; 4087 reg = <0 0x1b300000 0 0x100>; 4088 4089 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 4090 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4091 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4092 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4093 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4094 interrupt-names = "wdog", "fatal", "ready", 4095 "handover", "stop-ack"; 4096 4097 clocks = <&rpmhcc RPMH_CXO_CLK>; 4098 clock-names = "xo"; 4099 4100 power-domains = <&rpmhpd SC8280XP_NSP>; 4101 power-domain-names = "nsp"; 4102 4103 memory-region = <&pil_nsp0_mem>; 4104 4105 qcom,smem-states = <&smp2p_nsp0_out 0>; 4106 qcom,smem-state-names = "stop"; 4107 4108 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4109 4110 status = "disabled"; 4111 4112 glink-edge { 4113 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4114 IPCC_MPROC_SIGNAL_GLINK_QMP 4115 IRQ_TYPE_EDGE_RISING>; 4116 mboxes = <&ipcc IPCC_CLIENT_CDSP 4117 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4118 4119 label = "nsp0"; 4120 qcom,remote-pid = <5>; 4121 4122 fastrpc { 4123 compatible = "qcom,fastrpc"; 4124 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4125 label = "cdsp"; 4126 #address-cells = <1>; 4127 #size-cells = <0>; 4128 4129 compute-cb@1 { 4130 compatible = "qcom,fastrpc-compute-cb"; 4131 reg = <1>; 4132 iommus = <&apps_smmu 0x3181 0x0420>; 4133 }; 4134 4135 compute-cb@2 { 4136 compatible = "qcom,fastrpc-compute-cb"; 4137 reg = <2>; 4138 iommus = <&apps_smmu 0x3182 0x0420>; 4139 }; 4140 4141 compute-cb@3 { 4142 compatible = "qcom,fastrpc-compute-cb"; 4143 reg = <3>; 4144 iommus = <&apps_smmu 0x3183 0x0420>; 4145 }; 4146 4147 compute-cb@4 { 4148 compatible = "qcom,fastrpc-compute-cb"; 4149 reg = <4>; 4150 iommus = <&apps_smmu 0x3184 0x0420>; 4151 }; 4152 4153 compute-cb@5 { 4154 compatible = "qcom,fastrpc-compute-cb"; 4155 reg = <5>; 4156 iommus = <&apps_smmu 0x3185 0x0420>; 4157 }; 4158 4159 compute-cb@6 { 4160 compatible = "qcom,fastrpc-compute-cb"; 4161 reg = <6>; 4162 iommus = <&apps_smmu 0x3186 0x0420>; 4163 }; 4164 4165 compute-cb@7 { 4166 compatible = "qcom,fastrpc-compute-cb"; 4167 reg = <7>; 4168 iommus = <&apps_smmu 0x3187 0x0420>; 4169 }; 4170 4171 compute-cb@8 { 4172 compatible = "qcom,fastrpc-compute-cb"; 4173 reg = <8>; 4174 iommus = <&apps_smmu 0x3188 0x0420>; 4175 }; 4176 4177 compute-cb@9 { 4178 compatible = "qcom,fastrpc-compute-cb"; 4179 reg = <9>; 4180 iommus = <&apps_smmu 0x318b 0x0420>; 4181 }; 4182 4183 compute-cb@10 { 4184 compatible = "qcom,fastrpc-compute-cb"; 4185 reg = <10>; 4186 iommus = <&apps_smmu 0x318b 0x0420>; 4187 }; 4188 4189 compute-cb@11 { 4190 compatible = "qcom,fastrpc-compute-cb"; 4191 reg = <11>; 4192 iommus = <&apps_smmu 0x318c 0x0420>; 4193 }; 4194 4195 compute-cb@12 { 4196 compatible = "qcom,fastrpc-compute-cb"; 4197 reg = <12>; 4198 iommus = <&apps_smmu 0x318d 0x0420>; 4199 }; 4200 4201 compute-cb@13 { 4202 compatible = "qcom,fastrpc-compute-cb"; 4203 reg = <13>; 4204 iommus = <&apps_smmu 0x318e 0x0420>; 4205 }; 4206 4207 compute-cb@14 { 4208 compatible = "qcom,fastrpc-compute-cb"; 4209 reg = <14>; 4210 iommus = <&apps_smmu 0x318f 0x0420>; 4211 }; 4212 }; 4213 }; 4214 }; 4215 4216 remoteproc_nsp1: remoteproc@21300000 { 4217 compatible = "qcom,sc8280xp-nsp1-pas"; 4218 reg = <0 0x21300000 0 0x100>; 4219 4220 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4221 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4222 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4223 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4224 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4225 interrupt-names = "wdog", "fatal", "ready", 4226 "handover", "stop-ack"; 4227 4228 clocks = <&rpmhcc RPMH_CXO_CLK>; 4229 clock-names = "xo"; 4230 4231 power-domains = <&rpmhpd SC8280XP_NSP>; 4232 power-domain-names = "nsp"; 4233 4234 memory-region = <&pil_nsp1_mem>; 4235 4236 qcom,smem-states = <&smp2p_nsp1_out 0>; 4237 qcom,smem-state-names = "stop"; 4238 4239 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 4240 4241 status = "disabled"; 4242 4243 glink-edge { 4244 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4245 IPCC_MPROC_SIGNAL_GLINK_QMP 4246 IRQ_TYPE_EDGE_RISING>; 4247 mboxes = <&ipcc IPCC_CLIENT_NSP1 4248 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4249 4250 label = "nsp1"; 4251 qcom,remote-pid = <12>; 4252 }; 4253 }; 4254 4255 mdss1: display-subsystem@22000000 { 4256 compatible = "qcom,sc8280xp-mdss"; 4257 reg = <0 0x22000000 0 0x1000>; 4258 reg-names = "mdss"; 4259 4260 clocks = <&gcc GCC_DISP_AHB_CLK>, 4261 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4262 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 4263 clock-names = "iface", 4264 "ahb", 4265 "core"; 4266 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 4267 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 4268 interconnect-names = "mdp0-mem", "mdp1-mem"; 4269 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4270 4271 iommus = <&apps_smmu 0x1800 0x402>; 4272 power-domains = <&dispcc1 MDSS_GDSC>; 4273 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 4274 4275 interrupt-controller; 4276 #interrupt-cells = <1>; 4277 #address-cells = <2>; 4278 #size-cells = <2>; 4279 ranges; 4280 4281 status = "disabled"; 4282 4283 mdss1_mdp: display-controller@22001000 { 4284 compatible = "qcom,sc8280xp-dpu"; 4285 reg = <0 0x22001000 0 0x8f000>, 4286 <0 0x220b0000 0 0x2008>; 4287 reg-names = "mdp", "vbif"; 4288 4289 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4290 <&gcc GCC_DISP_SF_AXI_CLK>, 4291 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4292 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 4293 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 4294 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4295 clock-names = "bus", 4296 "nrt_bus", 4297 "iface", 4298 "lut", 4299 "core", 4300 "vsync"; 4301 interrupt-parent = <&mdss1>; 4302 interrupts = <0>; 4303 power-domains = <&rpmhpd SC8280XP_MMCX>; 4304 4305 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 4306 assigned-clock-rates = <19200000>; 4307 operating-points-v2 = <&mdss1_mdp_opp_table>; 4308 4309 ports { 4310 #address-cells = <1>; 4311 #size-cells = <0>; 4312 4313 port@0 { 4314 reg = <0>; 4315 mdss1_intf0_out: endpoint { 4316 remote-endpoint = <&mdss1_dp0_in>; 4317 }; 4318 }; 4319 4320 port@4 { 4321 reg = <4>; 4322 mdss1_intf4_out: endpoint { 4323 remote-endpoint = <&mdss1_dp1_in>; 4324 }; 4325 }; 4326 4327 port@5 { 4328 reg = <5>; 4329 mdss1_intf5_out: endpoint { 4330 remote-endpoint = <&mdss1_dp3_in>; 4331 }; 4332 }; 4333 4334 port@6 { 4335 reg = <6>; 4336 mdss1_intf6_out: endpoint { 4337 remote-endpoint = <&mdss1_dp2_in>; 4338 }; 4339 }; 4340 }; 4341 4342 mdss1_mdp_opp_table: opp-table { 4343 compatible = "operating-points-v2"; 4344 4345 opp-200000000 { 4346 opp-hz = /bits/ 64 <200000000>; 4347 required-opps = <&rpmhpd_opp_low_svs>; 4348 }; 4349 4350 opp-300000000 { 4351 opp-hz = /bits/ 64 <300000000>; 4352 required-opps = <&rpmhpd_opp_svs>; 4353 }; 4354 4355 opp-375000000 { 4356 opp-hz = /bits/ 64 <375000000>; 4357 required-opps = <&rpmhpd_opp_svs_l1>; 4358 }; 4359 4360 opp-500000000 { 4361 opp-hz = /bits/ 64 <500000000>; 4362 required-opps = <&rpmhpd_opp_nom>; 4363 }; 4364 opp-600000000 { 4365 opp-hz = /bits/ 64 <600000000>; 4366 required-opps = <&rpmhpd_opp_turbo_l1>; 4367 }; 4368 }; 4369 }; 4370 4371 mdss1_dp0: displayport-controller@22090000 { 4372 compatible = "qcom,sc8280xp-dp"; 4373 reg = <0 0x22090000 0 0x200>, 4374 <0 0x22090200 0 0x200>, 4375 <0 0x22090400 0 0x600>, 4376 <0 0x22091000 0 0x400>, 4377 <0 0x22091400 0 0x400>; 4378 4379 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4380 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4381 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4382 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4383 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4384 clock-names = "core_iface", "core_aux", 4385 "ctrl_link", 4386 "ctrl_link_iface", "stream_pixel"; 4387 interrupt-parent = <&mdss1>; 4388 interrupts = <12>; 4389 phys = <&mdss1_dp0_phy>; 4390 phy-names = "dp"; 4391 power-domains = <&rpmhpd SC8280XP_MMCX>; 4392 4393 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4394 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4395 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 4396 operating-points-v2 = <&mdss1_dp0_opp_table>; 4397 4398 #sound-dai-cells = <0>; 4399 4400 status = "disabled"; 4401 4402 ports { 4403 #address-cells = <1>; 4404 #size-cells = <0>; 4405 4406 port@0 { 4407 reg = <0>; 4408 mdss1_dp0_in: endpoint { 4409 remote-endpoint = <&mdss1_intf0_out>; 4410 }; 4411 }; 4412 4413 port@1 { 4414 reg = <1>; 4415 }; 4416 }; 4417 4418 mdss1_dp0_opp_table: opp-table { 4419 compatible = "operating-points-v2"; 4420 4421 opp-160000000 { 4422 opp-hz = /bits/ 64 <160000000>; 4423 required-opps = <&rpmhpd_opp_low_svs>; 4424 }; 4425 4426 opp-270000000 { 4427 opp-hz = /bits/ 64 <270000000>; 4428 required-opps = <&rpmhpd_opp_svs>; 4429 }; 4430 4431 opp-540000000 { 4432 opp-hz = /bits/ 64 <540000000>; 4433 required-opps = <&rpmhpd_opp_svs_l1>; 4434 }; 4435 4436 opp-810000000 { 4437 opp-hz = /bits/ 64 <810000000>; 4438 required-opps = <&rpmhpd_opp_nom>; 4439 }; 4440 }; 4441 }; 4442 4443 mdss1_dp1: displayport-controller@22098000 { 4444 compatible = "qcom,sc8280xp-dp"; 4445 reg = <0 0x22098000 0 0x200>, 4446 <0 0x22098200 0 0x200>, 4447 <0 0x22098400 0 0x600>, 4448 <0 0x22099000 0 0x400>, 4449 <0 0x22099400 0 0x400>; 4450 4451 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4452 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4453 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4454 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4455 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4456 clock-names = "core_iface", "core_aux", 4457 "ctrl_link", 4458 "ctrl_link_iface", "stream_pixel"; 4459 interrupt-parent = <&mdss1>; 4460 interrupts = <13>; 4461 phys = <&mdss1_dp1_phy>; 4462 phy-names = "dp"; 4463 power-domains = <&rpmhpd SC8280XP_MMCX>; 4464 4465 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4466 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4467 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 4468 operating-points-v2 = <&mdss1_dp1_opp_table>; 4469 4470 #sound-dai-cells = <0>; 4471 4472 status = "disabled"; 4473 4474 ports { 4475 #address-cells = <1>; 4476 #size-cells = <0>; 4477 4478 port@0 { 4479 reg = <0>; 4480 mdss1_dp1_in: endpoint { 4481 remote-endpoint = <&mdss1_intf4_out>; 4482 }; 4483 }; 4484 4485 port@1 { 4486 reg = <1>; 4487 }; 4488 }; 4489 4490 mdss1_dp1_opp_table: opp-table { 4491 compatible = "operating-points-v2"; 4492 4493 opp-160000000 { 4494 opp-hz = /bits/ 64 <160000000>; 4495 required-opps = <&rpmhpd_opp_low_svs>; 4496 }; 4497 4498 opp-270000000 { 4499 opp-hz = /bits/ 64 <270000000>; 4500 required-opps = <&rpmhpd_opp_svs>; 4501 }; 4502 4503 opp-540000000 { 4504 opp-hz = /bits/ 64 <540000000>; 4505 required-opps = <&rpmhpd_opp_svs_l1>; 4506 }; 4507 4508 opp-810000000 { 4509 opp-hz = /bits/ 64 <810000000>; 4510 required-opps = <&rpmhpd_opp_nom>; 4511 }; 4512 }; 4513 }; 4514 4515 mdss1_dp2: displayport-controller@2209a000 { 4516 compatible = "qcom,sc8280xp-dp"; 4517 reg = <0 0x2209a000 0 0x200>, 4518 <0 0x2209a200 0 0x200>, 4519 <0 0x2209a400 0 0x600>, 4520 <0 0x2209b000 0 0x400>, 4521 <0 0x2209b400 0 0x400>; 4522 4523 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4524 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4525 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4526 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4527 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4528 clock-names = "core_iface", "core_aux", 4529 "ctrl_link", 4530 "ctrl_link_iface", "stream_pixel"; 4531 interrupt-parent = <&mdss1>; 4532 interrupts = <14>; 4533 phys = <&mdss1_dp2_phy>; 4534 phy-names = "dp"; 4535 power-domains = <&rpmhpd SC8280XP_MMCX>; 4536 4537 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4538 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4539 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 4540 operating-points-v2 = <&mdss1_dp2_opp_table>; 4541 4542 #sound-dai-cells = <0>; 4543 4544 status = "disabled"; 4545 4546 ports { 4547 #address-cells = <1>; 4548 #size-cells = <0>; 4549 4550 port@0 { 4551 reg = <0>; 4552 mdss1_dp2_in: endpoint { 4553 remote-endpoint = <&mdss1_intf6_out>; 4554 }; 4555 }; 4556 4557 port@1 { 4558 reg = <1>; 4559 }; 4560 }; 4561 4562 mdss1_dp2_opp_table: opp-table { 4563 compatible = "operating-points-v2"; 4564 4565 opp-160000000 { 4566 opp-hz = /bits/ 64 <160000000>; 4567 required-opps = <&rpmhpd_opp_low_svs>; 4568 }; 4569 4570 opp-270000000 { 4571 opp-hz = /bits/ 64 <270000000>; 4572 required-opps = <&rpmhpd_opp_svs>; 4573 }; 4574 4575 opp-540000000 { 4576 opp-hz = /bits/ 64 <540000000>; 4577 required-opps = <&rpmhpd_opp_svs_l1>; 4578 }; 4579 4580 opp-810000000 { 4581 opp-hz = /bits/ 64 <810000000>; 4582 required-opps = <&rpmhpd_opp_nom>; 4583 }; 4584 }; 4585 }; 4586 4587 mdss1_dp3: displayport-controller@220a0000 { 4588 compatible = "qcom,sc8280xp-dp"; 4589 reg = <0 0x220a0000 0 0x200>, 4590 <0 0x220a0200 0 0x200>, 4591 <0 0x220a0400 0 0x600>, 4592 <0 0x220a1000 0 0x400>, 4593 <0 0x220a1400 0 0x400>; 4594 4595 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 4596 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4597 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4598 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4599 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4600 clock-names = "core_iface", "core_aux", 4601 "ctrl_link", 4602 "ctrl_link_iface", "stream_pixel"; 4603 interrupt-parent = <&mdss1>; 4604 interrupts = <15>; 4605 phys = <&mdss1_dp3_phy>; 4606 phy-names = "dp"; 4607 power-domains = <&rpmhpd SC8280XP_MMCX>; 4608 4609 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4610 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4611 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 4612 operating-points-v2 = <&mdss1_dp3_opp_table>; 4613 4614 #sound-dai-cells = <0>; 4615 4616 status = "disabled"; 4617 4618 ports { 4619 #address-cells = <1>; 4620 #size-cells = <0>; 4621 4622 port@0 { 4623 reg = <0>; 4624 mdss1_dp3_in: endpoint { 4625 remote-endpoint = <&mdss1_intf5_out>; 4626 }; 4627 }; 4628 4629 port@1 { 4630 reg = <1>; 4631 }; 4632 }; 4633 4634 mdss1_dp3_opp_table: opp-table { 4635 compatible = "operating-points-v2"; 4636 4637 opp-160000000 { 4638 opp-hz = /bits/ 64 <160000000>; 4639 required-opps = <&rpmhpd_opp_low_svs>; 4640 }; 4641 4642 opp-270000000 { 4643 opp-hz = /bits/ 64 <270000000>; 4644 required-opps = <&rpmhpd_opp_svs>; 4645 }; 4646 4647 opp-540000000 { 4648 opp-hz = /bits/ 64 <540000000>; 4649 required-opps = <&rpmhpd_opp_svs_l1>; 4650 }; 4651 4652 opp-810000000 { 4653 opp-hz = /bits/ 64 <810000000>; 4654 required-opps = <&rpmhpd_opp_nom>; 4655 }; 4656 }; 4657 }; 4658 }; 4659 4660 mdss1_dp2_phy: phy@220c2a00 { 4661 compatible = "qcom,sc8280xp-dp-phy"; 4662 reg = <0 0x220c2a00 0 0x19c>, 4663 <0 0x220c2200 0 0xec>, 4664 <0 0x220c2600 0 0xec>, 4665 <0 0x220c2000 0 0x1c8>; 4666 4667 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4668 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4669 clock-names = "aux", "cfg_ahb"; 4670 power-domains = <&rpmhpd SC8280XP_MX>; 4671 4672 #clock-cells = <1>; 4673 #phy-cells = <0>; 4674 4675 status = "disabled"; 4676 }; 4677 4678 mdss1_dp3_phy: phy@220c5a00 { 4679 compatible = "qcom,sc8280xp-dp-phy"; 4680 reg = <0 0x220c5a00 0 0x19c>, 4681 <0 0x220c5200 0 0xec>, 4682 <0 0x220c5600 0 0xec>, 4683 <0 0x220c5000 0 0x1c8>; 4684 4685 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4686 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 4687 clock-names = "aux", "cfg_ahb"; 4688 power-domains = <&rpmhpd SC8280XP_MX>; 4689 4690 #clock-cells = <1>; 4691 #phy-cells = <0>; 4692 4693 status = "disabled"; 4694 }; 4695 4696 dispcc1: clock-controller@22100000 { 4697 compatible = "qcom,sc8280xp-dispcc1"; 4698 reg = <0 0x22100000 0 0x20000>; 4699 4700 clocks = <&gcc GCC_DISP_AHB_CLK>, 4701 <&rpmhcc RPMH_CXO_CLK>, 4702 <0>, 4703 <&mdss1_dp0_phy 0>, 4704 <&mdss1_dp0_phy 1>, 4705 <&mdss1_dp1_phy 0>, 4706 <&mdss1_dp1_phy 1>, 4707 <&mdss1_dp2_phy 0>, 4708 <&mdss1_dp2_phy 1>, 4709 <&mdss1_dp3_phy 0>, 4710 <&mdss1_dp3_phy 1>, 4711 <0>, 4712 <0>, 4713 <0>, 4714 <0>; 4715 power-domains = <&rpmhpd SC8280XP_MMCX>; 4716 4717 #clock-cells = <1>; 4718 #power-domain-cells = <1>; 4719 #reset-cells = <1>; 4720 4721 status = "disabled"; 4722 }; 4723 }; 4724 4725 sound: sound { 4726 }; 4727 4728 thermal-zones { 4729 cpu0-thermal { 4730 polling-delay-passive = <250>; 4731 polling-delay = <1000>; 4732 4733 thermal-sensors = <&tsens0 1>; 4734 4735 trips { 4736 cpu-crit { 4737 temperature = <110000>; 4738 hysteresis = <1000>; 4739 type = "critical"; 4740 }; 4741 }; 4742 }; 4743 4744 cpu1-thermal { 4745 polling-delay-passive = <250>; 4746 polling-delay = <1000>; 4747 4748 thermal-sensors = <&tsens0 2>; 4749 4750 trips { 4751 cpu-crit { 4752 temperature = <110000>; 4753 hysteresis = <1000>; 4754 type = "critical"; 4755 }; 4756 }; 4757 }; 4758 4759 cpu2-thermal { 4760 polling-delay-passive = <250>; 4761 polling-delay = <1000>; 4762 4763 thermal-sensors = <&tsens0 3>; 4764 4765 trips { 4766 cpu-crit { 4767 temperature = <110000>; 4768 hysteresis = <1000>; 4769 type = "critical"; 4770 }; 4771 }; 4772 }; 4773 4774 cpu3-thermal { 4775 polling-delay-passive = <250>; 4776 polling-delay = <1000>; 4777 4778 thermal-sensors = <&tsens0 4>; 4779 4780 trips { 4781 cpu-crit { 4782 temperature = <110000>; 4783 hysteresis = <1000>; 4784 type = "critical"; 4785 }; 4786 }; 4787 }; 4788 4789 cpu4-thermal { 4790 polling-delay-passive = <250>; 4791 polling-delay = <1000>; 4792 4793 thermal-sensors = <&tsens0 5>; 4794 4795 trips { 4796 cpu-crit { 4797 temperature = <110000>; 4798 hysteresis = <1000>; 4799 type = "critical"; 4800 }; 4801 }; 4802 }; 4803 4804 cpu5-thermal { 4805 polling-delay-passive = <250>; 4806 polling-delay = <1000>; 4807 4808 thermal-sensors = <&tsens0 6>; 4809 4810 trips { 4811 cpu-crit { 4812 temperature = <110000>; 4813 hysteresis = <1000>; 4814 type = "critical"; 4815 }; 4816 }; 4817 }; 4818 4819 cpu6-thermal { 4820 polling-delay-passive = <250>; 4821 polling-delay = <1000>; 4822 4823 thermal-sensors = <&tsens0 7>; 4824 4825 trips { 4826 cpu-crit { 4827 temperature = <110000>; 4828 hysteresis = <1000>; 4829 type = "critical"; 4830 }; 4831 }; 4832 }; 4833 4834 cpu7-thermal { 4835 polling-delay-passive = <250>; 4836 polling-delay = <1000>; 4837 4838 thermal-sensors = <&tsens0 8>; 4839 4840 trips { 4841 cpu-crit { 4842 temperature = <110000>; 4843 hysteresis = <1000>; 4844 type = "critical"; 4845 }; 4846 }; 4847 }; 4848 4849 cluster0-thermal { 4850 polling-delay-passive = <250>; 4851 polling-delay = <1000>; 4852 4853 thermal-sensors = <&tsens0 9>; 4854 4855 trips { 4856 cpu-crit { 4857 temperature = <110000>; 4858 hysteresis = <1000>; 4859 type = "critical"; 4860 }; 4861 }; 4862 }; 4863 4864 mem-thermal { 4865 polling-delay-passive = <250>; 4866 polling-delay = <1000>; 4867 4868 thermal-sensors = <&tsens1 15>; 4869 4870 trips { 4871 trip-point0 { 4872 temperature = <90000>; 4873 hysteresis = <2000>; 4874 type = "hot"; 4875 }; 4876 }; 4877 }; 4878 }; 4879 4880 timer { 4881 compatible = "arm,armv8-timer"; 4882 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4883 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4884 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4885 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4886 }; 4887}; 4888