1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,osm-l3.h> 13#include <dt-bindings/interconnect/qcom,sc8180x.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 clocks { 26 xo_board_clk: xo-board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <38400000>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo485"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 capacity-dmips-mhz = <602>; 50 next-level-cache = <&L2_0>; 51 qcom,freq-domain = <&cpufreq_hw 0>; 52 operating-points-v2 = <&cpu0_opp_table>; 53 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 54 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 55 power-domains = <&CPU_PD0>; 56 power-domain-names = "psci"; 57 #cooling-cells = <2>; 58 clocks = <&cpufreq_hw 0>; 59 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo485"; 76 reg = <0x0 0x100>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <602>; 79 next-level-cache = <&L2_100>; 80 qcom,freq-domain = <&cpufreq_hw 0>; 81 operating-points-v2 = <&cpu0_opp_table>; 82 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 83 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 #cooling-cells = <2>; 87 clocks = <&cpufreq_hw 0>; 88 89 L2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&L3_0>; 94 }; 95 96 }; 97 98 CPU2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo485"; 101 reg = <0x0 0x200>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <602>; 104 next-level-cache = <&L2_200>; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 operating-points-v2 = <&cpu0_opp_table>; 107 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 108 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 109 power-domains = <&CPU_PD2>; 110 power-domain-names = "psci"; 111 #cooling-cells = <2>; 112 clocks = <&cpufreq_hw 0>; 113 114 L2_200: l2-cache { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-unified; 118 next-level-cache = <&L3_0>; 119 }; 120 }; 121 122 CPU3: cpu@300 { 123 device_type = "cpu"; 124 compatible = "qcom,kryo485"; 125 reg = <0x0 0x300>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <602>; 128 next-level-cache = <&L2_300>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 operating-points-v2 = <&cpu0_opp_table>; 131 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133 power-domains = <&CPU_PD3>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 clocks = <&cpufreq_hw 0>; 137 138 L2_300: l2-cache { 139 compatible = "cache"; 140 cache-unified; 141 cache-level = <2>; 142 next-level-cache = <&L3_0>; 143 }; 144 }; 145 146 CPU4: cpu@400 { 147 device_type = "cpu"; 148 compatible = "qcom,kryo485"; 149 reg = <0x0 0x400>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <1024>; 152 next-level-cache = <&L2_400>; 153 qcom,freq-domain = <&cpufreq_hw 1>; 154 operating-points-v2 = <&cpu4_opp_table>; 155 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 156 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 157 power-domains = <&CPU_PD4>; 158 power-domain-names = "psci"; 159 #cooling-cells = <2>; 160 clocks = <&cpufreq_hw 1>; 161 162 L2_400: l2-cache { 163 compatible = "cache"; 164 cache-unified; 165 cache-level = <2>; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU5: cpu@500 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo485"; 173 reg = <0x0 0x500>; 174 enable-method = "psci"; 175 capacity-dmips-mhz = <1024>; 176 next-level-cache = <&L2_500>; 177 qcom,freq-domain = <&cpufreq_hw 1>; 178 operating-points-v2 = <&cpu4_opp_table>; 179 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 180 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 181 power-domains = <&CPU_PD5>; 182 power-domain-names = "psci"; 183 #cooling-cells = <2>; 184 clocks = <&cpufreq_hw 1>; 185 186 L2_500: l2-cache { 187 compatible = "cache"; 188 cache-unified; 189 cache-level = <2>; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU6: cpu@600 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo485"; 197 reg = <0x0 0x600>; 198 enable-method = "psci"; 199 capacity-dmips-mhz = <1024>; 200 next-level-cache = <&L2_600>; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 operating-points-v2 = <&cpu4_opp_table>; 203 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 power-domains = <&CPU_PD6>; 206 power-domain-names = "psci"; 207 #cooling-cells = <2>; 208 clocks = <&cpufreq_hw 1>; 209 210 L2_600: l2-cache { 211 compatible = "cache"; 212 cache-unified; 213 cache-level = <2>; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU7: cpu@700 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo485"; 221 reg = <0x0 0x700>; 222 enable-method = "psci"; 223 capacity-dmips-mhz = <1024>; 224 next-level-cache = <&L2_700>; 225 qcom,freq-domain = <&cpufreq_hw 1>; 226 operating-points-v2 = <&cpu4_opp_table>; 227 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 229 power-domains = <&CPU_PD7>; 230 power-domain-names = "psci"; 231 #cooling-cells = <2>; 232 clocks = <&cpufreq_hw 1>; 233 234 L2_700: l2-cache { 235 compatible = "cache"; 236 cache-unified; 237 cache-level = <2>; 238 next-level-cache = <&L3_0>; 239 }; 240 }; 241 242 cpu-map { 243 cluster0 { 244 core0 { 245 cpu = <&CPU0>; 246 }; 247 248 core1 { 249 cpu = <&CPU1>; 250 }; 251 252 core2 { 253 cpu = <&CPU2>; 254 }; 255 256 core3 { 257 cpu = <&CPU3>; 258 }; 259 260 core4 { 261 cpu = <&CPU4>; 262 }; 263 264 core5 { 265 cpu = <&CPU5>; 266 }; 267 268 core6 { 269 cpu = <&CPU6>; 270 }; 271 272 core7 { 273 cpu = <&CPU7>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 282 compatible = "arm,idle-state"; 283 arm,psci-suspend-param = <0x40000004>; 284 entry-latency-us = <355>; 285 exit-latency-us = <909>; 286 min-residency-us = <3934>; 287 local-timer-stop; 288 }; 289 290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 arm,psci-suspend-param = <0x40000004>; 293 entry-latency-us = <241>; 294 exit-latency-us = <1461>; 295 min-residency-us = <4488>; 296 local-timer-stop; 297 }; 298 }; 299 300 domain-idle-states { 301 CLUSTER_SLEEP_0: cluster-sleep-0 { 302 compatible = "domain-idle-state"; 303 arm,psci-suspend-param = <0x4100a344>; 304 entry-latency-us = <3263>; 305 exit-latency-us = <6562>; 306 min-residency-us = <9987>; 307 }; 308 }; 309 }; 310 311 cpu0_opp_table: opp-table-cpu0 { 312 compatible = "operating-points-v2"; 313 opp-shared; 314 315 opp-300000000 { 316 opp-hz = /bits/ 64 <300000000>; 317 opp-peak-kBps = <800000 9600000>; 318 }; 319 320 opp-422400000 { 321 opp-hz = /bits/ 64 <422400000>; 322 opp-peak-kBps = <800000 9600000>; 323 }; 324 325 opp-537600000 { 326 opp-hz = /bits/ 64 <537600000>; 327 opp-peak-kBps = <800000 12902400>; 328 }; 329 330 opp-652800000 { 331 opp-hz = /bits/ 64 <652800000>; 332 opp-peak-kBps = <800000 12902400>; 333 }; 334 335 opp-768000000 { 336 opp-hz = /bits/ 64 <768000000>; 337 opp-peak-kBps = <800000 15974400>; 338 }; 339 340 opp-883200000 { 341 opp-hz = /bits/ 64 <883200000>; 342 opp-peak-kBps = <1804000 19660800>; 343 }; 344 345 opp-998400000 { 346 opp-hz = /bits/ 64 <998400000>; 347 opp-peak-kBps = <1804000 19660800>; 348 }; 349 350 opp-1113600000 { 351 opp-hz = /bits/ 64 <1113600000>; 352 opp-peak-kBps = <1804000 22732800>; 353 }; 354 355 opp-1228800000 { 356 opp-hz = /bits/ 64 <1228800000>; 357 opp-peak-kBps = <1804000 22732800>; 358 }; 359 360 opp-1363200000 { 361 opp-hz = /bits/ 64 <1363200000>; 362 opp-peak-kBps = <2188000 25804800>; 363 }; 364 365 opp-1478400000 { 366 opp-hz = /bits/ 64 <1478400000>; 367 opp-peak-kBps = <2188000 31948800>; 368 }; 369 370 opp-1574400000 { 371 opp-hz = /bits/ 64 <1574400000>; 372 opp-peak-kBps = <3072000 31948800>; 373 }; 374 375 opp-1670400000 { 376 opp-hz = /bits/ 64 <1670400000>; 377 opp-peak-kBps = <3072000 31948800>; 378 }; 379 380 opp-1766400000 { 381 opp-hz = /bits/ 64 <1766400000>; 382 opp-peak-kBps = <3072000 31948800>; 383 }; 384 }; 385 386 cpu4_opp_table: opp-table-cpu4 { 387 compatible = "operating-points-v2"; 388 opp-shared; 389 390 opp-825600000 { 391 opp-hz = /bits/ 64 <825600000>; 392 opp-peak-kBps = <1804000 15974400>; 393 }; 394 395 opp-940800000 { 396 opp-hz = /bits/ 64 <940800000>; 397 opp-peak-kBps = <2188000 19660800>; 398 }; 399 400 opp-1056000000 { 401 opp-hz = /bits/ 64 <1056000000>; 402 opp-peak-kBps = <2188000 22732800>; 403 }; 404 405 opp-1171200000 { 406 opp-hz = /bits/ 64 <1171200000>; 407 opp-peak-kBps = <3072000 25804800>; 408 }; 409 410 opp-1286400000 { 411 opp-hz = /bits/ 64 <1286400000>; 412 opp-peak-kBps = <3072000 31948800>; 413 }; 414 415 opp-1420800000 { 416 opp-hz = /bits/ 64 <1420800000>; 417 opp-peak-kBps = <4068000 31948800>; 418 }; 419 420 opp-1536000000 { 421 opp-hz = /bits/ 64 <1536000000>; 422 opp-peak-kBps = <4068000 31948800>; 423 }; 424 425 opp-1651200000 { 426 opp-hz = /bits/ 64 <1651200000>; 427 opp-peak-kBps = <4068000 40550400>; 428 }; 429 430 opp-1766400000 { 431 opp-hz = /bits/ 64 <1766400000>; 432 opp-peak-kBps = <4068000 40550400>; 433 }; 434 435 opp-1881600000 { 436 opp-hz = /bits/ 64 <1881600000>; 437 opp-peak-kBps = <4068000 43008000>; 438 }; 439 440 opp-1996800000 { 441 opp-hz = /bits/ 64 <1996800000>; 442 opp-peak-kBps = <6220000 43008000>; 443 }; 444 445 opp-2131200000 { 446 opp-hz = /bits/ 64 <2131200000>; 447 opp-peak-kBps = <6220000 49152000>; 448 }; 449 450 opp-2246400000 { 451 opp-hz = /bits/ 64 <2246400000>; 452 opp-peak-kBps = <7216000 49152000>; 453 }; 454 455 opp-2361600000 { 456 opp-hz = /bits/ 64 <2361600000>; 457 opp-peak-kBps = <8368000 49152000>; 458 }; 459 460 opp-2457600000 { 461 opp-hz = /bits/ 64 <2457600000>; 462 opp-peak-kBps = <8368000 51609600>; 463 }; 464 465 opp-2553600000 { 466 opp-hz = /bits/ 64 <2553600000>; 467 opp-peak-kBps = <8368000 51609600>; 468 }; 469 470 opp-2649600000 { 471 opp-hz = /bits/ 64 <2649600000>; 472 opp-peak-kBps = <8368000 51609600>; 473 }; 474 475 opp-2745600000 { 476 opp-hz = /bits/ 64 <2745600000>; 477 opp-peak-kBps = <8368000 51609600>; 478 }; 479 480 opp-2841600000 { 481 opp-hz = /bits/ 64 <2841600000>; 482 opp-peak-kBps = <8368000 51609600>; 483 }; 484 485 opp-2918400000 { 486 opp-hz = /bits/ 64 <2918400000>; 487 opp-peak-kBps = <8368000 51609600>; 488 }; 489 490 opp-2995200000 { 491 opp-hz = /bits/ 64 <2995200000>; 492 opp-peak-kBps = <8368000 51609600>; 493 }; 494 }; 495 496 firmware { 497 scm: scm { 498 compatible = "qcom,scm-sc8180x", "qcom,scm"; 499 }; 500 }; 501 502 camnoc_virt: interconnect-camnoc-virt { 503 compatible = "qcom,sc8180x-camnoc-virt"; 504 #interconnect-cells = <2>; 505 qcom,bcm-voters = <&apps_bcm_voter>; 506 }; 507 508 mc_virt: interconnect-mc-virt { 509 compatible = "qcom,sc8180x-mc-virt"; 510 #interconnect-cells = <2>; 511 qcom,bcm-voters = <&apps_bcm_voter>; 512 }; 513 514 qup_virt: interconnect-qup-virt { 515 compatible = "qcom,sc8180x-qup-virt"; 516 #interconnect-cells = <2>; 517 qcom,bcm-voters = <&apps_bcm_voter>; 518 }; 519 520 memory@80000000 { 521 device_type = "memory"; 522 /* We expect the bootloader to fill in the size */ 523 reg = <0x0 0x80000000 0x0 0x0>; 524 }; 525 526 pmu { 527 compatible = "arm,armv8-pmuv3"; 528 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 529 }; 530 531 psci { 532 compatible = "arm,psci-1.0"; 533 method = "smc"; 534 535 CPU_PD0: power-domain-cpu0 { 536 #power-domain-cells = <0>; 537 power-domains = <&CLUSTER_PD>; 538 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 539 }; 540 541 CPU_PD1: power-domain-cpu1 { 542 #power-domain-cells = <0>; 543 power-domains = <&CLUSTER_PD>; 544 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 545 }; 546 547 CPU_PD2: power-domain-cpu2 { 548 #power-domain-cells = <0>; 549 power-domains = <&CLUSTER_PD>; 550 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 551 }; 552 553 CPU_PD3: power-domain-cpu3 { 554 #power-domain-cells = <0>; 555 power-domains = <&CLUSTER_PD>; 556 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 557 }; 558 559 CPU_PD4: power-domain-cpu4 { 560 #power-domain-cells = <0>; 561 power-domains = <&CLUSTER_PD>; 562 domain-idle-states = <&BIG_CPU_SLEEP_0>; 563 }; 564 565 CPU_PD5: power-domain-cpu5 { 566 #power-domain-cells = <0>; 567 power-domains = <&CLUSTER_PD>; 568 domain-idle-states = <&BIG_CPU_SLEEP_0>; 569 }; 570 571 CPU_PD6: power-domain-cpu6 { 572 #power-domain-cells = <0>; 573 power-domains = <&CLUSTER_PD>; 574 domain-idle-states = <&BIG_CPU_SLEEP_0>; 575 }; 576 577 CPU_PD7: power-domain-cpu7 { 578 #power-domain-cells = <0>; 579 power-domains = <&CLUSTER_PD>; 580 domain-idle-states = <&BIG_CPU_SLEEP_0>; 581 }; 582 583 CLUSTER_PD: power-domain-cpu-cluster0 { 584 #power-domain-cells = <0>; 585 domain-idle-states = <&CLUSTER_SLEEP_0>; 586 }; 587 }; 588 589 reserved-memory { 590 #address-cells = <2>; 591 #size-cells = <2>; 592 ranges; 593 594 hyp_mem: hyp@85700000 { 595 reg = <0x0 0x85700000 0x0 0x600000>; 596 no-map; 597 }; 598 599 xbl_mem: xbl@85d00000 { 600 reg = <0x0 0x85d00000 0x0 0x140000>; 601 no-map; 602 }; 603 604 aop_mem: aop@85f00000 { 605 reg = <0x0 0x85f00000 0x0 0x20000>; 606 no-map; 607 }; 608 609 aop_cmd_db: cmd-db@85f20000 { 610 compatible = "qcom,cmd-db"; 611 reg = <0x0 0x85f20000 0x0 0x20000>; 612 no-map; 613 }; 614 615 reserved@85f40000 { 616 reg = <0x0 0x85f40000 0x0 0x10000>; 617 no-map; 618 }; 619 620 smem_mem: smem@86000000 { 621 compatible = "qcom,smem"; 622 reg = <0x0 0x86000000 0x0 0x200000>; 623 no-map; 624 hwlocks = <&tcsr_mutex 3>; 625 }; 626 627 reserved@86200000 { 628 reg = <0x0 0x86200000 0x0 0x3900000>; 629 no-map; 630 }; 631 632 reserved@89b00000 { 633 reg = <0x0 0x89b00000 0x0 0x1c00000>; 634 no-map; 635 }; 636 637 reserved@9d400000 { 638 reg = <0x0 0x9d400000 0x0 0x1000000>; 639 no-map; 640 }; 641 642 reserved@9e400000 { 643 reg = <0x0 0x9e400000 0x0 0x1400000>; 644 no-map; 645 }; 646 647 reserved@9f800000 { 648 reg = <0x0 0x9f800000 0x0 0x800000>; 649 no-map; 650 }; 651 }; 652 653 smp2p-cdsp { 654 compatible = "qcom,smp2p"; 655 qcom,smem = <94>, <432>; 656 657 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 658 659 mboxes = <&apss_shared 6>; 660 661 qcom,local-pid = <0>; 662 qcom,remote-pid = <5>; 663 664 cdsp_smp2p_out: master-kernel { 665 qcom,entry-name = "master-kernel"; 666 #qcom,smem-state-cells = <1>; 667 }; 668 669 cdsp_smp2p_in: slave-kernel { 670 qcom,entry-name = "slave-kernel"; 671 672 interrupt-controller; 673 #interrupt-cells = <2>; 674 }; 675 }; 676 677 smp2p-lpass { 678 compatible = "qcom,smp2p"; 679 qcom,smem = <443>, <429>; 680 681 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 682 683 mboxes = <&apss_shared 10>; 684 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <2>; 687 688 adsp_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 adsp_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 696 interrupt-controller; 697 #interrupt-cells = <2>; 698 }; 699 }; 700 701 smp2p-mpss { 702 compatible = "qcom,smp2p"; 703 qcom,smem = <435>, <428>; 704 705 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 706 707 mboxes = <&apss_shared 14>; 708 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <1>; 711 712 modem_smp2p_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 modem_smp2p_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 724 modem_smp2p_ipa_out: ipa-ap-to-modem { 725 qcom,entry-name = "ipa"; 726 #qcom,smem-state-cells = <1>; 727 }; 728 729 modem_smp2p_ipa_in: ipa-modem-to-ap { 730 qcom,entry-name = "ipa"; 731 interrupt-controller; 732 #interrupt-cells = <2>; 733 }; 734 735 modem_smp2p_wlan_in: wlan-wpss-to-ap { 736 qcom,entry-name = "wlan"; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 }; 740 }; 741 742 smp2p-slpi { 743 compatible = "qcom,smp2p"; 744 qcom,smem = <481>, <430>; 745 746 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 747 748 mboxes = <&apss_shared 26>; 749 750 qcom,local-pid = <0>; 751 qcom,remote-pid = <3>; 752 753 slpi_smp2p_out: master-kernel { 754 qcom,entry-name = "master-kernel"; 755 #qcom,smem-state-cells = <1>; 756 }; 757 758 slpi_smp2p_in: slave-kernel { 759 qcom,entry-name = "slave-kernel"; 760 761 interrupt-controller; 762 #interrupt-cells = <2>; 763 }; 764 }; 765 766 soc: soc@0 { 767 compatible = "simple-bus"; 768 #address-cells = <2>; 769 #size-cells = <2>; 770 ranges = <0 0 0 0 0x10 0>; 771 dma-ranges = <0 0 0 0 0x10 0>; 772 773 gcc: clock-controller@100000 { 774 compatible = "qcom,gcc-sc8180x"; 775 reg = <0x0 0x00100000 0x0 0x1f0000>; 776 #clock-cells = <1>; 777 #reset-cells = <1>; 778 #power-domain-cells = <1>; 779 clocks = <&rpmhcc RPMH_CXO_CLK>, 780 <&rpmhcc RPMH_CXO_CLK_A>, 781 <&sleep_clk>; 782 clock-names = "bi_tcxo", 783 "bi_tcxo_ao", 784 "sleep_clk"; 785 }; 786 787 qupv3_id_0: geniqup@8c0000 { 788 compatible = "qcom,geni-se-qup"; 789 reg = <0 0x008c0000 0 0x6000>; 790 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 791 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 792 clock-names = "m-ahb", "s-ahb"; 793 #address-cells = <2>; 794 #size-cells = <2>; 795 ranges; 796 iommus = <&apps_smmu 0x4c3 0>; 797 status = "disabled"; 798 799 i2c0: i2c@880000 { 800 compatible = "qcom,geni-i2c"; 801 reg = <0 0x00880000 0 0x4000>; 802 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 803 clock-names = "se"; 804 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 805 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 806 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 807 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 808 interconnect-names = "qup-core", "qup-config", "qup-memory"; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 status = "disabled"; 812 }; 813 814 spi0: spi@880000 { 815 compatible = "qcom,geni-spi"; 816 reg = <0 0x00880000 0 0x4000>; 817 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 818 clock-names = "se"; 819 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 820 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 821 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 822 interconnect-names = "qup-core", "qup-config"; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 status = "disabled"; 826 }; 827 828 uart0: serial@880000 { 829 compatible = "qcom,geni-uart"; 830 reg = <0 0x00880000 0 0x4000>; 831 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 832 clock-names = "se"; 833 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 834 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 835 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 836 interconnect-names = "qup-core", "qup-config"; 837 status = "disabled"; 838 }; 839 840 i2c1: i2c@884000 { 841 compatible = "qcom,geni-i2c"; 842 reg = <0 0x00884000 0 0x4000>; 843 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 844 clock-names = "se"; 845 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 846 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 848 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 849 interconnect-names = "qup-core", "qup-config", "qup-memory"; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 status = "disabled"; 853 }; 854 855 spi1: spi@884000 { 856 compatible = "qcom,geni-spi"; 857 reg = <0 0x00884000 0 0x4000>; 858 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 859 clock-names = "se"; 860 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 861 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 862 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 863 interconnect-names = "qup-core", "qup-config"; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 status = "disabled"; 867 }; 868 869 uart1: serial@884000 { 870 compatible = "qcom,geni-uart"; 871 reg = <0 0x00884000 0 0x4000>; 872 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 873 clock-names = "se"; 874 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 875 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 876 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 877 interconnect-names = "qup-core", "qup-config"; 878 status = "disabled"; 879 }; 880 881 i2c2: i2c@888000 { 882 compatible = "qcom,geni-i2c"; 883 reg = <0 0x00888000 0 0x4000>; 884 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 885 clock-names = "se"; 886 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 887 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 888 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 889 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 890 interconnect-names = "qup-core", "qup-config", "qup-memory"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 status = "disabled"; 894 }; 895 896 spi2: spi@888000 { 897 compatible = "qcom,geni-spi"; 898 reg = <0 0x00888000 0 0x4000>; 899 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 900 clock-names = "se"; 901 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 902 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 903 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 904 interconnect-names = "qup-core", "qup-config"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 status = "disabled"; 908 }; 909 910 uart2: serial@888000 { 911 compatible = "qcom,geni-uart"; 912 reg = <0 0x00888000 0 0x4000>; 913 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 914 clock-names = "se"; 915 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 916 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 917 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 918 interconnect-names = "qup-core", "qup-config"; 919 status = "disabled"; 920 }; 921 922 i2c3: i2c@88c000 { 923 compatible = "qcom,geni-i2c"; 924 reg = <0 0x0088c000 0 0x4000>; 925 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 926 clock-names = "se"; 927 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 928 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 929 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 930 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 931 interconnect-names = "qup-core", "qup-config", "qup-memory"; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 }; 936 937 spi3: spi@88c000 { 938 compatible = "qcom,geni-spi"; 939 reg = <0 0x0088c000 0 0x4000>; 940 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 941 clock-names = "se"; 942 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 943 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 944 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 945 interconnect-names = "qup-core", "qup-config"; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 status = "disabled"; 949 }; 950 951 uart3: serial@88c000 { 952 compatible = "qcom,geni-uart"; 953 reg = <0 0x0088c000 0 0x4000>; 954 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 955 clock-names = "se"; 956 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 957 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 958 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 959 interconnect-names = "qup-core", "qup-config"; 960 status = "disabled"; 961 }; 962 963 i2c4: i2c@890000 { 964 compatible = "qcom,geni-i2c"; 965 reg = <0 0x00890000 0 0x4000>; 966 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 967 clock-names = "se"; 968 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 969 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 970 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 971 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 972 interconnect-names = "qup-core", "qup-config", "qup-memory"; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 status = "disabled"; 976 }; 977 978 spi4: spi@890000 { 979 compatible = "qcom,geni-spi"; 980 reg = <0 0x00890000 0 0x4000>; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 982 clock-names = "se"; 983 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 984 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 985 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 986 interconnect-names = "qup-core", "qup-config"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 uart4: serial@890000 { 993 compatible = "qcom,geni-uart"; 994 reg = <0 0x00890000 0 0x4000>; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 996 clock-names = "se"; 997 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 998 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 999 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1000 interconnect-names = "qup-core", "qup-config"; 1001 status = "disabled"; 1002 }; 1003 1004 i2c5: i2c@894000 { 1005 compatible = "qcom,geni-i2c"; 1006 reg = <0 0x00894000 0 0x4000>; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1008 clock-names = "se"; 1009 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1010 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1011 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1012 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1013 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 spi5: spi@894000 { 1020 compatible = "qcom,geni-spi"; 1021 reg = <0 0x00894000 0 0x4000>; 1022 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1023 clock-names = "se"; 1024 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1025 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1026 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1027 interconnect-names = "qup-core", "qup-config"; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 status = "disabled"; 1031 }; 1032 1033 uart5: serial@894000 { 1034 compatible = "qcom,geni-uart"; 1035 reg = <0 0x00894000 0 0x4000>; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1037 clock-names = "se"; 1038 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1039 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1040 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1041 interconnect-names = "qup-core", "qup-config"; 1042 status = "disabled"; 1043 }; 1044 1045 i2c6: i2c@898000 { 1046 compatible = "qcom,geni-i2c"; 1047 reg = <0 0x00898000 0 0x4000>; 1048 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1049 clock-names = "se"; 1050 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1051 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1052 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1053 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1054 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 status = "disabled"; 1058 }; 1059 1060 spi6: spi@898000 { 1061 compatible = "qcom,geni-spi"; 1062 reg = <0 0x00898000 0 0x4000>; 1063 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1064 clock-names = "se"; 1065 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1066 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1067 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1068 interconnect-names = "qup-core", "qup-config"; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 status = "disabled"; 1072 }; 1073 1074 uart6: serial@898000 { 1075 compatible = "qcom,geni-uart"; 1076 reg = <0 0x00898000 0 0x4000>; 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1078 clock-names = "se"; 1079 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1080 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1081 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1082 interconnect-names = "qup-core", "qup-config"; 1083 status = "disabled"; 1084 }; 1085 1086 i2c7: i2c@89c000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0 0x0089c000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1090 clock-names = "se"; 1091 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1092 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1093 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1094 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1095 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 status = "disabled"; 1099 }; 1100 1101 spi7: spi@89c000 { 1102 compatible = "qcom,geni-spi"; 1103 reg = <0 0x0089c000 0 0x4000>; 1104 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1105 clock-names = "se"; 1106 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1107 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1108 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1109 interconnect-names = "qup-core", "qup-config"; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 status = "disabled"; 1113 }; 1114 1115 uart7: serial@89c000 { 1116 compatible = "qcom,geni-uart"; 1117 reg = <0 0x0089c000 0 0x4000>; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1119 clock-names = "se"; 1120 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1121 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1122 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1123 interconnect-names = "qup-core", "qup-config"; 1124 status = "disabled"; 1125 }; 1126 }; 1127 1128 qupv3_id_1: geniqup@ac0000 { 1129 compatible = "qcom,geni-se-qup"; 1130 reg = <0x0 0x00ac0000 0x0 0x6000>; 1131 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1132 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1133 clock-names = "m-ahb", "s-ahb"; 1134 #address-cells = <2>; 1135 #size-cells = <2>; 1136 ranges; 1137 iommus = <&apps_smmu 0x603 0>; 1138 status = "disabled"; 1139 1140 i2c8: i2c@a80000 { 1141 compatible = "qcom,geni-i2c"; 1142 reg = <0 0x00a80000 0 0x4000>; 1143 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1144 clock-names = "se"; 1145 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1146 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1147 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1148 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1149 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 status = "disabled"; 1153 }; 1154 1155 spi8: spi@a80000 { 1156 compatible = "qcom,geni-spi"; 1157 reg = <0 0x00a80000 0 0x4000>; 1158 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1159 clock-names = "se"; 1160 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1161 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1162 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1163 interconnect-names = "qup-core", "qup-config"; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 status = "disabled"; 1167 }; 1168 1169 uart8: serial@a80000 { 1170 compatible = "qcom,geni-uart"; 1171 reg = <0 0x00a80000 0 0x4000>; 1172 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1173 clock-names = "se"; 1174 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1175 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1176 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1177 interconnect-names = "qup-core", "qup-config"; 1178 status = "disabled"; 1179 }; 1180 1181 i2c9: i2c@a84000 { 1182 compatible = "qcom,geni-i2c"; 1183 reg = <0 0x00a84000 0 0x4000>; 1184 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1185 clock-names = "se"; 1186 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1187 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1188 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1189 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1190 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 status = "disabled"; 1194 }; 1195 1196 spi9: spi@a84000 { 1197 compatible = "qcom,geni-spi"; 1198 reg = <0 0x00a84000 0 0x4000>; 1199 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1200 clock-names = "se"; 1201 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1203 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1204 interconnect-names = "qup-core", "qup-config"; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 status = "disabled"; 1208 }; 1209 1210 uart9: serial@a84000 { 1211 compatible = "qcom,geni-debug-uart"; 1212 reg = <0 0x00a84000 0 0x4000>; 1213 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1214 clock-names = "se"; 1215 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1216 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1217 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1218 interconnect-names = "qup-core", "qup-config"; 1219 status = "disabled"; 1220 }; 1221 1222 i2c10: i2c@a88000 { 1223 compatible = "qcom,geni-i2c"; 1224 reg = <0 0x00a88000 0 0x4000>; 1225 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1226 clock-names = "se"; 1227 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1228 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1229 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1230 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1231 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 spi10: spi@a88000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0 0x00a88000 0 0x4000>; 1240 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1241 clock-names = "se"; 1242 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1243 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1244 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1245 interconnect-names = "qup-core", "qup-config"; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 status = "disabled"; 1249 }; 1250 1251 uart10: serial@a88000 { 1252 compatible = "qcom,geni-uart"; 1253 reg = <0 0x00a88000 0 0x4000>; 1254 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1255 clock-names = "se"; 1256 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1257 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1258 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1259 interconnect-names = "qup-core", "qup-config"; 1260 status = "disabled"; 1261 }; 1262 1263 i2c11: i2c@a8c000 { 1264 compatible = "qcom,geni-i2c"; 1265 reg = <0 0x00a8c000 0 0x4000>; 1266 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1267 clock-names = "se"; 1268 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1269 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1270 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1271 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1272 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 status = "disabled"; 1276 }; 1277 1278 spi11: spi@a8c000 { 1279 compatible = "qcom,geni-spi"; 1280 reg = <0 0x00a8c000 0 0x4000>; 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1282 clock-names = "se"; 1283 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1284 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1285 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1286 interconnect-names = "qup-core", "qup-config"; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 status = "disabled"; 1290 }; 1291 1292 uart11: serial@a8c000 { 1293 compatible = "qcom,geni-uart"; 1294 reg = <0 0x00a8c000 0 0x4000>; 1295 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1296 clock-names = "se"; 1297 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1298 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1299 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1300 interconnect-names = "qup-core", "qup-config"; 1301 status = "disabled"; 1302 }; 1303 1304 i2c12: i2c@a90000 { 1305 compatible = "qcom,geni-i2c"; 1306 reg = <0 0x00a90000 0 0x4000>; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1308 clock-names = "se"; 1309 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1310 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1311 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1312 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1313 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 spi12: spi@a90000 { 1320 compatible = "qcom,geni-spi"; 1321 reg = <0 0x00a90000 0 0x4000>; 1322 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1323 clock-names = "se"; 1324 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1325 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1326 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1327 interconnect-names = "qup-core", "qup-config"; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 uart12: serial@a90000 { 1334 compatible = "qcom,geni-uart"; 1335 reg = <0 0x00a90000 0 0x4000>; 1336 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1337 clock-names = "se"; 1338 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1339 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1340 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1341 interconnect-names = "qup-core", "qup-config"; 1342 status = "disabled"; 1343 }; 1344 1345 i2c16: i2c@a94000 { 1346 compatible = "qcom,geni-i2c"; 1347 reg = <0 0x00a94000 0 0x4000>; 1348 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1349 clock-names = "se"; 1350 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1351 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1352 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1353 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1354 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 status = "disabled"; 1358 }; 1359 1360 spi16: spi@a94000 { 1361 compatible = "qcom,geni-spi"; 1362 reg = <0 0x00a94000 0 0x4000>; 1363 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1364 clock-names = "se"; 1365 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1366 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1367 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1368 interconnect-names = "qup-core", "qup-config"; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 uart16: serial@a94000 { 1375 compatible = "qcom,geni-uart"; 1376 reg = <0 0x00a94000 0 0x4000>; 1377 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1378 clock-names = "se"; 1379 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1380 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1381 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1382 interconnect-names = "qup-core", "qup-config"; 1383 status = "disabled"; 1384 }; 1385 }; 1386 1387 qupv3_id_2: geniqup@cc0000 { 1388 compatible = "qcom,geni-se-qup"; 1389 reg = <0x0 0x00cc0000 0x0 0x6000>; 1390 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1391 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1392 clock-names = "m-ahb", "s-ahb"; 1393 #address-cells = <2>; 1394 #size-cells = <2>; 1395 ranges; 1396 iommus = <&apps_smmu 0x7a3 0>; 1397 status = "disabled"; 1398 1399 i2c17: i2c@c80000 { 1400 compatible = "qcom,geni-i2c"; 1401 reg = <0 0x00c80000 0 0x4000>; 1402 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1403 clock-names = "se"; 1404 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1405 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1406 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1407 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1408 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 status = "disabled"; 1412 }; 1413 1414 spi17: spi@c80000 { 1415 compatible = "qcom,geni-spi"; 1416 reg = <0 0x00c80000 0 0x4000>; 1417 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1418 clock-names = "se"; 1419 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1420 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1421 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1422 interconnect-names = "qup-core", "qup-config"; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 status = "disabled"; 1426 }; 1427 1428 uart17: serial@c80000 { 1429 compatible = "qcom,geni-uart"; 1430 reg = <0 0x00c80000 0 0x4000>; 1431 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1432 clock-names = "se"; 1433 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1434 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1435 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1436 interconnect-names = "qup-core", "qup-config"; 1437 status = "disabled"; 1438 }; 1439 1440 i2c18: i2c@c84000 { 1441 compatible = "qcom,geni-i2c"; 1442 reg = <0 0x00c84000 0 0x4000>; 1443 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1444 clock-names = "se"; 1445 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1446 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1447 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1448 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1449 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 status = "disabled"; 1453 }; 1454 1455 spi18: spi@c84000 { 1456 compatible = "qcom,geni-spi"; 1457 reg = <0 0x00c84000 0 0x4000>; 1458 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1459 clock-names = "se"; 1460 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1461 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1462 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1463 interconnect-names = "qup-core", "qup-config"; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 status = "disabled"; 1467 }; 1468 1469 uart18: serial@c84000 { 1470 compatible = "qcom,geni-uart"; 1471 reg = <0 0x00c84000 0 0x4000>; 1472 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1473 clock-names = "se"; 1474 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1475 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1476 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1477 interconnect-names = "qup-core", "qup-config"; 1478 status = "disabled"; 1479 }; 1480 1481 i2c19: i2c@c88000 { 1482 compatible = "qcom,geni-i2c"; 1483 reg = <0 0x00c88000 0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1485 clock-names = "se"; 1486 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1487 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1488 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1489 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1490 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 spi19: spi@c88000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0 0x00c88000 0 0x4000>; 1499 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1500 clock-names = "se"; 1501 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1502 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1503 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1504 interconnect-names = "qup-core", "qup-config"; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 status = "disabled"; 1508 }; 1509 1510 uart19: serial@c88000 { 1511 compatible = "qcom,geni-uart"; 1512 reg = <0 0x00c88000 0 0x4000>; 1513 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1514 clock-names = "se"; 1515 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1516 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1517 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1518 interconnect-names = "qup-core", "qup-config"; 1519 status = "disabled"; 1520 }; 1521 1522 i2c13: i2c@c8c000 { 1523 compatible = "qcom,geni-i2c"; 1524 reg = <0 0x00c8c000 0 0x4000>; 1525 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1526 clock-names = "se"; 1527 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1528 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1529 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1530 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1531 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 status = "disabled"; 1535 }; 1536 1537 spi13: spi@c8c000 { 1538 compatible = "qcom,geni-spi"; 1539 reg = <0 0x00c8c000 0 0x4000>; 1540 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1541 clock-names = "se"; 1542 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1543 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1544 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1545 interconnect-names = "qup-core", "qup-config"; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 status = "disabled"; 1549 }; 1550 1551 uart13: serial@c8c000 { 1552 compatible = "qcom,geni-uart"; 1553 reg = <0 0x00c8c000 0 0x4000>; 1554 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1555 clock-names = "se"; 1556 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1557 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1558 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1559 interconnect-names = "qup-core", "qup-config"; 1560 status = "disabled"; 1561 }; 1562 1563 i2c14: i2c@c90000 { 1564 compatible = "qcom,geni-i2c"; 1565 reg = <0 0x00c90000 0 0x4000>; 1566 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1567 clock-names = "se"; 1568 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1569 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1570 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1571 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1572 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1573 #address-cells = <1>; 1574 #size-cells = <0>; 1575 status = "disabled"; 1576 }; 1577 1578 spi14: spi@c90000 { 1579 compatible = "qcom,geni-spi"; 1580 reg = <0 0x00c90000 0 0x4000>; 1581 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1582 clock-names = "se"; 1583 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1584 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1585 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1586 interconnect-names = "qup-core", "qup-config"; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 status = "disabled"; 1590 }; 1591 1592 uart14: serial@c90000 { 1593 compatible = "qcom,geni-uart"; 1594 reg = <0 0x00c90000 0 0x4000>; 1595 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1596 clock-names = "se"; 1597 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1598 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1599 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1600 interconnect-names = "qup-core", "qup-config"; 1601 status = "disabled"; 1602 }; 1603 1604 i2c15: i2c@c94000 { 1605 compatible = "qcom,geni-i2c"; 1606 reg = <0 0x00c94000 0 0x4000>; 1607 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1608 clock-names = "se"; 1609 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1610 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1611 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1612 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1613 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 status = "disabled"; 1617 }; 1618 1619 spi15: spi@c94000 { 1620 compatible = "qcom,geni-spi"; 1621 reg = <0 0x00c94000 0 0x4000>; 1622 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1623 clock-names = "se"; 1624 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1625 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1626 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1627 interconnect-names = "qup-core", "qup-config"; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 status = "disabled"; 1631 }; 1632 1633 uart15: serial@c94000 { 1634 compatible = "qcom,geni-uart"; 1635 reg = <0 0x00c94000 0 0x4000>; 1636 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1637 clock-names = "se"; 1638 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1639 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1640 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1641 interconnect-names = "qup-core", "qup-config"; 1642 status = "disabled"; 1643 }; 1644 }; 1645 1646 config_noc: interconnect@1500000 { 1647 compatible = "qcom,sc8180x-config-noc"; 1648 reg = <0 0x01500000 0 0x7400>; 1649 #interconnect-cells = <2>; 1650 qcom,bcm-voters = <&apps_bcm_voter>; 1651 }; 1652 1653 system_noc: interconnect@1620000 { 1654 compatible = "qcom,sc8180x-system-noc"; 1655 reg = <0 0x01620000 0 0x19400>; 1656 #interconnect-cells = <2>; 1657 qcom,bcm-voters = <&apps_bcm_voter>; 1658 }; 1659 1660 aggre1_noc: interconnect@16e0000 { 1661 compatible = "qcom,sc8180x-aggre1-noc"; 1662 reg = <0 0x016e0000 0 0xd080>; 1663 #interconnect-cells = <2>; 1664 qcom,bcm-voters = <&apps_bcm_voter>; 1665 }; 1666 1667 aggre2_noc: interconnect@1700000 { 1668 compatible = "qcom,sc8180x-aggre2-noc"; 1669 reg = <0 0x01700000 0 0x20000>; 1670 #interconnect-cells = <2>; 1671 qcom,bcm-voters = <&apps_bcm_voter>; 1672 }; 1673 1674 compute_noc: interconnect@1720000 { 1675 compatible = "qcom,sc8180x-compute-noc"; 1676 reg = <0 0x01720000 0 0x7000>; 1677 #interconnect-cells = <2>; 1678 qcom,bcm-voters = <&apps_bcm_voter>; 1679 }; 1680 1681 mmss_noc: interconnect@1740000 { 1682 compatible = "qcom,sc8180x-mmss-noc"; 1683 reg = <0 0x01740000 0 0x1c100>; 1684 #interconnect-cells = <2>; 1685 qcom,bcm-voters = <&apps_bcm_voter>; 1686 }; 1687 1688 pcie0: pcie@1c00000 { 1689 compatible = "qcom,pcie-sc8180x"; 1690 reg = <0 0x01c00000 0 0x3000>, 1691 <0 0x60000000 0 0xf1d>, 1692 <0 0x60000f20 0 0xa8>, 1693 <0 0x60001000 0 0x1000>, 1694 <0 0x60100000 0 0x100000>; 1695 reg-names = "parf", 1696 "dbi", 1697 "elbi", 1698 "atu", 1699 "config"; 1700 device_type = "pci"; 1701 linux,pci-domain = <0>; 1702 bus-range = <0x00 0xff>; 1703 num-lanes = <2>; 1704 1705 #address-cells = <3>; 1706 #size-cells = <2>; 1707 1708 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1709 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1710 1711 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1712 interrupt-names = "msi"; 1713 #interrupt-cells = <1>; 1714 interrupt-map-mask = <0 0 0 0x7>; 1715 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1716 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1717 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1718 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1719 1720 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1721 <&gcc GCC_PCIE_0_AUX_CLK>, 1722 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1723 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1724 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1725 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1726 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1727 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1728 clock-names = "pipe", 1729 "aux", 1730 "cfg", 1731 "bus_master", 1732 "bus_slave", 1733 "slave_q2a", 1734 "ref", 1735 "tbu"; 1736 1737 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1738 assigned-clock-rates = <19200000>; 1739 1740 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1741 <0x100 &apps_smmu 0x1d81 0x1>; 1742 1743 resets = <&gcc GCC_PCIE_0_BCR>; 1744 reset-names = "pci"; 1745 1746 power-domains = <&gcc PCIE_0_GDSC>; 1747 1748 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1749 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1750 interconnect-names = "pcie-mem", "cpu-pcie"; 1751 1752 phys = <&pcie0_phy>; 1753 phy-names = "pciephy"; 1754 dma-coherent; 1755 1756 status = "disabled"; 1757 }; 1758 1759 pcie0_phy: phy@1c06000 { 1760 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1761 reg = <0 0x01c06000 0 0x1000>; 1762 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1763 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1764 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1765 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1766 <&gcc GCC_PCIE_0_PIPE_CLK>; 1767 clock-names = "aux", 1768 "cfg_ahb", 1769 "ref", 1770 "refgen", 1771 "pipe"; 1772 #clock-cells = <0>; 1773 clock-output-names = "pcie_0_pipe_clk"; 1774 #phy-cells = <0>; 1775 1776 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1777 reset-names = "phy"; 1778 1779 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1780 assigned-clock-rates = <100000000>; 1781 1782 status = "disabled"; 1783 }; 1784 1785 pcie3: pcie@1c08000 { 1786 compatible = "qcom,pcie-sc8180x"; 1787 reg = <0 0x01c08000 0 0x3000>, 1788 <0 0x40000000 0 0xf1d>, 1789 <0 0x40000f20 0 0xa8>, 1790 <0 0x40001000 0 0x1000>, 1791 <0 0x40100000 0 0x100000>; 1792 reg-names = "parf", 1793 "dbi", 1794 "elbi", 1795 "atu", 1796 "config"; 1797 device_type = "pci"; 1798 linux,pci-domain = <3>; 1799 bus-range = <0x00 0xff>; 1800 num-lanes = <2>; 1801 1802 #address-cells = <3>; 1803 #size-cells = <2>; 1804 1805 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1806 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1807 1808 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1809 interrupt-names = "msi"; 1810 #interrupt-cells = <1>; 1811 interrupt-map-mask = <0 0 0 0x7>; 1812 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1813 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1814 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1815 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1816 1817 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1818 <&gcc GCC_PCIE_3_AUX_CLK>, 1819 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1820 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1821 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1822 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 1823 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1824 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1825 clock-names = "pipe", 1826 "aux", 1827 "cfg", 1828 "bus_master", 1829 "bus_slave", 1830 "slave_q2a", 1831 "ref", 1832 "tbu"; 1833 1834 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1835 assigned-clock-rates = <19200000>; 1836 1837 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1838 <0x100 &apps_smmu 0x1e01 0x1>; 1839 1840 resets = <&gcc GCC_PCIE_3_BCR>; 1841 reset-names = "pci"; 1842 1843 power-domains = <&gcc PCIE_3_GDSC>; 1844 1845 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1847 interconnect-names = "pcie-mem", "cpu-pcie"; 1848 1849 phys = <&pcie3_phy>; 1850 phy-names = "pciephy"; 1851 dma-coherent; 1852 1853 status = "disabled"; 1854 }; 1855 1856 pcie3_phy: phy@1c0c000 { 1857 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1858 reg = <0 0x01c0c000 0 0x1000>; 1859 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1860 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1861 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1862 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, 1863 <&gcc GCC_PCIE_3_PIPE_CLK>; 1864 clock-names = "aux", 1865 "cfg_ahb", 1866 "ref", 1867 "refgen", 1868 "pipe"; 1869 #clock-cells = <0>; 1870 clock-output-names = "pcie_3_pipe_clk"; 1871 1872 #phy-cells = <0>; 1873 1874 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1875 reset-names = "phy"; 1876 1877 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1878 assigned-clock-rates = <100000000>; 1879 1880 status = "disabled"; 1881 }; 1882 1883 pcie1: pcie@1c10000 { 1884 compatible = "qcom,pcie-sc8180x"; 1885 reg = <0 0x01c10000 0 0x3000>, 1886 <0 0x68000000 0 0xf1d>, 1887 <0 0x68000f20 0 0xa8>, 1888 <0 0x68001000 0 0x1000>, 1889 <0 0x68100000 0 0x100000>; 1890 reg-names = "parf", 1891 "dbi", 1892 "elbi", 1893 "atu", 1894 "config"; 1895 device_type = "pci"; 1896 linux,pci-domain = <1>; 1897 bus-range = <0x00 0xff>; 1898 num-lanes = <2>; 1899 1900 #address-cells = <3>; 1901 #size-cells = <2>; 1902 1903 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1904 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1905 1906 interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; 1907 interrupt-names = "msi"; 1908 #interrupt-cells = <1>; 1909 interrupt-map-mask = <0 0 0 0x7>; 1910 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1911 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1912 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1913 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1914 1915 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1916 <&gcc GCC_PCIE_1_AUX_CLK>, 1917 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1918 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1919 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1920 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1921 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1922 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1923 clock-names = "pipe", 1924 "aux", 1925 "cfg", 1926 "bus_master", 1927 "bus_slave", 1928 "slave_q2a", 1929 "ref", 1930 "tbu"; 1931 1932 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1933 assigned-clock-rates = <19200000>; 1934 1935 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1936 <0x100 &apps_smmu 0x1c81 0x1>; 1937 1938 resets = <&gcc GCC_PCIE_1_BCR>; 1939 reset-names = "pci"; 1940 1941 power-domains = <&gcc PCIE_1_GDSC>; 1942 1943 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 1944 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1945 interconnect-names = "pcie-mem", "cpu-pcie"; 1946 1947 phys = <&pcie1_phy>; 1948 phy-names = "pciephy"; 1949 dma-coherent; 1950 1951 status = "disabled"; 1952 }; 1953 1954 pcie1_phy: phy@1c16000 { 1955 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1956 reg = <0 0x01c16000 0 0x1000>; 1957 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1958 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1959 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1960 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 1961 <&gcc GCC_PCIE_1_PIPE_CLK>; 1962 clock-names = "aux", 1963 "cfg_ahb", 1964 "ref", 1965 "refgen", 1966 "pipe"; 1967 #clock-cells = <0>; 1968 clock-output-names = "pcie_1_pipe_clk"; 1969 1970 #phy-cells = <0>; 1971 1972 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1973 reset-names = "phy"; 1974 1975 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1976 assigned-clock-rates = <100000000>; 1977 1978 status = "disabled"; 1979 }; 1980 1981 pcie2: pcie@1c18000 { 1982 compatible = "qcom,pcie-sc8180x"; 1983 reg = <0 0x01c18000 0 0x3000>, 1984 <0 0x70000000 0 0xf1d>, 1985 <0 0x70000f20 0 0xa8>, 1986 <0 0x70001000 0 0x1000>, 1987 <0 0x70100000 0 0x100000>; 1988 reg-names = "parf", 1989 "dbi", 1990 "elbi", 1991 "atu", 1992 "config"; 1993 device_type = "pci"; 1994 linux,pci-domain = <2>; 1995 bus-range = <0x00 0xff>; 1996 num-lanes = <4>; 1997 1998 #address-cells = <3>; 1999 #size-cells = <2>; 2000 2001 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2002 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2003 2004 interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>; 2005 interrupt-names = "msi"; 2006 #interrupt-cells = <1>; 2007 interrupt-map-mask = <0 0 0 0x7>; 2008 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2009 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2010 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2011 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2012 2013 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2014 <&gcc GCC_PCIE_2_AUX_CLK>, 2015 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2016 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2017 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2018 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2019 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2020 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2021 clock-names = "pipe", 2022 "aux", 2023 "cfg", 2024 "bus_master", 2025 "bus_slave", 2026 "slave_q2a", 2027 "ref", 2028 "tbu"; 2029 2030 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2031 assigned-clock-rates = <19200000>; 2032 2033 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2034 <0x100 &apps_smmu 0x1d01 0x1>; 2035 2036 resets = <&gcc GCC_PCIE_2_BCR>; 2037 reset-names = "pci"; 2038 2039 power-domains = <&gcc PCIE_2_GDSC>; 2040 2041 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2042 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 2043 interconnect-names = "pcie-mem", "cpu-pcie"; 2044 2045 phys = <&pcie2_phy>; 2046 phy-names = "pciephy"; 2047 dma-coherent; 2048 2049 status = "disabled"; 2050 }; 2051 2052 pcie2_phy: phy@1c1c000 { 2053 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2054 reg = <0 0x01c1c000 0 0x1000>; 2055 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2056 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2057 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2058 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2059 <&gcc GCC_PCIE_2_PIPE_CLK>; 2060 clock-names = "aux", 2061 "cfg_ahb", 2062 "ref", 2063 "refgen", 2064 "pipe"; 2065 #clock-cells = <0>; 2066 clock-output-names = "pcie_2_pipe_clk"; 2067 2068 #phy-cells = <0>; 2069 2070 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2071 reset-names = "phy"; 2072 2073 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2074 assigned-clock-rates = <100000000>; 2075 2076 status = "disabled"; 2077 }; 2078 2079 ufs_mem_hc: ufshc@1d84000 { 2080 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2081 "jedec,ufs-2.0"; 2082 reg = <0 0x01d84000 0 0x2500>; 2083 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2084 phys = <&ufs_mem_phy>; 2085 phy-names = "ufsphy"; 2086 lanes-per-direction = <2>; 2087 #reset-cells = <1>; 2088 resets = <&gcc GCC_UFS_PHY_BCR>; 2089 reset-names = "rst"; 2090 2091 iommus = <&apps_smmu 0x300 0>; 2092 2093 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2094 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2095 <&gcc GCC_UFS_PHY_AHB_CLK>, 2096 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2097 <&rpmhcc RPMH_CXO_CLK>, 2098 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2099 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2100 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2101 clock-names = "core_clk", 2102 "bus_aggr_clk", 2103 "iface_clk", 2104 "core_clk_unipro", 2105 "ref_clk", 2106 "tx_lane0_sync_clk", 2107 "rx_lane0_sync_clk", 2108 "rx_lane1_sync_clk"; 2109 freq-table-hz = <37500000 300000000>, 2110 <0 0>, 2111 <0 0>, 2112 <37500000 300000000>, 2113 <0 0>, 2114 <0 0>, 2115 <0 0>, 2116 <0 0>; 2117 2118 power-domains = <&gcc UFS_PHY_GDSC>; 2119 2120 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2121 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2122 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2123 &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>; 2124 interconnect-names = "ufs-ddr", "cpu-ufs"; 2125 2126 status = "disabled"; 2127 }; 2128 2129 ufs_mem_phy: phy-wrapper@1d87000 { 2130 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2131 reg = <0 0x01d87000 0 0x1000>; 2132 2133 clocks = <&rpmhcc RPMH_CXO_CLK>, 2134 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2135 clock-names = "ref", 2136 "ref_aux"; 2137 2138 resets = <&ufs_mem_hc 0>; 2139 reset-names = "ufsphy"; 2140 2141 #phy-cells = <0>; 2142 2143 status = "disabled"; 2144 }; 2145 2146 ipa_virt: interconnect@1e00000 { 2147 compatible = "qcom,sc8180x-ipa-virt"; 2148 reg = <0 0x01e00000 0 0x1000>; 2149 #interconnect-cells = <2>; 2150 qcom,bcm-voters = <&apps_bcm_voter>; 2151 }; 2152 2153 tcsr_mutex: hwlock@1f40000 { 2154 compatible = "qcom,tcsr-mutex"; 2155 reg = <0x0 0x01f40000 0x0 0x40000>; 2156 #hwlock-cells = <1>; 2157 }; 2158 2159 gpu: gpu@2c00000 { 2160 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2161 #stream-id-cells = <16>; 2162 2163 reg = <0 0x02c00000 0 0x40000>; 2164 reg-names = "kgsl_3d0_reg_memory"; 2165 2166 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2167 2168 iommus = <&adreno_smmu 0 0xc01>; 2169 2170 operating-points-v2 = <&gpu_opp_table>; 2171 2172 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2173 interconnect-names = "gfx-mem"; 2174 2175 qcom,gmu = <&gmu>; 2176 status = "disabled"; 2177 2178 gpu_opp_table: opp-table { 2179 compatible = "operating-points-v2"; 2180 2181 opp-514000000 { 2182 opp-hz = /bits/ 64 <514000000>; 2183 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2184 }; 2185 2186 opp-500000000 { 2187 opp-hz = /bits/ 64 <500000000>; 2188 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2189 }; 2190 2191 opp-461000000 { 2192 opp-hz = /bits/ 64 <461000000>; 2193 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2194 }; 2195 2196 opp-405000000 { 2197 opp-hz = /bits/ 64 <405000000>; 2198 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2199 }; 2200 2201 opp-315000000 { 2202 opp-hz = /bits/ 64 <315000000>; 2203 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2204 }; 2205 2206 opp-256000000 { 2207 opp-hz = /bits/ 64 <256000000>; 2208 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2209 }; 2210 2211 opp-177000000 { 2212 opp-hz = /bits/ 64 <177000000>; 2213 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2214 }; 2215 }; 2216 }; 2217 2218 gmu: gmu@2c6a000 { 2219 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2220 2221 reg = <0 0x02c6a000 0 0x30000>, 2222 <0 0x0b290000 0 0x10000>, 2223 <0 0x0b490000 0 0x10000>; 2224 reg-names = "gmu", 2225 "gmu_pdc", 2226 "gmu_pdc_seq"; 2227 2228 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2230 interrupt-names = "hfi", "gmu"; 2231 2232 clocks = <&gpucc GPU_CC_AHB_CLK>, 2233 <&gpucc GPU_CC_CX_GMU_CLK>, 2234 <&gpucc GPU_CC_CXO_CLK>, 2235 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2236 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2237 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2238 2239 power-domains = <&gpucc GPU_CX_GDSC>, 2240 <&gpucc GPU_GX_GDSC>; 2241 power-domain-names = "cx", "gx"; 2242 2243 iommus = <&adreno_smmu 5 0xc00>; 2244 2245 operating-points-v2 = <&gmu_opp_table>; 2246 2247 gmu_opp_table: opp-table { 2248 compatible = "operating-points-v2"; 2249 2250 opp-200000000 { 2251 opp-hz = /bits/ 64 <200000000>; 2252 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2253 }; 2254 2255 opp-500000000 { 2256 opp-hz = /bits/ 64 <500000000>; 2257 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2258 }; 2259 }; 2260 }; 2261 2262 gpucc: clock-controller@2c90000 { 2263 compatible = "qcom,sc8180x-gpucc"; 2264 reg = <0 0x02c90000 0 0x9000>; 2265 clocks = <&rpmhcc RPMH_CXO_CLK>, 2266 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2267 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2268 clock-names = "bi_tcxo", 2269 "gcc_gpu_gpll0_clk_src", 2270 "gcc_gpu_gpll0_div_clk_src"; 2271 #clock-cells = <1>; 2272 #reset-cells = <1>; 2273 #power-domain-cells = <1>; 2274 }; 2275 2276 adreno_smmu: iommu@2ca0000 { 2277 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2278 "qcom,smmu-500", "arm,mmu-500"; 2279 reg = <0 0x02ca0000 0 0x10000>; 2280 #iommu-cells = <2>; 2281 #global-interrupts = <1>; 2282 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2283 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2284 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2285 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2286 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2287 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2288 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2289 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2290 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2291 clocks = <&gpucc GPU_CC_AHB_CLK>, 2292 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2293 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2294 clock-names = "ahb", "bus", "iface"; 2295 2296 power-domains = <&gpucc GPU_CX_GDSC>; 2297 }; 2298 2299 tlmm: pinctrl@3100000 { 2300 compatible = "qcom,sc8180x-tlmm"; 2301 reg = <0 0x03100000 0 0x300000>, 2302 <0 0x03500000 0 0x700000>, 2303 <0 0x03d00000 0 0x300000>; 2304 reg-names = "west", "east", "south"; 2305 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2306 gpio-controller; 2307 #gpio-cells = <2>; 2308 interrupt-controller; 2309 #interrupt-cells = <2>; 2310 gpio-ranges = <&tlmm 0 0 191>; 2311 wakeup-parent = <&pdc>; 2312 }; 2313 2314 remoteproc_mpss: remoteproc@4080000 { 2315 compatible = "qcom,sc8180x-mpss-pas"; 2316 reg = <0x0 0x04080000 0x0 0x4040>; 2317 2318 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2319 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2320 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2321 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2322 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2323 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2324 interrupt-names = "wdog", "fatal", "ready", "handover", 2325 "stop-ack", "shutdown-ack"; 2326 2327 clocks = <&rpmhcc RPMH_CXO_CLK>; 2328 clock-names = "xo"; 2329 2330 power-domains = <&rpmhpd SC8180X_CX>, 2331 <&rpmhpd SC8180X_MSS>; 2332 power-domain-names = "cx", "mss"; 2333 2334 qcom,qmp = <&aoss_qmp>; 2335 2336 qcom,smem-states = <&modem_smp2p_out 0>; 2337 qcom,smem-state-names = "stop"; 2338 2339 glink-edge { 2340 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2341 label = "modem"; 2342 qcom,remote-pid = <1>; 2343 mboxes = <&apss_shared 12>; 2344 }; 2345 }; 2346 2347 remoteproc_cdsp: remoteproc@8300000 { 2348 compatible = "qcom,sc8180x-cdsp-pas"; 2349 reg = <0x0 0x08300000 0x0 0x4040>; 2350 2351 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2352 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2353 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2354 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2355 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2356 interrupt-names = "wdog", "fatal", "ready", 2357 "handover", "stop-ack"; 2358 2359 clocks = <&rpmhcc RPMH_CXO_CLK>; 2360 clock-names = "xo"; 2361 2362 power-domains = <&rpmhpd SC8180X_CX>; 2363 power-domain-names = "cx"; 2364 2365 qcom,qmp = <&aoss_qmp>; 2366 2367 qcom,smem-states = <&cdsp_smp2p_out 0>; 2368 qcom,smem-state-names = "stop"; 2369 2370 status = "disabled"; 2371 2372 glink-edge { 2373 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2374 label = "cdsp"; 2375 qcom,remote-pid = <5>; 2376 mboxes = <&apss_shared 4>; 2377 }; 2378 }; 2379 2380 usb_prim_hsphy: phy@88e2000 { 2381 compatible = "qcom,sc8180x-usb-hs-phy", 2382 "qcom,usb-snps-hs-7nm-phy"; 2383 reg = <0 0x088e2000 0 0x400>; 2384 clocks = <&rpmhcc RPMH_CXO_CLK>; 2385 clock-names = "ref"; 2386 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2387 2388 #phy-cells = <0>; 2389 2390 status = "disabled"; 2391 }; 2392 2393 usb_sec_hsphy: phy@88e3000 { 2394 compatible = "qcom,sc8180x-usb-hs-phy", 2395 "qcom,usb-snps-hs-7nm-phy"; 2396 reg = <0 0x088e3000 0 0x400>; 2397 clocks = <&rpmhcc RPMH_CXO_CLK>; 2398 clock-names = "ref"; 2399 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2400 2401 #phy-cells = <0>; 2402 2403 status = "disabled"; 2404 }; 2405 2406 usb_prim_qmpphy: phy@88e9000 { 2407 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2408 reg = <0 0x088e9000 0 0x18c>, 2409 <0 0x088e8000 0 0x38>, 2410 <0 0x088ea000 0 0x40>; 2411 reg-names = "reg-base", "dp_com"; 2412 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2413 <&rpmhcc RPMH_CXO_CLK>, 2414 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2415 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2416 clock-names = "aux", 2417 "ref_clk_src", 2418 "ref", 2419 "com_aux"; 2420 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2421 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2422 reset-names = "phy", "common"; 2423 2424 #clock-cells = <1>; 2425 #address-cells = <2>; 2426 #size-cells = <2>; 2427 ranges; 2428 2429 status = "disabled"; 2430 2431 ports { 2432 #address-cells = <1>; 2433 #size-cells = <0>; 2434 2435 port@0 { 2436 reg = <0>; 2437 2438 usb_prim_qmpphy_out: endpoint {}; 2439 }; 2440 2441 port@2 { 2442 reg = <2>; 2443 2444 usb_prim_qmpphy_dp_in: endpoint {}; 2445 }; 2446 }; 2447 2448 usb_prim_ssphy: usb3-phy@88e9200 { 2449 reg = <0 0x088e9200 0 0x200>, 2450 <0 0x088e9400 0 0x200>, 2451 <0 0x088e9c00 0 0x218>, 2452 <0 0x088e9600 0 0x200>, 2453 <0 0x088e9800 0 0x200>, 2454 <0 0x088e9a00 0 0x100>; 2455 #phy-cells = <0>; 2456 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2457 clock-names = "pipe0"; 2458 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 2459 }; 2460 2461 usb_prim_dpphy: dp-phy@88ea200 { 2462 reg = <0 0x088ea200 0 0x200>, 2463 <0 0x088ea400 0 0x200>, 2464 <0 0x088eaa00 0 0x200>, 2465 <0 0x088ea600 0 0x200>, 2466 <0 0x088ea800 0 0x200>; 2467 #clock-cells = <1>; 2468 #phy-cells = <0>; 2469 }; 2470 }; 2471 2472 usb_sec_qmpphy: phy@88ee000 { 2473 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2474 reg = <0 0x088ee000 0 0x18c>, 2475 <0 0x088ed000 0 0x10>, 2476 <0 0x088ef000 0 0x40>; 2477 reg-names = "reg-base", "dp_com"; 2478 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2479 <&rpmhcc RPMH_CXO_CLK>, 2480 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2481 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2482 clock-names = "aux", 2483 "ref_clk_src", 2484 "ref", 2485 "com_aux"; 2486 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2487 <&gcc GCC_USB3_PHY_SEC_BCR>; 2488 reset-names = "phy", "common"; 2489 2490 #clock-cells = <1>; 2491 #address-cells = <2>; 2492 #size-cells = <2>; 2493 ranges; 2494 2495 status = "disabled"; 2496 2497 ports { 2498 #address-cells = <1>; 2499 #size-cells = <0>; 2500 2501 port@0 { 2502 reg = <0>; 2503 2504 usb_sec_qmpphy_out: endpoint {}; 2505 }; 2506 2507 port@2 { 2508 reg = <2>; 2509 2510 usb_sec_qmpphy_dp_in: endpoint {}; 2511 }; 2512 }; 2513 2514 usb_sec_ssphy: usb3-phy@88e9200 { 2515 reg = <0 0x088ee200 0 0x200>, 2516 <0 0x088ee400 0 0x200>, 2517 <0 0x088eec00 0 0x218>, 2518 <0 0x088ee600 0 0x200>, 2519 <0 0x088ee800 0 0x200>, 2520 <0 0x088eea00 0 0x100>; 2521 #phy-cells = <0>; 2522 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2523 clock-names = "pipe0"; 2524 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 2525 }; 2526 2527 usb_sec_dpphy: dp-phy@88ef200 { 2528 reg = <0 0x088ef200 0 0x200>, 2529 <0 0x088ef400 0 0x200>, 2530 <0 0x088efa00 0 0x200>, 2531 <0 0x088ef600 0 0x200>, 2532 <0 0x088ef800 0 0x200>; 2533 #clock-cells = <1>; 2534 #phy-cells = <0>; 2535 clock-output-names = "qmp_dptx1_phy_pll_link_clk", 2536 "qmp_dptx1_phy_pll_vco_div_clk"; 2537 }; 2538 }; 2539 2540 system-cache-controller@9200000 { 2541 compatible = "qcom,sc8180x-llcc"; 2542 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 2543 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 2544 <0 0x09600000 0 0x50000>; 2545 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2546 "llcc3_base", "llcc_broadcast_base"; 2547 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2548 }; 2549 2550 gem_noc: interconnect@9680000 { 2551 compatible = "qcom,sc8180x-gem-noc"; 2552 reg = <0 0x09680000 0 0x58200>; 2553 #interconnect-cells = <2>; 2554 qcom,bcm-voters = <&apps_bcm_voter>; 2555 }; 2556 2557 usb_prim: usb@a6f8800 { 2558 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2559 reg = <0 0x0a6f8800 0 0x400>; 2560 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2561 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2562 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2563 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2564 interrupt-names = "hs_phy_irq", 2565 "ss_phy_irq", 2566 "dm_hs_phy_irq", 2567 "dp_hs_phy_irq"; 2568 2569 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2570 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2571 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2572 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2573 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2574 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2575 clock-names = "cfg_noc", 2576 "core", 2577 "iface", 2578 "sleep", 2579 "mock_utmi", 2580 "xo"; 2581 resets = <&gcc GCC_USB30_PRIM_BCR>; 2582 power-domains = <&gcc USB30_PRIM_GDSC>; 2583 2584 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2585 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2586 interconnect-names = "usb-ddr", "apps-usb"; 2587 2588 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2589 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2590 assigned-clock-rates = <19200000>, <200000000>; 2591 2592 #address-cells = <2>; 2593 #size-cells = <2>; 2594 ranges; 2595 dma-ranges; 2596 2597 status = "disabled"; 2598 2599 usb_prim_dwc3: usb@a600000 { 2600 compatible = "snps,dwc3"; 2601 reg = <0 0x0a600000 0 0xcd00>; 2602 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2603 iommus = <&apps_smmu 0x140 0>; 2604 snps,dis_u2_susphy_quirk; 2605 snps,dis_enblslpm_quirk; 2606 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; 2607 phy-names = "usb2-phy", "usb3-phy"; 2608 2609 port { 2610 usb_prim_role_switch: endpoint { 2611 }; 2612 }; 2613 }; 2614 }; 2615 2616 usb_sec: usb@a8f8800 { 2617 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2618 reg = <0 0x0a8f8800 0 0x400>; 2619 2620 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2621 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2622 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2623 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2624 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2625 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2626 clock-names = "cfg_noc", 2627 "core", 2628 "iface", 2629 "sleep", 2630 "mock_utmi", 2631 "xo"; 2632 resets = <&gcc GCC_USB30_SEC_BCR>; 2633 power-domains = <&gcc USB30_SEC_GDSC>; 2634 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2635 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 2636 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2637 <&pdc 11 IRQ_TYPE_EDGE_BOTH>; 2638 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2639 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2640 2641 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2642 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2643 assigned-clock-rates = <19200000>, <200000000>; 2644 2645 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2646 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2647 interconnect-names = "usb-ddr", "apps-usb"; 2648 2649 #address-cells = <2>; 2650 #size-cells = <2>; 2651 ranges; 2652 dma-ranges; 2653 2654 status = "disabled"; 2655 2656 usb_sec_dwc3: usb@a800000 { 2657 compatible = "snps,dwc3"; 2658 reg = <0 0x0a800000 0 0xcd00>; 2659 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2660 iommus = <&apps_smmu 0x160 0>; 2661 snps,dis_u2_susphy_quirk; 2662 snps,dis_enblslpm_quirk; 2663 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; 2664 phy-names = "usb2-phy", "usb3-phy"; 2665 2666 port { 2667 usb_sec_role_switch: endpoint { 2668 }; 2669 }; 2670 }; 2671 }; 2672 2673 mdss: mdss@ae00000 { 2674 compatible = "qcom,sc8180x-mdss"; 2675 reg = <0 0x0ae00000 0 0x1000>; 2676 reg-names = "mdss"; 2677 2678 power-domains = <&dispcc MDSS_GDSC>; 2679 2680 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2681 <&gcc GCC_DISP_HF_AXI_CLK>, 2682 <&gcc GCC_DISP_SF_AXI_CLK>, 2683 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2684 clock-names = "iface", 2685 "bus", 2686 "nrt_bus", 2687 "core"; 2688 2689 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2690 2691 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2692 interrupt-controller; 2693 #interrupt-cells = <1>; 2694 2695 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 2696 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 2697 interconnect-names = "mdp0-mem", "mdp1-mem"; 2698 2699 iommus = <&apps_smmu 0x800 0x420>; 2700 2701 #address-cells = <2>; 2702 #size-cells = <2>; 2703 ranges; 2704 2705 status = "disabled"; 2706 2707 mdss_mdp: mdp@ae01000 { 2708 compatible = "qcom,sc8180x-dpu"; 2709 reg = <0 0x0ae01000 0 0x8f000>, 2710 <0 0x0aeb0000 0 0x2008>; 2711 reg-names = "mdp", "vbif"; 2712 2713 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2714 <&gcc GCC_DISP_HF_AXI_CLK>, 2715 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2716 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2717 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2718 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; 2719 clock-names = "iface", 2720 "bus", 2721 "core", 2722 "vsync", 2723 "rot", 2724 "lut"; 2725 2726 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2727 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2728 assigned-clock-rates = <460000000>, 2729 <19200000>; 2730 2731 operating-points-v2 = <&mdp_opp_table>; 2732 power-domains = <&rpmhpd SC8180X_MMCX>; 2733 2734 interrupt-parent = <&mdss>; 2735 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2736 2737 ports { 2738 #address-cells = <1>; 2739 #size-cells = <0>; 2740 2741 port@0 { 2742 reg = <0>; 2743 dpu_intf0_out: endpoint { 2744 remote-endpoint = <&dp0_in>; 2745 }; 2746 }; 2747 2748 port@1 { 2749 reg = <1>; 2750 dpu_intf1_out: endpoint { 2751 remote-endpoint = <&mdss_dsi0_in>; 2752 }; 2753 }; 2754 2755 port@2 { 2756 reg = <2>; 2757 dpu_intf2_out: endpoint { 2758 remote-endpoint = <&mdss_dsi1_in>; 2759 }; 2760 }; 2761 2762 port@4 { 2763 reg = <4>; 2764 dpu_intf4_out: endpoint { 2765 remote-endpoint = <&dp1_in>; 2766 }; 2767 }; 2768 2769 port@5 { 2770 reg = <5>; 2771 dpu_intf5_out: endpoint { 2772 remote-endpoint = <&edp_in>; 2773 }; 2774 }; 2775 }; 2776 2777 mdp_opp_table: opp-table { 2778 compatible = "operating-points-v2"; 2779 2780 opp-200000000 { 2781 opp-hz = /bits/ 64 <200000000>; 2782 required-opps = <&rpmhpd_opp_low_svs>; 2783 }; 2784 2785 opp-300000000 { 2786 opp-hz = /bits/ 64 <300000000>; 2787 required-opps = <&rpmhpd_opp_svs>; 2788 }; 2789 2790 opp-345000000 { 2791 opp-hz = /bits/ 64 <345000000>; 2792 required-opps = <&rpmhpd_opp_svs_l1>; 2793 }; 2794 2795 opp-460000000 { 2796 opp-hz = /bits/ 64 <460000000>; 2797 required-opps = <&rpmhpd_opp_nom>; 2798 }; 2799 }; 2800 }; 2801 2802 mdss_dsi0: dsi@ae94000 { 2803 compatible = "qcom,mdss-dsi-ctrl"; 2804 reg = <0 0x0ae94000 0 0x400>; 2805 reg-names = "dsi_ctrl"; 2806 2807 interrupt-parent = <&mdss>; 2808 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2809 2810 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2811 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2812 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2813 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2814 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2815 <&gcc GCC_DISP_HF_AXI_CLK>; 2816 clock-names = "byte", 2817 "byte_intf", 2818 "pixel", 2819 "core", 2820 "iface", 2821 "bus"; 2822 2823 operating-points-v2 = <&dsi_opp_table>; 2824 power-domains = <&rpmhpd SC8180X_MMCX>; 2825 2826 phys = <&mdss_dsi0_phy>; 2827 phy-names = "dsi"; 2828 2829 status = "disabled"; 2830 2831 ports { 2832 #address-cells = <1>; 2833 #size-cells = <0>; 2834 2835 port@0 { 2836 reg = <0>; 2837 mdss_dsi0_in: endpoint { 2838 remote-endpoint = <&dpu_intf1_out>; 2839 }; 2840 }; 2841 2842 port@1 { 2843 reg = <1>; 2844 mdss_dsi0_out: endpoint { 2845 }; 2846 }; 2847 }; 2848 2849 dsi_opp_table: opp-table { 2850 compatible = "operating-points-v2"; 2851 2852 opp-187500000 { 2853 opp-hz = /bits/ 64 <187500000>; 2854 required-opps = <&rpmhpd_opp_low_svs>; 2855 }; 2856 2857 opp-300000000 { 2858 opp-hz = /bits/ 64 <300000000>; 2859 required-opps = <&rpmhpd_opp_svs>; 2860 }; 2861 2862 opp-358000000 { 2863 opp-hz = /bits/ 64 <358000000>; 2864 required-opps = <&rpmhpd_opp_svs_l1>; 2865 }; 2866 }; 2867 }; 2868 2869 mdss_dsi0_phy: dsi-phy@ae94400 { 2870 compatible = "qcom,dsi-phy-7nm"; 2871 reg = <0 0x0ae94400 0 0x200>, 2872 <0 0x0ae94600 0 0x280>, 2873 <0 0x0ae94900 0 0x260>; 2874 reg-names = "dsi_phy", 2875 "dsi_phy_lane", 2876 "dsi_pll"; 2877 2878 #clock-cells = <1>; 2879 #phy-cells = <0>; 2880 2881 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2882 <&rpmhcc RPMH_CXO_CLK>; 2883 clock-names = "iface", "ref"; 2884 2885 status = "disabled"; 2886 }; 2887 2888 mdss_dsi1: dsi@ae96000 { 2889 compatible = "qcom,mdss-dsi-ctrl"; 2890 reg = <0 0x0ae96000 0 0x400>; 2891 reg-names = "dsi_ctrl"; 2892 2893 interrupt-parent = <&mdss>; 2894 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2895 2896 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2897 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2898 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2899 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2900 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2901 <&gcc GCC_DISP_HF_AXI_CLK>; 2902 clock-names = "byte", 2903 "byte_intf", 2904 "pixel", 2905 "core", 2906 "iface", 2907 "bus"; 2908 2909 operating-points-v2 = <&dsi_opp_table>; 2910 power-domains = <&rpmhpd SC8180X_MMCX>; 2911 2912 phys = <&mdss_dsi1_phy>; 2913 phy-names = "dsi"; 2914 2915 status = "disabled"; 2916 2917 ports { 2918 #address-cells = <1>; 2919 #size-cells = <0>; 2920 2921 port@0 { 2922 reg = <0>; 2923 mdss_dsi1_in: endpoint { 2924 remote-endpoint = <&dpu_intf2_out>; 2925 }; 2926 }; 2927 2928 port@1 { 2929 reg = <1>; 2930 mdss_dsi1_out: endpoint { 2931 }; 2932 }; 2933 }; 2934 }; 2935 2936 mdss_dsi1_phy: dsi-phy@ae96400 { 2937 compatible = "qcom,dsi-phy-7nm"; 2938 reg = <0 0x0ae96400 0 0x200>, 2939 <0 0x0ae96600 0 0x280>, 2940 <0 0x0ae96900 0 0x260>; 2941 reg-names = "dsi_phy", 2942 "dsi_phy_lane", 2943 "dsi_pll"; 2944 2945 #clock-cells = <1>; 2946 #phy-cells = <0>; 2947 2948 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2949 <&rpmhcc RPMH_CXO_CLK>; 2950 clock-names = "iface", "ref"; 2951 2952 status = "disabled"; 2953 }; 2954 2955 mdss_dp0: displayport-controller@ae90000 { 2956 compatible = "qcom,sc8180x-dp"; 2957 reg = <0 0xae90000 0 0x200>, 2958 <0 0xae90200 0 0x200>, 2959 <0 0xae90400 0 0x600>, 2960 <0 0xae90a00 0 0x400>; 2961 interrupt-parent = <&mdss>; 2962 interrupts = <12>; 2963 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2964 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2965 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2966 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2967 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2968 clock-names = "core_iface", 2969 "core_aux", 2970 "ctrl_link", 2971 "ctrl_link_iface", 2972 "stream_pixel"; 2973 2974 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2975 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2976 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; 2977 2978 phys = <&usb_prim_dpphy>; 2979 phy-names = "dp"; 2980 2981 #sound-dai-cells = <0>; 2982 2983 operating-points-v2 = <&dp0_opp_table>; 2984 power-domains = <&rpmhpd SC8180X_MMCX>; 2985 2986 status = "disabled"; 2987 2988 ports { 2989 #address-cells = <1>; 2990 #size-cells = <0>; 2991 2992 port@0 { 2993 reg = <0>; 2994 dp0_in: endpoint { 2995 remote-endpoint = <&dpu_intf0_out>; 2996 }; 2997 }; 2998 2999 port@1 { 3000 reg = <1>; 3001 mdss_dp0_out: endpoint { 3002 }; 3003 }; 3004 }; 3005 3006 dp0_opp_table: opp-table { 3007 compatible = "operating-points-v2"; 3008 3009 opp-160000000 { 3010 opp-hz = /bits/ 64 <160000000>; 3011 required-opps = <&rpmhpd_opp_low_svs>; 3012 }; 3013 3014 opp-270000000 { 3015 opp-hz = /bits/ 64 <270000000>; 3016 required-opps = <&rpmhpd_opp_svs>; 3017 }; 3018 3019 opp-540000000 { 3020 opp-hz = /bits/ 64 <540000000>; 3021 required-opps = <&rpmhpd_opp_svs_l1>; 3022 }; 3023 3024 opp-810000000 { 3025 opp-hz = /bits/ 64 <810000000>; 3026 required-opps = <&rpmhpd_opp_nom>; 3027 }; 3028 }; 3029 }; 3030 3031 mdss_dp1: displayport-controller@ae98000 { 3032 compatible = "qcom,sc8180x-dp"; 3033 reg = <0 0xae98000 0 0x200>, 3034 <0 0xae98200 0 0x200>, 3035 <0 0xae98400 0 0x600>, 3036 <0 0xae98a00 0 0x400>; 3037 interrupt-parent = <&mdss>; 3038 interrupts = <13>; 3039 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3040 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3041 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3042 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3043 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; 3044 clock-names = "core_iface", 3045 "core_aux", 3046 "ctrl_link", 3047 "ctrl_link_iface", 3048 "stream_pixel"; 3049 3050 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3051 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; 3052 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; 3053 3054 phys = <&usb_sec_dpphy>; 3055 phy-names = "dp"; 3056 3057 #sound-dai-cells = <0>; 3058 3059 operating-points-v2 = <&dp0_opp_table>; 3060 power-domains = <&rpmhpd SC8180X_MMCX>; 3061 3062 status = "disabled"; 3063 3064 ports { 3065 #address-cells = <1>; 3066 #size-cells = <0>; 3067 3068 port@0 { 3069 reg = <0>; 3070 dp1_in: endpoint { 3071 remote-endpoint = <&dpu_intf4_out>; 3072 }; 3073 }; 3074 3075 port@1 { 3076 reg = <1>; 3077 mdss_dp1_out: endpoint { 3078 }; 3079 }; 3080 }; 3081 3082 dp1_opp_table: opp-table { 3083 compatible = "operating-points-v2"; 3084 3085 opp-160000000 { 3086 opp-hz = /bits/ 64 <160000000>; 3087 required-opps = <&rpmhpd_opp_low_svs>; 3088 }; 3089 3090 opp-270000000 { 3091 opp-hz = /bits/ 64 <270000000>; 3092 required-opps = <&rpmhpd_opp_svs>; 3093 }; 3094 3095 opp-540000000 { 3096 opp-hz = /bits/ 64 <540000000>; 3097 required-opps = <&rpmhpd_opp_svs_l1>; 3098 }; 3099 3100 opp-810000000 { 3101 opp-hz = /bits/ 64 <810000000>; 3102 required-opps = <&rpmhpd_opp_nom>; 3103 }; 3104 }; 3105 }; 3106 3107 mdss_edp: displayport-controller@ae9a000 { 3108 compatible = "qcom,sc8180x-edp"; 3109 reg = <0 0xae9a000 0 0x200>, 3110 <0 0xae9a200 0 0x200>, 3111 <0 0xae9a400 0 0x600>, 3112 <0 0xae9aa00 0 0x400>; 3113 interrupt-parent = <&mdss>; 3114 interrupts = <14>; 3115 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3116 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3117 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3118 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3119 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3120 clock-names = "core_iface", 3121 "core_aux", 3122 "ctrl_link", 3123 "ctrl_link_iface", 3124 "stream_pixel"; 3125 3126 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3127 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3128 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3129 3130 phys = <&edp_phy>; 3131 phy-names = "dp"; 3132 3133 operating-points-v2 = <&edp_opp_table>; 3134 power-domains = <&rpmhpd SC8180X_MMCX>; 3135 3136 status = "disabled"; 3137 3138 ports { 3139 #address-cells = <1>; 3140 #size-cells = <0>; 3141 3142 port@0 { 3143 reg = <0>; 3144 edp_in: endpoint { 3145 remote-endpoint = <&dpu_intf5_out>; 3146 }; 3147 }; 3148 }; 3149 3150 edp_opp_table: opp-table { 3151 compatible = "operating-points-v2"; 3152 3153 opp-160000000 { 3154 opp-hz = /bits/ 64 <160000000>; 3155 required-opps = <&rpmhpd_opp_low_svs>; 3156 }; 3157 3158 opp-270000000 { 3159 opp-hz = /bits/ 64 <270000000>; 3160 required-opps = <&rpmhpd_opp_svs>; 3161 }; 3162 3163 opp-540000000 { 3164 opp-hz = /bits/ 64 <540000000>; 3165 required-opps = <&rpmhpd_opp_svs_l1>; 3166 }; 3167 3168 opp-810000000 { 3169 opp-hz = /bits/ 64 <810000000>; 3170 required-opps = <&rpmhpd_opp_nom>; 3171 }; 3172 }; 3173 }; 3174 }; 3175 3176 edp_phy: phy@aec2a00 { 3177 compatible = "qcom,sc8180x-edp-phy"; 3178 reg = <0 0x0aec2a00 0 0x1c0>, 3179 <0 0x0aec2200 0 0xa0>, 3180 <0 0x0aec2600 0 0xa0>, 3181 <0 0x0aec2000 0 0x19c>; 3182 3183 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3184 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3185 clock-names = "aux", "cfg_ahb"; 3186 3187 power-domains = <&dispcc MDSS_GDSC>; 3188 3189 #clock-cells = <1>; 3190 #phy-cells = <0>; 3191 }; 3192 3193 dispcc: clock-controller@af00000 { 3194 compatible = "qcom,sc8180x-dispcc"; 3195 reg = <0 0x0af00000 0 0x20000>; 3196 clocks = <&rpmhcc RPMH_CXO_CLK>, 3197 <&sleep_clk>, 3198 <&usb_prim_dpphy 0>, 3199 <&usb_prim_dpphy 1>, 3200 <&usb_sec_dpphy 0>, 3201 <&usb_sec_dpphy 1>, 3202 <&edp_phy 0>, 3203 <&edp_phy 1>; 3204 clock-names = "bi_tcxo", 3205 "sleep_clk", 3206 "dp_phy_pll_link_clk", 3207 "dp_phy_pll_vco_div_clk", 3208 "dptx1_phy_pll_link_clk", 3209 "dptx1_phy_pll_vco_div_clk", 3210 "edp_phy_pll_link_clk", 3211 "edp_phy_pll_vco_div_clk"; 3212 power-domains = <&rpmhpd SC8180X_MMCX>; 3213 #clock-cells = <1>; 3214 #reset-cells = <1>; 3215 #power-domain-cells = <1>; 3216 }; 3217 3218 pdc: interrupt-controller@b220000 { 3219 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3220 reg = <0 0x0b220000 0 0x30000>; 3221 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3222 #interrupt-cells = <2>; 3223 interrupt-parent = <&intc>; 3224 interrupt-controller; 3225 }; 3226 3227 tsens0: thermal-sensor@c263000 { 3228 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3229 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3230 <0 0x0c222000 0 0x1ff>; /* SROT */ 3231 #qcom,sensors = <16>; 3232 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3234 interrupt-names = "uplow", "critical"; 3235 #thermal-sensor-cells = <1>; 3236 }; 3237 3238 tsens1: thermal-sensor@c265000 { 3239 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3240 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3241 <0 0x0c223000 0 0x1ff>; /* SROT */ 3242 #qcom,sensors = <9>; 3243 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3245 interrupt-names = "uplow", "critical"; 3246 #thermal-sensor-cells = <1>; 3247 }; 3248 3249 aoss_qmp: power-controller@c300000 { 3250 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3251 reg = <0x0 0x0c300000 0x0 0x100000>; 3252 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3253 mboxes = <&apss_shared 0>; 3254 3255 #clock-cells = <0>; 3256 #power-domain-cells = <1>; 3257 }; 3258 3259 spmi_bus: spmi@c440000 { 3260 compatible = "qcom,spmi-pmic-arb"; 3261 reg = <0x0 0x0c440000 0x0 0x0001100>, 3262 <0x0 0x0c600000 0x0 0x2000000>, 3263 <0x0 0x0e600000 0x0 0x0100000>, 3264 <0x0 0x0e700000 0x0 0x00a0000>, 3265 <0x0 0x0c40a000 0x0 0x0026000>; 3266 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3267 interrupt-names = "periph_irq"; 3268 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3269 qcom,ee = <0>; 3270 qcom,channel = <0>; 3271 #address-cells = <2>; 3272 #size-cells = <0>; 3273 interrupt-controller; 3274 #interrupt-cells = <4>; 3275 }; 3276 3277 apps_smmu: iommu@15000000 { 3278 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3279 reg = <0 0x15000000 0 0x100000>; 3280 #iommu-cells = <2>; 3281 #global-interrupts = <1>; 3282 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3389 3390 }; 3391 3392 remoteproc_adsp: remoteproc@17300000 { 3393 compatible = "qcom,sc8180x-adsp-pas"; 3394 reg = <0x0 0x17300000 0x0 0x4040>; 3395 3396 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3397 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3398 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3399 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3400 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3401 interrupt-names = "wdog", "fatal", "ready", 3402 "handover", "stop-ack"; 3403 3404 clocks = <&rpmhcc RPMH_CXO_CLK>; 3405 clock-names = "xo"; 3406 3407 power-domains = <&rpmhpd SC8180X_CX>; 3408 power-domain-names = "cx"; 3409 3410 qcom,qmp = <&aoss_qmp>; 3411 3412 qcom,smem-states = <&adsp_smp2p_out 0>; 3413 qcom,smem-state-names = "stop"; 3414 3415 status = "disabled"; 3416 3417 remoteproc_adsp_glink: glink-edge { 3418 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3419 label = "lpass"; 3420 qcom,remote-pid = <2>; 3421 mboxes = <&apss_shared 8>; 3422 }; 3423 }; 3424 3425 intc: interrupt-controller@17a00000 { 3426 compatible = "arm,gic-v3"; 3427 interrupt-controller; 3428 #interrupt-cells = <3>; 3429 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3430 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3431 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3432 #redistributor-regions = <1>; 3433 redistributor-stride = <0 0x20000>; 3434 }; 3435 3436 apss_shared: mailbox@17c00000 { 3437 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared"; 3438 reg = <0x0 0x17c00000 0x0 0x1000>; 3439 #mbox-cells = <1>; 3440 }; 3441 3442 timer@17c20000 { 3443 compatible = "arm,armv7-timer-mem"; 3444 reg = <0x0 0x17c20000 0x0 0x1000>; 3445 3446 #address-cells = <1>; 3447 #size-cells = <1>; 3448 ranges = <0 0 0 0x20000000>; 3449 3450 frame@17c21000 { 3451 reg = <0x17c21000 0x1000>, 3452 <0x17c22000 0x1000>; 3453 frame-number = <0>; 3454 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3456 }; 3457 3458 frame@17c23000 { 3459 reg = <0x17c23000 0x1000>; 3460 frame-number = <1>; 3461 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3462 status = "disabled"; 3463 }; 3464 3465 frame@17c25000 { 3466 reg = <0x17c25000 0x1000>; 3467 frame-number = <2>; 3468 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3469 status = "disabled"; 3470 }; 3471 3472 frame@17c27000 { 3473 reg = <0x17c26000 0x1000>; 3474 frame-number = <3>; 3475 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3476 status = "disabled"; 3477 }; 3478 3479 frame@17c29000 { 3480 reg = <0x17c29000 0x1000>; 3481 frame-number = <4>; 3482 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3483 status = "disabled"; 3484 }; 3485 3486 frame@17c2b000 { 3487 reg = <0x17c2b000 0x1000>; 3488 frame-number = <5>; 3489 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3490 status = "disabled"; 3491 }; 3492 3493 frame@17c2d000 { 3494 reg = <0x17c2d000 0x1000>; 3495 frame-number = <6>; 3496 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3497 status = "disabled"; 3498 }; 3499 }; 3500 3501 apps_rsc: rsc@18200000 { 3502 compatible = "qcom,rpmh-rsc"; 3503 reg = <0x0 0x18200000 0x0 0x10000>, 3504 <0x0 0x18210000 0x0 0x10000>, 3505 <0x0 0x18220000 0x0 0x10000>; 3506 reg-names = "drv-0", "drv-1", "drv-2"; 3507 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3510 qcom,tcs-offset = <0xd00>; 3511 qcom,drv-id = <2>; 3512 qcom,tcs-config = <ACTIVE_TCS 2>, 3513 <SLEEP_TCS 1>, 3514 <WAKE_TCS 1>, 3515 <CONTROL_TCS 0>; 3516 label = "apps_rsc"; 3517 power-domains = <&CLUSTER_PD>; 3518 3519 apps_bcm_voter: bcm-voter { 3520 compatible = "qcom,bcm-voter"; 3521 }; 3522 3523 rpmhcc: clock-controller { 3524 compatible = "qcom,sc8180x-rpmh-clk"; 3525 #clock-cells = <1>; 3526 clock-names = "xo"; 3527 clocks = <&xo_board_clk>; 3528 }; 3529 3530 rpmhpd: power-controller { 3531 compatible = "qcom,sc8180x-rpmhpd"; 3532 #power-domain-cells = <1>; 3533 operating-points-v2 = <&rpmhpd_opp_table>; 3534 3535 rpmhpd_opp_table: opp-table { 3536 compatible = "operating-points-v2"; 3537 3538 rpmhpd_opp_ret: opp1 { 3539 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3540 }; 3541 3542 rpmhpd_opp_min_svs: opp2 { 3543 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3544 }; 3545 3546 rpmhpd_opp_low_svs: opp3 { 3547 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3548 }; 3549 3550 rpmhpd_opp_svs: opp4 { 3551 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3552 }; 3553 3554 rpmhpd_opp_svs_l1: opp5 { 3555 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3556 }; 3557 3558 rpmhpd_opp_nom: opp6 { 3559 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3560 }; 3561 3562 rpmhpd_opp_nom_l1: opp7 { 3563 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3564 }; 3565 3566 rpmhpd_opp_nom_l2: opp8 { 3567 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3568 }; 3569 3570 rpmhpd_opp_turbo: opp9 { 3571 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3572 }; 3573 3574 rpmhpd_opp_turbo_l1: opp10 { 3575 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3576 }; 3577 }; 3578 }; 3579 }; 3580 3581 osm_l3: interconnect@18321000 { 3582 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3583 reg = <0 0x18321000 0 0x1400>; 3584 3585 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3586 clock-names = "xo", "alternate"; 3587 3588 #interconnect-cells = <1>; 3589 }; 3590 3591 lmh@18350800 { 3592 compatible = "qcom,sc8180x-lmh"; 3593 reg = <0 0x18350800 0 0x400>; 3594 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3595 cpus = <&CPU4>; 3596 qcom,lmh-temp-arm-millicelsius = <65000>; 3597 qcom,lmh-temp-low-millicelsius = <94500>; 3598 qcom,lmh-temp-high-millicelsius = <95000>; 3599 interrupt-controller; 3600 #interrupt-cells = <1>; 3601 }; 3602 3603 lmh@18358800 { 3604 compatible = "qcom,sc8180x-lmh"; 3605 reg = <0 0x18358800 0 0x400>; 3606 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3607 cpus = <&CPU0>; 3608 qcom,lmh-temp-arm-millicelsius = <65000>; 3609 qcom,lmh-temp-low-millicelsius = <94500>; 3610 qcom,lmh-temp-high-millicelsius = <95000>; 3611 interrupt-controller; 3612 #interrupt-cells = <1>; 3613 }; 3614 3615 cpufreq_hw: cpufreq@18323000 { 3616 compatible = "qcom,cpufreq-hw"; 3617 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3618 reg-names = "freq-domain0", "freq-domain1"; 3619 3620 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3621 clock-names = "xo", "alternate"; 3622 3623 #freq-domain-cells = <1>; 3624 #clock-cells = <1>; 3625 }; 3626 3627 wifi: wifi@18800000 { 3628 compatible = "qcom,wcn3990-wifi"; 3629 reg = <0 0x18800000 0 0x800000>; 3630 reg-names = "membase"; 3631 clock-names = "cxo_ref_clk_pin"; 3632 clocks = <&rpmhcc RPMH_RF_CLK2>; 3633 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3645 iommus = <&apps_smmu 0x0640 0x1>; 3646 qcom,msa-fixed-perm; 3647 status = "disabled"; 3648 }; 3649 }; 3650 3651 thermal-zones { 3652 cpu0-thermal { 3653 polling-delay-passive = <250>; 3654 polling-delay = <1000>; 3655 3656 thermal-sensors = <&tsens0 1>; 3657 3658 trips { 3659 cpu-crit { 3660 temperature = <110000>; 3661 hysteresis = <1000>; 3662 type = "critical"; 3663 }; 3664 }; 3665 }; 3666 3667 cpu1-thermal { 3668 polling-delay-passive = <250>; 3669 polling-delay = <1000>; 3670 3671 thermal-sensors = <&tsens0 2>; 3672 3673 trips { 3674 cpu-crit { 3675 temperature = <110000>; 3676 hysteresis = <1000>; 3677 type = "critical"; 3678 }; 3679 }; 3680 }; 3681 3682 cpu2-thermal { 3683 polling-delay-passive = <250>; 3684 polling-delay = <1000>; 3685 3686 thermal-sensors = <&tsens0 3>; 3687 3688 trips { 3689 cpu-crit { 3690 temperature = <110000>; 3691 hysteresis = <1000>; 3692 type = "critical"; 3693 }; 3694 }; 3695 }; 3696 3697 cpu3-thermal { 3698 polling-delay-passive = <250>; 3699 polling-delay = <1000>; 3700 3701 thermal-sensors = <&tsens0 4>; 3702 3703 trips { 3704 cpu-crit { 3705 temperature = <110000>; 3706 hysteresis = <1000>; 3707 type = "critical"; 3708 }; 3709 }; 3710 }; 3711 3712 cpu4-top-thermal { 3713 polling-delay-passive = <250>; 3714 polling-delay = <1000>; 3715 3716 thermal-sensors = <&tsens0 7>; 3717 3718 trips { 3719 cpu-crit { 3720 temperature = <110000>; 3721 hysteresis = <1000>; 3722 type = "critical"; 3723 }; 3724 }; 3725 }; 3726 3727 cpu5-top-thermal { 3728 polling-delay-passive = <250>; 3729 polling-delay = <1000>; 3730 3731 thermal-sensors = <&tsens0 8>; 3732 3733 trips { 3734 cpu-crit { 3735 temperature = <110000>; 3736 hysteresis = <1000>; 3737 type = "critical"; 3738 }; 3739 }; 3740 }; 3741 3742 cpu6-top-thermal { 3743 polling-delay-passive = <250>; 3744 polling-delay = <1000>; 3745 3746 thermal-sensors = <&tsens0 9>; 3747 3748 trips { 3749 cpu-crit { 3750 temperature = <110000>; 3751 hysteresis = <1000>; 3752 type = "critical"; 3753 }; 3754 }; 3755 }; 3756 3757 cpu7-top-thermal { 3758 polling-delay-passive = <250>; 3759 polling-delay = <1000>; 3760 3761 thermal-sensors = <&tsens0 10>; 3762 3763 trips { 3764 cpu-crit { 3765 temperature = <110000>; 3766 hysteresis = <1000>; 3767 type = "critical"; 3768 }; 3769 }; 3770 }; 3771 3772 cpu4-bottom-thermal { 3773 polling-delay-passive = <250>; 3774 polling-delay = <1000>; 3775 3776 thermal-sensors = <&tsens0 11>; 3777 3778 trips { 3779 cpu-crit { 3780 temperature = <110000>; 3781 hysteresis = <1000>; 3782 type = "critical"; 3783 }; 3784 }; 3785 }; 3786 3787 cpu5-bottom-thermal { 3788 polling-delay-passive = <250>; 3789 polling-delay = <1000>; 3790 3791 thermal-sensors = <&tsens0 12>; 3792 3793 trips { 3794 cpu-crit { 3795 temperature = <110000>; 3796 hysteresis = <1000>; 3797 type = "critical"; 3798 }; 3799 }; 3800 }; 3801 3802 cpu6-bottom-thermal { 3803 polling-delay-passive = <250>; 3804 polling-delay = <1000>; 3805 3806 thermal-sensors = <&tsens0 13>; 3807 3808 trips { 3809 cpu-crit { 3810 temperature = <110000>; 3811 hysteresis = <1000>; 3812 type = "critical"; 3813 }; 3814 }; 3815 }; 3816 3817 cpu7-bottom-thermal { 3818 polling-delay-passive = <250>; 3819 polling-delay = <1000>; 3820 3821 thermal-sensors = <&tsens0 14>; 3822 3823 trips { 3824 cpu-crit { 3825 temperature = <110000>; 3826 hysteresis = <1000>; 3827 type = "critical"; 3828 }; 3829 }; 3830 }; 3831 3832 aoss0-thermal { 3833 polling-delay-passive = <250>; 3834 polling-delay = <1000>; 3835 3836 thermal-sensors = <&tsens0 0>; 3837 3838 trips { 3839 trip-point0 { 3840 temperature = <90000>; 3841 hysteresis = <2000>; 3842 type = "hot"; 3843 }; 3844 }; 3845 }; 3846 3847 cluster0-thermal { 3848 polling-delay-passive = <250>; 3849 polling-delay = <1000>; 3850 3851 thermal-sensors = <&tsens0 5>; 3852 3853 trips { 3854 cluster-crit { 3855 temperature = <110000>; 3856 hysteresis = <2000>; 3857 type = "critical"; 3858 }; 3859 }; 3860 }; 3861 3862 cluster1-thermal { 3863 polling-delay-passive = <250>; 3864 polling-delay = <1000>; 3865 3866 thermal-sensors = <&tsens0 6>; 3867 3868 trips { 3869 cluster-crit { 3870 temperature = <110000>; 3871 hysteresis = <2000>; 3872 type = "critical"; 3873 }; 3874 }; 3875 }; 3876 3877 gpu-top-thermal { 3878 polling-delay-passive = <250>; 3879 polling-delay = <1000>; 3880 3881 thermal-sensors = <&tsens0 15>; 3882 3883 trips { 3884 trip-point0 { 3885 temperature = <90000>; 3886 hysteresis = <2000>; 3887 type = "hot"; 3888 }; 3889 }; 3890 }; 3891 3892 aoss1-thermal { 3893 polling-delay-passive = <250>; 3894 polling-delay = <1000>; 3895 3896 thermal-sensors = <&tsens1 0>; 3897 3898 trips { 3899 trip-point0 { 3900 temperature = <90000>; 3901 hysteresis = <2000>; 3902 type = "hot"; 3903 }; 3904 }; 3905 }; 3906 3907 wlan-thermal { 3908 polling-delay-passive = <250>; 3909 polling-delay = <1000>; 3910 3911 thermal-sensors = <&tsens1 1>; 3912 3913 trips { 3914 trip-point0 { 3915 temperature = <90000>; 3916 hysteresis = <2000>; 3917 type = "hot"; 3918 }; 3919 }; 3920 }; 3921 3922 video-thermal { 3923 polling-delay-passive = <250>; 3924 polling-delay = <1000>; 3925 3926 thermal-sensors = <&tsens1 2>; 3927 3928 trips { 3929 trip-point0 { 3930 temperature = <90000>; 3931 hysteresis = <2000>; 3932 type = "hot"; 3933 }; 3934 }; 3935 }; 3936 3937 mem-thermal { 3938 polling-delay-passive = <250>; 3939 polling-delay = <1000>; 3940 3941 thermal-sensors = <&tsens1 3>; 3942 3943 trips { 3944 trip-point0 { 3945 temperature = <90000>; 3946 hysteresis = <2000>; 3947 type = "hot"; 3948 }; 3949 }; 3950 }; 3951 3952 q6-hvx-thermal { 3953 polling-delay-passive = <250>; 3954 polling-delay = <1000>; 3955 3956 thermal-sensors = <&tsens1 4>; 3957 3958 trips { 3959 trip-point0 { 3960 temperature = <90000>; 3961 hysteresis = <2000>; 3962 type = "hot"; 3963 }; 3964 }; 3965 }; 3966 3967 camera-thermal { 3968 polling-delay-passive = <250>; 3969 polling-delay = <1000>; 3970 3971 thermal-sensors = <&tsens1 5>; 3972 3973 trips { 3974 trip-point0 { 3975 temperature = <90000>; 3976 hysteresis = <2000>; 3977 type = "hot"; 3978 }; 3979 }; 3980 }; 3981 3982 compute-thermal { 3983 polling-delay-passive = <250>; 3984 polling-delay = <1000>; 3985 3986 thermal-sensors = <&tsens1 6>; 3987 3988 trips { 3989 trip-point0 { 3990 temperature = <90000>; 3991 hysteresis = <2000>; 3992 type = "hot"; 3993 }; 3994 }; 3995 }; 3996 3997 mdm-dsp-thermal { 3998 polling-delay-passive = <250>; 3999 polling-delay = <1000>; 4000 4001 thermal-sensors = <&tsens1 7>; 4002 4003 trips { 4004 trip-point0 { 4005 temperature = <90000>; 4006 hysteresis = <2000>; 4007 type = "hot"; 4008 }; 4009 }; 4010 }; 4011 4012 npu-thermal { 4013 polling-delay-passive = <250>; 4014 polling-delay = <1000>; 4015 4016 thermal-sensors = <&tsens1 8>; 4017 4018 trips { 4019 trip-point0 { 4020 temperature = <90000>; 4021 hysteresis = <2000>; 4022 type = "hot"; 4023 }; 4024 }; 4025 }; 4026 4027 gpu-bottom-thermal { 4028 polling-delay-passive = <250>; 4029 polling-delay = <1000>; 4030 4031 thermal-sensors = <&tsens1 11>; 4032 4033 trips { 4034 trip-point0 { 4035 temperature = <90000>; 4036 hysteresis = <2000>; 4037 type = "hot"; 4038 }; 4039 }; 4040 }; 4041 }; 4042 4043 timer { 4044 compatible = "arm,armv8-timer"; 4045 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4046 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4047 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4048 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4049 }; 4050}; 4051