1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * 4 * This file defines the common audio settings for the child boards 5 * using rt5682 codec and having 3 dmics connected to sc7280. 6 * 7 * Copyright 2022 Google LLC. 8 */ 9 10/ { 11 /* BOARD-SPECIFIC TOP LEVEL NODES */ 12 sound: sound { 13 compatible = "google,sc7280-herobrine"; 14 model = "sc7280-rt5682-max98360a-3mic"; 15 16 audio-routing = "VA DMIC0", "vdd-micb", 17 "VA DMIC1", "vdd-micb", 18 "VA DMIC2", "vdd-micb", 19 "VA DMIC3", "vdd-micb", 20 21 "Headphone Jack", "HPOL", 22 "Headphone Jack", "HPOR"; 23 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 dai-link@0 { 28 link-name = "MAX98360"; 29 reg = <0>; 30 31 cpu { 32 sound-dai = <&lpass_cpu MI2S_SECONDARY>; 33 }; 34 35 codec { 36 sound-dai = <&max98360a>; 37 }; 38 }; 39 40 dai-link@1 { 41 link-name = "DisplayPort"; 42 reg = <1>; 43 44 cpu { 45 sound-dai = <&lpass_cpu LPASS_DP_RX>; 46 }; 47 48 codec { 49 sound-dai = <&mdss_dp>; 50 }; 51 }; 52 53 dai-link@2 { 54 link-name = "ALC5682"; 55 reg = <2>; 56 57 cpu { 58 sound-dai = <&lpass_cpu MI2S_PRIMARY>; 59 }; 60 61 codec { 62 sound-dai = <&alc5682 0 /* aif1 */>; 63 }; 64 }; 65 66 dai-link@4 { 67 link-name = "DMIC"; 68 reg = <4>; 69 70 cpu { 71 sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>; 72 }; 73 74 codec { 75 sound-dai = <&lpass_va_macro 0>; 76 }; 77 }; 78 }; 79}; 80 81hp_i2c: &i2c2 { 82 clock-frequency = <400000>; 83 status = "okay"; 84 85 alc5682: codec@1a { 86 compatible = "realtek,rt5682s"; 87 reg = <0x1a>; 88 pinctrl-names = "default"; 89 pinctrl-0 = <&hp_irq>; 90 91 #sound-dai-cells = <1>; 92 93 interrupt-parent = <&tlmm>; 94 interrupts = <101 IRQ_TYPE_EDGE_BOTH>; 95 96 AVDD-supply = <&pp1800_alc5682>; 97 DBVDD-supply = <&pp1800_alc5682>; 98 LDO1-IN-supply = <&pp1800_alc5682>; 99 MICVDD-supply = <&pp3300_codec>; 100 101 realtek,dmic1-data-pin = <1>; 102 realtek,dmic1-clk-pin = <2>; 103 realtek,jd-src = <1>; 104 realtek,dmic-clk-rate-hz = <2048000>; 105 }; 106}; 107 108&lpass_cpu { 109 pinctrl-names = "default"; 110 pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>, 111 <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>; 112 113 #address-cells = <1>; 114 #size-cells = <0>; 115 116 status = "okay"; 117 118 dai-link@0 { 119 reg = <MI2S_PRIMARY>; 120 qcom,playback-sd-lines = <1>; 121 qcom,capture-sd-lines = <0>; 122 }; 123 124 dai-link@1 { 125 reg = <MI2S_SECONDARY>; 126 qcom,playback-sd-lines = <0>; 127 }; 128 129 dai-link@5 { 130 reg = <LPASS_DP_RX>; 131 }; 132 133 dai-link@25 { 134 reg = <LPASS_CDC_DMA_VA_TX0>; 135 }; 136}; 137 138&lpass_va_macro { 139 vdd-micb-supply = <&pp1800_l2c>; 140 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, <&lpass_dmic23_clk>, 141 <&lpass_dmic23_data>; 142 143 status = "okay"; 144}; 145 146/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ 147 148&lpass_dmic01_clk { 149 drive-strength = <8>; 150 bias-disable; 151}; 152 153&lpass_dmic01_data { 154 bias-pull-down; 155}; 156 157&lpass_dmic23_clk { 158 drive-strength = <8>; 159 bias-disable; 160}; 161 162&lpass_dmic23_data { 163 bias-pull-down; 164}; 165 166&mi2s0_data0 { 167 drive-strength = <6>; 168 bias-disable; 169}; 170 171&mi2s0_data1 { 172 drive-strength = <6>; 173 bias-disable; 174}; 175 176&mi2s0_mclk { 177 drive-strength = <6>; 178 bias-disable; 179}; 180 181&mi2s0_sclk { 182 drive-strength = <6>; 183 bias-disable; 184}; 185 186&mi2s0_ws { 187 drive-strength = <6>; 188 bias-disable; 189}; 190