1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,videocc-sc7180.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sc7180.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/phy/phy-qcom-qusb2.h> 17#include <dt-bindings/power/qcom-aoss-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/reset/qcom,sdm845-aoss.h> 20#include <dt-bindings/reset/qcom,sdm845-pdc.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 spi0 = &spi0; 46 spi1 = &spi1; 47 spi3 = &spi3; 48 spi5 = &spi5; 49 spi6 = &spi6; 50 spi8 = &spi8; 51 spi10 = &spi10; 52 spi11 = &spi11; 53 }; 54 55 clocks { 56 xo_board: xo-board { 57 compatible = "fixed-clock"; 58 clock-frequency = <38400000>; 59 #clock-cells = <0>; 60 }; 61 62 sleep_clk: sleep-clk { 63 compatible = "fixed-clock"; 64 clock-frequency = <32764>; 65 #clock-cells = <0>; 66 }; 67 }; 68 69 reserved_memory: reserved-memory { 70 #address-cells = <2>; 71 #size-cells = <2>; 72 ranges; 73 74 hyp_mem: memory@80000000 { 75 reg = <0x0 0x80000000 0x0 0x600000>; 76 no-map; 77 }; 78 79 xbl_mem: memory@80600000 { 80 reg = <0x0 0x80600000 0x0 0x200000>; 81 no-map; 82 }; 83 84 aop_mem: memory@80800000 { 85 reg = <0x0 0x80800000 0x0 0x20000>; 86 no-map; 87 }; 88 89 aop_cmd_db_mem: memory@80820000 { 90 reg = <0x0 0x80820000 0x0 0x20000>; 91 compatible = "qcom,cmd-db"; 92 no-map; 93 }; 94 95 sec_apps_mem: memory@808ff000 { 96 reg = <0x0 0x808ff000 0x0 0x1000>; 97 no-map; 98 }; 99 100 smem_mem: memory@80900000 { 101 reg = <0x0 0x80900000 0x0 0x200000>; 102 no-map; 103 }; 104 105 tz_mem: memory@80b00000 { 106 reg = <0x0 0x80b00000 0x0 0x3900000>; 107 no-map; 108 }; 109 110 rmtfs_mem: memory@84400000 { 111 compatible = "qcom,rmtfs-mem"; 112 reg = <0x0 0x84400000 0x0 0x200000>; 113 no-map; 114 115 qcom,client-id = <1>; 116 qcom,vmid = <15>; 117 }; 118 }; 119 120 cpus { 121 #address-cells = <2>; 122 #size-cells = <0>; 123 124 CPU0: cpu@0 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo468"; 127 reg = <0x0 0x0>; 128 enable-method = "psci"; 129 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 130 &LITTLE_CPU_SLEEP_1 131 &CLUSTER_SLEEP_0>; 132 capacity-dmips-mhz = <1024>; 133 dynamic-power-coefficient = <100>; 134 operating-points-v2 = <&cpu0_opp_table>; 135 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, 136 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 137 next-level-cache = <&L2_0>; 138 #cooling-cells = <2>; 139 qcom,freq-domain = <&cpufreq_hw 0>; 140 L2_0: l2-cache { 141 compatible = "cache"; 142 next-level-cache = <&L3_0>; 143 L3_0: l3-cache { 144 compatible = "cache"; 145 }; 146 }; 147 }; 148 149 CPU1: cpu@100 { 150 device_type = "cpu"; 151 compatible = "qcom,kryo468"; 152 reg = <0x0 0x100>; 153 enable-method = "psci"; 154 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 155 &LITTLE_CPU_SLEEP_1 156 &CLUSTER_SLEEP_0>; 157 capacity-dmips-mhz = <1024>; 158 dynamic-power-coefficient = <100>; 159 next-level-cache = <&L2_100>; 160 operating-points-v2 = <&cpu0_opp_table>; 161 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, 162 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 163 #cooling-cells = <2>; 164 qcom,freq-domain = <&cpufreq_hw 0>; 165 L2_100: l2-cache { 166 compatible = "cache"; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU2: cpu@200 { 172 device_type = "cpu"; 173 compatible = "qcom,kryo468"; 174 reg = <0x0 0x200>; 175 enable-method = "psci"; 176 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 177 &LITTLE_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 capacity-dmips-mhz = <1024>; 180 dynamic-power-coefficient = <100>; 181 next-level-cache = <&L2_200>; 182 operating-points-v2 = <&cpu0_opp_table>; 183 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, 184 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 185 #cooling-cells = <2>; 186 qcom,freq-domain = <&cpufreq_hw 0>; 187 L2_200: l2-cache { 188 compatible = "cache"; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU3: cpu@300 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo468"; 196 reg = <0x0 0x300>; 197 enable-method = "psci"; 198 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 199 &LITTLE_CPU_SLEEP_1 200 &CLUSTER_SLEEP_0>; 201 capacity-dmips-mhz = <1024>; 202 dynamic-power-coefficient = <100>; 203 next-level-cache = <&L2_300>; 204 operating-points-v2 = <&cpu0_opp_table>; 205 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, 206 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 207 #cooling-cells = <2>; 208 qcom,freq-domain = <&cpufreq_hw 0>; 209 L2_300: l2-cache { 210 compatible = "cache"; 211 next-level-cache = <&L3_0>; 212 }; 213 }; 214 215 CPU4: cpu@400 { 216 device_type = "cpu"; 217 compatible = "qcom,kryo468"; 218 reg = <0x0 0x400>; 219 enable-method = "psci"; 220 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 221 &LITTLE_CPU_SLEEP_1 222 &CLUSTER_SLEEP_0>; 223 capacity-dmips-mhz = <1024>; 224 dynamic-power-coefficient = <100>; 225 next-level-cache = <&L2_400>; 226 operating-points-v2 = <&cpu0_opp_table>; 227 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, 228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 229 #cooling-cells = <2>; 230 qcom,freq-domain = <&cpufreq_hw 0>; 231 L2_400: l2-cache { 232 compatible = "cache"; 233 next-level-cache = <&L3_0>; 234 }; 235 }; 236 237 CPU5: cpu@500 { 238 device_type = "cpu"; 239 compatible = "qcom,kryo468"; 240 reg = <0x0 0x500>; 241 enable-method = "psci"; 242 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 243 &LITTLE_CPU_SLEEP_1 244 &CLUSTER_SLEEP_0>; 245 capacity-dmips-mhz = <1024>; 246 dynamic-power-coefficient = <100>; 247 next-level-cache = <&L2_500>; 248 operating-points-v2 = <&cpu0_opp_table>; 249 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, 250 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 251 #cooling-cells = <2>; 252 qcom,freq-domain = <&cpufreq_hw 0>; 253 L2_500: l2-cache { 254 compatible = "cache"; 255 next-level-cache = <&L3_0>; 256 }; 257 }; 258 259 CPU6: cpu@600 { 260 device_type = "cpu"; 261 compatible = "qcom,kryo468"; 262 reg = <0x0 0x600>; 263 enable-method = "psci"; 264 cpu-idle-states = <&BIG_CPU_SLEEP_0 265 &BIG_CPU_SLEEP_1 266 &CLUSTER_SLEEP_0>; 267 capacity-dmips-mhz = <1740>; 268 dynamic-power-coefficient = <405>; 269 next-level-cache = <&L2_600>; 270 operating-points-v2 = <&cpu6_opp_table>; 271 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, 272 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 273 #cooling-cells = <2>; 274 qcom,freq-domain = <&cpufreq_hw 1>; 275 L2_600: l2-cache { 276 compatible = "cache"; 277 next-level-cache = <&L3_0>; 278 }; 279 }; 280 281 CPU7: cpu@700 { 282 device_type = "cpu"; 283 compatible = "qcom,kryo468"; 284 reg = <0x0 0x700>; 285 enable-method = "psci"; 286 cpu-idle-states = <&BIG_CPU_SLEEP_0 287 &BIG_CPU_SLEEP_1 288 &CLUSTER_SLEEP_0>; 289 capacity-dmips-mhz = <1740>; 290 dynamic-power-coefficient = <405>; 291 next-level-cache = <&L2_700>; 292 operating-points-v2 = <&cpu6_opp_table>; 293 interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, 294 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 295 #cooling-cells = <2>; 296 qcom,freq-domain = <&cpufreq_hw 1>; 297 L2_700: l2-cache { 298 compatible = "cache"; 299 next-level-cache = <&L3_0>; 300 }; 301 }; 302 303 cpu-map { 304 cluster0 { 305 core0 { 306 cpu = <&CPU0>; 307 }; 308 309 core1 { 310 cpu = <&CPU1>; 311 }; 312 313 core2 { 314 cpu = <&CPU2>; 315 }; 316 317 core3 { 318 cpu = <&CPU3>; 319 }; 320 321 core4 { 322 cpu = <&CPU4>; 323 }; 324 325 core5 { 326 cpu = <&CPU5>; 327 }; 328 329 core6 { 330 cpu = <&CPU6>; 331 }; 332 333 core7 { 334 cpu = <&CPU7>; 335 }; 336 }; 337 }; 338 339 idle-states { 340 entry-method = "psci"; 341 342 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "little-power-down"; 345 arm,psci-suspend-param = <0x40000003>; 346 entry-latency-us = <549>; 347 exit-latency-us = <901>; 348 min-residency-us = <1774>; 349 local-timer-stop; 350 }; 351 352 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 353 compatible = "arm,idle-state"; 354 idle-state-name = "little-rail-power-down"; 355 arm,psci-suspend-param = <0x40000004>; 356 entry-latency-us = <702>; 357 exit-latency-us = <915>; 358 min-residency-us = <4001>; 359 local-timer-stop; 360 }; 361 362 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 363 compatible = "arm,idle-state"; 364 idle-state-name = "big-power-down"; 365 arm,psci-suspend-param = <0x40000003>; 366 entry-latency-us = <523>; 367 exit-latency-us = <1244>; 368 min-residency-us = <2207>; 369 local-timer-stop; 370 }; 371 372 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 373 compatible = "arm,idle-state"; 374 idle-state-name = "big-rail-power-down"; 375 arm,psci-suspend-param = <0x40000004>; 376 entry-latency-us = <526>; 377 exit-latency-us = <1854>; 378 min-residency-us = <5555>; 379 local-timer-stop; 380 }; 381 382 CLUSTER_SLEEP_0: cluster-sleep-0 { 383 compatible = "arm,idle-state"; 384 idle-state-name = "cluster-power-down"; 385 arm,psci-suspend-param = <0x40003444>; 386 entry-latency-us = <3263>; 387 exit-latency-us = <6562>; 388 min-residency-us = <9926>; 389 local-timer-stop; 390 }; 391 }; 392 }; 393 394 cpu0_opp_table: cpu0_opp_table { 395 compatible = "operating-points-v2"; 396 opp-shared; 397 398 cpu0_opp1: opp-300000000 { 399 opp-hz = /bits/ 64 <300000000>; 400 opp-peak-kBps = <1200000 4800000>; 401 }; 402 403 cpu0_opp2: opp-576000000 { 404 opp-hz = /bits/ 64 <576000000>; 405 opp-peak-kBps = <1200000 4800000>; 406 }; 407 408 cpu0_opp3: opp-768000000 { 409 opp-hz = /bits/ 64 <768000000>; 410 opp-peak-kBps = <1200000 4800000>; 411 }; 412 413 cpu0_opp4: opp-1017600000 { 414 opp-hz = /bits/ 64 <1017600000>; 415 opp-peak-kBps = <1804000 8908800>; 416 }; 417 418 cpu0_opp5: opp-1248000000 { 419 opp-hz = /bits/ 64 <1248000000>; 420 opp-peak-kBps = <2188000 12902400>; 421 }; 422 423 cpu0_opp6: opp-1324800000 { 424 opp-hz = /bits/ 64 <1324800000>; 425 opp-peak-kBps = <2188000 12902400>; 426 }; 427 428 cpu0_opp7: opp-1516800000 { 429 opp-hz = /bits/ 64 <1516800000>; 430 opp-peak-kBps = <3072000 15052800>; 431 }; 432 433 cpu0_opp8: opp-1612800000 { 434 opp-hz = /bits/ 64 <1612800000>; 435 opp-peak-kBps = <3072000 15052800>; 436 }; 437 438 cpu0_opp9: opp-1708800000 { 439 opp-hz = /bits/ 64 <1708800000>; 440 opp-peak-kBps = <3072000 15052800>; 441 }; 442 443 cpu0_opp10: opp-1804800000 { 444 opp-hz = /bits/ 64 <1804800000>; 445 opp-peak-kBps = <4068000 22425600>; 446 }; 447 }; 448 449 cpu6_opp_table: cpu6_opp_table { 450 compatible = "operating-points-v2"; 451 opp-shared; 452 453 cpu6_opp1: opp-300000000 { 454 opp-hz = /bits/ 64 <300000000>; 455 opp-peak-kBps = <2188000 8908800>; 456 }; 457 458 cpu6_opp2: opp-652800000 { 459 opp-hz = /bits/ 64 <652800000>; 460 opp-peak-kBps = <2188000 8908800>; 461 }; 462 463 cpu6_opp3: opp-825600000 { 464 opp-hz = /bits/ 64 <825600000>; 465 opp-peak-kBps = <2188000 8908800>; 466 }; 467 468 cpu6_opp4: opp-979200000 { 469 opp-hz = /bits/ 64 <979200000>; 470 opp-peak-kBps = <2188000 8908800>; 471 }; 472 473 cpu6_opp5: opp-1113600000 { 474 opp-hz = /bits/ 64 <1113600000>; 475 opp-peak-kBps = <2188000 8908800>; 476 }; 477 478 cpu6_opp6: opp-1267200000 { 479 opp-hz = /bits/ 64 <1267200000>; 480 opp-peak-kBps = <4068000 12902400>; 481 }; 482 483 cpu6_opp7: opp-1555200000 { 484 opp-hz = /bits/ 64 <1555200000>; 485 opp-peak-kBps = <4068000 15052800>; 486 }; 487 488 cpu6_opp8: opp-1708800000 { 489 opp-hz = /bits/ 64 <1708800000>; 490 opp-peak-kBps = <6220000 19353600>; 491 }; 492 493 cpu6_opp9: opp-1843200000 { 494 opp-hz = /bits/ 64 <1843200000>; 495 opp-peak-kBps = <6220000 19353600>; 496 }; 497 498 cpu6_opp10: opp-1900800000 { 499 opp-hz = /bits/ 64 <1900800000>; 500 opp-peak-kBps = <6220000 22425600>; 501 }; 502 503 cpu6_opp11: opp-1996800000 { 504 opp-hz = /bits/ 64 <1996800000>; 505 opp-peak-kBps = <6220000 22425600>; 506 }; 507 508 cpu6_opp12: opp-2112000000 { 509 opp-hz = /bits/ 64 <2112000000>; 510 opp-peak-kBps = <6220000 22425600>; 511 }; 512 513 cpu6_opp13: opp-2208000000 { 514 opp-hz = /bits/ 64 <2208000000>; 515 opp-peak-kBps = <7216000 22425600>; 516 }; 517 518 cpu6_opp14: opp-2323200000 { 519 opp-hz = /bits/ 64 <2323200000>; 520 opp-peak-kBps = <7216000 22425600>; 521 }; 522 523 cpu6_opp15: opp-2400000000 { 524 opp-hz = /bits/ 64 <2400000000>; 525 opp-peak-kBps = <8532000 23347200>; 526 }; 527 }; 528 529 memory@80000000 { 530 device_type = "memory"; 531 /* We expect the bootloader to fill in the size */ 532 reg = <0 0x80000000 0 0>; 533 }; 534 535 pmu { 536 compatible = "arm,armv8-pmuv3"; 537 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 538 }; 539 540 firmware { 541 scm { 542 compatible = "qcom,scm-sc7180", "qcom,scm"; 543 }; 544 }; 545 546 tcsr_mutex: hwlock { 547 compatible = "qcom,tcsr-mutex"; 548 syscon = <&tcsr_mutex_regs 0 0x1000>; 549 #hwlock-cells = <1>; 550 }; 551 552 smem { 553 compatible = "qcom,smem"; 554 memory-region = <&smem_mem>; 555 hwlocks = <&tcsr_mutex 3>; 556 }; 557 558 smp2p-cdsp { 559 compatible = "qcom,smp2p"; 560 qcom,smem = <94>, <432>; 561 562 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 563 564 mboxes = <&apss_shared 6>; 565 566 qcom,local-pid = <0>; 567 qcom,remote-pid = <5>; 568 569 cdsp_smp2p_out: master-kernel { 570 qcom,entry-name = "master-kernel"; 571 #qcom,smem-state-cells = <1>; 572 }; 573 574 cdsp_smp2p_in: slave-kernel { 575 qcom,entry-name = "slave-kernel"; 576 577 interrupt-controller; 578 #interrupt-cells = <2>; 579 }; 580 }; 581 582 smp2p-lpass { 583 compatible = "qcom,smp2p"; 584 qcom,smem = <443>, <429>; 585 586 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 587 588 mboxes = <&apss_shared 10>; 589 590 qcom,local-pid = <0>; 591 qcom,remote-pid = <2>; 592 593 adsp_smp2p_out: master-kernel { 594 qcom,entry-name = "master-kernel"; 595 #qcom,smem-state-cells = <1>; 596 }; 597 598 adsp_smp2p_in: slave-kernel { 599 qcom,entry-name = "slave-kernel"; 600 601 interrupt-controller; 602 #interrupt-cells = <2>; 603 }; 604 }; 605 606 smp2p-mpss { 607 compatible = "qcom,smp2p"; 608 qcom,smem = <435>, <428>; 609 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 610 mboxes = <&apss_shared 14>; 611 qcom,local-pid = <0>; 612 qcom,remote-pid = <1>; 613 614 modem_smp2p_out: master-kernel { 615 qcom,entry-name = "master-kernel"; 616 #qcom,smem-state-cells = <1>; 617 }; 618 619 modem_smp2p_in: slave-kernel { 620 qcom,entry-name = "slave-kernel"; 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 }; 624 625 ipa_smp2p_out: ipa-ap-to-modem { 626 qcom,entry-name = "ipa"; 627 #qcom,smem-state-cells = <1>; 628 }; 629 630 ipa_smp2p_in: ipa-modem-to-ap { 631 qcom,entry-name = "ipa"; 632 interrupt-controller; 633 #interrupt-cells = <2>; 634 }; 635 }; 636 637 psci { 638 compatible = "arm,psci-1.0"; 639 method = "smc"; 640 }; 641 642 soc: soc@0 { 643 #address-cells = <2>; 644 #size-cells = <2>; 645 ranges = <0 0 0 0 0x10 0>; 646 dma-ranges = <0 0 0 0 0x10 0>; 647 compatible = "simple-bus"; 648 649 gcc: clock-controller@100000 { 650 compatible = "qcom,gcc-sc7180"; 651 reg = <0 0x00100000 0 0x1f0000>; 652 clocks = <&rpmhcc RPMH_CXO_CLK>, 653 <&rpmhcc RPMH_CXO_CLK_A>, 654 <&sleep_clk>; 655 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 656 #clock-cells = <1>; 657 #reset-cells = <1>; 658 #power-domain-cells = <1>; 659 }; 660 661 qfprom: efuse@784000 { 662 compatible = "qcom,qfprom"; 663 reg = <0 0x00784000 0 0x8ff>, 664 <0 0x00780000 0 0x7a0>, 665 <0 0x00782000 0 0x100>, 666 <0 0x00786000 0 0x1fff>; 667 668 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 669 clock-names = "core"; 670 #address-cells = <1>; 671 #size-cells = <1>; 672 673 qusb2p_hstx_trim: hstx-trim-primary@25b { 674 reg = <0x25b 0x1>; 675 bits = <1 3>; 676 }; 677 }; 678 679 sdhc_1: sdhci@7c4000 { 680 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 681 reg = <0 0x7c4000 0 0x1000>, 682 <0 0x07c5000 0 0x1000>; 683 reg-names = "hc", "cqhci"; 684 685 iommus = <&apps_smmu 0x60 0x0>; 686 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 688 interrupt-names = "hc_irq", "pwr_irq"; 689 690 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 691 <&gcc GCC_SDCC1_AHB_CLK>; 692 clock-names = "core", "iface"; 693 power-domains = <&rpmhpd SC7180_CX>; 694 operating-points-v2 = <&sdhc1_opp_table>; 695 696 bus-width = <8>; 697 non-removable; 698 supports-cqe; 699 700 mmc-ddr-1_8v; 701 mmc-hs200-1_8v; 702 mmc-hs400-1_8v; 703 mmc-hs400-enhanced-strobe; 704 705 status = "disabled"; 706 707 sdhc1_opp_table: sdhc1-opp-table { 708 compatible = "operating-points-v2"; 709 710 opp-100000000 { 711 opp-hz = /bits/ 64 <100000000>; 712 required-opps = <&rpmhpd_opp_low_svs>; 713 }; 714 715 opp-384000000 { 716 opp-hz = /bits/ 64 <384000000>; 717 required-opps = <&rpmhpd_opp_svs_l1>; 718 }; 719 }; 720 }; 721 722 qup_opp_table: qup-opp-table { 723 compatible = "operating-points-v2"; 724 725 opp-75000000 { 726 opp-hz = /bits/ 64 <75000000>; 727 required-opps = <&rpmhpd_opp_low_svs>; 728 }; 729 730 opp-100000000 { 731 opp-hz = /bits/ 64 <100000000>; 732 required-opps = <&rpmhpd_opp_svs>; 733 }; 734 735 opp-128000000 { 736 opp-hz = /bits/ 64 <128000000>; 737 required-opps = <&rpmhpd_opp_nom>; 738 }; 739 }; 740 741 qupv3_id_0: geniqup@8c0000 { 742 compatible = "qcom,geni-se-qup"; 743 reg = <0 0x008c0000 0 0x6000>; 744 clock-names = "m-ahb", "s-ahb"; 745 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 746 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 747 #address-cells = <2>; 748 #size-cells = <2>; 749 ranges; 750 iommus = <&apps_smmu 0x43 0x0>; 751 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>; 752 interconnect-names = "qup-core"; 753 status = "disabled"; 754 755 i2c0: i2c@880000 { 756 compatible = "qcom,geni-i2c"; 757 reg = <0 0x00880000 0 0x4000>; 758 clock-names = "se"; 759 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&qup_i2c0_default>; 762 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 766 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, 767 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; 768 interconnect-names = "qup-core", "qup-config", 769 "qup-memory"; 770 status = "disabled"; 771 }; 772 773 spi0: spi@880000 { 774 compatible = "qcom,geni-spi"; 775 reg = <0 0x00880000 0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&qup_spi0_default>; 780 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 power-domains = <&rpmhpd SC7180_CX>; 784 operating-points-v2 = <&qup_opp_table>; 785 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 786 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 787 interconnect-names = "qup-core", "qup-config"; 788 status = "disabled"; 789 }; 790 791 uart0: serial@880000 { 792 compatible = "qcom,geni-uart"; 793 reg = <0 0x00880000 0 0x4000>; 794 clock-names = "se"; 795 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 796 pinctrl-names = "default"; 797 pinctrl-0 = <&qup_uart0_default>; 798 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 799 power-domains = <&rpmhpd SC7180_CX>; 800 operating-points-v2 = <&qup_opp_table>; 801 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 802 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 803 interconnect-names = "qup-core", "qup-config"; 804 status = "disabled"; 805 }; 806 807 i2c1: i2c@884000 { 808 compatible = "qcom,geni-i2c"; 809 reg = <0 0x00884000 0 0x4000>; 810 clock-names = "se"; 811 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&qup_i2c1_default>; 814 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 818 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, 819 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; 820 interconnect-names = "qup-core", "qup-config", 821 "qup-memory"; 822 status = "disabled"; 823 }; 824 825 spi1: spi@884000 { 826 compatible = "qcom,geni-spi"; 827 reg = <0 0x00884000 0 0x4000>; 828 clock-names = "se"; 829 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&qup_spi1_default>; 832 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 power-domains = <&rpmhpd SC7180_CX>; 836 operating-points-v2 = <&qup_opp_table>; 837 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 838 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 839 interconnect-names = "qup-core", "qup-config"; 840 status = "disabled"; 841 }; 842 843 uart1: serial@884000 { 844 compatible = "qcom,geni-uart"; 845 reg = <0 0x00884000 0 0x4000>; 846 clock-names = "se"; 847 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 848 pinctrl-names = "default"; 849 pinctrl-0 = <&qup_uart1_default>; 850 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 851 power-domains = <&rpmhpd SC7180_CX>; 852 operating-points-v2 = <&qup_opp_table>; 853 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 854 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 855 interconnect-names = "qup-core", "qup-config"; 856 status = "disabled"; 857 }; 858 859 i2c2: i2c@888000 { 860 compatible = "qcom,geni-i2c"; 861 reg = <0 0x00888000 0 0x4000>; 862 clock-names = "se"; 863 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&qup_i2c2_default>; 866 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 870 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, 871 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; 872 interconnect-names = "qup-core", "qup-config", 873 "qup-memory"; 874 status = "disabled"; 875 }; 876 877 uart2: serial@888000 { 878 compatible = "qcom,geni-uart"; 879 reg = <0 0x00888000 0 0x4000>; 880 clock-names = "se"; 881 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&qup_uart2_default>; 884 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 885 power-domains = <&rpmhpd SC7180_CX>; 886 operating-points-v2 = <&qup_opp_table>; 887 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 888 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 889 interconnect-names = "qup-core", "qup-config"; 890 status = "disabled"; 891 }; 892 893 i2c3: i2c@88c000 { 894 compatible = "qcom,geni-i2c"; 895 reg = <0 0x0088c000 0 0x4000>; 896 clock-names = "se"; 897 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&qup_i2c3_default>; 900 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 904 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, 905 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; 906 interconnect-names = "qup-core", "qup-config", 907 "qup-memory"; 908 status = "disabled"; 909 }; 910 911 spi3: spi@88c000 { 912 compatible = "qcom,geni-spi"; 913 reg = <0 0x0088c000 0 0x4000>; 914 clock-names = "se"; 915 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&qup_spi3_default>; 918 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 power-domains = <&rpmhpd SC7180_CX>; 922 operating-points-v2 = <&qup_opp_table>; 923 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 924 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 925 interconnect-names = "qup-core", "qup-config"; 926 status = "disabled"; 927 }; 928 929 uart3: serial@88c000 { 930 compatible = "qcom,geni-uart"; 931 reg = <0 0x0088c000 0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_uart3_default>; 936 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 937 power-domains = <&rpmhpd SC7180_CX>; 938 operating-points-v2 = <&qup_opp_table>; 939 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 940 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 941 interconnect-names = "qup-core", "qup-config"; 942 status = "disabled"; 943 }; 944 945 i2c4: i2c@890000 { 946 compatible = "qcom,geni-i2c"; 947 reg = <0 0x00890000 0 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&qup_i2c4_default>; 952 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 956 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, 957 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; 958 interconnect-names = "qup-core", "qup-config", 959 "qup-memory"; 960 status = "disabled"; 961 }; 962 963 uart4: serial@890000 { 964 compatible = "qcom,geni-uart"; 965 reg = <0 0x00890000 0 0x4000>; 966 clock-names = "se"; 967 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&qup_uart4_default>; 970 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 971 power-domains = <&rpmhpd SC7180_CX>; 972 operating-points-v2 = <&qup_opp_table>; 973 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 974 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 975 interconnect-names = "qup-core", "qup-config"; 976 status = "disabled"; 977 }; 978 979 i2c5: i2c@894000 { 980 compatible = "qcom,geni-i2c"; 981 reg = <0 0x00894000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_i2c5_default>; 986 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 990 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, 991 <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; 992 interconnect-names = "qup-core", "qup-config", 993 "qup-memory"; 994 status = "disabled"; 995 }; 996 997 spi5: spi@894000 { 998 compatible = "qcom,geni-spi"; 999 reg = <0 0x00894000 0 0x4000>; 1000 clock-names = "se"; 1001 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_spi5_default>; 1004 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 power-domains = <&rpmhpd SC7180_CX>; 1008 operating-points-v2 = <&qup_opp_table>; 1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 1010 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 1011 interconnect-names = "qup-core", "qup-config"; 1012 status = "disabled"; 1013 }; 1014 1015 uart5: serial@894000 { 1016 compatible = "qcom,geni-uart"; 1017 reg = <0 0x00894000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_uart5_default>; 1022 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1023 power-domains = <&rpmhpd SC7180_CX>; 1024 operating-points-v2 = <&qup_opp_table>; 1025 interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, 1026 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; 1027 interconnect-names = "qup-core", "qup-config"; 1028 status = "disabled"; 1029 }; 1030 }; 1031 1032 qupv3_id_1: geniqup@ac0000 { 1033 compatible = "qcom,geni-se-qup"; 1034 reg = <0 0x00ac0000 0 0x6000>; 1035 clock-names = "m-ahb", "s-ahb"; 1036 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1037 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1038 #address-cells = <2>; 1039 #size-cells = <2>; 1040 ranges; 1041 iommus = <&apps_smmu 0x4c3 0x0>; 1042 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>; 1043 interconnect-names = "qup-core"; 1044 status = "disabled"; 1045 1046 i2c6: i2c@a80000 { 1047 compatible = "qcom,geni-i2c"; 1048 reg = <0 0x00a80000 0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&qup_i2c6_default>; 1053 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1057 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, 1058 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; 1059 interconnect-names = "qup-core", "qup-config", 1060 "qup-memory"; 1061 status = "disabled"; 1062 }; 1063 1064 spi6: spi@a80000 { 1065 compatible = "qcom,geni-spi"; 1066 reg = <0 0x00a80000 0 0x4000>; 1067 clock-names = "se"; 1068 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_spi6_default>; 1071 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 power-domains = <&rpmhpd SC7180_CX>; 1075 operating-points-v2 = <&qup_opp_table>; 1076 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1077 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1078 interconnect-names = "qup-core", "qup-config"; 1079 status = "disabled"; 1080 }; 1081 1082 uart6: serial@a80000 { 1083 compatible = "qcom,geni-uart"; 1084 reg = <0 0x00a80000 0 0x4000>; 1085 clock-names = "se"; 1086 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_uart6_default>; 1089 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1090 power-domains = <&rpmhpd SC7180_CX>; 1091 operating-points-v2 = <&qup_opp_table>; 1092 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1093 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1094 interconnect-names = "qup-core", "qup-config"; 1095 status = "disabled"; 1096 }; 1097 1098 i2c7: i2c@a84000 { 1099 compatible = "qcom,geni-i2c"; 1100 reg = <0 0x00a84000 0 0x4000>; 1101 clock-names = "se"; 1102 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_i2c7_default>; 1105 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1109 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, 1110 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; 1111 interconnect-names = "qup-core", "qup-config", 1112 "qup-memory"; 1113 status = "disabled"; 1114 }; 1115 1116 uart7: serial@a84000 { 1117 compatible = "qcom,geni-uart"; 1118 reg = <0 0x00a84000 0 0x4000>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&qup_uart7_default>; 1123 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1124 power-domains = <&rpmhpd SC7180_CX>; 1125 operating-points-v2 = <&qup_opp_table>; 1126 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1127 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1128 interconnect-names = "qup-core", "qup-config"; 1129 status = "disabled"; 1130 }; 1131 1132 i2c8: i2c@a88000 { 1133 compatible = "qcom,geni-i2c"; 1134 reg = <0 0x00a88000 0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&qup_i2c8_default>; 1139 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1143 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, 1144 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; 1145 interconnect-names = "qup-core", "qup-config", 1146 "qup-memory"; 1147 status = "disabled"; 1148 }; 1149 1150 spi8: spi@a88000 { 1151 compatible = "qcom,geni-spi"; 1152 reg = <0 0x00a88000 0 0x4000>; 1153 clock-names = "se"; 1154 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_spi8_default>; 1157 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 power-domains = <&rpmhpd SC7180_CX>; 1161 operating-points-v2 = <&qup_opp_table>; 1162 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1163 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1164 interconnect-names = "qup-core", "qup-config"; 1165 status = "disabled"; 1166 }; 1167 1168 uart8: serial@a88000 { 1169 compatible = "qcom,geni-debug-uart"; 1170 reg = <0 0x00a88000 0 0x4000>; 1171 clock-names = "se"; 1172 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&qup_uart8_default>; 1175 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1176 power-domains = <&rpmhpd SC7180_CX>; 1177 operating-points-v2 = <&qup_opp_table>; 1178 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1179 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1180 interconnect-names = "qup-core", "qup-config"; 1181 status = "disabled"; 1182 }; 1183 1184 i2c9: i2c@a8c000 { 1185 compatible = "qcom,geni-i2c"; 1186 reg = <0 0x00a8c000 0 0x4000>; 1187 clock-names = "se"; 1188 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_i2c9_default>; 1191 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1195 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, 1196 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; 1197 interconnect-names = "qup-core", "qup-config", 1198 "qup-memory"; 1199 status = "disabled"; 1200 }; 1201 1202 uart9: serial@a8c000 { 1203 compatible = "qcom,geni-uart"; 1204 reg = <0 0x00a8c000 0 0x4000>; 1205 clock-names = "se"; 1206 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_uart9_default>; 1209 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1210 power-domains = <&rpmhpd SC7180_CX>; 1211 operating-points-v2 = <&qup_opp_table>; 1212 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1213 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1214 interconnect-names = "qup-core", "qup-config"; 1215 status = "disabled"; 1216 }; 1217 1218 i2c10: i2c@a90000 { 1219 compatible = "qcom,geni-i2c"; 1220 reg = <0 0x00a90000 0 0x4000>; 1221 clock-names = "se"; 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c10_default>; 1225 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1229 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, 1230 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; 1231 interconnect-names = "qup-core", "qup-config", 1232 "qup-memory"; 1233 status = "disabled"; 1234 }; 1235 1236 spi10: spi@a90000 { 1237 compatible = "qcom,geni-spi"; 1238 reg = <0 0x00a90000 0 0x4000>; 1239 clock-names = "se"; 1240 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1241 pinctrl-names = "default"; 1242 pinctrl-0 = <&qup_spi10_default>; 1243 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 power-domains = <&rpmhpd SC7180_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1249 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1250 interconnect-names = "qup-core", "qup-config"; 1251 status = "disabled"; 1252 }; 1253 1254 uart10: serial@a90000 { 1255 compatible = "qcom,geni-uart"; 1256 reg = <0 0x00a90000 0 0x4000>; 1257 clock-names = "se"; 1258 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1259 pinctrl-names = "default"; 1260 pinctrl-0 = <&qup_uart10_default>; 1261 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1262 power-domains = <&rpmhpd SC7180_CX>; 1263 operating-points-v2 = <&qup_opp_table>; 1264 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1265 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1266 interconnect-names = "qup-core", "qup-config"; 1267 status = "disabled"; 1268 }; 1269 1270 i2c11: i2c@a94000 { 1271 compatible = "qcom,geni-i2c"; 1272 reg = <0 0x00a94000 0 0x4000>; 1273 clock-names = "se"; 1274 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1275 pinctrl-names = "default"; 1276 pinctrl-0 = <&qup_i2c11_default>; 1277 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1281 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, 1282 <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; 1283 interconnect-names = "qup-core", "qup-config", 1284 "qup-memory"; 1285 status = "disabled"; 1286 }; 1287 1288 spi11: spi@a94000 { 1289 compatible = "qcom,geni-spi"; 1290 reg = <0 0x00a94000 0 0x4000>; 1291 clock-names = "se"; 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&qup_spi11_default>; 1295 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 power-domains = <&rpmhpd SC7180_CX>; 1299 operating-points-v2 = <&qup_opp_table>; 1300 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1301 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1302 interconnect-names = "qup-core", "qup-config"; 1303 status = "disabled"; 1304 }; 1305 1306 uart11: serial@a94000 { 1307 compatible = "qcom,geni-uart"; 1308 reg = <0 0x00a94000 0 0x4000>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1311 pinctrl-names = "default"; 1312 pinctrl-0 = <&qup_uart11_default>; 1313 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1314 power-domains = <&rpmhpd SC7180_CX>; 1315 operating-points-v2 = <&qup_opp_table>; 1316 interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, 1317 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; 1318 interconnect-names = "qup-core", "qup-config"; 1319 status = "disabled"; 1320 }; 1321 }; 1322 1323 config_noc: interconnect@1500000 { 1324 compatible = "qcom,sc7180-config-noc"; 1325 reg = <0 0x01500000 0 0x28000>; 1326 #interconnect-cells = <1>; 1327 qcom,bcm-voters = <&apps_bcm_voter>; 1328 }; 1329 1330 system_noc: interconnect@1620000 { 1331 compatible = "qcom,sc7180-system-noc"; 1332 reg = <0 0x01620000 0 0x17080>; 1333 #interconnect-cells = <1>; 1334 qcom,bcm-voters = <&apps_bcm_voter>; 1335 }; 1336 1337 mc_virt: interconnect@1638000 { 1338 compatible = "qcom,sc7180-mc-virt"; 1339 reg = <0 0x01638000 0 0x1000>; 1340 #interconnect-cells = <1>; 1341 qcom,bcm-voters = <&apps_bcm_voter>; 1342 }; 1343 1344 qup_virt: interconnect@1650000 { 1345 compatible = "qcom,sc7180-qup-virt"; 1346 reg = <0 0x01650000 0 0x1000>; 1347 #interconnect-cells = <1>; 1348 qcom,bcm-voters = <&apps_bcm_voter>; 1349 }; 1350 1351 aggre1_noc: interconnect@16e0000 { 1352 compatible = "qcom,sc7180-aggre1-noc"; 1353 reg = <0 0x016e0000 0 0x15080>; 1354 #interconnect-cells = <1>; 1355 qcom,bcm-voters = <&apps_bcm_voter>; 1356 }; 1357 1358 aggre2_noc: interconnect@1705000 { 1359 compatible = "qcom,sc7180-aggre2-noc"; 1360 reg = <0 0x01705000 0 0x9000>; 1361 #interconnect-cells = <1>; 1362 qcom,bcm-voters = <&apps_bcm_voter>; 1363 }; 1364 1365 compute_noc: interconnect@170e000 { 1366 compatible = "qcom,sc7180-compute-noc"; 1367 reg = <0 0x0170e000 0 0x6000>; 1368 #interconnect-cells = <1>; 1369 qcom,bcm-voters = <&apps_bcm_voter>; 1370 }; 1371 1372 mmss_noc: interconnect@1740000 { 1373 compatible = "qcom,sc7180-mmss-noc"; 1374 reg = <0 0x01740000 0 0x1c100>; 1375 #interconnect-cells = <1>; 1376 qcom,bcm-voters = <&apps_bcm_voter>; 1377 }; 1378 1379 ipa_virt: interconnect@1e00000 { 1380 compatible = "qcom,sc7180-ipa-virt"; 1381 reg = <0 0x01e00000 0 0x1000>; 1382 #interconnect-cells = <1>; 1383 qcom,bcm-voters = <&apps_bcm_voter>; 1384 }; 1385 1386 ipa: ipa@1e40000 { 1387 compatible = "qcom,sc7180-ipa"; 1388 1389 iommus = <&apps_smmu 0x440 0x3>; 1390 reg = <0 0x1e40000 0 0x7000>, 1391 <0 0x1e47000 0 0x2000>, 1392 <0 0x1e04000 0 0x2c000>; 1393 reg-names = "ipa-reg", 1394 "ipa-shared", 1395 "gsi"; 1396 1397 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, 1398 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 1399 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1400 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1401 interrupt-names = "ipa", 1402 "gsi", 1403 "ipa-clock-query", 1404 "ipa-setup-ready"; 1405 1406 clocks = <&rpmhcc RPMH_IPA_CLK>; 1407 clock-names = "core"; 1408 1409 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, 1410 <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>, 1411 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; 1412 interconnect-names = "memory", 1413 "imem", 1414 "config"; 1415 1416 qcom,smem-states = <&ipa_smp2p_out 0>, 1417 <&ipa_smp2p_out 1>; 1418 qcom,smem-state-names = "ipa-clock-enabled-valid", 1419 "ipa-clock-enabled"; 1420 1421 modem-remoteproc = <&remoteproc_mpss>; 1422 1423 status = "disabled"; 1424 }; 1425 1426 tcsr_mutex_regs: syscon@1f40000 { 1427 compatible = "syscon"; 1428 reg = <0 0x01f40000 0 0x40000>; 1429 }; 1430 1431 tcsr_regs: syscon@1fc0000 { 1432 compatible = "syscon"; 1433 reg = <0 0x01fc0000 0 0x40000>; 1434 }; 1435 1436 tlmm: pinctrl@3500000 { 1437 compatible = "qcom,sc7180-pinctrl"; 1438 reg = <0 0x03500000 0 0x300000>, 1439 <0 0x03900000 0 0x300000>, 1440 <0 0x03d00000 0 0x300000>; 1441 reg-names = "west", "north", "south"; 1442 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1443 gpio-controller; 1444 #gpio-cells = <2>; 1445 interrupt-controller; 1446 #interrupt-cells = <2>; 1447 gpio-ranges = <&tlmm 0 0 120>; 1448 wakeup-parent = <&pdc>; 1449 1450 qspi_clk: qspi-clk { 1451 pinmux { 1452 pins = "gpio63"; 1453 function = "qspi_clk"; 1454 }; 1455 }; 1456 1457 qspi_cs0: qspi-cs0 { 1458 pinmux { 1459 pins = "gpio68"; 1460 function = "qspi_cs"; 1461 }; 1462 }; 1463 1464 qspi_cs1: qspi-cs1 { 1465 pinmux { 1466 pins = "gpio72"; 1467 function = "qspi_cs"; 1468 }; 1469 }; 1470 1471 qspi_data01: qspi-data01 { 1472 pinmux-data { 1473 pins = "gpio64", "gpio65"; 1474 function = "qspi_data"; 1475 }; 1476 }; 1477 1478 qspi_data12: qspi-data12 { 1479 pinmux-data { 1480 pins = "gpio66", "gpio67"; 1481 function = "qspi_data"; 1482 }; 1483 }; 1484 1485 qup_i2c0_default: qup-i2c0-default { 1486 pinmux { 1487 pins = "gpio34", "gpio35"; 1488 function = "qup00"; 1489 }; 1490 }; 1491 1492 qup_i2c1_default: qup-i2c1-default { 1493 pinmux { 1494 pins = "gpio0", "gpio1"; 1495 function = "qup01"; 1496 }; 1497 }; 1498 1499 qup_i2c2_default: qup-i2c2-default { 1500 pinmux { 1501 pins = "gpio15", "gpio16"; 1502 function = "qup02_i2c"; 1503 }; 1504 }; 1505 1506 qup_i2c3_default: qup-i2c3-default { 1507 pinmux { 1508 pins = "gpio38", "gpio39"; 1509 function = "qup03"; 1510 }; 1511 }; 1512 1513 qup_i2c4_default: qup-i2c4-default { 1514 pinmux { 1515 pins = "gpio115", "gpio116"; 1516 function = "qup04_i2c"; 1517 }; 1518 }; 1519 1520 qup_i2c5_default: qup-i2c5-default { 1521 pinmux { 1522 pins = "gpio25", "gpio26"; 1523 function = "qup05"; 1524 }; 1525 }; 1526 1527 qup_i2c6_default: qup-i2c6-default { 1528 pinmux { 1529 pins = "gpio59", "gpio60"; 1530 function = "qup10"; 1531 }; 1532 }; 1533 1534 qup_i2c7_default: qup-i2c7-default { 1535 pinmux { 1536 pins = "gpio6", "gpio7"; 1537 function = "qup11_i2c"; 1538 }; 1539 }; 1540 1541 qup_i2c8_default: qup-i2c8-default { 1542 pinmux { 1543 pins = "gpio42", "gpio43"; 1544 function = "qup12"; 1545 }; 1546 }; 1547 1548 qup_i2c9_default: qup-i2c9-default { 1549 pinmux { 1550 pins = "gpio46", "gpio47"; 1551 function = "qup13_i2c"; 1552 }; 1553 }; 1554 1555 qup_i2c10_default: qup-i2c10-default { 1556 pinmux { 1557 pins = "gpio86", "gpio87"; 1558 function = "qup14"; 1559 }; 1560 }; 1561 1562 qup_i2c11_default: qup-i2c11-default { 1563 pinmux { 1564 pins = "gpio53", "gpio54"; 1565 function = "qup15"; 1566 }; 1567 }; 1568 1569 qup_spi0_default: qup-spi0-default { 1570 pinmux { 1571 pins = "gpio34", "gpio35", 1572 "gpio36", "gpio37"; 1573 function = "qup00"; 1574 }; 1575 }; 1576 1577 qup_spi1_default: qup-spi1-default { 1578 pinmux { 1579 pins = "gpio0", "gpio1", 1580 "gpio2", "gpio3"; 1581 function = "qup01"; 1582 }; 1583 }; 1584 1585 qup_spi3_default: qup-spi3-default { 1586 pinmux { 1587 pins = "gpio38", "gpio39", 1588 "gpio40", "gpio41"; 1589 function = "qup03"; 1590 }; 1591 }; 1592 1593 qup_spi5_default: qup-spi5-default { 1594 pinmux { 1595 pins = "gpio25", "gpio26", 1596 "gpio27", "gpio28"; 1597 function = "qup05"; 1598 }; 1599 }; 1600 1601 qup_spi6_default: qup-spi6-default { 1602 pinmux { 1603 pins = "gpio59", "gpio60", 1604 "gpio61", "gpio62"; 1605 function = "qup10"; 1606 }; 1607 }; 1608 1609 qup_spi8_default: qup-spi8-default { 1610 pinmux { 1611 pins = "gpio42", "gpio43", 1612 "gpio44", "gpio45"; 1613 function = "qup12"; 1614 }; 1615 }; 1616 1617 qup_spi10_default: qup-spi10-default { 1618 pinmux { 1619 pins = "gpio86", "gpio87", 1620 "gpio88", "gpio89"; 1621 function = "qup14"; 1622 }; 1623 }; 1624 1625 qup_spi11_default: qup-spi11-default { 1626 pinmux { 1627 pins = "gpio53", "gpio54", 1628 "gpio55", "gpio56"; 1629 function = "qup15"; 1630 }; 1631 }; 1632 1633 qup_uart0_default: qup-uart0-default { 1634 pinmux { 1635 pins = "gpio34", "gpio35", 1636 "gpio36", "gpio37"; 1637 function = "qup00"; 1638 }; 1639 }; 1640 1641 qup_uart1_default: qup-uart1-default { 1642 pinmux { 1643 pins = "gpio0", "gpio1", 1644 "gpio2", "gpio3"; 1645 function = "qup01"; 1646 }; 1647 }; 1648 1649 qup_uart2_default: qup-uart2-default { 1650 pinmux { 1651 pins = "gpio15", "gpio16"; 1652 function = "qup02_uart"; 1653 }; 1654 }; 1655 1656 qup_uart3_default: qup-uart3-default { 1657 pinmux { 1658 pins = "gpio38", "gpio39", 1659 "gpio40", "gpio41"; 1660 function = "qup03"; 1661 }; 1662 }; 1663 1664 qup_uart4_default: qup-uart4-default { 1665 pinmux { 1666 pins = "gpio115", "gpio116"; 1667 function = "qup04_uart"; 1668 }; 1669 }; 1670 1671 qup_uart5_default: qup-uart5-default { 1672 pinmux { 1673 pins = "gpio25", "gpio26", 1674 "gpio27", "gpio28"; 1675 function = "qup05"; 1676 }; 1677 }; 1678 1679 qup_uart6_default: qup-uart6-default { 1680 pinmux { 1681 pins = "gpio59", "gpio60", 1682 "gpio61", "gpio62"; 1683 function = "qup10"; 1684 }; 1685 }; 1686 1687 qup_uart7_default: qup-uart7-default { 1688 pinmux { 1689 pins = "gpio6", "gpio7"; 1690 function = "qup11_uart"; 1691 }; 1692 }; 1693 1694 qup_uart8_default: qup-uart8-default { 1695 pinmux { 1696 pins = "gpio44", "gpio45"; 1697 function = "qup12"; 1698 }; 1699 }; 1700 1701 qup_uart9_default: qup-uart9-default { 1702 pinmux { 1703 pins = "gpio46", "gpio47"; 1704 function = "qup13_uart"; 1705 }; 1706 }; 1707 1708 qup_uart10_default: qup-uart10-default { 1709 pinmux { 1710 pins = "gpio86", "gpio87", 1711 "gpio88", "gpio89"; 1712 function = "qup14"; 1713 }; 1714 }; 1715 1716 qup_uart11_default: qup-uart11-default { 1717 pinmux { 1718 pins = "gpio53", "gpio54", 1719 "gpio55", "gpio56"; 1720 function = "qup15"; 1721 }; 1722 }; 1723 1724 sdc1_on: sdc1-on { 1725 pinconf-clk { 1726 pins = "sdc1_clk"; 1727 bias-disable; 1728 drive-strength = <16>; 1729 }; 1730 1731 pinconf-cmd { 1732 pins = "sdc1_cmd"; 1733 bias-pull-up; 1734 drive-strength = <10>; 1735 }; 1736 1737 pinconf-data { 1738 pins = "sdc1_data"; 1739 bias-pull-up; 1740 drive-strength = <10>; 1741 }; 1742 1743 pinconf-rclk { 1744 pins = "sdc1_rclk"; 1745 bias-pull-down; 1746 }; 1747 }; 1748 1749 sdc1_off: sdc1-off { 1750 pinconf-clk { 1751 pins = "sdc1_clk"; 1752 bias-disable; 1753 drive-strength = <2>; 1754 }; 1755 1756 pinconf-cmd { 1757 pins = "sdc1_cmd"; 1758 bias-pull-up; 1759 drive-strength = <2>; 1760 }; 1761 1762 pinconf-data { 1763 pins = "sdc1_data"; 1764 bias-pull-up; 1765 drive-strength = <2>; 1766 }; 1767 1768 pinconf-rclk { 1769 pins = "sdc1_rclk"; 1770 bias-pull-down; 1771 }; 1772 }; 1773 1774 sdc2_on: sdc2-on { 1775 pinconf-clk { 1776 pins = "sdc2_clk"; 1777 bias-disable; 1778 drive-strength = <16>; 1779 }; 1780 1781 pinconf-cmd { 1782 pins = "sdc2_cmd"; 1783 bias-pull-up; 1784 drive-strength = <10>; 1785 }; 1786 1787 pinconf-data { 1788 pins = "sdc2_data"; 1789 bias-pull-up; 1790 drive-strength = <10>; 1791 }; 1792 1793 pinconf-sd-cd { 1794 pins = "gpio69"; 1795 bias-pull-up; 1796 drive-strength = <2>; 1797 }; 1798 }; 1799 1800 sdc2_off: sdc2-off { 1801 pinconf-clk { 1802 pins = "sdc2_clk"; 1803 bias-disable; 1804 drive-strength = <2>; 1805 }; 1806 1807 pinconf-cmd { 1808 pins = "sdc2_cmd"; 1809 bias-pull-up; 1810 drive-strength = <2>; 1811 }; 1812 1813 pinconf-data { 1814 pins = "sdc2_data"; 1815 bias-pull-up; 1816 drive-strength = <2>; 1817 }; 1818 1819 pinconf-sd-cd { 1820 pins = "gpio69"; 1821 bias-disable; 1822 drive-strength = <2>; 1823 }; 1824 }; 1825 }; 1826 1827 remoteproc_mpss: remoteproc@4080000 { 1828 compatible = "qcom,sc7180-mpss-pas"; 1829 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1830 reg-names = "qdsp6", "rmb"; 1831 1832 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1833 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1834 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1835 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1836 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1837 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1838 interrupt-names = "wdog", "fatal", "ready", "handover", 1839 "stop-ack", "shutdown-ack"; 1840 1841 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1842 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1843 <&gcc GCC_MSS_NAV_AXI_CLK>, 1844 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1845 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1846 <&rpmhcc RPMH_CXO_CLK>; 1847 clock-names = "iface", "bus", "nav", "snoc_axi", 1848 "mnoc_axi", "xo"; 1849 1850 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 1851 <&rpmhpd SC7180_CX>, 1852 <&rpmhpd SC7180_MX>, 1853 <&rpmhpd SC7180_MSS>; 1854 power-domain-names = "load_state", "cx", "mx", "mss"; 1855 1856 memory-region = <&mpss_mem>; 1857 1858 qcom,smem-states = <&modem_smp2p_out 0>; 1859 qcom,smem-state-names = "stop"; 1860 1861 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1862 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1863 reset-names = "mss_restart", "pdc_reset"; 1864 1865 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1866 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 1867 1868 status = "disabled"; 1869 1870 glink-edge { 1871 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1872 label = "modem"; 1873 qcom,remote-pid = <1>; 1874 mboxes = <&apss_shared 12>; 1875 }; 1876 }; 1877 1878 gpu: gpu@5000000 { 1879 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1880 #stream-id-cells = <16>; 1881 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1882 <0 0x05061000 0 0x800>; 1883 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1884 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1885 iommus = <&adreno_smmu 0>; 1886 operating-points-v2 = <&gpu_opp_table>; 1887 qcom,gmu = <&gmu>; 1888 1889 interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; 1890 interconnect-names = "gfx-mem"; 1891 1892 gpu_opp_table: opp-table { 1893 compatible = "operating-points-v2"; 1894 1895 opp-800000000 { 1896 opp-hz = /bits/ 64 <800000000>; 1897 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1898 opp-peak-kBps = <8532000>; 1899 }; 1900 1901 opp-650000000 { 1902 opp-hz = /bits/ 64 <650000000>; 1903 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1904 opp-peak-kBps = <7216000>; 1905 }; 1906 1907 opp-565000000 { 1908 opp-hz = /bits/ 64 <565000000>; 1909 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1910 opp-peak-kBps = <5412000>; 1911 }; 1912 1913 opp-430000000 { 1914 opp-hz = /bits/ 64 <430000000>; 1915 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1916 opp-peak-kBps = <5412000>; 1917 }; 1918 1919 opp-355000000 { 1920 opp-hz = /bits/ 64 <355000000>; 1921 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1922 opp-peak-kBps = <3072000>; 1923 }; 1924 1925 opp-267000000 { 1926 opp-hz = /bits/ 64 <267000000>; 1927 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1928 opp-peak-kBps = <3072000>; 1929 }; 1930 1931 opp-180000000 { 1932 opp-hz = /bits/ 64 <180000000>; 1933 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1934 opp-peak-kBps = <1804000>; 1935 }; 1936 }; 1937 }; 1938 1939 adreno_smmu: iommu@5040000 { 1940 compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; 1941 reg = <0 0x05040000 0 0x10000>; 1942 #iommu-cells = <1>; 1943 #global-interrupts = <2>; 1944 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 1947 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 1948 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 1949 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 1950 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 1951 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 1952 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 1953 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 1954 1955 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1956 <&gcc GCC_GPU_CFG_AHB_CLK>; 1957 clock-names = "bus", "iface"; 1958 1959 power-domains = <&gpucc CX_GDSC>; 1960 }; 1961 1962 gmu: gmu@506a000 { 1963 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 1964 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 1965 <0 0x0b490000 0 0x10000>; 1966 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1967 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1969 interrupt-names = "hfi", "gmu"; 1970 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1971 <&gpucc GPU_CC_CXO_CLK>, 1972 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1973 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1974 clock-names = "gmu", "cxo", "axi", "memnoc"; 1975 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 1976 power-domain-names = "cx", "gx"; 1977 iommus = <&adreno_smmu 5>; 1978 operating-points-v2 = <&gmu_opp_table>; 1979 1980 gmu_opp_table: opp-table { 1981 compatible = "operating-points-v2"; 1982 1983 opp-200000000 { 1984 opp-hz = /bits/ 64 <200000000>; 1985 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1986 }; 1987 }; 1988 }; 1989 1990 gpucc: clock-controller@5090000 { 1991 compatible = "qcom,sc7180-gpucc"; 1992 reg = <0 0x05090000 0 0x9000>; 1993 clocks = <&rpmhcc RPMH_CXO_CLK>, 1994 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1995 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1996 clock-names = "bi_tcxo", 1997 "gcc_gpu_gpll0_clk_src", 1998 "gcc_gpu_gpll0_div_clk_src"; 1999 #clock-cells = <1>; 2000 #reset-cells = <1>; 2001 #power-domain-cells = <1>; 2002 }; 2003 2004 stm@6002000 { 2005 compatible = "arm,coresight-stm", "arm,primecell"; 2006 reg = <0 0x06002000 0 0x1000>, 2007 <0 0x16280000 0 0x180000>; 2008 reg-names = "stm-base", "stm-stimulus-base"; 2009 2010 clocks = <&aoss_qmp>; 2011 clock-names = "apb_pclk"; 2012 2013 out-ports { 2014 port { 2015 stm_out: endpoint { 2016 remote-endpoint = <&funnel0_in7>; 2017 }; 2018 }; 2019 }; 2020 }; 2021 2022 funnel@6041000 { 2023 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2024 reg = <0 0x06041000 0 0x1000>; 2025 2026 clocks = <&aoss_qmp>; 2027 clock-names = "apb_pclk"; 2028 2029 out-ports { 2030 port { 2031 funnel0_out: endpoint { 2032 remote-endpoint = <&merge_funnel_in0>; 2033 }; 2034 }; 2035 }; 2036 2037 in-ports { 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 2041 port@7 { 2042 reg = <7>; 2043 funnel0_in7: endpoint { 2044 remote-endpoint = <&stm_out>; 2045 }; 2046 }; 2047 }; 2048 }; 2049 2050 funnel@6042000 { 2051 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2052 reg = <0 0x06042000 0 0x1000>; 2053 2054 clocks = <&aoss_qmp>; 2055 clock-names = "apb_pclk"; 2056 2057 out-ports { 2058 port { 2059 funnel1_out: endpoint { 2060 remote-endpoint = <&merge_funnel_in1>; 2061 }; 2062 }; 2063 }; 2064 2065 in-ports { 2066 #address-cells = <1>; 2067 #size-cells = <0>; 2068 2069 port@4 { 2070 reg = <4>; 2071 funnel1_in4: endpoint { 2072 remote-endpoint = <&apss_merge_funnel_out>; 2073 }; 2074 }; 2075 }; 2076 }; 2077 2078 funnel@6045000 { 2079 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2080 reg = <0 0x06045000 0 0x1000>; 2081 2082 clocks = <&aoss_qmp>; 2083 clock-names = "apb_pclk"; 2084 2085 out-ports { 2086 port { 2087 merge_funnel_out: endpoint { 2088 remote-endpoint = <&swao_funnel_in>; 2089 }; 2090 }; 2091 }; 2092 2093 in-ports { 2094 #address-cells = <1>; 2095 #size-cells = <0>; 2096 2097 port@0 { 2098 reg = <0>; 2099 merge_funnel_in0: endpoint { 2100 remote-endpoint = <&funnel0_out>; 2101 }; 2102 }; 2103 2104 port@1 { 2105 reg = <1>; 2106 merge_funnel_in1: endpoint { 2107 remote-endpoint = <&funnel1_out>; 2108 }; 2109 }; 2110 }; 2111 }; 2112 2113 replicator@6046000 { 2114 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2115 reg = <0 0x06046000 0 0x1000>; 2116 2117 clocks = <&aoss_qmp>; 2118 clock-names = "apb_pclk"; 2119 2120 out-ports { 2121 port { 2122 replicator_out: endpoint { 2123 remote-endpoint = <&etr_in>; 2124 }; 2125 }; 2126 }; 2127 2128 in-ports { 2129 port { 2130 replicator_in: endpoint { 2131 remote-endpoint = <&swao_replicator_out>; 2132 }; 2133 }; 2134 }; 2135 }; 2136 2137 etr@6048000 { 2138 compatible = "arm,coresight-tmc", "arm,primecell"; 2139 reg = <0 0x06048000 0 0x1000>; 2140 iommus = <&apps_smmu 0x04a0 0x20>; 2141 2142 clocks = <&aoss_qmp>; 2143 clock-names = "apb_pclk"; 2144 arm,scatter-gather; 2145 2146 in-ports { 2147 port { 2148 etr_in: endpoint { 2149 remote-endpoint = <&replicator_out>; 2150 }; 2151 }; 2152 }; 2153 }; 2154 2155 funnel@6b04000 { 2156 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2157 reg = <0 0x06b04000 0 0x1000>; 2158 2159 clocks = <&aoss_qmp>; 2160 clock-names = "apb_pclk"; 2161 2162 out-ports { 2163 port { 2164 swao_funnel_out: endpoint { 2165 remote-endpoint = <&etf_in>; 2166 }; 2167 }; 2168 }; 2169 2170 in-ports { 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 2174 port@7 { 2175 reg = <7>; 2176 swao_funnel_in: endpoint { 2177 remote-endpoint = <&merge_funnel_out>; 2178 }; 2179 }; 2180 }; 2181 }; 2182 2183 etf@6b05000 { 2184 compatible = "arm,coresight-tmc", "arm,primecell"; 2185 reg = <0 0x06b05000 0 0x1000>; 2186 2187 clocks = <&aoss_qmp>; 2188 clock-names = "apb_pclk"; 2189 2190 out-ports { 2191 port { 2192 etf_out: endpoint { 2193 remote-endpoint = <&swao_replicator_in>; 2194 }; 2195 }; 2196 }; 2197 2198 in-ports { 2199 port { 2200 etf_in: endpoint { 2201 remote-endpoint = <&swao_funnel_out>; 2202 }; 2203 }; 2204 }; 2205 }; 2206 2207 replicator@6b06000 { 2208 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2209 reg = <0 0x06b06000 0 0x1000>; 2210 2211 clocks = <&aoss_qmp>; 2212 clock-names = "apb_pclk"; 2213 qcom,replicator-loses-context; 2214 2215 out-ports { 2216 port { 2217 swao_replicator_out: endpoint { 2218 remote-endpoint = <&replicator_in>; 2219 }; 2220 }; 2221 }; 2222 2223 in-ports { 2224 port { 2225 swao_replicator_in: endpoint { 2226 remote-endpoint = <&etf_out>; 2227 }; 2228 }; 2229 }; 2230 }; 2231 2232 etm@7040000 { 2233 compatible = "arm,coresight-etm4x", "arm,primecell"; 2234 reg = <0 0x07040000 0 0x1000>; 2235 2236 cpu = <&CPU0>; 2237 2238 clocks = <&aoss_qmp>; 2239 clock-names = "apb_pclk"; 2240 arm,coresight-loses-context-with-cpu; 2241 qcom,skip-power-up; 2242 2243 out-ports { 2244 port { 2245 etm0_out: endpoint { 2246 remote-endpoint = <&apss_funnel_in0>; 2247 }; 2248 }; 2249 }; 2250 }; 2251 2252 etm@7140000 { 2253 compatible = "arm,coresight-etm4x", "arm,primecell"; 2254 reg = <0 0x07140000 0 0x1000>; 2255 2256 cpu = <&CPU1>; 2257 2258 clocks = <&aoss_qmp>; 2259 clock-names = "apb_pclk"; 2260 arm,coresight-loses-context-with-cpu; 2261 qcom,skip-power-up; 2262 2263 out-ports { 2264 port { 2265 etm1_out: endpoint { 2266 remote-endpoint = <&apss_funnel_in1>; 2267 }; 2268 }; 2269 }; 2270 }; 2271 2272 etm@7240000 { 2273 compatible = "arm,coresight-etm4x", "arm,primecell"; 2274 reg = <0 0x07240000 0 0x1000>; 2275 2276 cpu = <&CPU2>; 2277 2278 clocks = <&aoss_qmp>; 2279 clock-names = "apb_pclk"; 2280 arm,coresight-loses-context-with-cpu; 2281 qcom,skip-power-up; 2282 2283 out-ports { 2284 port { 2285 etm2_out: endpoint { 2286 remote-endpoint = <&apss_funnel_in2>; 2287 }; 2288 }; 2289 }; 2290 }; 2291 2292 etm@7340000 { 2293 compatible = "arm,coresight-etm4x", "arm,primecell"; 2294 reg = <0 0x07340000 0 0x1000>; 2295 2296 cpu = <&CPU3>; 2297 2298 clocks = <&aoss_qmp>; 2299 clock-names = "apb_pclk"; 2300 arm,coresight-loses-context-with-cpu; 2301 qcom,skip-power-up; 2302 2303 out-ports { 2304 port { 2305 etm3_out: endpoint { 2306 remote-endpoint = <&apss_funnel_in3>; 2307 }; 2308 }; 2309 }; 2310 }; 2311 2312 etm@7440000 { 2313 compatible = "arm,coresight-etm4x", "arm,primecell"; 2314 reg = <0 0x07440000 0 0x1000>; 2315 2316 cpu = <&CPU4>; 2317 2318 clocks = <&aoss_qmp>; 2319 clock-names = "apb_pclk"; 2320 arm,coresight-loses-context-with-cpu; 2321 qcom,skip-power-up; 2322 2323 out-ports { 2324 port { 2325 etm4_out: endpoint { 2326 remote-endpoint = <&apss_funnel_in4>; 2327 }; 2328 }; 2329 }; 2330 }; 2331 2332 etm@7540000 { 2333 compatible = "arm,coresight-etm4x", "arm,primecell"; 2334 reg = <0 0x07540000 0 0x1000>; 2335 2336 cpu = <&CPU5>; 2337 2338 clocks = <&aoss_qmp>; 2339 clock-names = "apb_pclk"; 2340 arm,coresight-loses-context-with-cpu; 2341 qcom,skip-power-up; 2342 2343 out-ports { 2344 port { 2345 etm5_out: endpoint { 2346 remote-endpoint = <&apss_funnel_in5>; 2347 }; 2348 }; 2349 }; 2350 }; 2351 2352 etm@7640000 { 2353 compatible = "arm,coresight-etm4x", "arm,primecell"; 2354 reg = <0 0x07640000 0 0x1000>; 2355 2356 cpu = <&CPU6>; 2357 2358 clocks = <&aoss_qmp>; 2359 clock-names = "apb_pclk"; 2360 arm,coresight-loses-context-with-cpu; 2361 qcom,skip-power-up; 2362 2363 out-ports { 2364 port { 2365 etm6_out: endpoint { 2366 remote-endpoint = <&apss_funnel_in6>; 2367 }; 2368 }; 2369 }; 2370 }; 2371 2372 etm@7740000 { 2373 compatible = "arm,coresight-etm4x", "arm,primecell"; 2374 reg = <0 0x07740000 0 0x1000>; 2375 2376 cpu = <&CPU7>; 2377 2378 clocks = <&aoss_qmp>; 2379 clock-names = "apb_pclk"; 2380 arm,coresight-loses-context-with-cpu; 2381 qcom,skip-power-up; 2382 2383 out-ports { 2384 port { 2385 etm7_out: endpoint { 2386 remote-endpoint = <&apss_funnel_in7>; 2387 }; 2388 }; 2389 }; 2390 }; 2391 2392 funnel@7800000 { /* APSS Funnel */ 2393 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2394 reg = <0 0x07800000 0 0x1000>; 2395 2396 clocks = <&aoss_qmp>; 2397 clock-names = "apb_pclk"; 2398 2399 out-ports { 2400 port { 2401 apss_funnel_out: endpoint { 2402 remote-endpoint = <&apss_merge_funnel_in>; 2403 }; 2404 }; 2405 }; 2406 2407 in-ports { 2408 #address-cells = <1>; 2409 #size-cells = <0>; 2410 2411 port@0 { 2412 reg = <0>; 2413 apss_funnel_in0: endpoint { 2414 remote-endpoint = <&etm0_out>; 2415 }; 2416 }; 2417 2418 port@1 { 2419 reg = <1>; 2420 apss_funnel_in1: endpoint { 2421 remote-endpoint = <&etm1_out>; 2422 }; 2423 }; 2424 2425 port@2 { 2426 reg = <2>; 2427 apss_funnel_in2: endpoint { 2428 remote-endpoint = <&etm2_out>; 2429 }; 2430 }; 2431 2432 port@3 { 2433 reg = <3>; 2434 apss_funnel_in3: endpoint { 2435 remote-endpoint = <&etm3_out>; 2436 }; 2437 }; 2438 2439 port@4 { 2440 reg = <4>; 2441 apss_funnel_in4: endpoint { 2442 remote-endpoint = <&etm4_out>; 2443 }; 2444 }; 2445 2446 port@5 { 2447 reg = <5>; 2448 apss_funnel_in5: endpoint { 2449 remote-endpoint = <&etm5_out>; 2450 }; 2451 }; 2452 2453 port@6 { 2454 reg = <6>; 2455 apss_funnel_in6: endpoint { 2456 remote-endpoint = <&etm6_out>; 2457 }; 2458 }; 2459 2460 port@7 { 2461 reg = <7>; 2462 apss_funnel_in7: endpoint { 2463 remote-endpoint = <&etm7_out>; 2464 }; 2465 }; 2466 }; 2467 }; 2468 2469 funnel@7810000 { 2470 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2471 reg = <0 0x07810000 0 0x1000>; 2472 2473 clocks = <&aoss_qmp>; 2474 clock-names = "apb_pclk"; 2475 2476 out-ports { 2477 port { 2478 apss_merge_funnel_out: endpoint { 2479 remote-endpoint = <&funnel1_in4>; 2480 }; 2481 }; 2482 }; 2483 2484 in-ports { 2485 port { 2486 apss_merge_funnel_in: endpoint { 2487 remote-endpoint = <&apss_funnel_out>; 2488 }; 2489 }; 2490 }; 2491 }; 2492 2493 sdhc_2: sdhci@8804000 { 2494 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2495 reg = <0 0x08804000 0 0x1000>; 2496 2497 iommus = <&apps_smmu 0x80 0>; 2498 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2500 interrupt-names = "hc_irq", "pwr_irq"; 2501 2502 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2503 <&gcc GCC_SDCC2_AHB_CLK>; 2504 clock-names = "core", "iface"; 2505 power-domains = <&rpmhpd SC7180_CX>; 2506 operating-points-v2 = <&sdhc2_opp_table>; 2507 2508 bus-width = <4>; 2509 2510 status = "disabled"; 2511 2512 sdhc2_opp_table: sdhc2-opp-table { 2513 compatible = "operating-points-v2"; 2514 2515 opp-100000000 { 2516 opp-hz = /bits/ 64 <100000000>; 2517 required-opps = <&rpmhpd_opp_low_svs>; 2518 }; 2519 2520 opp-202000000 { 2521 opp-hz = /bits/ 64 <202000000>; 2522 required-opps = <&rpmhpd_opp_svs_l1>; 2523 }; 2524 }; 2525 }; 2526 2527 qspi_opp_table: qspi-opp-table { 2528 compatible = "operating-points-v2"; 2529 2530 opp-75000000 { 2531 opp-hz = /bits/ 64 <75000000>; 2532 required-opps = <&rpmhpd_opp_low_svs>; 2533 }; 2534 2535 opp-150000000 { 2536 opp-hz = /bits/ 64 <150000000>; 2537 required-opps = <&rpmhpd_opp_svs>; 2538 }; 2539 2540 opp-300000000 { 2541 opp-hz = /bits/ 64 <300000000>; 2542 required-opps = <&rpmhpd_opp_nom>; 2543 }; 2544 }; 2545 2546 qspi: spi@88dc000 { 2547 compatible = "qcom,qspi-v1"; 2548 reg = <0 0x088dc000 0 0x600>; 2549 #address-cells = <1>; 2550 #size-cells = <0>; 2551 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2552 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2553 <&gcc GCC_QSPI_CORE_CLK>; 2554 clock-names = "iface", "core"; 2555 interconnects = <&gem_noc MASTER_APPSS_PROC 2556 &config_noc SLAVE_QSPI_0>; 2557 interconnect-names = "qspi-config"; 2558 power-domains = <&rpmhpd SC7180_CX>; 2559 operating-points-v2 = <&qspi_opp_table>; 2560 status = "disabled"; 2561 }; 2562 2563 usb_1_hsphy: phy@88e3000 { 2564 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2565 reg = <0 0x088e3000 0 0x400>; 2566 status = "disabled"; 2567 #phy-cells = <0>; 2568 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2569 <&rpmhcc RPMH_CXO_CLK>; 2570 clock-names = "cfg_ahb", "ref"; 2571 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2572 2573 nvmem-cells = <&qusb2p_hstx_trim>; 2574 }; 2575 2576 usb_1_qmpphy: phy-wrapper@88e9000 { 2577 compatible = "qcom,sc7180-qmp-usb3-phy"; 2578 reg = <0 0x088e9000 0 0x18c>, 2579 <0 0x088e8000 0 0x38>; 2580 reg-names = "reg-base", "dp_com"; 2581 status = "disabled"; 2582 #clock-cells = <1>; 2583 #address-cells = <2>; 2584 #size-cells = <2>; 2585 ranges; 2586 2587 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2588 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2589 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2590 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2591 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2592 2593 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2594 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2595 reset-names = "phy", "common"; 2596 2597 usb_1_ssphy: phy@88e9200 { 2598 reg = <0 0x088e9200 0 0x128>, 2599 <0 0x088e9400 0 0x200>, 2600 <0 0x088e9c00 0 0x218>, 2601 <0 0x088e9600 0 0x128>, 2602 <0 0x088e9800 0 0x200>, 2603 <0 0x088e9a00 0 0x18>; 2604 #clock-cells = <0>; 2605 #phy-cells = <0>; 2606 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2607 clock-names = "pipe0"; 2608 clock-output-names = "usb3_phy_pipe_clk_src"; 2609 }; 2610 }; 2611 2612 dc_noc: interconnect@9160000 { 2613 compatible = "qcom,sc7180-dc-noc"; 2614 reg = <0 0x09160000 0 0x03200>; 2615 #interconnect-cells = <1>; 2616 qcom,bcm-voters = <&apps_bcm_voter>; 2617 }; 2618 2619 system-cache-controller@9200000 { 2620 compatible = "qcom,sc7180-llcc"; 2621 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 2622 reg-names = "llcc_base", "llcc_broadcast_base"; 2623 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2624 }; 2625 2626 gem_noc: interconnect@9680000 { 2627 compatible = "qcom,sc7180-gem-noc"; 2628 reg = <0 0x09680000 0 0x3e200>; 2629 #interconnect-cells = <1>; 2630 qcom,bcm-voters = <&apps_bcm_voter>; 2631 }; 2632 2633 npu_noc: interconnect@9990000 { 2634 compatible = "qcom,sc7180-npu-noc"; 2635 reg = <0 0x09990000 0 0x1600>; 2636 #interconnect-cells = <1>; 2637 qcom,bcm-voters = <&apps_bcm_voter>; 2638 }; 2639 2640 usb_1: usb@a6f8800 { 2641 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2642 reg = <0 0x0a6f8800 0 0x400>; 2643 status = "disabled"; 2644 #address-cells = <2>; 2645 #size-cells = <2>; 2646 ranges; 2647 dma-ranges; 2648 2649 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2650 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2651 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2652 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2653 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2654 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2655 "sleep"; 2656 2657 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2658 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2659 assigned-clock-rates = <19200000>, <150000000>; 2660 2661 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2662 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2663 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2664 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2665 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2666 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2667 2668 power-domains = <&gcc USB30_PRIM_GDSC>; 2669 2670 resets = <&gcc GCC_USB30_PRIM_BCR>; 2671 2672 interconnects = <&aggre2_noc MASTER_USB3 &mc_virt SLAVE_EBI1>, 2673 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3>; 2674 interconnect-names = "usb-ddr", "apps-usb"; 2675 2676 usb_1_dwc3: dwc3@a600000 { 2677 compatible = "snps,dwc3"; 2678 reg = <0 0x0a600000 0 0xe000>; 2679 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2680 iommus = <&apps_smmu 0x540 0>; 2681 snps,dis_u2_susphy_quirk; 2682 snps,dis_enblslpm_quirk; 2683 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2684 phy-names = "usb2-phy", "usb3-phy"; 2685 maximum-speed = "super-speed"; 2686 }; 2687 }; 2688 2689 venus: video-codec@aa00000 { 2690 compatible = "qcom,sc7180-venus"; 2691 reg = <0 0x0aa00000 0 0xff000>; 2692 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2693 power-domains = <&videocc VENUS_GDSC>, 2694 <&videocc VCODEC0_GDSC>; 2695 power-domain-names = "venus", "vcodec0"; 2696 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2697 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2698 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2699 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2700 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2701 clock-names = "core", "iface", "bus", 2702 "vcodec0_core", "vcodec0_bus"; 2703 iommus = <&apps_smmu 0x0c00 0x60>; 2704 memory-region = <&venus_mem>; 2705 interconnects = <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>, 2706 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; 2707 interconnect-names = "video-mem", "cpu-cfg"; 2708 2709 video-decoder { 2710 compatible = "venus-decoder"; 2711 }; 2712 2713 video-encoder { 2714 compatible = "venus-encoder"; 2715 }; 2716 }; 2717 2718 videocc: clock-controller@ab00000 { 2719 compatible = "qcom,sc7180-videocc"; 2720 reg = <0 0x0ab00000 0 0x10000>; 2721 clocks = <&rpmhcc RPMH_CXO_CLK>; 2722 clock-names = "bi_tcxo"; 2723 #clock-cells = <1>; 2724 #reset-cells = <1>; 2725 #power-domain-cells = <1>; 2726 }; 2727 2728 camnoc_virt: interconnect@ac00000 { 2729 compatible = "qcom,sc7180-camnoc-virt"; 2730 reg = <0 0x0ac00000 0 0x1000>; 2731 #interconnect-cells = <1>; 2732 qcom,bcm-voters = <&apps_bcm_voter>; 2733 }; 2734 2735 mdss: mdss@ae00000 { 2736 compatible = "qcom,sc7180-mdss"; 2737 reg = <0 0x0ae00000 0 0x1000>; 2738 reg-names = "mdss"; 2739 2740 power-domains = <&dispcc MDSS_GDSC>; 2741 2742 clocks = <&gcc GCC_DISP_AHB_CLK>, 2743 <&gcc GCC_DISP_HF_AXI_CLK>, 2744 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2745 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2746 clock-names = "iface", "bus", "ahb", "core"; 2747 2748 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2749 assigned-clock-rates = <300000000>; 2750 2751 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2752 interrupt-controller; 2753 #interrupt-cells = <1>; 2754 2755 iommus = <&apps_smmu 0x800 0x2>; 2756 2757 #address-cells = <2>; 2758 #size-cells = <2>; 2759 ranges; 2760 2761 status = "disabled"; 2762 2763 mdp: mdp@ae01000 { 2764 compatible = "qcom,sc7180-dpu"; 2765 reg = <0 0x0ae01000 0 0x8f000>, 2766 <0 0x0aeb0000 0 0x2008>; 2767 reg-names = "mdp", "vbif"; 2768 2769 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2770 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2771 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2772 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2773 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2774 clock-names = "iface", "rot", "lut", "core", 2775 "vsync"; 2776 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2777 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2778 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2779 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2780 assigned-clock-rates = <300000000>, 2781 <19200000>, 2782 <19200000>, 2783 <19200000>; 2784 operating-points-v2 = <&mdp_opp_table>; 2785 power-domains = <&rpmhpd SC7180_CX>; 2786 2787 interrupt-parent = <&mdss>; 2788 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2789 2790 status = "disabled"; 2791 2792 ports { 2793 #address-cells = <1>; 2794 #size-cells = <0>; 2795 2796 port@0 { 2797 reg = <0>; 2798 dpu_intf1_out: endpoint { 2799 remote-endpoint = <&dsi0_in>; 2800 }; 2801 }; 2802 }; 2803 2804 mdp_opp_table: mdp-opp-table { 2805 compatible = "operating-points-v2"; 2806 2807 opp-200000000 { 2808 opp-hz = /bits/ 64 <200000000>; 2809 required-opps = <&rpmhpd_opp_low_svs>; 2810 }; 2811 2812 opp-300000000 { 2813 opp-hz = /bits/ 64 <300000000>; 2814 required-opps = <&rpmhpd_opp_svs>; 2815 }; 2816 2817 opp-345000000 { 2818 opp-hz = /bits/ 64 <345000000>; 2819 required-opps = <&rpmhpd_opp_svs_l1>; 2820 }; 2821 2822 opp-460000000 { 2823 opp-hz = /bits/ 64 <460000000>; 2824 required-opps = <&rpmhpd_opp_nom>; 2825 }; 2826 }; 2827 2828 }; 2829 2830 dsi0: dsi@ae94000 { 2831 compatible = "qcom,mdss-dsi-ctrl"; 2832 reg = <0 0x0ae94000 0 0x400>; 2833 reg-names = "dsi_ctrl"; 2834 2835 interrupt-parent = <&mdss>; 2836 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2837 2838 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2839 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2840 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2841 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2842 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2843 <&gcc GCC_DISP_HF_AXI_CLK>; 2844 clock-names = "byte", 2845 "byte_intf", 2846 "pixel", 2847 "core", 2848 "iface", 2849 "bus"; 2850 2851 operating-points-v2 = <&dsi_opp_table>; 2852 power-domains = <&rpmhpd SC7180_CX>; 2853 2854 phys = <&dsi_phy>; 2855 phy-names = "dsi"; 2856 2857 #address-cells = <1>; 2858 #size-cells = <0>; 2859 2860 status = "disabled"; 2861 2862 ports { 2863 #address-cells = <1>; 2864 #size-cells = <0>; 2865 2866 port@0 { 2867 reg = <0>; 2868 dsi0_in: endpoint { 2869 remote-endpoint = <&dpu_intf1_out>; 2870 }; 2871 }; 2872 2873 port@1 { 2874 reg = <1>; 2875 dsi0_out: endpoint { 2876 }; 2877 }; 2878 }; 2879 2880 dsi_opp_table: dsi-opp-table { 2881 compatible = "operating-points-v2"; 2882 2883 opp-187500000 { 2884 opp-hz = /bits/ 64 <187500000>; 2885 required-opps = <&rpmhpd_opp_low_svs>; 2886 }; 2887 2888 opp-300000000 { 2889 opp-hz = /bits/ 64 <300000000>; 2890 required-opps = <&rpmhpd_opp_svs>; 2891 }; 2892 2893 opp-358000000 { 2894 opp-hz = /bits/ 64 <358000000>; 2895 required-opps = <&rpmhpd_opp_svs_l1>; 2896 }; 2897 }; 2898 }; 2899 2900 dsi_phy: dsi-phy@ae94400 { 2901 compatible = "qcom,dsi-phy-10nm"; 2902 reg = <0 0x0ae94400 0 0x200>, 2903 <0 0x0ae94600 0 0x280>, 2904 <0 0x0ae94a00 0 0x1e0>; 2905 reg-names = "dsi_phy", 2906 "dsi_phy_lane", 2907 "dsi_pll"; 2908 2909 #clock-cells = <1>; 2910 #phy-cells = <0>; 2911 2912 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2913 <&rpmhcc RPMH_CXO_CLK>; 2914 clock-names = "iface", "ref"; 2915 2916 status = "disabled"; 2917 }; 2918 }; 2919 2920 dispcc: clock-controller@af00000 { 2921 compatible = "qcom,sc7180-dispcc"; 2922 reg = <0 0x0af00000 0 0x200000>; 2923 clocks = <&rpmhcc RPMH_CXO_CLK>, 2924 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2925 <&dsi_phy 0>, 2926 <&dsi_phy 1>, 2927 <0>, 2928 <0>; 2929 clock-names = "bi_tcxo", 2930 "gcc_disp_gpll0_clk_src", 2931 "dsi0_phy_pll_out_byteclk", 2932 "dsi0_phy_pll_out_dsiclk", 2933 "dp_phy_pll_link_clk", 2934 "dp_phy_pll_vco_div_clk"; 2935 #clock-cells = <1>; 2936 #reset-cells = <1>; 2937 #power-domain-cells = <1>; 2938 }; 2939 2940 pdc: interrupt-controller@b220000 { 2941 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 2942 reg = <0 0x0b220000 0 0x30000>; 2943 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 2944 #interrupt-cells = <2>; 2945 interrupt-parent = <&intc>; 2946 interrupt-controller; 2947 }; 2948 2949 pdc_reset: reset-controller@b2e0000 { 2950 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 2951 reg = <0 0x0b2e0000 0 0x20000>; 2952 #reset-cells = <1>; 2953 }; 2954 2955 tsens0: thermal-sensor@c263000 { 2956 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 2957 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2958 <0 0x0c222000 0 0x1ff>; /* SROT */ 2959 #qcom,sensors = <15>; 2960 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2961 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2962 interrupt-names = "uplow","critical"; 2963 #thermal-sensor-cells = <1>; 2964 }; 2965 2966 tsens1: thermal-sensor@c265000 { 2967 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 2968 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2969 <0 0x0c223000 0 0x1ff>; /* SROT */ 2970 #qcom,sensors = <10>; 2971 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2973 interrupt-names = "uplow","critical"; 2974 #thermal-sensor-cells = <1>; 2975 }; 2976 2977 aoss_reset: reset-controller@c2a0000 { 2978 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 2979 reg = <0 0x0c2a0000 0 0x31000>; 2980 #reset-cells = <1>; 2981 }; 2982 2983 aoss_qmp: qmp@c300000 { 2984 compatible = "qcom,sc7180-aoss-qmp"; 2985 reg = <0 0x0c300000 0 0x100000>; 2986 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 2987 mboxes = <&apss_shared 0>; 2988 2989 #clock-cells = <0>; 2990 #power-domain-cells = <1>; 2991 }; 2992 2993 spmi_bus: spmi@c440000 { 2994 compatible = "qcom,spmi-pmic-arb"; 2995 reg = <0 0x0c440000 0 0x1100>, 2996 <0 0x0c600000 0 0x2000000>, 2997 <0 0x0e600000 0 0x100000>, 2998 <0 0x0e700000 0 0xa0000>, 2999 <0 0x0c40a000 0 0x26000>; 3000 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3001 interrupt-names = "periph_irq"; 3002 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3003 qcom,ee = <0>; 3004 qcom,channel = <0>; 3005 #address-cells = <1>; 3006 #size-cells = <1>; 3007 interrupt-controller; 3008 #interrupt-cells = <4>; 3009 cell-index = <0>; 3010 }; 3011 3012 apps_smmu: iommu@15000000 { 3013 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3014 reg = <0 0x15000000 0 0x100000>; 3015 #iommu-cells = <2>; 3016 #global-interrupts = <1>; 3017 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3018 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3019 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3020 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3021 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3022 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3023 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3024 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3025 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3026 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3027 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3028 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3030 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3031 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3032 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3033 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3034 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3035 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3036 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3037 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3038 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3039 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3040 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3041 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3042 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3043 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3044 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3045 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3046 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3047 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3048 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3049 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3050 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3051 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3052 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3053 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3054 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3055 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3056 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3057 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3058 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3061 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3062 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3063 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3066 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3067 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3098 }; 3099 3100 intc: interrupt-controller@17a00000 { 3101 compatible = "arm,gic-v3"; 3102 #address-cells = <2>; 3103 #size-cells = <2>; 3104 ranges; 3105 #interrupt-cells = <3>; 3106 interrupt-controller; 3107 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3108 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3109 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3110 3111 msi-controller@17a40000 { 3112 compatible = "arm,gic-v3-its"; 3113 msi-controller; 3114 #msi-cells = <1>; 3115 reg = <0 0x17a40000 0 0x20000>; 3116 status = "disabled"; 3117 }; 3118 }; 3119 3120 apss_shared: mailbox@17c00000 { 3121 compatible = "qcom,sc7180-apss-shared"; 3122 reg = <0 0x17c00000 0 0x10000>; 3123 #mbox-cells = <1>; 3124 }; 3125 3126 watchdog@17c10000 { 3127 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3128 reg = <0 0x17c10000 0 0x1000>; 3129 clocks = <&sleep_clk>; 3130 }; 3131 3132 timer@17c20000{ 3133 #address-cells = <2>; 3134 #size-cells = <2>; 3135 ranges; 3136 compatible = "arm,armv7-timer-mem"; 3137 reg = <0 0x17c20000 0 0x1000>; 3138 3139 frame@17c21000 { 3140 frame-number = <0>; 3141 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3143 reg = <0 0x17c21000 0 0x1000>, 3144 <0 0x17c22000 0 0x1000>; 3145 }; 3146 3147 frame@17c23000 { 3148 frame-number = <1>; 3149 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3150 reg = <0 0x17c23000 0 0x1000>; 3151 status = "disabled"; 3152 }; 3153 3154 frame@17c25000 { 3155 frame-number = <2>; 3156 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3157 reg = <0 0x17c25000 0 0x1000>; 3158 status = "disabled"; 3159 }; 3160 3161 frame@17c27000 { 3162 frame-number = <3>; 3163 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3164 reg = <0 0x17c27000 0 0x1000>; 3165 status = "disabled"; 3166 }; 3167 3168 frame@17c29000 { 3169 frame-number = <4>; 3170 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3171 reg = <0 0x17c29000 0 0x1000>; 3172 status = "disabled"; 3173 }; 3174 3175 frame@17c2b000 { 3176 frame-number = <5>; 3177 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3178 reg = <0 0x17c2b000 0 0x1000>; 3179 status = "disabled"; 3180 }; 3181 3182 frame@17c2d000 { 3183 frame-number = <6>; 3184 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3185 reg = <0 0x17c2d000 0 0x1000>; 3186 status = "disabled"; 3187 }; 3188 }; 3189 3190 apps_rsc: rsc@18200000 { 3191 compatible = "qcom,rpmh-rsc"; 3192 reg = <0 0x18200000 0 0x10000>, 3193 <0 0x18210000 0 0x10000>, 3194 <0 0x18220000 0 0x10000>; 3195 reg-names = "drv-0", "drv-1", "drv-2"; 3196 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3199 qcom,tcs-offset = <0xd00>; 3200 qcom,drv-id = <2>; 3201 qcom,tcs-config = <ACTIVE_TCS 2>, 3202 <SLEEP_TCS 3>, 3203 <WAKE_TCS 3>, 3204 <CONTROL_TCS 1>; 3205 3206 rpmhcc: clock-controller { 3207 compatible = "qcom,sc7180-rpmh-clk"; 3208 clocks = <&xo_board>; 3209 clock-names = "xo"; 3210 #clock-cells = <1>; 3211 }; 3212 3213 rpmhpd: power-controller { 3214 compatible = "qcom,sc7180-rpmhpd"; 3215 #power-domain-cells = <1>; 3216 operating-points-v2 = <&rpmhpd_opp_table>; 3217 3218 rpmhpd_opp_table: opp-table { 3219 compatible = "operating-points-v2"; 3220 3221 rpmhpd_opp_ret: opp1 { 3222 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3223 }; 3224 3225 rpmhpd_opp_min_svs: opp2 { 3226 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3227 }; 3228 3229 rpmhpd_opp_low_svs: opp3 { 3230 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3231 }; 3232 3233 rpmhpd_opp_svs: opp4 { 3234 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3235 }; 3236 3237 rpmhpd_opp_svs_l1: opp5 { 3238 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3239 }; 3240 3241 rpmhpd_opp_svs_l2: opp6 { 3242 opp-level = <224>; 3243 }; 3244 3245 rpmhpd_opp_nom: opp7 { 3246 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3247 }; 3248 3249 rpmhpd_opp_nom_l1: opp8 { 3250 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3251 }; 3252 3253 rpmhpd_opp_nom_l2: opp9 { 3254 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3255 }; 3256 3257 rpmhpd_opp_turbo: opp10 { 3258 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3259 }; 3260 3261 rpmhpd_opp_turbo_l1: opp11 { 3262 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3263 }; 3264 }; 3265 }; 3266 3267 apps_bcm_voter: bcm_voter { 3268 compatible = "qcom,bcm-voter"; 3269 }; 3270 }; 3271 3272 osm_l3: interconnect@18321000 { 3273 compatible = "qcom,sc7180-osm-l3"; 3274 reg = <0 0x18321000 0 0x1400>; 3275 3276 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3277 clock-names = "xo", "alternate"; 3278 3279 #interconnect-cells = <1>; 3280 }; 3281 3282 cpufreq_hw: cpufreq@18323000 { 3283 compatible = "qcom,cpufreq-hw"; 3284 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3285 reg-names = "freq-domain0", "freq-domain1"; 3286 3287 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3288 clock-names = "xo", "alternate"; 3289 3290 #freq-domain-cells = <1>; 3291 }; 3292 3293 wifi: wifi@18800000 { 3294 compatible = "qcom,wcn3990-wifi"; 3295 reg = <0 0x18800000 0 0x800000>; 3296 reg-names = "membase"; 3297 iommus = <&apps_smmu 0xc0 0x1>; 3298 interrupts = 3299 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3300 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3301 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3302 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3303 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3304 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3305 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3306 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3307 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3308 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3309 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3310 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3311 memory-region = <&wlan_mem>; 3312 qcom,msa-fixed-perm; 3313 status = "disabled"; 3314 }; 3315 }; 3316 3317 thermal-zones { 3318 cpu0-thermal { 3319 polling-delay-passive = <0>; 3320 polling-delay = <0>; 3321 3322 thermal-sensors = <&tsens0 1>; 3323 3324 trips { 3325 cpu0_alert0: trip-point0 { 3326 temperature = <90000>; 3327 hysteresis = <2000>; 3328 type = "passive"; 3329 }; 3330 3331 cpu0_alert1: trip-point1 { 3332 temperature = <95000>; 3333 hysteresis = <2000>; 3334 type = "passive"; 3335 }; 3336 3337 cpu0_crit: cpu_crit { 3338 temperature = <110000>; 3339 hysteresis = <1000>; 3340 type = "critical"; 3341 }; 3342 }; 3343 3344 cooling-maps { 3345 map0 { 3346 trip = <&cpu0_alert0>; 3347 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3348 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3349 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3350 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3351 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3352 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3353 }; 3354 map1 { 3355 trip = <&cpu0_alert1>; 3356 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3357 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3358 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3359 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3360 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3361 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3362 }; 3363 }; 3364 }; 3365 3366 cpu1-thermal { 3367 polling-delay-passive = <0>; 3368 polling-delay = <0>; 3369 3370 thermal-sensors = <&tsens0 2>; 3371 3372 trips { 3373 cpu1_alert0: trip-point0 { 3374 temperature = <90000>; 3375 hysteresis = <2000>; 3376 type = "passive"; 3377 }; 3378 3379 cpu1_alert1: trip-point1 { 3380 temperature = <95000>; 3381 hysteresis = <2000>; 3382 type = "passive"; 3383 }; 3384 3385 cpu1_crit: cpu_crit { 3386 temperature = <110000>; 3387 hysteresis = <1000>; 3388 type = "critical"; 3389 }; 3390 }; 3391 3392 cooling-maps { 3393 map0 { 3394 trip = <&cpu1_alert0>; 3395 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3396 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3397 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3398 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3399 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3400 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3401 }; 3402 map1 { 3403 trip = <&cpu1_alert1>; 3404 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3405 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3406 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3407 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3408 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3409 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3410 }; 3411 }; 3412 }; 3413 3414 cpu2-thermal { 3415 polling-delay-passive = <0>; 3416 polling-delay = <0>; 3417 3418 thermal-sensors = <&tsens0 3>; 3419 3420 trips { 3421 cpu2_alert0: trip-point0 { 3422 temperature = <90000>; 3423 hysteresis = <2000>; 3424 type = "passive"; 3425 }; 3426 3427 cpu2_alert1: trip-point1 { 3428 temperature = <95000>; 3429 hysteresis = <2000>; 3430 type = "passive"; 3431 }; 3432 3433 cpu2_crit: cpu_crit { 3434 temperature = <110000>; 3435 hysteresis = <1000>; 3436 type = "critical"; 3437 }; 3438 }; 3439 3440 cooling-maps { 3441 map0 { 3442 trip = <&cpu2_alert0>; 3443 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3444 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3445 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3446 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3447 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3448 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3449 }; 3450 map1 { 3451 trip = <&cpu2_alert1>; 3452 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3453 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3454 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3455 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3456 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3457 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3458 }; 3459 }; 3460 }; 3461 3462 cpu3-thermal { 3463 polling-delay-passive = <0>; 3464 polling-delay = <0>; 3465 3466 thermal-sensors = <&tsens0 4>; 3467 3468 trips { 3469 cpu3_alert0: trip-point0 { 3470 temperature = <90000>; 3471 hysteresis = <2000>; 3472 type = "passive"; 3473 }; 3474 3475 cpu3_alert1: trip-point1 { 3476 temperature = <95000>; 3477 hysteresis = <2000>; 3478 type = "passive"; 3479 }; 3480 3481 cpu3_crit: cpu_crit { 3482 temperature = <110000>; 3483 hysteresis = <1000>; 3484 type = "critical"; 3485 }; 3486 }; 3487 3488 cooling-maps { 3489 map0 { 3490 trip = <&cpu3_alert0>; 3491 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3492 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3493 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3494 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3495 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3496 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3497 }; 3498 map1 { 3499 trip = <&cpu3_alert1>; 3500 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3501 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3502 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3503 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3504 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3505 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3506 }; 3507 }; 3508 }; 3509 3510 cpu4-thermal { 3511 polling-delay-passive = <0>; 3512 polling-delay = <0>; 3513 3514 thermal-sensors = <&tsens0 5>; 3515 3516 trips { 3517 cpu4_alert0: trip-point0 { 3518 temperature = <90000>; 3519 hysteresis = <2000>; 3520 type = "passive"; 3521 }; 3522 3523 cpu4_alert1: trip-point1 { 3524 temperature = <95000>; 3525 hysteresis = <2000>; 3526 type = "passive"; 3527 }; 3528 3529 cpu4_crit: cpu_crit { 3530 temperature = <110000>; 3531 hysteresis = <1000>; 3532 type = "critical"; 3533 }; 3534 }; 3535 3536 cooling-maps { 3537 map0 { 3538 trip = <&cpu4_alert0>; 3539 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3540 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3541 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3542 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3543 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3544 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3545 }; 3546 map1 { 3547 trip = <&cpu4_alert1>; 3548 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3549 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3550 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3551 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3552 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3553 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3554 }; 3555 }; 3556 }; 3557 3558 cpu5-thermal { 3559 polling-delay-passive = <0>; 3560 polling-delay = <0>; 3561 3562 thermal-sensors = <&tsens0 6>; 3563 3564 trips { 3565 cpu5_alert0: trip-point0 { 3566 temperature = <90000>; 3567 hysteresis = <2000>; 3568 type = "passive"; 3569 }; 3570 3571 cpu5_alert1: trip-point1 { 3572 temperature = <95000>; 3573 hysteresis = <2000>; 3574 type = "passive"; 3575 }; 3576 3577 cpu5_crit: cpu_crit { 3578 temperature = <110000>; 3579 hysteresis = <1000>; 3580 type = "critical"; 3581 }; 3582 }; 3583 3584 cooling-maps { 3585 map0 { 3586 trip = <&cpu5_alert0>; 3587 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3588 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3589 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3590 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3591 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3593 }; 3594 map1 { 3595 trip = <&cpu5_alert1>; 3596 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3597 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3598 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3599 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3600 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3601 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3602 }; 3603 }; 3604 }; 3605 3606 cpu6-thermal { 3607 polling-delay-passive = <0>; 3608 polling-delay = <0>; 3609 3610 thermal-sensors = <&tsens0 9>; 3611 3612 trips { 3613 cpu6_alert0: trip-point0 { 3614 temperature = <90000>; 3615 hysteresis = <2000>; 3616 type = "passive"; 3617 }; 3618 3619 cpu6_alert1: trip-point1 { 3620 temperature = <95000>; 3621 hysteresis = <2000>; 3622 type = "passive"; 3623 }; 3624 3625 cpu6_crit: cpu_crit { 3626 temperature = <110000>; 3627 hysteresis = <1000>; 3628 type = "critical"; 3629 }; 3630 }; 3631 3632 cooling-maps { 3633 map0 { 3634 trip = <&cpu6_alert0>; 3635 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3636 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3637 }; 3638 map1 { 3639 trip = <&cpu6_alert1>; 3640 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3641 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3642 }; 3643 }; 3644 }; 3645 3646 cpu7-thermal { 3647 polling-delay-passive = <0>; 3648 polling-delay = <0>; 3649 3650 thermal-sensors = <&tsens0 10>; 3651 3652 trips { 3653 cpu7_alert0: trip-point0 { 3654 temperature = <90000>; 3655 hysteresis = <2000>; 3656 type = "passive"; 3657 }; 3658 3659 cpu7_alert1: trip-point1 { 3660 temperature = <95000>; 3661 hysteresis = <2000>; 3662 type = "passive"; 3663 }; 3664 3665 cpu7_crit: cpu_crit { 3666 temperature = <110000>; 3667 hysteresis = <1000>; 3668 type = "critical"; 3669 }; 3670 }; 3671 3672 cooling-maps { 3673 map0 { 3674 trip = <&cpu7_alert0>; 3675 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3676 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3677 }; 3678 map1 { 3679 trip = <&cpu7_alert1>; 3680 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3681 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3682 }; 3683 }; 3684 }; 3685 3686 cpu8-thermal { 3687 polling-delay-passive = <0>; 3688 polling-delay = <0>; 3689 3690 thermal-sensors = <&tsens0 11>; 3691 3692 trips { 3693 cpu8_alert0: trip-point0 { 3694 temperature = <90000>; 3695 hysteresis = <2000>; 3696 type = "passive"; 3697 }; 3698 3699 cpu8_alert1: trip-point1 { 3700 temperature = <95000>; 3701 hysteresis = <2000>; 3702 type = "passive"; 3703 }; 3704 3705 cpu8_crit: cpu_crit { 3706 temperature = <110000>; 3707 hysteresis = <1000>; 3708 type = "critical"; 3709 }; 3710 }; 3711 3712 cooling-maps { 3713 map0 { 3714 trip = <&cpu8_alert0>; 3715 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3716 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3717 }; 3718 map1 { 3719 trip = <&cpu8_alert1>; 3720 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3721 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3722 }; 3723 }; 3724 }; 3725 3726 cpu9-thermal { 3727 polling-delay-passive = <0>; 3728 polling-delay = <0>; 3729 3730 thermal-sensors = <&tsens0 12>; 3731 3732 trips { 3733 cpu9_alert0: trip-point0 { 3734 temperature = <90000>; 3735 hysteresis = <2000>; 3736 type = "passive"; 3737 }; 3738 3739 cpu9_alert1: trip-point1 { 3740 temperature = <95000>; 3741 hysteresis = <2000>; 3742 type = "passive"; 3743 }; 3744 3745 cpu9_crit: cpu_crit { 3746 temperature = <110000>; 3747 hysteresis = <1000>; 3748 type = "critical"; 3749 }; 3750 }; 3751 3752 cooling-maps { 3753 map0 { 3754 trip = <&cpu9_alert0>; 3755 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3756 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3757 }; 3758 map1 { 3759 trip = <&cpu9_alert1>; 3760 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3761 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3762 }; 3763 }; 3764 }; 3765 3766 aoss0-thermal { 3767 polling-delay-passive = <0>; 3768 polling-delay = <0>; 3769 3770 thermal-sensors = <&tsens0 0>; 3771 3772 trips { 3773 aoss0_alert0: trip-point0 { 3774 temperature = <90000>; 3775 hysteresis = <2000>; 3776 type = "hot"; 3777 }; 3778 3779 aoss0_crit: aoss0_crit { 3780 temperature = <110000>; 3781 hysteresis = <2000>; 3782 type = "critical"; 3783 }; 3784 }; 3785 }; 3786 3787 cpuss0-thermal { 3788 polling-delay-passive = <0>; 3789 polling-delay = <0>; 3790 3791 thermal-sensors = <&tsens0 7>; 3792 3793 trips { 3794 cpuss0_alert0: trip-point0 { 3795 temperature = <90000>; 3796 hysteresis = <2000>; 3797 type = "hot"; 3798 }; 3799 cpuss0_crit: cluster0_crit { 3800 temperature = <110000>; 3801 hysteresis = <2000>; 3802 type = "critical"; 3803 }; 3804 }; 3805 }; 3806 3807 cpuss1-thermal { 3808 polling-delay-passive = <0>; 3809 polling-delay = <0>; 3810 3811 thermal-sensors = <&tsens0 8>; 3812 3813 trips { 3814 cpuss1_alert0: trip-point0 { 3815 temperature = <90000>; 3816 hysteresis = <2000>; 3817 type = "hot"; 3818 }; 3819 cpuss1_crit: cluster0_crit { 3820 temperature = <110000>; 3821 hysteresis = <2000>; 3822 type = "critical"; 3823 }; 3824 }; 3825 }; 3826 3827 gpuss0-thermal { 3828 polling-delay-passive = <0>; 3829 polling-delay = <0>; 3830 3831 thermal-sensors = <&tsens0 13>; 3832 3833 trips { 3834 gpuss0_alert0: trip-point0 { 3835 temperature = <90000>; 3836 hysteresis = <2000>; 3837 type = "hot"; 3838 }; 3839 3840 gpuss0_crit: gpuss0_crit { 3841 temperature = <110000>; 3842 hysteresis = <2000>; 3843 type = "critical"; 3844 }; 3845 }; 3846 }; 3847 3848 gpuss1-thermal { 3849 polling-delay-passive = <0>; 3850 polling-delay = <0>; 3851 3852 thermal-sensors = <&tsens0 14>; 3853 3854 trips { 3855 gpuss1_alert0: trip-point0 { 3856 temperature = <90000>; 3857 hysteresis = <2000>; 3858 type = "hot"; 3859 }; 3860 3861 gpuss1_crit: gpuss1_crit { 3862 temperature = <110000>; 3863 hysteresis = <2000>; 3864 type = "critical"; 3865 }; 3866 }; 3867 }; 3868 3869 aoss1-thermal { 3870 polling-delay-passive = <0>; 3871 polling-delay = <0>; 3872 3873 thermal-sensors = <&tsens1 0>; 3874 3875 trips { 3876 aoss1_alert0: trip-point0 { 3877 temperature = <90000>; 3878 hysteresis = <2000>; 3879 type = "hot"; 3880 }; 3881 3882 aoss1_crit: aoss1_crit { 3883 temperature = <110000>; 3884 hysteresis = <2000>; 3885 type = "critical"; 3886 }; 3887 }; 3888 }; 3889 3890 cwlan-thermal { 3891 polling-delay-passive = <0>; 3892 polling-delay = <0>; 3893 3894 thermal-sensors = <&tsens1 1>; 3895 3896 trips { 3897 cwlan_alert0: trip-point0 { 3898 temperature = <90000>; 3899 hysteresis = <2000>; 3900 type = "hot"; 3901 }; 3902 3903 cwlan_crit: cwlan_crit { 3904 temperature = <110000>; 3905 hysteresis = <2000>; 3906 type = "critical"; 3907 }; 3908 }; 3909 }; 3910 3911 audio-thermal { 3912 polling-delay-passive = <0>; 3913 polling-delay = <0>; 3914 3915 thermal-sensors = <&tsens1 2>; 3916 3917 trips { 3918 audio_alert0: trip-point0 { 3919 temperature = <90000>; 3920 hysteresis = <2000>; 3921 type = "hot"; 3922 }; 3923 3924 audio_crit: audio_crit { 3925 temperature = <110000>; 3926 hysteresis = <2000>; 3927 type = "critical"; 3928 }; 3929 }; 3930 }; 3931 3932 ddr-thermal { 3933 polling-delay-passive = <0>; 3934 polling-delay = <0>; 3935 3936 thermal-sensors = <&tsens1 3>; 3937 3938 trips { 3939 ddr_alert0: trip-point0 { 3940 temperature = <90000>; 3941 hysteresis = <2000>; 3942 type = "hot"; 3943 }; 3944 3945 ddr_crit: ddr_crit { 3946 temperature = <110000>; 3947 hysteresis = <2000>; 3948 type = "critical"; 3949 }; 3950 }; 3951 }; 3952 3953 q6-hvx-thermal { 3954 polling-delay-passive = <0>; 3955 polling-delay = <0>; 3956 3957 thermal-sensors = <&tsens1 4>; 3958 3959 trips { 3960 q6_hvx_alert0: trip-point0 { 3961 temperature = <90000>; 3962 hysteresis = <2000>; 3963 type = "hot"; 3964 }; 3965 3966 q6_hvx_crit: q6_hvx_crit { 3967 temperature = <110000>; 3968 hysteresis = <2000>; 3969 type = "critical"; 3970 }; 3971 }; 3972 }; 3973 3974 camera-thermal { 3975 polling-delay-passive = <0>; 3976 polling-delay = <0>; 3977 3978 thermal-sensors = <&tsens1 5>; 3979 3980 trips { 3981 camera_alert0: trip-point0 { 3982 temperature = <90000>; 3983 hysteresis = <2000>; 3984 type = "hot"; 3985 }; 3986 3987 camera_crit: camera_crit { 3988 temperature = <110000>; 3989 hysteresis = <2000>; 3990 type = "critical"; 3991 }; 3992 }; 3993 }; 3994 3995 mdm-core-thermal { 3996 polling-delay-passive = <0>; 3997 polling-delay = <0>; 3998 3999 thermal-sensors = <&tsens1 6>; 4000 4001 trips { 4002 mdm_alert0: trip-point0 { 4003 temperature = <90000>; 4004 hysteresis = <2000>; 4005 type = "hot"; 4006 }; 4007 4008 mdm_crit: mdm_crit { 4009 temperature = <110000>; 4010 hysteresis = <2000>; 4011 type = "critical"; 4012 }; 4013 }; 4014 }; 4015 4016 mdm-dsp-thermal { 4017 polling-delay-passive = <0>; 4018 polling-delay = <0>; 4019 4020 thermal-sensors = <&tsens1 7>; 4021 4022 trips { 4023 mdm_dsp_alert0: trip-point0 { 4024 temperature = <90000>; 4025 hysteresis = <2000>; 4026 type = "hot"; 4027 }; 4028 4029 mdm_dsp_crit: mdm_dsp_crit { 4030 temperature = <110000>; 4031 hysteresis = <2000>; 4032 type = "critical"; 4033 }; 4034 }; 4035 }; 4036 4037 npu-thermal { 4038 polling-delay-passive = <0>; 4039 polling-delay = <0>; 4040 4041 thermal-sensors = <&tsens1 8>; 4042 4043 trips { 4044 npu_alert0: trip-point0 { 4045 temperature = <90000>; 4046 hysteresis = <2000>; 4047 type = "hot"; 4048 }; 4049 4050 npu_crit: npu_crit { 4051 temperature = <110000>; 4052 hysteresis = <2000>; 4053 type = "critical"; 4054 }; 4055 }; 4056 }; 4057 4058 video-thermal { 4059 polling-delay-passive = <0>; 4060 polling-delay = <0>; 4061 4062 thermal-sensors = <&tsens1 9>; 4063 4064 trips { 4065 video_alert0: trip-point0 { 4066 temperature = <90000>; 4067 hysteresis = <2000>; 4068 type = "hot"; 4069 }; 4070 4071 video_crit: video_crit { 4072 temperature = <110000>; 4073 hysteresis = <2000>; 4074 type = "critical"; 4075 }; 4076 }; 4077 }; 4078 }; 4079 4080 timer { 4081 compatible = "arm,armv8-timer"; 4082 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4083 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4084 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4085 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4086 }; 4087}; 4088