1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,icc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 clocks { 23 xo_board_clk: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 qcom,freq-domain = <&cpufreq_hw 0>; 44 next-level-cache = <&L2_0>; 45 L2_0: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 cache-unified; 49 next-level-cache = <&L3_0>; 50 L3_0: l3-cache { 51 compatible = "cache"; 52 cache-level = <3>; 53 cache-unified; 54 }; 55 }; 56 }; 57 58 CPU1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "qcom,kryo"; 61 reg = <0x0 0x100>; 62 enable-method = "psci"; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 next-level-cache = <&L2_1>; 65 L2_1: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 }; 71 }; 72 73 CPU2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 next-level-cache = <&L2_2>; 80 L2_2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU3: cpu@300 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo"; 91 reg = <0x0 0x300>; 92 enable-method = "psci"; 93 qcom,freq-domain = <&cpufreq_hw 0>; 94 next-level-cache = <&L2_3>; 95 L2_3: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&L3_0>; 100 }; 101 }; 102 103 CPU4: cpu@10000 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo"; 106 reg = <0x0 0x10000>; 107 enable-method = "psci"; 108 qcom,freq-domain = <&cpufreq_hw 1>; 109 next-level-cache = <&L2_4>; 110 L2_4: l2-cache { 111 compatible = "cache"; 112 cache-level = <2>; 113 cache-unified; 114 next-level-cache = <&L3_1>; 115 L3_1: l3-cache { 116 compatible = "cache"; 117 cache-level = <3>; 118 cache-unified; 119 }; 120 121 }; 122 }; 123 124 CPU5: cpu@10100 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo"; 127 reg = <0x0 0x10100>; 128 enable-method = "psci"; 129 qcom,freq-domain = <&cpufreq_hw 1>; 130 next-level-cache = <&L2_5>; 131 L2_5: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 next-level-cache = <&L3_1>; 136 }; 137 }; 138 139 CPU6: cpu@10200 { 140 device_type = "cpu"; 141 compatible = "qcom,kryo"; 142 reg = <0x0 0x10200>; 143 enable-method = "psci"; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 next-level-cache = <&L2_6>; 146 L2_6: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_1>; 151 }; 152 }; 153 154 CPU7: cpu@10300 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo"; 157 reg = <0x0 0x10300>; 158 enable-method = "psci"; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 next-level-cache = <&L2_7>; 161 L2_7: l2-cache { 162 compatible = "cache"; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&L3_1>; 166 }; 167 }; 168 169 cpu-map { 170 cluster0 { 171 core0 { 172 cpu = <&CPU0>; 173 }; 174 175 core1 { 176 cpu = <&CPU1>; 177 }; 178 179 core2 { 180 cpu = <&CPU2>; 181 }; 182 183 core3 { 184 cpu = <&CPU3>; 185 }; 186 }; 187 188 cluster1 { 189 core0 { 190 cpu = <&CPU4>; 191 }; 192 193 core1 { 194 cpu = <&CPU5>; 195 }; 196 197 core2 { 198 cpu = <&CPU6>; 199 }; 200 201 core3 { 202 cpu = <&CPU7>; 203 }; 204 }; 205 }; 206 }; 207 208 firmware { 209 scm { 210 compatible = "qcom,scm-sa8775p", "qcom,scm"; 211 }; 212 }; 213 214 aggre1_noc: interconnect-aggre1-noc { 215 compatible = "qcom,sa8775p-aggre1-noc"; 216 #interconnect-cells = <2>; 217 qcom,bcm-voters = <&apps_bcm_voter>; 218 }; 219 220 aggre2_noc: interconnect-aggre2-noc { 221 compatible = "qcom,sa8775p-aggre2-noc"; 222 #interconnect-cells = <2>; 223 qcom,bcm-voters = <&apps_bcm_voter>; 224 }; 225 226 clk_virt: interconnect-clk-virt { 227 compatible = "qcom,sa8775p-clk-virt"; 228 #interconnect-cells = <2>; 229 qcom,bcm-voters = <&apps_bcm_voter>; 230 }; 231 232 config_noc: interconnect-config-noc { 233 compatible = "qcom,sa8775p-config-noc"; 234 #interconnect-cells = <2>; 235 qcom,bcm-voters = <&apps_bcm_voter>; 236 }; 237 238 dc_noc: interconnect-dc-noc { 239 compatible = "qcom,sa8775p-dc-noc"; 240 #interconnect-cells = <2>; 241 qcom,bcm-voters = <&apps_bcm_voter>; 242 }; 243 244 gem_noc: interconnect-gem-noc { 245 compatible = "qcom,sa8775p-gem-noc"; 246 #interconnect-cells = <2>; 247 qcom,bcm-voters = <&apps_bcm_voter>; 248 }; 249 250 gpdsp_anoc: interconnect-gpdsp-anoc { 251 compatible = "qcom,sa8775p-gpdsp-anoc"; 252 #interconnect-cells = <2>; 253 qcom,bcm-voters = <&apps_bcm_voter>; 254 }; 255 256 lpass_ag_noc: interconnect-lpass-ag-noc { 257 compatible = "qcom,sa8775p-lpass-ag-noc"; 258 #interconnect-cells = <2>; 259 qcom,bcm-voters = <&apps_bcm_voter>; 260 }; 261 262 mc_virt: interconnect-mc-virt { 263 compatible = "qcom,sa8775p-mc-virt"; 264 #interconnect-cells = <2>; 265 qcom,bcm-voters = <&apps_bcm_voter>; 266 }; 267 268 mmss_noc: interconnect-mmss-noc { 269 compatible = "qcom,sa8775p-mmss-noc"; 270 #interconnect-cells = <2>; 271 qcom,bcm-voters = <&apps_bcm_voter>; 272 }; 273 274 nspa_noc: interconnect-nspa-noc { 275 compatible = "qcom,sa8775p-nspa-noc"; 276 #interconnect-cells = <2>; 277 qcom,bcm-voters = <&apps_bcm_voter>; 278 }; 279 280 nspb_noc: interconnect-nspb-noc { 281 compatible = "qcom,sa8775p-nspb-noc"; 282 #interconnect-cells = <2>; 283 qcom,bcm-voters = <&apps_bcm_voter>; 284 }; 285 286 pcie_anoc: interconnect-pcie-anoc { 287 compatible = "qcom,sa8775p-pcie-anoc"; 288 #interconnect-cells = <2>; 289 qcom,bcm-voters = <&apps_bcm_voter>; 290 }; 291 292 system_noc: interconnect-system-noc { 293 compatible = "qcom,sa8775p-system-noc"; 294 #interconnect-cells = <2>; 295 qcom,bcm-voters = <&apps_bcm_voter>; 296 }; 297 298 /* Will be updated by the bootloader. */ 299 memory@80000000 { 300 device_type = "memory"; 301 reg = <0x0 0x80000000 0x0 0x0>; 302 }; 303 304 qup_opp_table_100mhz: opp-table-qup100mhz { 305 compatible = "operating-points-v2"; 306 307 opp-100000000 { 308 opp-hz = /bits/ 64 <100000000>; 309 required-opps = <&rpmhpd_opp_svs_l1>; 310 }; 311 }; 312 313 pmu { 314 compatible = "arm,armv8-pmuv3"; 315 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 316 }; 317 318 psci { 319 compatible = "arm,psci-1.0"; 320 method = "smc"; 321 }; 322 323 reserved-memory { 324 #address-cells = <2>; 325 #size-cells = <2>; 326 ranges; 327 328 sail_ss_mem: sail-ss@80000000 { 329 reg = <0x0 0x80000000 0x0 0x10000000>; 330 no-map; 331 }; 332 333 hyp_mem: hyp@90000000 { 334 reg = <0x0 0x90000000 0x0 0x600000>; 335 no-map; 336 }; 337 338 xbl_boot_mem: xbl-boot@90600000 { 339 reg = <0x0 0x90600000 0x0 0x200000>; 340 no-map; 341 }; 342 343 aop_image_mem: aop-image@90800000 { 344 reg = <0x0 0x90800000 0x0 0x60000>; 345 no-map; 346 }; 347 348 aop_cmd_db_mem: aop-cmd-db@90860000 { 349 compatible = "qcom,cmd-db"; 350 reg = <0x0 0x90860000 0x0 0x20000>; 351 no-map; 352 }; 353 354 uefi_log: uefi-log@908b0000 { 355 reg = <0x0 0x908b0000 0x0 0x10000>; 356 no-map; 357 }; 358 359 reserved_mem: reserved@908f0000 { 360 reg = <0x0 0x908f0000 0x0 0xf000>; 361 no-map; 362 }; 363 364 secdata_apss_mem: secdata-apss@908ff000 { 365 reg = <0x0 0x908ff000 0x0 0x1000>; 366 no-map; 367 }; 368 369 smem_mem: smem@90900000 { 370 compatible = "qcom,smem"; 371 reg = <0x0 0x90900000 0x0 0x200000>; 372 no-map; 373 hwlocks = <&tcsr_mutex 3>; 374 }; 375 376 cpucp_fw_mem: cpucp-fw@90b00000 { 377 reg = <0x0 0x90b00000 0x0 0x100000>; 378 no-map; 379 }; 380 381 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 382 reg = <0x0 0x93b00000 0x0 0xf00000>; 383 no-map; 384 }; 385 386 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 387 reg = <0x0 0x94a00000 0x0 0x800000>; 388 no-map; 389 }; 390 391 pil_camera_mem: pil-camera@95200000 { 392 reg = <0x0 0x95200000 0x0 0x500000>; 393 no-map; 394 }; 395 396 pil_adsp_mem: pil-adsp@95c00000 { 397 reg = <0x0 0x95c00000 0x0 0x1e00000>; 398 no-map; 399 }; 400 401 pil_gdsp0_mem: pil-gdsp0@97b00000 { 402 reg = <0x0 0x97b00000 0x0 0x1e00000>; 403 no-map; 404 }; 405 406 pil_gdsp1_mem: pil-gdsp1@99900000 { 407 reg = <0x0 0x99900000 0x0 0x1e00000>; 408 no-map; 409 }; 410 411 pil_cdsp0_mem: pil-cdsp0@9b800000 { 412 reg = <0x0 0x9b800000 0x0 0x1e00000>; 413 no-map; 414 }; 415 416 pil_gpu_mem: pil-gpu@9d600000 { 417 reg = <0x0 0x9d600000 0x0 0x2000>; 418 no-map; 419 }; 420 421 pil_cdsp1_mem: pil-cdsp1@9d700000 { 422 reg = <0x0 0x9d700000 0x0 0x1e00000>; 423 no-map; 424 }; 425 426 pil_cvp_mem: pil-cvp@9f500000 { 427 reg = <0x0 0x9f500000 0x0 0x700000>; 428 no-map; 429 }; 430 431 pil_video_mem: pil-video@9fc00000 { 432 reg = <0x0 0x9fc00000 0x0 0x700000>; 433 no-map; 434 }; 435 436 hyptz_reserved_mem: hyptz-reserved@beb00000 { 437 reg = <0x0 0xbeb00000 0x0 0x11500000>; 438 no-map; 439 }; 440 441 tz_stat_mem: tz-stat@d0000000 { 442 reg = <0x0 0xd0000000 0x0 0x100000>; 443 no-map; 444 }; 445 446 tags_mem: tags@d0100000 { 447 reg = <0x0 0xd0100000 0x0 0x1200000>; 448 no-map; 449 }; 450 451 qtee_mem: qtee@d1300000 { 452 reg = <0x0 0xd1300000 0x0 0x500000>; 453 no-map; 454 }; 455 456 trusted_apps_mem: trusted-apps@d1800000 { 457 reg = <0x0 0xd1800000 0x0 0x3900000>; 458 no-map; 459 }; 460 }; 461 462 soc: soc@0 { 463 compatible = "simple-bus"; 464 #address-cells = <2>; 465 #size-cells = <2>; 466 ranges = <0 0 0 0 0x10 0>; 467 468 gcc: clock-controller@100000 { 469 compatible = "qcom,sa8775p-gcc"; 470 reg = <0x0 0x00100000 0x0 0xc7018>; 471 #clock-cells = <1>; 472 #reset-cells = <1>; 473 #power-domain-cells = <1>; 474 clocks = <&rpmhcc RPMH_CXO_CLK>, 475 <&sleep_clk>, 476 <0>, 477 <0>, 478 <0>, 479 <&usb_0_qmpphy>, 480 <&usb_1_qmpphy>, 481 <0>, 482 <0>, 483 <0>, 484 <&pcie0_phy>, 485 <&pcie1_phy>, 486 <0>, 487 <0>, 488 <0>; 489 power-domains = <&rpmhpd SA8775P_CX>; 490 }; 491 492 ipcc: mailbox@408000 { 493 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 494 reg = <0x0 0x00408000 0x0 0x1000>; 495 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-controller; 497 #interrupt-cells = <3>; 498 #mbox-cells = <2>; 499 }; 500 501 qupv3_id_2: geniqup@8c0000 { 502 compatible = "qcom,geni-se-qup"; 503 reg = <0x0 0x008c0000 0x0 0x6000>; 504 ranges; 505 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 506 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 507 clock-names = "m-ahb", "s-ahb"; 508 iommus = <&apps_smmu 0x5a3 0x0>; 509 #address-cells = <2>; 510 #size-cells = <2>; 511 status = "disabled"; 512 513 i2c14: i2c@880000 { 514 compatible = "qcom,geni-i2c"; 515 reg = <0x0 0x880000 0x0 0x4000>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 520 clock-names = "se"; 521 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 522 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 523 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 524 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 525 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 526 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 527 interconnect-names = "qup-core", 528 "qup-config", 529 "qup-memory"; 530 power-domains = <&rpmhpd SA8775P_CX>; 531 status = "disabled"; 532 }; 533 534 spi14: spi@880000 { 535 compatible = "qcom,geni-spi"; 536 reg = <0x0 0x880000 0x0 0x4000>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 541 clock-names = "se"; 542 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 543 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 544 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 545 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 546 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 547 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 548 interconnect-names = "qup-core", 549 "qup-config", 550 "qup-memory"; 551 power-domains = <&rpmhpd SA8775P_CX>; 552 status = "disabled"; 553 }; 554 555 i2c15: i2c@884000 { 556 compatible = "qcom,geni-i2c"; 557 reg = <0x0 0x884000 0x0 0x4000>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 562 clock-names = "se"; 563 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 564 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 565 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 566 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 567 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 568 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 569 interconnect-names = "qup-core", 570 "qup-config", 571 "qup-memory"; 572 power-domains = <&rpmhpd SA8775P_CX>; 573 status = "disabled"; 574 }; 575 576 spi15: spi@884000 { 577 compatible = "qcom,geni-spi"; 578 reg = <0x0 0x884000 0x0 0x4000>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 583 clock-names = "se"; 584 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 585 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 586 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 587 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 588 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 589 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 590 interconnect-names = "qup-core", 591 "qup-config", 592 "qup-memory"; 593 power-domains = <&rpmhpd SA8775P_CX>; 594 status = "disabled"; 595 }; 596 597 i2c16: i2c@888000 { 598 compatible = "qcom,geni-i2c"; 599 reg = <0x0 0x888000 0x0 0x4000>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 604 clock-names = "se"; 605 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 606 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 607 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 608 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 609 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 610 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 611 interconnect-names = "qup-core", 612 "qup-config", 613 "qup-memory"; 614 power-domains = <&rpmhpd SA8775P_CX>; 615 status = "disabled"; 616 }; 617 618 spi16: spi@888000 { 619 compatible = "qcom,geni-spi"; 620 reg = <0x0 0x00888000 0x0 0x4000>; 621 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 623 clock-names = "se"; 624 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 625 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 626 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 627 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 628 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 629 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 630 interconnect-names = "qup-core", 631 "qup-config", 632 "qup-memory"; 633 power-domains = <&rpmhpd SA8775P_CX>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 status = "disabled"; 637 }; 638 639 i2c17: i2c@88c000 { 640 compatible = "qcom,geni-i2c"; 641 reg = <0x0 0x88c000 0x0 0x4000>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 646 clock-names = "se"; 647 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 648 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 650 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 651 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 652 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 653 interconnect-names = "qup-core", 654 "qup-config", 655 "qup-memory"; 656 power-domains = <&rpmhpd SA8775P_CX>; 657 status = "disabled"; 658 }; 659 660 spi17: spi@88c000 { 661 compatible = "qcom,geni-spi"; 662 reg = <0x0 0x88c000 0x0 0x4000>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 667 clock-names = "se"; 668 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 669 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 670 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 671 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 672 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 673 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 674 interconnect-names = "qup-core", 675 "qup-config", 676 "qup-memory"; 677 power-domains = <&rpmhpd SA8775P_CX>; 678 status = "disabled"; 679 }; 680 681 uart17: serial@88c000 { 682 compatible = "qcom,geni-uart"; 683 reg = <0x0 0x0088c000 0x0 0x4000>; 684 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 686 clock-names = "se"; 687 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 688 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 689 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 690 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 691 interconnect-names = "qup-core", "qup-config"; 692 power-domains = <&rpmhpd SA8775P_CX>; 693 status = "disabled"; 694 }; 695 696 i2c18: i2c@890000 { 697 compatible = "qcom,geni-i2c"; 698 reg = <0x0 0x00890000 0x0 0x4000>; 699 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 701 clock-names = "se"; 702 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 703 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 704 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 705 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 706 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 707 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 708 interconnect-names = "qup-core", 709 "qup-config", 710 "qup-memory"; 711 power-domains = <&rpmhpd SA8775P_CX>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 status = "disabled"; 715 }; 716 717 spi18: spi@890000 { 718 compatible = "qcom,geni-spi"; 719 reg = <0x0 0x890000 0x0 0x4000>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 724 clock-names = "se"; 725 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 726 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 728 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 729 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 731 interconnect-names = "qup-core", 732 "qup-config", 733 "qup-memory"; 734 power-domains = <&rpmhpd SA8775P_CX>; 735 status = "disabled"; 736 }; 737 738 i2c19: i2c@894000 { 739 compatible = "qcom,geni-i2c"; 740 reg = <0x0 0x894000 0x0 0x4000>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 745 clock-names = "se"; 746 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 747 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 748 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 749 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 750 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 751 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 752 interconnect-names = "qup-core", 753 "qup-config", 754 "qup-memory"; 755 power-domains = <&rpmhpd SA8775P_CX>; 756 status = "disabled"; 757 }; 758 759 spi19: spi@894000 { 760 compatible = "qcom,geni-spi"; 761 reg = <0x0 0x894000 0x0 0x4000>; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 766 clock-names = "se"; 767 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 768 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 769 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 770 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 771 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 772 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 773 interconnect-names = "qup-core", 774 "qup-config", 775 "qup-memory"; 776 power-domains = <&rpmhpd SA8775P_CX>; 777 status = "disabled"; 778 }; 779 780 i2c20: i2c@898000 { 781 compatible = "qcom,geni-i2c"; 782 reg = <0x0 0x898000 0x0 0x4000>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 787 clock-names = "se"; 788 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 789 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 790 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 791 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 792 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 793 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 794 interconnect-names = "qup-core", 795 "qup-config", 796 "qup-memory"; 797 power-domains = <&rpmhpd SA8775P_CX>; 798 status = "disabled"; 799 }; 800 801 spi20: spi@898000 { 802 compatible = "qcom,geni-spi"; 803 reg = <0x0 0x898000 0x0 0x4000>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 808 clock-names = "se"; 809 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 810 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 811 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 812 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 813 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 814 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 815 interconnect-names = "qup-core", 816 "qup-config", 817 "qup-memory"; 818 power-domains = <&rpmhpd SA8775P_CX>; 819 status = "disabled"; 820 }; 821 }; 822 823 qupv3_id_0: geniqup@9c0000 { 824 compatible = "qcom,geni-se-qup"; 825 reg = <0x0 0x9c0000 0x0 0x6000>; 826 #address-cells = <2>; 827 #size-cells = <2>; 828 ranges; 829 clock-names = "m-ahb", "s-ahb"; 830 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 831 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 832 iommus = <&apps_smmu 0x403 0x0>; 833 status = "disabled"; 834 835 i2c0: i2c@980000 { 836 compatible = "qcom,geni-i2c"; 837 reg = <0x0 0x980000 0x0 0x4000>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 842 clock-names = "se"; 843 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 844 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 845 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 846 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 847 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 848 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 849 interconnect-names = "qup-core", 850 "qup-config", 851 "qup-memory"; 852 power-domains = <&rpmhpd SA8775P_CX>; 853 status = "disabled"; 854 }; 855 856 spi0: spi@980000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0x0 0x980000 0x0 0x4000>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 863 clock-names = "se"; 864 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 865 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 866 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 867 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 868 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 869 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 870 interconnect-names = "qup-core", 871 "qup-config", 872 "qup-memory"; 873 power-domains = <&rpmhpd SA8775P_CX>; 874 status = "disabled"; 875 }; 876 877 i2c1: i2c@984000 { 878 compatible = "qcom,geni-i2c"; 879 reg = <0x0 0x984000 0x0 0x4000>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 884 clock-names = "se"; 885 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 886 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 887 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 888 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 889 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 890 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 891 interconnect-names = "qup-core", 892 "qup-config", 893 "qup-memory"; 894 power-domains = <&rpmhpd SA8775P_CX>; 895 status = "disabled"; 896 }; 897 898 spi1: spi@984000 { 899 compatible = "qcom,geni-spi"; 900 reg = <0x0 0x984000 0x0 0x4000>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 905 clock-names = "se"; 906 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 907 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 908 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 909 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 910 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 912 interconnect-names = "qup-core", 913 "qup-config", 914 "qup-memory"; 915 power-domains = <&rpmhpd SA8775P_CX>; 916 status = "disabled"; 917 }; 918 919 i2c2: i2c@988000 { 920 compatible = "qcom,geni-i2c"; 921 reg = <0x0 0x988000 0x0 0x4000>; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 926 clock-names = "se"; 927 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 928 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 929 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 930 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 931 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 932 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 933 interconnect-names = "qup-core", 934 "qup-config", 935 "qup-memory"; 936 power-domains = <&rpmhpd SA8775P_CX>; 937 status = "disabled"; 938 }; 939 940 spi2: spi@988000 { 941 compatible = "qcom,geni-spi"; 942 reg = <0x0 0x988000 0x0 0x4000>; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 947 clock-names = "se"; 948 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 949 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 950 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 951 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 952 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 953 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 954 interconnect-names = "qup-core", 955 "qup-config", 956 "qup-memory"; 957 power-domains = <&rpmhpd SA8775P_CX>; 958 status = "disabled"; 959 }; 960 961 i2c3: i2c@98c000 { 962 compatible = "qcom,geni-i2c"; 963 reg = <0x0 0x98c000 0x0 0x4000>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 968 clock-names = "se"; 969 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 970 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 971 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 972 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 973 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 974 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 975 interconnect-names = "qup-core", 976 "qup-config", 977 "qup-memory"; 978 power-domains = <&rpmhpd SA8775P_CX>; 979 status = "disabled"; 980 }; 981 982 spi3: spi@98c000 { 983 compatible = "qcom,geni-spi"; 984 reg = <0x0 0x98c000 0x0 0x4000>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 989 clock-names = "se"; 990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 994 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 996 interconnect-names = "qup-core", 997 "qup-config", 998 "qup-memory"; 999 power-domains = <&rpmhpd SA8775P_CX>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c4: i2c@990000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0x0 0x990000 0x0 0x4000>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1010 clock-names = "se"; 1011 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1012 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1013 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1014 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1015 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1016 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1017 interconnect-names = "qup-core", 1018 "qup-config", 1019 "qup-memory"; 1020 power-domains = <&rpmhpd SA8775P_CX>; 1021 status = "disabled"; 1022 }; 1023 1024 spi4: spi@990000 { 1025 compatible = "qcom,geni-spi"; 1026 reg = <0x0 0x990000 0x0 0x4000>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1031 clock-names = "se"; 1032 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1033 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1035 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1036 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1037 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1038 interconnect-names = "qup-core", 1039 "qup-config", 1040 "qup-memory"; 1041 power-domains = <&rpmhpd SA8775P_CX>; 1042 status = "disabled"; 1043 }; 1044 1045 i2c5: i2c@994000 { 1046 compatible = "qcom,geni-i2c"; 1047 reg = <0x0 0x994000 0x0 0x4000>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1052 clock-names = "se"; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1054 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1056 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1057 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1059 interconnect-names = "qup-core", 1060 "qup-config", 1061 "qup-memory"; 1062 power-domains = <&rpmhpd SA8775P_CX>; 1063 status = "disabled"; 1064 }; 1065 1066 spi5: spi@994000 { 1067 compatible = "qcom,geni-spi"; 1068 reg = <0x0 0x994000 0x0 0x4000>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1073 clock-names = "se"; 1074 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1075 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1076 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1077 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1078 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1079 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1080 interconnect-names = "qup-core", 1081 "qup-config", 1082 "qup-memory"; 1083 power-domains = <&rpmhpd SA8775P_CX>; 1084 status = "disabled"; 1085 }; 1086 1087 uart5: serial@994000 { 1088 compatible = "qcom,geni-uart"; 1089 reg = <0x0 0x994000 0x0 0x4000>; 1090 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1092 clock-names = "se"; 1093 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1094 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1095 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1096 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1097 interconnect-names = "qup-core", "qup-config"; 1098 power-domains = <&rpmhpd SA8775P_CX>; 1099 status = "disabled"; 1100 }; 1101 }; 1102 1103 qupv3_id_1: geniqup@ac0000 { 1104 compatible = "qcom,geni-se-qup"; 1105 reg = <0x0 0x00ac0000 0x0 0x6000>; 1106 #address-cells = <2>; 1107 #size-cells = <2>; 1108 ranges; 1109 clock-names = "m-ahb", "s-ahb"; 1110 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1111 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1112 iommus = <&apps_smmu 0x443 0x0>; 1113 status = "disabled"; 1114 1115 i2c7: i2c@a80000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0x0 0xa80000 0x0 0x4000>; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1122 clock-names = "se"; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1124 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1125 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1126 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1127 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1128 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1129 interconnect-names = "qup-core", 1130 "qup-config", 1131 "qup-memory"; 1132 power-domains = <&rpmhpd SA8775P_CX>; 1133 status = "disabled"; 1134 }; 1135 1136 spi7: spi@a80000 { 1137 compatible = "qcom,geni-spi"; 1138 reg = <0x0 0xa80000 0x0 0x4000>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1143 clock-names = "se"; 1144 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1145 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1146 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1147 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1148 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1150 interconnect-names = "qup-core", 1151 "qup-config", 1152 "qup-memory"; 1153 power-domains = <&rpmhpd SA8775P_CX>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c8: i2c@a84000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0x0 0xa84000 0x0 0x4000>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1164 clock-names = "se"; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1166 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1167 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1168 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1169 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1170 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1171 interconnect-names = "qup-core", 1172 "qup-config", 1173 "qup-memory"; 1174 power-domains = <&rpmhpd SA8775P_CX>; 1175 status = "disabled"; 1176 }; 1177 1178 spi8: spi@a84000 { 1179 compatible = "qcom,geni-spi"; 1180 reg = <0x0 0xa84000 0x0 0x4000>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1185 clock-names = "se"; 1186 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1187 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1189 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1190 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1192 interconnect-names = "qup-core", 1193 "qup-config", 1194 "qup-memory"; 1195 power-domains = <&rpmhpd SA8775P_CX>; 1196 status = "disabled"; 1197 }; 1198 1199 i2c9: i2c@a88000 { 1200 compatible = "qcom,geni-i2c"; 1201 reg = <0x0 0xa88000 0x0 0x4000>; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1205 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1206 clock-names = "se"; 1207 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1208 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1209 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1210 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1211 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1212 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1213 interconnect-names = "qup-core", 1214 "qup-config", 1215 "qup-memory"; 1216 power-domains = <&rpmhpd SA8775P_CX>; 1217 status = "disabled"; 1218 }; 1219 1220 spi9: spi@a88000 { 1221 compatible = "qcom,geni-spi"; 1222 reg = <0x0 0xa88000 0x0 0x4000>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1226 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1227 clock-names = "se"; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1229 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1230 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1231 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1232 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1233 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1234 interconnect-names = "qup-core", 1235 "qup-config", 1236 "qup-memory"; 1237 power-domains = <&rpmhpd SA8775P_CX>; 1238 status = "disabled"; 1239 }; 1240 1241 uart9: serial@a88000 { 1242 compatible = "qcom,geni-uart"; 1243 reg = <0x0 0xa88000 0x0 0x4000>; 1244 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1246 clock-names = "se"; 1247 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1248 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1249 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1250 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1251 interconnect-names = "qup-core", "qup-config"; 1252 power-domains = <&rpmhpd SA8775P_CX>; 1253 status = "disabled"; 1254 }; 1255 1256 i2c10: i2c@a8c000 { 1257 compatible = "qcom,geni-i2c"; 1258 reg = <0x0 0xa8c000 0x0 0x4000>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1263 clock-names = "se"; 1264 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1265 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1266 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1267 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1268 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1269 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1270 interconnect-names = "qup-core", 1271 "qup-config", 1272 "qup-memory"; 1273 power-domains = <&rpmhpd SA8775P_CX>; 1274 status = "disabled"; 1275 }; 1276 1277 spi10: spi@a8c000 { 1278 compatible = "qcom,geni-spi"; 1279 reg = <0x0 0xa8c000 0x0 0x4000>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1284 clock-names = "se"; 1285 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1286 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1287 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1288 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1289 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1290 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1291 interconnect-names = "qup-core", 1292 "qup-config", 1293 "qup-memory"; 1294 power-domains = <&rpmhpd SA8775P_CX>; 1295 status = "disabled"; 1296 }; 1297 1298 uart10: serial@a8c000 { 1299 compatible = "qcom,geni-uart"; 1300 reg = <0x0 0x00a8c000 0x0 0x4000>; 1301 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1304 interconnect-names = "qup-core", "qup-config"; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 1306 &clk_virt SLAVE_QUP_CORE_1 0>, 1307 <&gem_noc MASTER_APPSS_PROC 0 1308 &config_noc SLAVE_QUP_1 0>; 1309 power-domains = <&rpmhpd SA8775P_CX>; 1310 operating-points-v2 = <&qup_opp_table_100mhz>; 1311 status = "disabled"; 1312 }; 1313 1314 i2c11: i2c@a90000 { 1315 compatible = "qcom,geni-i2c"; 1316 reg = <0x0 0xa90000 0x0 0x4000>; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1321 clock-names = "se"; 1322 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1323 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1324 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1325 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1326 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1328 interconnect-names = "qup-core", 1329 "qup-config", 1330 "qup-memory"; 1331 power-domains = <&rpmhpd SA8775P_CX>; 1332 status = "disabled"; 1333 }; 1334 1335 spi11: spi@a90000 { 1336 compatible = "qcom,geni-spi"; 1337 reg = <0x0 0xa90000 0x0 0x4000>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1342 clock-names = "se"; 1343 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1344 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1345 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1346 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1347 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1348 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1349 interconnect-names = "qup-core", 1350 "qup-config", 1351 "qup-memory"; 1352 power-domains = <&rpmhpd SA8775P_CX>; 1353 status = "disabled"; 1354 }; 1355 1356 i2c12: i2c@a94000 { 1357 compatible = "qcom,geni-i2c"; 1358 reg = <0x0 0xa94000 0x0 0x4000>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1363 clock-names = "se"; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1365 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1366 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1367 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1368 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1369 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1370 interconnect-names = "qup-core", 1371 "qup-config", 1372 "qup-memory"; 1373 power-domains = <&rpmhpd SA8775P_CX>; 1374 status = "disabled"; 1375 }; 1376 1377 spi12: spi@a94000 { 1378 compatible = "qcom,geni-spi"; 1379 reg = <0x0 0xa94000 0x0 0x4000>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1383 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1384 clock-names = "se"; 1385 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1386 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1388 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1389 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1391 interconnect-names = "qup-core", 1392 "qup-config", 1393 "qup-memory"; 1394 power-domains = <&rpmhpd SA8775P_CX>; 1395 status = "disabled"; 1396 }; 1397 1398 uart12: serial@a94000 { 1399 compatible = "qcom,geni-uart"; 1400 reg = <0x0 0x00a94000 0x0 0x4000>; 1401 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1402 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1403 clock-names = "se"; 1404 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1405 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1406 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1407 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1408 interconnect-names = "qup-core", "qup-config"; 1409 power-domains = <&rpmhpd SA8775P_CX>; 1410 status = "disabled"; 1411 }; 1412 1413 i2c13: i2c@a98000 { 1414 compatible = "qcom,geni-i2c"; 1415 reg = <0x0 0xa98000 0x0 0x4000>; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1419 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1420 clock-names = "se"; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1422 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1423 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1424 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1425 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1426 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1427 interconnect-names = "qup-core", 1428 "qup-config", 1429 "qup-memory"; 1430 power-domains = <&rpmhpd SA8775P_CX>; 1431 status = "disabled"; 1432 }; 1433 }; 1434 1435 qupv3_id_3: geniqup@bc0000 { 1436 compatible = "qcom,geni-se-qup"; 1437 reg = <0x0 0xbc0000 0x0 0x6000>; 1438 #address-cells = <2>; 1439 #size-cells = <2>; 1440 ranges; 1441 clock-names = "m-ahb", "s-ahb"; 1442 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 1443 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 1444 iommus = <&apps_smmu 0x43 0x0>; 1445 status = "disabled"; 1446 1447 i2c21: i2c@b80000 { 1448 compatible = "qcom,geni-i2c"; 1449 reg = <0x0 0xb80000 0x0 0x4000>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1453 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1454 clock-names = "se"; 1455 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1456 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1457 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1458 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1459 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1460 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1461 interconnect-names = "qup-core", 1462 "qup-config", 1463 "qup-memory"; 1464 power-domains = <&rpmhpd SA8775P_CX>; 1465 status = "disabled"; 1466 }; 1467 1468 spi21: spi@b80000 { 1469 compatible = "qcom,geni-spi"; 1470 reg = <0x0 0xb80000 0x0 0x4000>; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1474 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1475 clock-names = "se"; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1477 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1479 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1480 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1482 interconnect-names = "qup-core", 1483 "qup-config", 1484 "qup-memory"; 1485 power-domains = <&rpmhpd SA8775P_CX>; 1486 status = "disabled"; 1487 }; 1488 }; 1489 1490 rng: rng@10d2000 { 1491 compatible = "qcom,sa8775p-trng", "qcom,trng"; 1492 reg = <0 0x010d2000 0 0x1000>; 1493 }; 1494 1495 ufs_mem_hc: ufs@1d84000 { 1496 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1497 reg = <0x0 0x01d84000 0x0 0x3000>; 1498 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1499 phys = <&ufs_mem_phy>; 1500 phy-names = "ufsphy"; 1501 lanes-per-direction = <2>; 1502 #reset-cells = <1>; 1503 resets = <&gcc GCC_UFS_PHY_BCR>; 1504 reset-names = "rst"; 1505 power-domains = <&gcc UFS_PHY_GDSC>; 1506 required-opps = <&rpmhpd_opp_nom>; 1507 iommus = <&apps_smmu 0x100 0x0>; 1508 dma-coherent; 1509 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1510 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1511 <&gcc GCC_UFS_PHY_AHB_CLK>, 1512 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1513 <&rpmhcc RPMH_CXO_CLK>, 1514 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1515 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1516 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1517 clock-names = "core_clk", 1518 "bus_aggr_clk", 1519 "iface_clk", 1520 "core_clk_unipro", 1521 "ref_clk", 1522 "tx_lane0_sync_clk", 1523 "rx_lane0_sync_clk", 1524 "rx_lane1_sync_clk"; 1525 freq-table-hz = <75000000 300000000>, 1526 <0 0>, 1527 <0 0>, 1528 <75000000 300000000>, 1529 <0 0>, 1530 <0 0>, 1531 <0 0>, 1532 <0 0>; 1533 qcom,ice = <&ice>; 1534 status = "disabled"; 1535 }; 1536 1537 ufs_mem_phy: phy@1d87000 { 1538 compatible = "qcom,sa8775p-qmp-ufs-phy"; 1539 reg = <0x0 0x01d87000 0x0 0xe10>; 1540 /* 1541 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 1542 * enables the CXO clock to eDP *and* UFS PHY. 1543 */ 1544 clocks = <&rpmhcc RPMH_CXO_CLK>, 1545 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1546 <&gcc GCC_EDP_REF_CLKREF_EN>; 1547 clock-names = "ref", "ref_aux", "qref"; 1548 power-domains = <&gcc UFS_PHY_GDSC>; 1549 resets = <&ufs_mem_hc 0>; 1550 reset-names = "ufsphy"; 1551 #phy-cells = <0>; 1552 status = "disabled"; 1553 }; 1554 1555 ice: crypto@1d88000 { 1556 compatible = "qcom,sa8775p-inline-crypto-engine", 1557 "qcom,inline-crypto-engine"; 1558 reg = <0x0 0x01d88000 0x0 0x8000>; 1559 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1560 }; 1561 1562 usb_0_hsphy: phy@88e4000 { 1563 compatible = "qcom,sa8775p-usb-hs-phy", 1564 "qcom,usb-snps-hs-5nm-phy"; 1565 reg = <0 0x088e4000 0 0x120>; 1566 clocks = <&rpmhcc RPMH_CXO_CLK>; 1567 clock-names = "ref"; 1568 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 1569 1570 #phy-cells = <0>; 1571 1572 status = "disabled"; 1573 }; 1574 1575 usb_0_qmpphy: phy@88e8000 { 1576 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 1577 reg = <0 0x088e8000 0 0x2000>; 1578 1579 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1580 <&gcc GCC_USB_CLKREF_EN>, 1581 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1582 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1583 clock-names = "aux", "ref", "com_aux", "pipe"; 1584 1585 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1586 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 1587 reset-names = "phy", "phy_phy"; 1588 1589 power-domains = <&gcc USB30_PRIM_GDSC>; 1590 1591 #clock-cells = <0>; 1592 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 1593 1594 #phy-cells = <0>; 1595 1596 status = "disabled"; 1597 }; 1598 1599 usb_0: usb@a6f8800 { 1600 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 1601 reg = <0 0x0a6f8800 0 0x400>; 1602 #address-cells = <2>; 1603 #size-cells = <2>; 1604 ranges; 1605 1606 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1607 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1608 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1609 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1610 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1611 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 1612 1613 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1614 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1615 assigned-clock-rates = <19200000>, <200000000>; 1616 1617 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 1618 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1619 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1620 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 1621 interrupt-names = "pwr_event", 1622 "dp_hs_phy_irq", 1623 "dm_hs_phy_irq", 1624 "ss_phy_irq"; 1625 1626 power-domains = <&gcc USB30_PRIM_GDSC>; 1627 required-opps = <&rpmhpd_opp_nom>; 1628 1629 resets = <&gcc GCC_USB30_PRIM_BCR>; 1630 1631 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1632 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 1633 interconnect-names = "usb-ddr", "apps-usb"; 1634 1635 wakeup-source; 1636 1637 status = "disabled"; 1638 1639 usb_0_dwc3: usb@a600000 { 1640 compatible = "snps,dwc3"; 1641 reg = <0 0x0a600000 0 0xe000>; 1642 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 1643 iommus = <&apps_smmu 0x080 0x0>; 1644 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 1645 phy-names = "usb2-phy", "usb3-phy"; 1646 }; 1647 }; 1648 1649 usb_1_hsphy: phy@88e6000 { 1650 compatible = "qcom,sa8775p-usb-hs-phy", 1651 "qcom,usb-snps-hs-5nm-phy"; 1652 reg = <0 0x088e6000 0 0x120>; 1653 clocks = <&gcc GCC_USB_CLKREF_EN>; 1654 clock-names = "ref"; 1655 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 1656 1657 #phy-cells = <0>; 1658 1659 status = "disabled"; 1660 }; 1661 1662 usb_1_qmpphy: phy@88ea000 { 1663 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 1664 reg = <0 0x088ea000 0 0x2000>; 1665 1666 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1667 <&gcc GCC_USB_CLKREF_EN>, 1668 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 1669 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1670 clock-names = "aux", "ref", "com_aux", "pipe"; 1671 1672 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 1673 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 1674 reset-names = "phy", "phy_phy"; 1675 1676 power-domains = <&gcc USB30_SEC_GDSC>; 1677 1678 #clock-cells = <0>; 1679 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 1680 1681 #phy-cells = <0>; 1682 1683 status = "disabled"; 1684 }; 1685 1686 usb_1: usb@a8f8800 { 1687 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 1688 reg = <0 0x0a8f8800 0 0x400>; 1689 #address-cells = <2>; 1690 #size-cells = <2>; 1691 ranges; 1692 1693 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1694 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1695 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1696 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 1697 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 1698 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 1699 1700 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1701 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1702 assigned-clock-rates = <19200000>, <200000000>; 1703 1704 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 1705 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 1706 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 1707 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 1708 interrupt-names = "pwr_event", 1709 "dp_hs_phy_irq", 1710 "dm_hs_phy_irq", 1711 "ss_phy_irq"; 1712 1713 power-domains = <&gcc USB30_SEC_GDSC>; 1714 required-opps = <&rpmhpd_opp_nom>; 1715 1716 resets = <&gcc GCC_USB30_SEC_BCR>; 1717 1718 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 1719 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 1720 interconnect-names = "usb-ddr", "apps-usb"; 1721 1722 wakeup-source; 1723 1724 status = "disabled"; 1725 1726 usb_1_dwc3: usb@a800000 { 1727 compatible = "snps,dwc3"; 1728 reg = <0 0x0a800000 0 0xe000>; 1729 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 1730 iommus = <&apps_smmu 0x0a0 0x0>; 1731 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 1732 phy-names = "usb2-phy", "usb3-phy"; 1733 }; 1734 }; 1735 1736 usb_2_hsphy: phy@88e7000 { 1737 compatible = "qcom,sa8775p-usb-hs-phy", 1738 "qcom,usb-snps-hs-5nm-phy"; 1739 reg = <0 0x088e7000 0 0x120>; 1740 clocks = <&gcc GCC_USB_CLKREF_EN>; 1741 clock-names = "ref"; 1742 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 1743 1744 #phy-cells = <0>; 1745 1746 status = "disabled"; 1747 }; 1748 1749 usb_2: usb@a4f8800 { 1750 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 1751 reg = <0 0x0a4f8800 0 0x400>; 1752 #address-cells = <2>; 1753 #size-cells = <2>; 1754 ranges; 1755 1756 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 1757 <&gcc GCC_USB20_MASTER_CLK>, 1758 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 1759 <&gcc GCC_USB20_SLEEP_CLK>, 1760 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 1761 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 1762 1763 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1764 <&gcc GCC_USB20_MASTER_CLK>; 1765 assigned-clock-rates = <19200000>, <200000000>; 1766 1767 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 1768 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 1769 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 1770 interrupt-names = "pwr_event", 1771 "dp_hs_phy_irq", 1772 "dm_hs_phy_irq"; 1773 1774 power-domains = <&gcc USB20_PRIM_GDSC>; 1775 required-opps = <&rpmhpd_opp_nom>; 1776 1777 resets = <&gcc GCC_USB20_PRIM_BCR>; 1778 1779 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1780 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 1781 interconnect-names = "usb-ddr", "apps-usb"; 1782 1783 wakeup-source; 1784 1785 status = "disabled"; 1786 1787 usb_2_dwc3: usb@a400000 { 1788 compatible = "snps,dwc3"; 1789 reg = <0 0x0a400000 0 0xe000>; 1790 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 1791 iommus = <&apps_smmu 0x020 0x0>; 1792 phys = <&usb_2_hsphy>; 1793 phy-names = "usb2-phy"; 1794 }; 1795 }; 1796 1797 tcsr_mutex: hwlock@1f40000 { 1798 compatible = "qcom,tcsr-mutex"; 1799 reg = <0x0 0x01f40000 0x0 0x20000>; 1800 #hwlock-cells = <1>; 1801 }; 1802 1803 gpucc: clock-controller@3d90000 { 1804 compatible = "qcom,sa8775p-gpucc"; 1805 reg = <0x0 0x03d90000 0x0 0xa000>; 1806 clocks = <&rpmhcc RPMH_CXO_CLK>, 1807 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1808 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1809 clock-names = "bi_tcxo", 1810 "gcc_gpu_gpll0_clk_src", 1811 "gcc_gpu_gpll0_div_clk_src"; 1812 #clock-cells = <1>; 1813 #reset-cells = <1>; 1814 #power-domain-cells = <1>; 1815 }; 1816 1817 adreno_smmu: iommu@3da0000 { 1818 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 1819 "qcom,smmu-500", "arm,mmu-500"; 1820 reg = <0x0 0x03da0000 0x0 0x20000>; 1821 #iommu-cells = <2>; 1822 #global-interrupts = <2>; 1823 dma-coherent; 1824 power-domains = <&gpucc GPU_CC_CX_GDSC>; 1825 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1826 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1827 <&gpucc GPU_CC_AHB_CLK>, 1828 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1829 <&gpucc GPU_CC_CX_GMU_CLK>, 1830 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1831 <&gpucc GPU_CC_HUB_AON_CLK>; 1832 clock-names = "gcc_gpu_memnoc_gfx_clk", 1833 "gcc_gpu_snoc_dvm_gfx_clk", 1834 "gpu_cc_ahb_clk", 1835 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1836 "gpu_cc_cx_gmu_clk", 1837 "gpu_cc_hub_cx_int_clk", 1838 "gpu_cc_hub_aon_clk"; 1839 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1851 }; 1852 1853 serdes0: phy@8901000 { 1854 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 1855 reg = <0x0 0x08901000 0x0 0xe10>; 1856 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 1857 clock-names = "sgmi_ref"; 1858 #phy-cells = <0>; 1859 status = "disabled"; 1860 }; 1861 1862 serdes1: phy@8902000 { 1863 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 1864 reg = <0x0 0x08902000 0x0 0xe10>; 1865 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 1866 clock-names = "sgmi_ref"; 1867 #phy-cells = <0>; 1868 status = "disabled"; 1869 }; 1870 1871 pdc: interrupt-controller@b220000 { 1872 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 1873 reg = <0x0 0x0b220000 0x0 0x30000>, 1874 <0x0 0x17c000f0 0x0 0x64>; 1875 qcom,pdc-ranges = <0 480 40>, 1876 <40 140 14>, 1877 <54 263 1>, 1878 <55 306 4>, 1879 <59 312 3>, 1880 <62 374 2>, 1881 <64 434 2>, 1882 <66 438 2>, 1883 <70 520 1>, 1884 <73 523 1>, 1885 <118 568 6>, 1886 <124 609 3>, 1887 <159 638 1>, 1888 <160 720 3>, 1889 <169 728 30>, 1890 <199 416 2>, 1891 <201 449 1>, 1892 <202 89 1>, 1893 <203 451 1>, 1894 <204 462 1>, 1895 <205 264 1>, 1896 <206 579 1>, 1897 <207 653 1>, 1898 <208 656 1>, 1899 <209 659 1>, 1900 <210 122 1>, 1901 <211 699 1>, 1902 <212 705 1>, 1903 <213 450 1>, 1904 <214 643 2>, 1905 <216 646 5>, 1906 <221 390 5>, 1907 <226 700 2>, 1908 <228 440 1>, 1909 <229 663 1>, 1910 <230 524 2>, 1911 <232 612 3>, 1912 <235 723 5>; 1913 #interrupt-cells = <2>; 1914 interrupt-parent = <&intc>; 1915 interrupt-controller; 1916 }; 1917 1918 tsens2: thermal-sensor@c251000 { 1919 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 1920 reg = <0x0 0x0c251000 0x0 0x1ff>, 1921 <0x0 0x0c224000 0x0 0x8>; 1922 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 1924 #qcom,sensors = <13>; 1925 interrupt-names = "uplow", "critical"; 1926 #thermal-sensor-cells = <1>; 1927 }; 1928 1929 tsens3: thermal-sensor@c252000 { 1930 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 1931 reg = <0x0 0x0c252000 0x0 0x1ff>, 1932 <0x0 0x0c225000 0x0 0x8>; 1933 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 1935 #qcom,sensors = <13>; 1936 interrupt-names = "uplow", "critical"; 1937 #thermal-sensor-cells = <1>; 1938 }; 1939 1940 tsens0: thermal-sensor@c263000 { 1941 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 1942 reg = <0x0 0x0c263000 0x0 0x1ff>, 1943 <0x0 0x0c222000 0x0 0x8>; 1944 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1946 #qcom,sensors = <12>; 1947 interrupt-names = "uplow", "critical"; 1948 #thermal-sensor-cells = <1>; 1949 }; 1950 1951 tsens1: thermal-sensor@c265000 { 1952 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 1953 reg = <0x0 0x0c265000 0x0 0x1ff>, 1954 <0x0 0x0c223000 0x0 0x8>; 1955 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1957 #qcom,sensors = <12>; 1958 interrupt-names = "uplow", "critical"; 1959 #thermal-sensor-cells = <1>; 1960 }; 1961 1962 aoss_qmp: power-management@c300000 { 1963 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 1964 reg = <0x0 0x0c300000 0x0 0x400>; 1965 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1966 IPCC_MPROC_SIGNAL_GLINK_QMP 1967 IRQ_TYPE_EDGE_RISING>; 1968 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1969 #clock-cells = <0>; 1970 }; 1971 1972 sram@c3f0000 { 1973 compatible = "qcom,rpmh-stats"; 1974 reg = <0x0 0x0c3f0000 0x0 0x400>; 1975 }; 1976 1977 spmi_bus: spmi@c440000 { 1978 compatible = "qcom,spmi-pmic-arb"; 1979 reg = <0x0 0x0c440000 0x0 0x1100>, 1980 <0x0 0x0c600000 0x0 0x2000000>, 1981 <0x0 0x0e600000 0x0 0x100000>, 1982 <0x0 0x0e700000 0x0 0xa0000>, 1983 <0x0 0x0c40a000 0x0 0x26000>; 1984 reg-names = "core", 1985 "chnls", 1986 "obsrvr", 1987 "intr", 1988 "cnfg"; 1989 qcom,channel = <0>; 1990 qcom,ee = <0>; 1991 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1992 interrupt-names = "periph_irq"; 1993 interrupt-controller; 1994 #interrupt-cells = <4>; 1995 #address-cells = <2>; 1996 #size-cells = <0>; 1997 }; 1998 1999 tlmm: pinctrl@f000000 { 2000 compatible = "qcom,sa8775p-tlmm"; 2001 reg = <0x0 0x0f000000 0x0 0x1000000>; 2002 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2003 gpio-controller; 2004 #gpio-cells = <2>; 2005 interrupt-controller; 2006 #interrupt-cells = <2>; 2007 gpio-ranges = <&tlmm 0 0 149>; 2008 wakeup-parent = <&pdc>; 2009 }; 2010 2011 apps_smmu: iommu@15000000 { 2012 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2013 reg = <0x0 0x15000000 0x0 0x100000>; 2014 #iommu-cells = <2>; 2015 #global-interrupts = <2>; 2016 2017 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2019 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 2147 }; 2148 2149 pcie_smmu: iommu@15200000 { 2150 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2151 reg = <0x0 0x15200000 0x0 0x80000>; 2152 #iommu-cells = <2>; 2153 #global-interrupts = <2>; 2154 2155 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 2195 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 2196 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 2197 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 2199 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 2200 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 2201 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2221 }; 2222 2223 intc: interrupt-controller@17a00000 { 2224 compatible = "arm,gic-v3"; 2225 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2226 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2227 interrupt-controller; 2228 #interrupt-cells = <3>; 2229 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2230 #redistributor-regions = <1>; 2231 redistributor-stride = <0x0 0x20000>; 2232 }; 2233 2234 watchdog@17c10000 { 2235 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 2236 reg = <0x0 0x17c10000 0x0 0x1000>; 2237 clocks = <&sleep_clk>; 2238 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2239 }; 2240 2241 memtimer: timer@17c20000 { 2242 compatible = "arm,armv7-timer-mem"; 2243 reg = <0x0 0x17c20000 0x0 0x1000>; 2244 ranges = <0x0 0x0 0x0 0x20000000>; 2245 #address-cells = <1>; 2246 #size-cells = <1>; 2247 2248 frame@17c21000 { 2249 reg = <0x17c21000 0x1000>, 2250 <0x17c22000 0x1000>; 2251 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2253 frame-number = <0>; 2254 }; 2255 2256 frame@17c23000 { 2257 reg = <0x17c23000 0x1000>; 2258 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2259 frame-number = <1>; 2260 status = "disabled"; 2261 }; 2262 2263 frame@17c25000 { 2264 reg = <0x17c25000 0x1000>; 2265 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2266 frame-number = <2>; 2267 status = "disabled"; 2268 }; 2269 2270 frame@17c27000 { 2271 reg = <0x17c27000 0x1000>; 2272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2273 frame-number = <3>; 2274 status = "disabled"; 2275 }; 2276 2277 frame@17c29000 { 2278 reg = <0x17c29000 0x1000>; 2279 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2280 frame-number = <4>; 2281 status = "disabled"; 2282 }; 2283 2284 frame@17c2b000 { 2285 reg = <0x17c2b000 0x1000>; 2286 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2287 frame-number = <5>; 2288 status = "disabled"; 2289 }; 2290 2291 frame@17c2d000 { 2292 reg = <0x17c2d000 0x1000>; 2293 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2294 frame-number = <6>; 2295 status = "disabled"; 2296 }; 2297 }; 2298 2299 apps_rsc: rsc@18200000 { 2300 compatible = "qcom,rpmh-rsc"; 2301 reg = <0x0 0x18200000 0x0 0x10000>, 2302 <0x0 0x18210000 0x0 0x10000>, 2303 <0x0 0x18220000 0x0 0x10000>; 2304 reg-names = "drv-0", "drv-1", "drv-2"; 2305 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2306 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2307 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2308 qcom,tcs-offset = <0xd00>; 2309 qcom,drv-id = <2>; 2310 qcom,tcs-config = <ACTIVE_TCS 2>, 2311 <SLEEP_TCS 3>, 2312 <WAKE_TCS 3>, 2313 <CONTROL_TCS 0>; 2314 label = "apps_rsc"; 2315 2316 apps_bcm_voter: bcm-voter { 2317 compatible = "qcom,bcm-voter"; 2318 }; 2319 2320 rpmhcc: clock-controller { 2321 compatible = "qcom,sa8775p-rpmh-clk"; 2322 #clock-cells = <1>; 2323 clock-names = "xo"; 2324 clocks = <&xo_board_clk>; 2325 }; 2326 2327 rpmhpd: power-controller { 2328 compatible = "qcom,sa8775p-rpmhpd"; 2329 #power-domain-cells = <1>; 2330 operating-points-v2 = <&rpmhpd_opp_table>; 2331 2332 rpmhpd_opp_table: opp-table { 2333 compatible = "operating-points-v2"; 2334 2335 rpmhpd_opp_ret: opp-0 { 2336 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2337 }; 2338 2339 rpmhpd_opp_min_svs: opp-1 { 2340 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2341 }; 2342 2343 rpmhpd_opp_low_svs: opp2 { 2344 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2345 }; 2346 2347 rpmhpd_opp_svs: opp3 { 2348 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2349 }; 2350 2351 rpmhpd_opp_svs_l1: opp-4 { 2352 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2353 }; 2354 2355 rpmhpd_opp_nom: opp-5 { 2356 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2357 }; 2358 2359 rpmhpd_opp_nom_l1: opp-6 { 2360 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2361 }; 2362 2363 rpmhpd_opp_nom_l2: opp-7 { 2364 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2365 }; 2366 2367 rpmhpd_opp_turbo: opp-8 { 2368 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2369 }; 2370 2371 rpmhpd_opp_turbo_l1: opp-9 { 2372 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2373 }; 2374 }; 2375 }; 2376 }; 2377 2378 cpufreq_hw: cpufreq@18591000 { 2379 compatible = "qcom,sa8775p-cpufreq-epss", 2380 "qcom,cpufreq-epss"; 2381 reg = <0x0 0x18591000 0x0 0x1000>, 2382 <0x0 0x18593000 0x0 0x1000>; 2383 reg-names = "freq-domain0", "freq-domain1"; 2384 2385 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2386 clock-names = "xo", "alternate"; 2387 2388 #freq-domain-cells = <1>; 2389 }; 2390 2391 ethernet1: ethernet@23000000 { 2392 compatible = "qcom,sa8775p-ethqos"; 2393 reg = <0x0 0x23000000 0x0 0x10000>, 2394 <0x0 0x23016000 0x0 0x100>; 2395 reg-names = "stmmaceth", "rgmii"; 2396 2397 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>; 2398 interrupt-names = "macirq"; 2399 2400 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 2401 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 2402 <&gcc GCC_EMAC1_PTP_CLK>, 2403 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 2404 clock-names = "stmmaceth", 2405 "pclk", 2406 "ptp_ref", 2407 "phyaux"; 2408 2409 power-domains = <&gcc EMAC1_GDSC>; 2410 2411 phys = <&serdes1>; 2412 phy-names = "serdes"; 2413 2414 iommus = <&apps_smmu 0x140 0xf>; 2415 2416 snps,tso; 2417 snps,pbl = <32>; 2418 rx-fifo-depth = <16384>; 2419 tx-fifo-depth = <16384>; 2420 2421 status = "disabled"; 2422 }; 2423 2424 ethernet0: ethernet@23040000 { 2425 compatible = "qcom,sa8775p-ethqos"; 2426 reg = <0x0 0x23040000 0x0 0x10000>, 2427 <0x0 0x23056000 0x0 0x100>; 2428 reg-names = "stmmaceth", "rgmii"; 2429 2430 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; 2431 interrupt-names = "macirq"; 2432 2433 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 2434 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 2435 <&gcc GCC_EMAC0_PTP_CLK>, 2436 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 2437 clock-names = "stmmaceth", 2438 "pclk", 2439 "ptp_ref", 2440 "phyaux"; 2441 2442 power-domains = <&gcc EMAC0_GDSC>; 2443 2444 phys = <&serdes0>; 2445 phy-names = "serdes"; 2446 2447 iommus = <&apps_smmu 0x120 0xf>; 2448 2449 snps,tso; 2450 snps,pbl = <32>; 2451 rx-fifo-depth = <16384>; 2452 tx-fifo-depth = <16384>; 2453 2454 status = "disabled"; 2455 }; 2456 }; 2457 2458 thermal-zones { 2459 aoss-0-thermal { 2460 polling-delay-passive = <0>; 2461 polling-delay = <0>; 2462 2463 thermal-sensors = <&tsens0 0>; 2464 2465 trips { 2466 trip-point0 { 2467 temperature = <105000>; 2468 hysteresis = <5000>; 2469 type = "passive"; 2470 }; 2471 2472 trip-point1 { 2473 temperature = <115000>; 2474 hysteresis = <5000>; 2475 type = "passive"; 2476 }; 2477 }; 2478 }; 2479 2480 cpu-0-0-0-thermal { 2481 polling-delay-passive = <10>; 2482 polling-delay = <0>; 2483 2484 thermal-sensors = <&tsens0 1>; 2485 2486 trips { 2487 trip-point0 { 2488 temperature = <105000>; 2489 hysteresis = <5000>; 2490 type = "passive"; 2491 }; 2492 2493 trip-point1 { 2494 temperature = <115000>; 2495 hysteresis = <5000>; 2496 type = "passive"; 2497 }; 2498 }; 2499 }; 2500 2501 cpu-0-1-0-thermal { 2502 polling-delay-passive = <10>; 2503 polling-delay = <0>; 2504 2505 thermal-sensors = <&tsens0 2>; 2506 2507 trips { 2508 trip-point0 { 2509 temperature = <105000>; 2510 hysteresis = <5000>; 2511 type = "passive"; 2512 }; 2513 2514 trip-point1 { 2515 temperature = <115000>; 2516 hysteresis = <5000>; 2517 type = "passive"; 2518 }; 2519 }; 2520 }; 2521 2522 cpu-0-2-0-thermal { 2523 polling-delay-passive = <10>; 2524 polling-delay = <0>; 2525 2526 thermal-sensors = <&tsens0 3>; 2527 2528 trips { 2529 trip-point0 { 2530 temperature = <105000>; 2531 hysteresis = <5000>; 2532 type = "passive"; 2533 }; 2534 2535 trip-point1 { 2536 temperature = <115000>; 2537 hysteresis = <5000>; 2538 type = "passive"; 2539 }; 2540 }; 2541 }; 2542 2543 cpu-0-3-0-thermal { 2544 polling-delay-passive = <10>; 2545 polling-delay = <0>; 2546 2547 thermal-sensors = <&tsens0 4>; 2548 2549 trips { 2550 trip-point0 { 2551 temperature = <105000>; 2552 hysteresis = <5000>; 2553 type = "passive"; 2554 }; 2555 2556 trip-point1 { 2557 temperature = <115000>; 2558 hysteresis = <5000>; 2559 type = "passive"; 2560 }; 2561 }; 2562 }; 2563 2564 gpuss-0-thermal { 2565 polling-delay-passive = <10>; 2566 polling-delay = <0>; 2567 2568 thermal-sensors = <&tsens0 5>; 2569 2570 trips { 2571 trip-point0 { 2572 temperature = <105000>; 2573 hysteresis = <5000>; 2574 type = "passive"; 2575 }; 2576 2577 trip-point1 { 2578 temperature = <115000>; 2579 hysteresis = <5000>; 2580 type = "passive"; 2581 }; 2582 }; 2583 }; 2584 2585 gpuss-1-thermal { 2586 polling-delay-passive = <10>; 2587 polling-delay = <0>; 2588 2589 thermal-sensors = <&tsens0 6>; 2590 2591 trips { 2592 trip-point0 { 2593 temperature = <105000>; 2594 hysteresis = <5000>; 2595 type = "passive"; 2596 }; 2597 2598 trip-point1 { 2599 temperature = <115000>; 2600 hysteresis = <5000>; 2601 type = "passive"; 2602 }; 2603 }; 2604 }; 2605 2606 gpuss-2-thermal { 2607 polling-delay-passive = <10>; 2608 polling-delay = <0>; 2609 2610 thermal-sensors = <&tsens0 7>; 2611 2612 trips { 2613 trip-point0 { 2614 temperature = <105000>; 2615 hysteresis = <5000>; 2616 type = "passive"; 2617 }; 2618 2619 trip-point1 { 2620 temperature = <115000>; 2621 hysteresis = <5000>; 2622 type = "passive"; 2623 }; 2624 }; 2625 }; 2626 2627 audio-thermal { 2628 polling-delay-passive = <0>; 2629 polling-delay = <0>; 2630 2631 thermal-sensors = <&tsens0 8>; 2632 2633 trips { 2634 trip-point0 { 2635 temperature = <105000>; 2636 hysteresis = <5000>; 2637 type = "passive"; 2638 }; 2639 2640 trip-point1 { 2641 temperature = <115000>; 2642 hysteresis = <5000>; 2643 type = "passive"; 2644 }; 2645 }; 2646 }; 2647 2648 camss-0-thermal { 2649 polling-delay-passive = <0>; 2650 polling-delay = <0>; 2651 2652 thermal-sensors = <&tsens0 9>; 2653 2654 trips { 2655 trip-point0 { 2656 temperature = <105000>; 2657 hysteresis = <5000>; 2658 type = "passive"; 2659 }; 2660 2661 trip-point1 { 2662 temperature = <115000>; 2663 hysteresis = <5000>; 2664 type = "passive"; 2665 }; 2666 }; 2667 }; 2668 2669 pcie-0-thermal { 2670 polling-delay-passive = <0>; 2671 polling-delay = <0>; 2672 2673 thermal-sensors = <&tsens0 10>; 2674 2675 trips { 2676 trip-point0 { 2677 temperature = <105000>; 2678 hysteresis = <5000>; 2679 type = "passive"; 2680 }; 2681 2682 trip-point1 { 2683 temperature = <115000>; 2684 hysteresis = <5000>; 2685 type = "passive"; 2686 }; 2687 }; 2688 }; 2689 2690 cpuss-0-0-thermal { 2691 polling-delay-passive = <0>; 2692 polling-delay = <0>; 2693 2694 thermal-sensors = <&tsens0 11>; 2695 2696 trips { 2697 trip-point0 { 2698 temperature = <105000>; 2699 hysteresis = <5000>; 2700 type = "passive"; 2701 }; 2702 2703 trip-point1 { 2704 temperature = <115000>; 2705 hysteresis = <5000>; 2706 type = "passive"; 2707 }; 2708 }; 2709 }; 2710 2711 aoss-1-thermal { 2712 polling-delay-passive = <0>; 2713 polling-delay = <0>; 2714 2715 thermal-sensors = <&tsens1 0>; 2716 2717 trips { 2718 trip-point0 { 2719 temperature = <105000>; 2720 hysteresis = <5000>; 2721 type = "passive"; 2722 }; 2723 2724 trip-point1 { 2725 temperature = <115000>; 2726 hysteresis = <5000>; 2727 type = "passive"; 2728 }; 2729 }; 2730 }; 2731 2732 cpu-0-0-1-thermal { 2733 polling-delay-passive = <10>; 2734 polling-delay = <0>; 2735 2736 thermal-sensors = <&tsens1 1>; 2737 2738 trips { 2739 trip-point0 { 2740 temperature = <105000>; 2741 hysteresis = <5000>; 2742 type = "passive"; 2743 }; 2744 2745 trip-point1 { 2746 temperature = <115000>; 2747 hysteresis = <5000>; 2748 type = "passive"; 2749 }; 2750 }; 2751 }; 2752 2753 cpu-0-1-1-thermal { 2754 polling-delay-passive = <10>; 2755 polling-delay = <0>; 2756 2757 thermal-sensors = <&tsens1 2>; 2758 2759 trips { 2760 trip-point0 { 2761 temperature = <105000>; 2762 hysteresis = <5000>; 2763 type = "passive"; 2764 }; 2765 2766 trip-point1 { 2767 temperature = <115000>; 2768 hysteresis = <5000>; 2769 type = "passive"; 2770 }; 2771 }; 2772 }; 2773 2774 cpu-0-2-1-thermal { 2775 polling-delay-passive = <10>; 2776 polling-delay = <0>; 2777 2778 thermal-sensors = <&tsens1 3>; 2779 2780 trips { 2781 trip-point0 { 2782 temperature = <105000>; 2783 hysteresis = <5000>; 2784 type = "passive"; 2785 }; 2786 2787 trip-point1 { 2788 temperature = <115000>; 2789 hysteresis = <5000>; 2790 type = "passive"; 2791 }; 2792 }; 2793 }; 2794 2795 cpu-0-3-1-thermal { 2796 polling-delay-passive = <10>; 2797 polling-delay = <0>; 2798 2799 thermal-sensors = <&tsens1 4>; 2800 2801 trips { 2802 trip-point0 { 2803 temperature = <105000>; 2804 hysteresis = <5000>; 2805 type = "passive"; 2806 }; 2807 2808 trip-point1 { 2809 temperature = <115000>; 2810 hysteresis = <5000>; 2811 type = "passive"; 2812 }; 2813 }; 2814 }; 2815 2816 gpuss-3-thermal { 2817 polling-delay-passive = <10>; 2818 polling-delay = <0>; 2819 2820 thermal-sensors = <&tsens1 5>; 2821 2822 trips { 2823 trip-point0 { 2824 temperature = <105000>; 2825 hysteresis = <5000>; 2826 type = "passive"; 2827 }; 2828 2829 trip-point1 { 2830 temperature = <115000>; 2831 hysteresis = <5000>; 2832 type = "passive"; 2833 }; 2834 }; 2835 }; 2836 2837 gpuss-4-thermal { 2838 polling-delay-passive = <10>; 2839 polling-delay = <0>; 2840 2841 thermal-sensors = <&tsens1 6>; 2842 2843 trips { 2844 trip-point0 { 2845 temperature = <105000>; 2846 hysteresis = <5000>; 2847 type = "passive"; 2848 }; 2849 2850 trip-point1 { 2851 temperature = <115000>; 2852 hysteresis = <5000>; 2853 type = "passive"; 2854 }; 2855 }; 2856 }; 2857 2858 gpuss-5-thermal { 2859 polling-delay-passive = <10>; 2860 polling-delay = <0>; 2861 2862 thermal-sensors = <&tsens1 7>; 2863 2864 trips { 2865 trip-point0 { 2866 temperature = <105000>; 2867 hysteresis = <5000>; 2868 type = "passive"; 2869 }; 2870 2871 trip-point1 { 2872 temperature = <115000>; 2873 hysteresis = <5000>; 2874 type = "passive"; 2875 }; 2876 }; 2877 }; 2878 2879 video-thermal { 2880 polling-delay-passive = <0>; 2881 polling-delay = <0>; 2882 2883 thermal-sensors = <&tsens1 8>; 2884 2885 trips { 2886 trip-point0 { 2887 temperature = <105000>; 2888 hysteresis = <5000>; 2889 type = "passive"; 2890 }; 2891 2892 trip-point1 { 2893 temperature = <115000>; 2894 hysteresis = <5000>; 2895 type = "passive"; 2896 }; 2897 }; 2898 }; 2899 2900 camss-1-thermal { 2901 polling-delay-passive = <0>; 2902 polling-delay = <0>; 2903 2904 thermal-sensors = <&tsens1 9>; 2905 2906 trips { 2907 trip-point0 { 2908 temperature = <105000>; 2909 hysteresis = <5000>; 2910 type = "passive"; 2911 }; 2912 2913 trip-point1 { 2914 temperature = <115000>; 2915 hysteresis = <5000>; 2916 type = "passive"; 2917 }; 2918 }; 2919 }; 2920 2921 pcie-1-thermal { 2922 polling-delay-passive = <0>; 2923 polling-delay = <0>; 2924 2925 thermal-sensors = <&tsens1 10>; 2926 2927 trips { 2928 trip-point0 { 2929 temperature = <105000>; 2930 hysteresis = <5000>; 2931 type = "passive"; 2932 }; 2933 2934 trip-point1 { 2935 temperature = <115000>; 2936 hysteresis = <5000>; 2937 type = "passive"; 2938 }; 2939 }; 2940 }; 2941 2942 cpuss-0-1-thermal { 2943 polling-delay-passive = <0>; 2944 polling-delay = <0>; 2945 2946 thermal-sensors = <&tsens1 11>; 2947 2948 trips { 2949 trip-point0 { 2950 temperature = <105000>; 2951 hysteresis = <5000>; 2952 type = "passive"; 2953 }; 2954 2955 trip-point1 { 2956 temperature = <115000>; 2957 hysteresis = <5000>; 2958 type = "passive"; 2959 }; 2960 }; 2961 }; 2962 2963 aoss-2-thermal { 2964 polling-delay-passive = <0>; 2965 polling-delay = <0>; 2966 2967 thermal-sensors = <&tsens2 0>; 2968 2969 trips { 2970 trip-point0 { 2971 temperature = <105000>; 2972 hysteresis = <5000>; 2973 type = "passive"; 2974 }; 2975 2976 trip-point1 { 2977 temperature = <115000>; 2978 hysteresis = <5000>; 2979 type = "passive"; 2980 }; 2981 }; 2982 }; 2983 2984 cpu-1-0-0-thermal { 2985 polling-delay-passive = <10>; 2986 polling-delay = <0>; 2987 2988 thermal-sensors = <&tsens2 1>; 2989 2990 trips { 2991 trip-point0 { 2992 temperature = <105000>; 2993 hysteresis = <5000>; 2994 type = "passive"; 2995 }; 2996 2997 trip-point1 { 2998 temperature = <115000>; 2999 hysteresis = <5000>; 3000 type = "passive"; 3001 }; 3002 }; 3003 }; 3004 3005 cpu-1-1-0-thermal { 3006 polling-delay-passive = <10>; 3007 polling-delay = <0>; 3008 3009 thermal-sensors = <&tsens2 2>; 3010 3011 trips { 3012 trip-point0 { 3013 temperature = <105000>; 3014 hysteresis = <5000>; 3015 type = "passive"; 3016 }; 3017 3018 trip-point1 { 3019 temperature = <115000>; 3020 hysteresis = <5000>; 3021 type = "passive"; 3022 }; 3023 }; 3024 }; 3025 3026 cpu-1-2-0-thermal { 3027 polling-delay-passive = <10>; 3028 polling-delay = <0>; 3029 3030 thermal-sensors = <&tsens2 3>; 3031 3032 trips { 3033 trip-point0 { 3034 temperature = <105000>; 3035 hysteresis = <5000>; 3036 type = "passive"; 3037 }; 3038 3039 trip-point1 { 3040 temperature = <115000>; 3041 hysteresis = <5000>; 3042 type = "passive"; 3043 }; 3044 }; 3045 }; 3046 3047 cpu-1-3-0-thermal { 3048 polling-delay-passive = <10>; 3049 polling-delay = <0>; 3050 3051 thermal-sensors = <&tsens2 4>; 3052 3053 trips { 3054 trip-point0 { 3055 temperature = <105000>; 3056 hysteresis = <5000>; 3057 type = "passive"; 3058 }; 3059 3060 trip-point1 { 3061 temperature = <115000>; 3062 hysteresis = <5000>; 3063 type = "passive"; 3064 }; 3065 }; 3066 }; 3067 3068 nsp-0-0-0-thermal { 3069 polling-delay-passive = <10>; 3070 polling-delay = <0>; 3071 3072 thermal-sensors = <&tsens2 5>; 3073 3074 trips { 3075 trip-point0 { 3076 temperature = <105000>; 3077 hysteresis = <5000>; 3078 type = "passive"; 3079 }; 3080 3081 trip-point1 { 3082 temperature = <115000>; 3083 hysteresis = <5000>; 3084 type = "passive"; 3085 }; 3086 }; 3087 }; 3088 3089 nsp-0-1-0-thermal { 3090 polling-delay-passive = <10>; 3091 polling-delay = <0>; 3092 3093 thermal-sensors = <&tsens2 6>; 3094 3095 trips { 3096 trip-point0 { 3097 temperature = <105000>; 3098 hysteresis = <5000>; 3099 type = "passive"; 3100 }; 3101 3102 trip-point1 { 3103 temperature = <115000>; 3104 hysteresis = <5000>; 3105 type = "passive"; 3106 }; 3107 }; 3108 }; 3109 3110 nsp-0-2-0-thermal { 3111 polling-delay-passive = <10>; 3112 polling-delay = <0>; 3113 3114 thermal-sensors = <&tsens2 7>; 3115 3116 trips { 3117 trip-point0 { 3118 temperature = <105000>; 3119 hysteresis = <5000>; 3120 type = "passive"; 3121 }; 3122 3123 trip-point1 { 3124 temperature = <115000>; 3125 hysteresis = <5000>; 3126 type = "passive"; 3127 }; 3128 }; 3129 }; 3130 3131 nsp-1-0-0-thermal { 3132 polling-delay-passive = <10>; 3133 polling-delay = <0>; 3134 3135 thermal-sensors = <&tsens2 8>; 3136 3137 trips { 3138 trip-point0 { 3139 temperature = <105000>; 3140 hysteresis = <5000>; 3141 type = "passive"; 3142 }; 3143 3144 trip-point1 { 3145 temperature = <115000>; 3146 hysteresis = <5000>; 3147 type = "passive"; 3148 }; 3149 }; 3150 }; 3151 3152 nsp-1-1-0-thermal { 3153 polling-delay-passive = <10>; 3154 polling-delay = <0>; 3155 3156 thermal-sensors = <&tsens2 9>; 3157 3158 trips { 3159 trip-point0 { 3160 temperature = <105000>; 3161 hysteresis = <5000>; 3162 type = "passive"; 3163 }; 3164 3165 trip-point1 { 3166 temperature = <115000>; 3167 hysteresis = <5000>; 3168 type = "passive"; 3169 }; 3170 }; 3171 }; 3172 3173 nsp-1-2-0-thermal { 3174 polling-delay-passive = <10>; 3175 polling-delay = <0>; 3176 3177 thermal-sensors = <&tsens2 10>; 3178 3179 trips { 3180 trip-point0 { 3181 temperature = <105000>; 3182 hysteresis = <5000>; 3183 type = "passive"; 3184 }; 3185 3186 trip-point1 { 3187 temperature = <115000>; 3188 hysteresis = <5000>; 3189 type = "passive"; 3190 }; 3191 }; 3192 }; 3193 3194 ddrss-0-thermal { 3195 polling-delay-passive = <0>; 3196 polling-delay = <0>; 3197 3198 thermal-sensors = <&tsens2 11>; 3199 3200 trips { 3201 trip-point0 { 3202 temperature = <105000>; 3203 hysteresis = <5000>; 3204 type = "passive"; 3205 }; 3206 3207 trip-point1 { 3208 temperature = <115000>; 3209 hysteresis = <5000>; 3210 type = "passive"; 3211 }; 3212 }; 3213 }; 3214 3215 cpuss-1-0-thermal { 3216 polling-delay-passive = <0>; 3217 polling-delay = <0>; 3218 3219 thermal-sensors = <&tsens2 12>; 3220 3221 trips { 3222 trip-point0 { 3223 temperature = <105000>; 3224 hysteresis = <5000>; 3225 type = "passive"; 3226 }; 3227 3228 trip-point1 { 3229 temperature = <115000>; 3230 hysteresis = <5000>; 3231 type = "passive"; 3232 }; 3233 }; 3234 }; 3235 3236 aoss-3-thermal { 3237 polling-delay-passive = <0>; 3238 polling-delay = <0>; 3239 3240 thermal-sensors = <&tsens3 0>; 3241 3242 trips { 3243 trip-point0 { 3244 temperature = <105000>; 3245 hysteresis = <5000>; 3246 type = "passive"; 3247 }; 3248 3249 trip-point1 { 3250 temperature = <115000>; 3251 hysteresis = <5000>; 3252 type = "passive"; 3253 }; 3254 }; 3255 }; 3256 3257 cpu-1-0-1-thermal { 3258 polling-delay-passive = <10>; 3259 polling-delay = <0>; 3260 3261 thermal-sensors = <&tsens3 1>; 3262 3263 trips { 3264 trip-point0 { 3265 temperature = <105000>; 3266 hysteresis = <5000>; 3267 type = "passive"; 3268 }; 3269 3270 trip-point1 { 3271 temperature = <115000>; 3272 hysteresis = <5000>; 3273 type = "passive"; 3274 }; 3275 }; 3276 }; 3277 3278 cpu-1-1-1-thermal { 3279 polling-delay-passive = <10>; 3280 polling-delay = <0>; 3281 3282 thermal-sensors = <&tsens3 2>; 3283 3284 trips { 3285 trip-point0 { 3286 temperature = <105000>; 3287 hysteresis = <5000>; 3288 type = "passive"; 3289 }; 3290 3291 trip-point1 { 3292 temperature = <115000>; 3293 hysteresis = <5000>; 3294 type = "passive"; 3295 }; 3296 }; 3297 }; 3298 3299 cpu-1-2-1-thermal { 3300 polling-delay-passive = <10>; 3301 polling-delay = <0>; 3302 3303 thermal-sensors = <&tsens3 3>; 3304 3305 trips { 3306 trip-point0 { 3307 temperature = <105000>; 3308 hysteresis = <5000>; 3309 type = "passive"; 3310 }; 3311 3312 trip-point1 { 3313 temperature = <115000>; 3314 hysteresis = <5000>; 3315 type = "passive"; 3316 }; 3317 }; 3318 }; 3319 3320 cpu-1-3-1-thermal { 3321 polling-delay-passive = <10>; 3322 polling-delay = <0>; 3323 3324 thermal-sensors = <&tsens3 4>; 3325 3326 trips { 3327 trip-point0 { 3328 temperature = <105000>; 3329 hysteresis = <5000>; 3330 type = "passive"; 3331 }; 3332 3333 trip-point1 { 3334 temperature = <115000>; 3335 hysteresis = <5000>; 3336 type = "passive"; 3337 }; 3338 }; 3339 }; 3340 3341 nsp-0-0-1-thermal { 3342 polling-delay-passive = <10>; 3343 polling-delay = <0>; 3344 3345 thermal-sensors = <&tsens3 5>; 3346 3347 trips { 3348 trip-point0 { 3349 temperature = <105000>; 3350 hysteresis = <5000>; 3351 type = "passive"; 3352 }; 3353 3354 trip-point1 { 3355 temperature = <115000>; 3356 hysteresis = <5000>; 3357 type = "passive"; 3358 }; 3359 }; 3360 }; 3361 3362 nsp-0-1-1-thermal { 3363 polling-delay-passive = <10>; 3364 polling-delay = <0>; 3365 3366 thermal-sensors = <&tsens3 6>; 3367 3368 trips { 3369 trip-point0 { 3370 temperature = <105000>; 3371 hysteresis = <5000>; 3372 type = "passive"; 3373 }; 3374 3375 trip-point1 { 3376 temperature = <115000>; 3377 hysteresis = <5000>; 3378 type = "passive"; 3379 }; 3380 }; 3381 }; 3382 3383 nsp-0-2-1-thermal { 3384 polling-delay-passive = <10>; 3385 polling-delay = <0>; 3386 3387 thermal-sensors = <&tsens3 7>; 3388 3389 trips { 3390 trip-point0 { 3391 temperature = <105000>; 3392 hysteresis = <5000>; 3393 type = "passive"; 3394 }; 3395 3396 trip-point1 { 3397 temperature = <115000>; 3398 hysteresis = <5000>; 3399 type = "passive"; 3400 }; 3401 }; 3402 }; 3403 3404 nsp-1-0-1-thermal { 3405 polling-delay-passive = <10>; 3406 polling-delay = <0>; 3407 3408 thermal-sensors = <&tsens3 8>; 3409 3410 trips { 3411 trip-point0 { 3412 temperature = <105000>; 3413 hysteresis = <5000>; 3414 type = "passive"; 3415 }; 3416 3417 trip-point1 { 3418 temperature = <115000>; 3419 hysteresis = <5000>; 3420 type = "passive"; 3421 }; 3422 }; 3423 }; 3424 3425 nsp-1-1-1-thermal { 3426 polling-delay-passive = <10>; 3427 polling-delay = <0>; 3428 3429 thermal-sensors = <&tsens3 9>; 3430 3431 trips { 3432 trip-point0 { 3433 temperature = <105000>; 3434 hysteresis = <5000>; 3435 type = "passive"; 3436 }; 3437 3438 trip-point1 { 3439 temperature = <115000>; 3440 hysteresis = <5000>; 3441 type = "passive"; 3442 }; 3443 }; 3444 }; 3445 3446 nsp-1-2-1-thermal { 3447 polling-delay-passive = <10>; 3448 polling-delay = <0>; 3449 3450 thermal-sensors = <&tsens3 10>; 3451 3452 trips { 3453 trip-point0 { 3454 temperature = <105000>; 3455 hysteresis = <5000>; 3456 type = "passive"; 3457 }; 3458 3459 trip-point1 { 3460 temperature = <115000>; 3461 hysteresis = <5000>; 3462 type = "passive"; 3463 }; 3464 }; 3465 }; 3466 3467 ddrss-1-thermal { 3468 polling-delay-passive = <0>; 3469 polling-delay = <0>; 3470 3471 thermal-sensors = <&tsens3 11>; 3472 3473 trips { 3474 trip-point0 { 3475 temperature = <105000>; 3476 hysteresis = <5000>; 3477 type = "passive"; 3478 }; 3479 3480 trip-point1 { 3481 temperature = <115000>; 3482 hysteresis = <5000>; 3483 type = "passive"; 3484 }; 3485 }; 3486 }; 3487 3488 cpuss-1-1-thermal { 3489 polling-delay-passive = <0>; 3490 polling-delay = <0>; 3491 3492 thermal-sensors = <&tsens3 12>; 3493 3494 trips { 3495 trip-point0 { 3496 temperature = <105000>; 3497 hysteresis = <5000>; 3498 type = "passive"; 3499 }; 3500 3501 trip-point1 { 3502 temperature = <115000>; 3503 hysteresis = <5000>; 3504 type = "passive"; 3505 }; 3506 }; 3507 }; 3508 }; 3509 3510 arch_timer: timer { 3511 compatible = "arm,armv8-timer"; 3512 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3513 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3514 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3515 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3516 }; 3517 3518 pcie0: pcie@1c00000 { 3519 compatible = "qcom,pcie-sa8775p"; 3520 reg = <0x0 0x01c00000 0x0 0x3000>, 3521 <0x0 0x40000000 0x0 0xf20>, 3522 <0x0 0x40000f20 0x0 0xa8>, 3523 <0x0 0x40001000 0x0 0x4000>, 3524 <0x0 0x40100000 0x0 0x100000>, 3525 <0x0 0x01c03000 0x0 0x1000>; 3526 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 3527 device_type = "pci"; 3528 3529 #address-cells = <3>; 3530 #size-cells = <2>; 3531 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 3532 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 3533 bus-range = <0x00 0xff>; 3534 3535 dma-coherent; 3536 3537 linux,pci-domain = <0>; 3538 num-lanes = <2>; 3539 3540 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 3548 interrupt-names = "msi0", "msi1", "msi2", "msi3", 3549 "msi4", "msi5", "msi6", "msi7"; 3550 #interrupt-cells = <1>; 3551 interrupt-map-mask = <0 0 0 0x7>; 3552 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 3553 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 3554 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 3555 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 3556 3557 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3558 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3559 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 3560 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 3561 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 3562 3563 clock-names = "aux", 3564 "cfg", 3565 "bus_master", 3566 "bus_slave", 3567 "slave_q2a"; 3568 3569 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 3570 assigned-clock-rates = <19200000>; 3571 3572 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 3573 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 3574 interconnect-names = "pcie-mem", "cpu-pcie"; 3575 3576 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 3577 <0x100 &pcie_smmu 0x0001 0x1>; 3578 3579 resets = <&gcc GCC_PCIE_0_BCR>; 3580 reset-names = "pci"; 3581 power-domains = <&gcc PCIE_0_GDSC>; 3582 3583 phys = <&pcie0_phy>; 3584 phy-names = "pciephy"; 3585 3586 status = "disabled"; 3587 }; 3588 3589 pcie0_phy: phy@1c04000 { 3590 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 3591 reg = <0x0 0x1c04000 0x0 0x2000>; 3592 3593 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3594 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3595 <&gcc GCC_PCIE_CLKREF_EN>, 3596 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 3597 <&gcc GCC_PCIE_0_PIPE_CLK>, 3598 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, 3599 <&gcc GCC_PCIE_0_PHY_AUX_CLK>; 3600 3601 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 3602 "pipediv2", "phy_aux"; 3603 3604 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 3605 assigned-clock-rates = <100000000>; 3606 3607 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 3608 reset-names = "phy"; 3609 3610 #clock-cells = <0>; 3611 clock-output-names = "pcie_0_pipe_clk"; 3612 3613 #phy-cells = <0>; 3614 3615 status = "disabled"; 3616 }; 3617 3618 pcie1: pcie@1c10000 { 3619 compatible = "qcom,pcie-sa8775p"; 3620 reg = <0x0 0x01c10000 0x0 0x3000>, 3621 <0x0 0x60000000 0x0 0xf20>, 3622 <0x0 0x60000f20 0x0 0xa8>, 3623 <0x0 0x60001000 0x0 0x4000>, 3624 <0x0 0x60100000 0x0 0x100000>, 3625 <0x0 0x01c13000 0x0 0x1000>; 3626 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 3627 device_type = "pci"; 3628 3629 #address-cells = <3>; 3630 #size-cells = <2>; 3631 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 3632 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 3633 bus-range = <0x00 0xff>; 3634 3635 dma-coherent; 3636 3637 linux,pci-domain = <1>; 3638 num-lanes = <4>; 3639 3640 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 3648 interrupt-names = "msi0", "msi1", "msi2", "msi3", 3649 "msi4", "msi5", "msi6", "msi7"; 3650 #interrupt-cells = <1>; 3651 interrupt-map-mask = <0 0 0 0x7>; 3652 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3653 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 3654 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 3655 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 3656 3657 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 3658 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3659 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 3660 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 3661 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 3662 3663 clock-names = "aux", 3664 "cfg", 3665 "bus_master", 3666 "bus_slave", 3667 "slave_q2a"; 3668 3669 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 3670 assigned-clock-rates = <19200000>; 3671 3672 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 3673 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 3674 interconnect-names = "pcie-mem", "cpu-pcie"; 3675 3676 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 3677 <0x100 &pcie_smmu 0x0081 0x1>; 3678 3679 resets = <&gcc GCC_PCIE_1_BCR>; 3680 reset-names = "pci"; 3681 power-domains = <&gcc PCIE_1_GDSC>; 3682 3683 phys = <&pcie1_phy>; 3684 phy-names = "pciephy"; 3685 3686 status = "disabled"; 3687 }; 3688 3689 pcie1_phy: phy@1c14000 { 3690 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 3691 reg = <0x0 0x1c14000 0x0 0x4000>; 3692 3693 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 3694 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3695 <&gcc GCC_PCIE_CLKREF_EN>, 3696 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 3697 <&gcc GCC_PCIE_1_PIPE_CLK>, 3698 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, 3699 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 3700 3701 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 3702 "pipediv2", "phy_aux"; 3703 3704 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 3705 assigned-clock-rates = <100000000>; 3706 3707 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 3708 reset-names = "phy"; 3709 3710 #clock-cells = <0>; 3711 clock-output-names = "pcie_1_pipe_clk"; 3712 3713 #phy-cells = <0>; 3714 3715 status = "disabled"; 3716 }; 3717}; 3718