1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,icc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 10#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clocks { 21 xo_board_clk: xo-board-clk { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 }; 25 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "qcom,kryo"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 qcom,freq-domain = <&cpufreq_hw 0>; 42 next-level-cache = <&L2_0>; 43 L2_0: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 next-level-cache = <&L3_0>; 48 L3_0: l3-cache { 49 compatible = "cache"; 50 cache-level = <3>; 51 cache-unified; 52 }; 53 }; 54 }; 55 56 CPU1: cpu@100 { 57 device_type = "cpu"; 58 compatible = "qcom,kryo"; 59 reg = <0x0 0x100>; 60 enable-method = "psci"; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 next-level-cache = <&L2_1>; 63 L2_1: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&L3_0>; 68 }; 69 }; 70 71 CPU2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "qcom,kryo"; 74 reg = <0x0 0x200>; 75 enable-method = "psci"; 76 qcom,freq-domain = <&cpufreq_hw 0>; 77 next-level-cache = <&L2_2>; 78 L2_2: l2-cache { 79 compatible = "cache"; 80 cache-level = <2>; 81 cache-unified; 82 next-level-cache = <&L3_0>; 83 }; 84 }; 85 86 CPU3: cpu@300 { 87 device_type = "cpu"; 88 compatible = "qcom,kryo"; 89 reg = <0x0 0x300>; 90 enable-method = "psci"; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 next-level-cache = <&L2_3>; 93 L2_3: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&L3_0>; 98 }; 99 }; 100 101 CPU4: cpu@10000 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo"; 104 reg = <0x0 0x10000>; 105 enable-method = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 1>; 107 next-level-cache = <&L2_4>; 108 L2_4: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_1>; 113 L3_1: l3-cache { 114 compatible = "cache"; 115 cache-level = <3>; 116 cache-unified; 117 }; 118 119 }; 120 }; 121 122 CPU5: cpu@10100 { 123 device_type = "cpu"; 124 compatible = "qcom,kryo"; 125 reg = <0x0 0x10100>; 126 enable-method = "psci"; 127 qcom,freq-domain = <&cpufreq_hw 1>; 128 next-level-cache = <&L2_5>; 129 L2_5: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&L3_1>; 134 }; 135 }; 136 137 CPU6: cpu@10200 { 138 device_type = "cpu"; 139 compatible = "qcom,kryo"; 140 reg = <0x0 0x10200>; 141 enable-method = "psci"; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 next-level-cache = <&L2_6>; 144 L2_6: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&L3_1>; 149 }; 150 }; 151 152 CPU7: cpu@10300 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo"; 155 reg = <0x0 0x10300>; 156 enable-method = "psci"; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 next-level-cache = <&L2_7>; 159 L2_7: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 cache-unified; 163 next-level-cache = <&L3_1>; 164 }; 165 }; 166 167 cpu-map { 168 cluster0 { 169 core0 { 170 cpu = <&CPU0>; 171 }; 172 173 core1 { 174 cpu = <&CPU1>; 175 }; 176 177 core2 { 178 cpu = <&CPU2>; 179 }; 180 181 core3 { 182 cpu = <&CPU3>; 183 }; 184 }; 185 186 cluster1 { 187 core0 { 188 cpu = <&CPU4>; 189 }; 190 191 core1 { 192 cpu = <&CPU5>; 193 }; 194 195 core2 { 196 cpu = <&CPU6>; 197 }; 198 199 core3 { 200 cpu = <&CPU7>; 201 }; 202 }; 203 }; 204 }; 205 206 firmware { 207 scm { 208 compatible = "qcom,scm-sa8775p", "qcom,scm"; 209 }; 210 }; 211 212 aggre1_noc: interconnect-aggre1-noc { 213 compatible = "qcom,sa8775p-aggre1-noc"; 214 #interconnect-cells = <2>; 215 qcom,bcm-voters = <&apps_bcm_voter>; 216 }; 217 218 aggre2_noc: interconnect-aggre2-noc { 219 compatible = "qcom,sa8775p-aggre2-noc"; 220 #interconnect-cells = <2>; 221 qcom,bcm-voters = <&apps_bcm_voter>; 222 }; 223 224 clk_virt: interconnect-clk-virt { 225 compatible = "qcom,sa8775p-clk-virt"; 226 #interconnect-cells = <2>; 227 qcom,bcm-voters = <&apps_bcm_voter>; 228 }; 229 230 config_noc: interconnect-config-noc { 231 compatible = "qcom,sa8775p-config-noc"; 232 #interconnect-cells = <2>; 233 qcom,bcm-voters = <&apps_bcm_voter>; 234 }; 235 236 dc_noc: interconnect-dc-noc { 237 compatible = "qcom,sa8775p-dc-noc"; 238 #interconnect-cells = <2>; 239 qcom,bcm-voters = <&apps_bcm_voter>; 240 }; 241 242 gem_noc: interconnect-gem-noc { 243 compatible = "qcom,sa8775p-gem-noc"; 244 #interconnect-cells = <2>; 245 qcom,bcm-voters = <&apps_bcm_voter>; 246 }; 247 248 gpdsp_anoc: interconnect-gpdsp-anoc { 249 compatible = "qcom,sa8775p-gpdsp-anoc"; 250 #interconnect-cells = <2>; 251 qcom,bcm-voters = <&apps_bcm_voter>; 252 }; 253 254 lpass_ag_noc: interconnect-lpass-ag-noc { 255 compatible = "qcom,sa8775p-lpass-ag-noc"; 256 #interconnect-cells = <2>; 257 qcom,bcm-voters = <&apps_bcm_voter>; 258 }; 259 260 mc_virt: interconnect-mc-virt { 261 compatible = "qcom,sa8775p-mc-virt"; 262 #interconnect-cells = <2>; 263 qcom,bcm-voters = <&apps_bcm_voter>; 264 }; 265 266 mmss_noc: interconnect-mmss-noc { 267 compatible = "qcom,sa8775p-mmss-noc"; 268 #interconnect-cells = <2>; 269 qcom,bcm-voters = <&apps_bcm_voter>; 270 }; 271 272 nspa_noc: interconnect-nspa-noc { 273 compatible = "qcom,sa8775p-nspa-noc"; 274 #interconnect-cells = <2>; 275 qcom,bcm-voters = <&apps_bcm_voter>; 276 }; 277 278 nspb_noc: interconnect-nspb-noc { 279 compatible = "qcom,sa8775p-nspb-noc"; 280 #interconnect-cells = <2>; 281 qcom,bcm-voters = <&apps_bcm_voter>; 282 }; 283 284 pcie_anoc: interconnect-pcie-anoc { 285 compatible = "qcom,sa8775p-pcie-anoc"; 286 #interconnect-cells = <2>; 287 qcom,bcm-voters = <&apps_bcm_voter>; 288 }; 289 290 system_noc: interconnect-system-noc { 291 compatible = "qcom,sa8775p-system-noc"; 292 #interconnect-cells = <2>; 293 qcom,bcm-voters = <&apps_bcm_voter>; 294 }; 295 296 /* Will be updated by the bootloader. */ 297 memory@80000000 { 298 device_type = "memory"; 299 reg = <0x0 0x80000000 0x0 0x0>; 300 }; 301 302 qup_opp_table_100mhz: opp-table-qup100mhz { 303 compatible = "operating-points-v2"; 304 305 opp-100000000 { 306 opp-hz = /bits/ 64 <100000000>; 307 required-opps = <&rpmhpd_opp_svs_l1>; 308 }; 309 }; 310 311 psci { 312 compatible = "arm,psci-1.0"; 313 method = "smc"; 314 }; 315 316 reserved-memory { 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 sail_ss_mem: sail-ss@80000000 { 322 reg = <0x0 0x80000000 0x0 0x10000000>; 323 no-map; 324 }; 325 326 hyp_mem: hyp@90000000 { 327 reg = <0x0 0x90000000 0x0 0x600000>; 328 no-map; 329 }; 330 331 xbl_boot_mem: xbl-boot@90600000 { 332 reg = <0x0 0x90600000 0x0 0x200000>; 333 no-map; 334 }; 335 336 aop_image_mem: aop-image@90800000 { 337 reg = <0x0 0x90800000 0x0 0x60000>; 338 no-map; 339 }; 340 341 aop_cmd_db_mem: aop-cmd-db@90860000 { 342 compatible = "qcom,cmd-db"; 343 reg = <0x0 0x90860000 0x0 0x20000>; 344 no-map; 345 }; 346 347 uefi_log: uefi-log@908b0000 { 348 reg = <0x0 0x908b0000 0x0 0x10000>; 349 no-map; 350 }; 351 352 reserved_mem: reserved@908f0000 { 353 reg = <0x0 0x908f0000 0x0 0xf000>; 354 no-map; 355 }; 356 357 secdata_apss_mem: secdata-apss@908ff000 { 358 reg = <0x0 0x908ff000 0x0 0x1000>; 359 no-map; 360 }; 361 362 smem_mem: smem@90900000 { 363 compatible = "qcom,smem"; 364 reg = <0x0 0x90900000 0x0 0x200000>; 365 no-map; 366 hwlocks = <&tcsr_mutex 3>; 367 }; 368 369 cpucp_fw_mem: cpucp-fw@90b00000 { 370 reg = <0x0 0x90b00000 0x0 0x100000>; 371 no-map; 372 }; 373 374 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 375 reg = <0x0 0x93b00000 0x0 0xf00000>; 376 no-map; 377 }; 378 379 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 380 reg = <0x0 0x94a00000 0x0 0x800000>; 381 no-map; 382 }; 383 384 pil_camera_mem: pil-camera@95200000 { 385 reg = <0x0 0x95200000 0x0 0x500000>; 386 no-map; 387 }; 388 389 pil_adsp_mem: pil-adsp@95c00000 { 390 reg = <0x0 0x95c00000 0x0 0x1e00000>; 391 no-map; 392 }; 393 394 pil_gdsp0_mem: pil-gdsp0@97b00000 { 395 reg = <0x0 0x97b00000 0x0 0x1e00000>; 396 no-map; 397 }; 398 399 pil_gdsp1_mem: pil-gdsp1@99900000 { 400 reg = <0x0 0x99900000 0x0 0x1e00000>; 401 no-map; 402 }; 403 404 pil_cdsp0_mem: pil-cdsp0@9b800000 { 405 reg = <0x0 0x9b800000 0x0 0x1e00000>; 406 no-map; 407 }; 408 409 pil_gpu_mem: pil-gpu@9d600000 { 410 reg = <0x0 0x9d600000 0x0 0x2000>; 411 no-map; 412 }; 413 414 pil_cdsp1_mem: pil-cdsp1@9d700000 { 415 reg = <0x0 0x9d700000 0x0 0x1e00000>; 416 no-map; 417 }; 418 419 pil_cvp_mem: pil-cvp@9f500000 { 420 reg = <0x0 0x9f500000 0x0 0x700000>; 421 no-map; 422 }; 423 424 pil_video_mem: pil-video@9fc00000 { 425 reg = <0x0 0x9fc00000 0x0 0x700000>; 426 no-map; 427 }; 428 429 hyptz_reserved_mem: hyptz-reserved@beb00000 { 430 reg = <0x0 0xbeb00000 0x0 0x11500000>; 431 no-map; 432 }; 433 434 tz_stat_mem: tz-stat@d0000000 { 435 reg = <0x0 0xd0000000 0x0 0x100000>; 436 no-map; 437 }; 438 439 tags_mem: tags@d0100000 { 440 reg = <0x0 0xd0100000 0x0 0x1200000>; 441 no-map; 442 }; 443 444 qtee_mem: qtee@d1300000 { 445 reg = <0x0 0xd1300000 0x0 0x500000>; 446 no-map; 447 }; 448 449 trusted_apps_mem: trusted-apps@d1800000 { 450 reg = <0x0 0xd1800000 0x0 0x3900000>; 451 no-map; 452 }; 453 }; 454 455 soc: soc@0 { 456 compatible = "simple-bus"; 457 #address-cells = <2>; 458 #size-cells = <2>; 459 ranges = <0 0 0 0 0x10 0>; 460 461 gcc: clock-controller@100000 { 462 compatible = "qcom,sa8775p-gcc"; 463 reg = <0x0 0x00100000 0x0 0xc7018>; 464 #clock-cells = <1>; 465 #reset-cells = <1>; 466 #power-domain-cells = <1>; 467 clocks = <&rpmhcc RPMH_CXO_CLK>, 468 <&sleep_clk>, 469 <0>, 470 <0>, 471 <0>, 472 <0>, 473 <0>, 474 <0>, 475 <0>, 476 <0>, 477 <0>, 478 <0>, 479 <0>, 480 <0>, 481 <0>; 482 power-domains = <&rpmhpd SA8775P_CX>; 483 }; 484 485 ipcc: mailbox@408000 { 486 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 487 reg = <0x0 0x00408000 0x0 0x1000>; 488 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-controller; 490 #interrupt-cells = <3>; 491 #mbox-cells = <2>; 492 }; 493 494 qupv3_id_2: geniqup@8c0000 { 495 compatible = "qcom,geni-se-qup"; 496 reg = <0x0 0x008c0000 0x0 0x6000>; 497 ranges; 498 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 499 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 500 clock-names = "m-ahb", "s-ahb"; 501 iommus = <&apps_smmu 0x5a3 0x0>; 502 #address-cells = <2>; 503 #size-cells = <2>; 504 status = "disabled"; 505 506 spi16: spi@888000 { 507 compatible = "qcom,geni-spi"; 508 reg = <0x0 0x00888000 0x0 0x4000>; 509 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 511 clock-names = "se"; 512 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 513 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 514 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 515 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 516 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 517 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 518 interconnect-names = "qup-core", 519 "qup-config", 520 "qup-memory"; 521 power-domains = <&rpmhpd SA8775P_CX>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 uart17: serial@88c000 { 528 compatible = "qcom,geni-uart"; 529 reg = <0x0 0x0088c000 0x0 0x4000>; 530 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 532 clock-names = "se"; 533 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 534 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 535 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 536 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 537 interconnect-names = "qup-core", "qup-config"; 538 power-domains = <&rpmhpd SA8775P_CX>; 539 status = "disabled"; 540 }; 541 542 i2c18: i2c@890000 { 543 compatible = "qcom,geni-i2c"; 544 reg = <0x0 0x00890000 0x0 0x4000>; 545 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 547 clock-names = "se"; 548 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 549 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 550 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 551 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 552 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 553 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 554 interconnect-names = "qup-core", 555 "qup-config", 556 "qup-memory"; 557 power-domains = <&rpmhpd SA8775P_CX>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 status = "disabled"; 561 }; 562 }; 563 564 qupv3_id_1: geniqup@ac0000 { 565 compatible = "qcom,geni-se-qup"; 566 reg = <0x0 0x00ac0000 0x0 0x6000>; 567 #address-cells = <2>; 568 #size-cells = <2>; 569 ranges; 570 clock-names = "m-ahb", "s-ahb"; 571 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 572 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 573 iommus = <&apps_smmu 0x443 0x0>; 574 status = "disabled"; 575 576 uart10: serial@a8c000 { 577 compatible = "qcom,geni-uart"; 578 reg = <0x0 0x00a8c000 0x0 0x4000>; 579 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 580 clock-names = "se"; 581 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 582 interconnect-names = "qup-core", "qup-config"; 583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 584 &clk_virt SLAVE_QUP_CORE_1 0>, 585 <&gem_noc MASTER_APPSS_PROC 0 586 &config_noc SLAVE_QUP_1 0>; 587 power-domains = <&rpmhpd SA8775P_CX>; 588 operating-points-v2 = <&qup_opp_table_100mhz>; 589 status = "disabled"; 590 }; 591 592 uart12: serial@a94000 { 593 compatible = "qcom,geni-uart"; 594 reg = <0x0 0x00a94000 0x0 0x4000>; 595 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 597 clock-names = "se"; 598 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 599 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 600 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 601 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 602 interconnect-names = "qup-core", "qup-config"; 603 power-domains = <&rpmhpd SA8775P_CX>; 604 status = "disabled"; 605 }; 606 }; 607 608 tcsr_mutex: hwlock@1f40000 { 609 compatible = "qcom,tcsr-mutex"; 610 reg = <0x0 0x01f40000 0x0 0x20000>; 611 #hwlock-cells = <1>; 612 }; 613 614 pdc: interrupt-controller@b220000 { 615 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 616 reg = <0x0 0x0b220000 0x0 0x30000>, 617 <0x0 0x17c000f0 0x0 0x64>; 618 qcom,pdc-ranges = <0 480 40>, 619 <40 140 14>, 620 <54 263 1>, 621 <55 306 4>, 622 <59 312 3>, 623 <62 374 2>, 624 <64 434 2>, 625 <66 438 2>, 626 <70 520 1>, 627 <73 523 1>, 628 <118 568 6>, 629 <124 609 3>, 630 <159 638 1>, 631 <160 720 3>, 632 <169 728 30>, 633 <199 416 2>, 634 <201 449 1>, 635 <202 89 1>, 636 <203 451 1>, 637 <204 462 1>, 638 <205 264 1>, 639 <206 579 1>, 640 <207 653 1>, 641 <208 656 1>, 642 <209 659 1>, 643 <210 122 1>, 644 <211 699 1>, 645 <212 705 1>, 646 <213 450 1>, 647 <214 643 2>, 648 <216 646 5>, 649 <221 390 5>, 650 <226 700 2>, 651 <228 440 1>, 652 <229 663 1>, 653 <230 524 2>, 654 <232 612 3>, 655 <235 723 5>; 656 #interrupt-cells = <2>; 657 interrupt-parent = <&intc>; 658 interrupt-controller; 659 }; 660 661 spmi_bus: spmi@c440000 { 662 compatible = "qcom,spmi-pmic-arb"; 663 reg = <0x0 0x0c440000 0x0 0x1100>, 664 <0x0 0x0c600000 0x0 0x2000000>, 665 <0x0 0x0e600000 0x0 0x100000>, 666 <0x0 0x0e700000 0x0 0xa0000>, 667 <0x0 0x0c40a000 0x0 0x26000>; 668 reg-names = "core", 669 "chnls", 670 "obsrvr", 671 "intr", 672 "cnfg"; 673 qcom,channel = <0>; 674 qcom,ee = <0>; 675 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 676 interrupt-names = "periph_irq"; 677 interrupt-controller; 678 #interrupt-cells = <4>; 679 #address-cells = <2>; 680 #size-cells = <0>; 681 }; 682 683 tlmm: pinctrl@f000000 { 684 compatible = "qcom,sa8775p-tlmm"; 685 reg = <0x0 0x0f000000 0x0 0x1000000>; 686 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 687 gpio-controller; 688 #gpio-cells = <2>; 689 interrupt-controller; 690 #interrupt-cells = <2>; 691 gpio-ranges = <&tlmm 0 0 149>; 692 }; 693 694 apps_smmu: iommu@15000000 { 695 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 696 reg = <0x0 0x15000000 0x0 0x100000>; 697 #iommu-cells = <2>; 698 #global-interrupts = <2>; 699 700 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 830 }; 831 832 intc: interrupt-controller@17a00000 { 833 compatible = "arm,gic-v3"; 834 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 835 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 836 interrupt-controller; 837 #interrupt-cells = <3>; 838 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 839 #redistributor-regions = <1>; 840 redistributor-stride = <0x0 0x20000>; 841 }; 842 843 memtimer: timer@17c20000 { 844 compatible = "arm,armv7-timer-mem"; 845 reg = <0x0 0x17c20000 0x0 0x1000>; 846 ranges = <0x0 0x0 0x0 0x20000000>; 847 #address-cells = <1>; 848 #size-cells = <1>; 849 850 frame@17c21000 { 851 reg = <0x17c21000 0x1000>, 852 <0x17c22000 0x1000>; 853 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 855 frame-number = <0>; 856 }; 857 858 frame@17c23000 { 859 reg = <0x17c23000 0x1000>; 860 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 861 frame-number = <1>; 862 status = "disabled"; 863 }; 864 865 frame@17c25000 { 866 reg = <0x17c25000 0x1000>; 867 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 868 frame-number = <2>; 869 status = "disabled"; 870 }; 871 872 frame@17c27000 { 873 reg = <0x17c27000 0x1000>; 874 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 875 frame-number = <3>; 876 status = "disabled"; 877 }; 878 879 frame@17c29000 { 880 reg = <0x17c29000 0x1000>; 881 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 882 frame-number = <4>; 883 status = "disabled"; 884 }; 885 886 frame@17c2b000 { 887 reg = <0x17c2b000 0x1000>; 888 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 889 frame-number = <5>; 890 status = "disabled"; 891 }; 892 893 frame@17c2d000 { 894 reg = <0x17c2d000 0x1000>; 895 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 896 frame-number = <6>; 897 status = "disabled"; 898 }; 899 }; 900 901 apps_rsc: rsc@18200000 { 902 compatible = "qcom,rpmh-rsc"; 903 reg = <0x0 0x18200000 0x0 0x10000>, 904 <0x0 0x18210000 0x0 0x10000>, 905 <0x0 0x18220000 0x0 0x10000>; 906 reg-names = "drv-0", "drv-1", "drv-2"; 907 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 910 qcom,tcs-offset = <0xd00>; 911 qcom,drv-id = <2>; 912 qcom,tcs-config = <ACTIVE_TCS 2>, 913 <SLEEP_TCS 3>, 914 <WAKE_TCS 3>, 915 <CONTROL_TCS 0>; 916 label = "apps_rsc"; 917 918 apps_bcm_voter: bcm-voter { 919 compatible = "qcom,bcm-voter"; 920 }; 921 922 rpmhcc: clock-controller { 923 compatible = "qcom,sa8775p-rpmh-clk"; 924 #clock-cells = <1>; 925 clock-names = "xo"; 926 clocks = <&xo_board_clk>; 927 }; 928 929 rpmhpd: power-controller { 930 compatible = "qcom,sa8775p-rpmhpd"; 931 #power-domain-cells = <1>; 932 operating-points-v2 = <&rpmhpd_opp_table>; 933 934 rpmhpd_opp_table: opp-table { 935 compatible = "operating-points-v2"; 936 937 rpmhpd_opp_ret: opp-0 { 938 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 939 }; 940 941 rpmhpd_opp_min_svs: opp-1 { 942 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 943 }; 944 945 rpmhpd_opp_low_svs: opp2 { 946 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 947 }; 948 949 rpmhpd_opp_svs: opp3 { 950 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 951 }; 952 953 rpmhpd_opp_svs_l1: opp-4 { 954 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 955 }; 956 957 rpmhpd_opp_nom: opp-5 { 958 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 959 }; 960 961 rpmhpd_opp_nom_l1: opp-6 { 962 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 963 }; 964 965 rpmhpd_opp_nom_l2: opp-7 { 966 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 967 }; 968 969 rpmhpd_opp_turbo: opp-8 { 970 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 971 }; 972 973 rpmhpd_opp_turbo_l1: opp-9 { 974 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 975 }; 976 }; 977 }; 978 }; 979 980 cpufreq_hw: cpufreq@18591000 { 981 compatible = "qcom,sa8775p-cpufreq-epss", 982 "qcom,cpufreq-epss"; 983 reg = <0x0 0x18591000 0x0 0x1000>, 984 <0x0 0x18593000 0x0 0x1000>; 985 reg-names = "freq-domain0", "freq-domain1"; 986 987 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 988 clock-names = "xo", "alternate"; 989 990 #freq-domain-cells = <1>; 991 }; 992 }; 993 994 arch_timer: timer { 995 compatible = "arm,armv8-timer"; 996 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 997 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 998 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 999 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1000 }; 1001}; 1002