1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11 12#include "sa8540p.dtsi" 13#include "sa8540p-pmics.dtsi" 14 15/ { 16 model = "Qualcomm SA8540P Ride"; 17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p"; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c12 = &i2c12; 23 i2c15 = &i2c15; 24 i2c18 = &i2c18; 25 serial0 = &uart17; 26 }; 27 28 chosen { 29 stdout-path = "serial0:115200n8"; 30 }; 31}; 32 33&apps_rsc { 34 regulators-0 { 35 compatible = "qcom,pm8150-rpmh-regulators"; 36 qcom,pmic-id = "a"; 37 38 vreg_l3a: ldo3 { 39 regulator-name = "vreg_l3a"; 40 regulator-min-microvolt = <1200000>; 41 regulator-max-microvolt = <1208000>; 42 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 43 }; 44 45 vreg_l5a: ldo5 { 46 regulator-name = "vreg_l5a"; 47 regulator-min-microvolt = <912000>; 48 regulator-max-microvolt = <912000>; 49 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 50 }; 51 52 vreg_l7a: ldo7 { 53 regulator-name = "vreg_l7a"; 54 regulator-min-microvolt = <1800000>; 55 regulator-max-microvolt = <1800000>; 56 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 57 }; 58 59 vreg_l11a: ldo11 { 60 regulator-name = "vreg_l11a"; 61 regulator-min-microvolt = <880000>; 62 regulator-max-microvolt = <880000>; 63 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 64 }; 65 66 vreg_l13a: ldo13 { 67 regulator-name = "vreg_l13a"; 68 regulator-min-microvolt = <3072000>; 69 regulator-max-microvolt = <3072000>; 70 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 71 }; 72 }; 73 74 regulators-1 { 75 compatible = "qcom,pm8150-rpmh-regulators"; 76 qcom,pmic-id = "c"; 77 78 vreg_l1c: ldo1 { 79 regulator-name = "vreg_l1c"; 80 regulator-min-microvolt = <912000>; 81 regulator-max-microvolt = <912000>; 82 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 83 }; 84 85 vreg_l2c: ldo2 { 86 regulator-name = "vreg_l2c"; 87 regulator-min-microvolt = <3072000>; 88 regulator-max-microvolt = <3072000>; 89 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 90 }; 91 92 vreg_l4c: ldo4 { 93 regulator-name = "vreg_l4c"; 94 regulator-min-microvolt = <1200000>; 95 regulator-max-microvolt = <1208000>; 96 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 97 }; 98 99 vreg_l6c: ldo6 { 100 regulator-name = "vreg_l6c"; 101 regulator-min-microvolt = <1200000>; 102 regulator-max-microvolt = <1200000>; 103 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 104 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM 105 RPMH_REGULATOR_MODE_HPM>; 106 regulator-allow-set-load; 107 }; 108 109 vreg_l7c: ldo7 { 110 regulator-name = "vreg_l7c"; 111 regulator-min-microvolt = <1800000>; 112 regulator-max-microvolt = <1800000>; 113 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 114 }; 115 116 vreg_l17c: ldo17 { 117 regulator-name = "vreg_l17c"; 118 regulator-min-microvolt = <2504000>; 119 regulator-max-microvolt = <2504000>; 120 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 121 regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM 122 RPMH_REGULATOR_MODE_HPM>; 123 regulator-allow-set-load; 124 }; 125 }; 126 127 regulators-2 { 128 compatible = "qcom,pm8150-rpmh-regulators"; 129 qcom,pmic-id = "g"; 130 131 vreg_l3g: ldo3 { 132 regulator-name = "vreg_l3g"; 133 regulator-min-microvolt = <1200000>; 134 regulator-max-microvolt = <1200000>; 135 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 136 }; 137 138 vreg_l7g: ldo7 { 139 regulator-name = "vreg_l7g"; 140 regulator-min-microvolt = <1800000>; 141 regulator-max-microvolt = <1800000>; 142 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 143 }; 144 145 vreg_l8g: ldo8 { 146 regulator-name = "vreg_l8g"; 147 regulator-min-microvolt = <880000>; 148 regulator-max-microvolt = <880000>; 149 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 150 }; 151 }; 152}; 153 154ðernet0 { 155 snps,mtl-rx-config = <ðernet0_mtl_rx_setup>; 156 snps,mtl-tx-config = <ðernet0_mtl_tx_setup>; 157 158 max-speed = <1000>; 159 phy-handle = <&rgmii_phy>; 160 phy-mode = "rgmii-txid"; 161 162 pinctrl-names = "default"; 163 pinctrl-0 = <ðernet0_default>; 164 165 status = "okay"; 166 167 mdio { 168 compatible = "snps,dwmac-mdio"; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 /* Marvell 88EA1512 */ 173 rgmii_phy: phy@8 { 174 compatible = "ethernet-phy-id0141.0dd4"; 175 reg = <0x8>; 176 177 interrupts-extended = <&tlmm 127 IRQ_TYPE_EDGE_FALLING>; 178 179 reset-gpios = <&pmm8540c_gpios 1 GPIO_ACTIVE_LOW>; 180 reset-assert-us = <11000>; 181 reset-deassert-us = <70000>; 182 183 device_type = "ethernet-phy"; 184 185 /* Set to RGMII_SGMII mode and soft reset. Turn off auto-negotiation 186 * from userspace to talk to the switch on the SGMII side of things 187 */ 188 marvell,reg-init = 189 /* Set MODE[2:0] to RGMII_SGMII */ 190 <0x12 0x14 0xfff8 0x4>, 191 /* Soft reset required after changing MODE[2:0] */ 192 <0x12 0x14 0x7fff 0x8000>; 193 }; 194 }; 195 196 ethernet0_mtl_rx_setup: rx-queues-config { 197 snps,rx-queues-to-use = <1>; 198 snps,rx-sched-sp; 199 200 queue0 { 201 snps,dcb-algorithm; 202 snps,map-to-dma-channel = <0x0>; 203 snps,route-up; 204 snps,priority = <0x1>; 205 }; 206 207 queue1 { 208 snps,dcb-algorithm; 209 snps,map-to-dma-channel = <0x1>; 210 snps,route-ptp; 211 }; 212 213 queue2 { 214 snps,avb-algorithm; 215 snps,map-to-dma-channel = <0x2>; 216 snps,route-avcp; 217 }; 218 219 queue3 { 220 snps,avb-algorithm; 221 snps,map-to-dma-channel = <0x3>; 222 snps,priority = <0xc>; 223 }; 224 }; 225 226 ethernet0_mtl_tx_setup: tx-queues-config { 227 snps,tx-queues-to-use = <1>; 228 snps,tx-sched-sp; 229 230 queue0 { 231 snps,dcb-algorithm; 232 }; 233 234 queue1 { 235 snps,dcb-algorithm; 236 }; 237 238 queue2 { 239 snps,avb-algorithm; 240 snps,send_slope = <0x1000>; 241 snps,idle_slope = <0x1000>; 242 snps,high_credit = <0x3e800>; 243 snps,low_credit = <0xffc18000>; 244 }; 245 246 queue3 { 247 snps,avb-algorithm; 248 snps,send_slope = <0x1000>; 249 snps,idle_slope = <0x1000>; 250 snps,high_credit = <0x3e800>; 251 snps,low_credit = <0xffc18000>; 252 }; 253 }; 254}; 255 256ðernet1 { 257 snps,mtl-rx-config = <ðernet1_mtl_rx_setup>; 258 snps,mtl-tx-config = <ðernet1_mtl_tx_setup>; 259 260 max-speed = <1000>; 261 phy-mode = "rgmii-txid"; 262 263 pinctrl-names = "default"; 264 pinctrl-0 = <ðernet1_default>; 265 266 status = "okay"; 267 268 fixed-link { 269 speed = <1000>; 270 full-duplex; 271 }; 272 273 ethernet1_mtl_rx_setup: rx-queues-config { 274 snps,rx-queues-to-use = <1>; 275 snps,rx-sched-sp; 276 277 queue0 { 278 snps,dcb-algorithm; 279 snps,map-to-dma-channel = <0x0>; 280 snps,route-up; 281 snps,priority = <0x1>; 282 }; 283 284 queue1 { 285 snps,dcb-algorithm; 286 snps,map-to-dma-channel = <0x1>; 287 snps,route-ptp; 288 }; 289 290 queue2 { 291 snps,avb-algorithm; 292 snps,map-to-dma-channel = <0x2>; 293 snps,route-avcp; 294 }; 295 296 queue3 { 297 snps,avb-algorithm; 298 snps,map-to-dma-channel = <0x3>; 299 snps,priority = <0xc>; 300 }; 301 }; 302 303 ethernet1_mtl_tx_setup: tx-queues-config { 304 snps,tx-queues-to-use = <1>; 305 snps,tx-sched-sp; 306 307 queue0 { 308 snps,dcb-algorithm; 309 }; 310 311 queue1 { 312 snps,dcb-algorithm; 313 }; 314 315 queue2 { 316 snps,avb-algorithm; 317 snps,send_slope = <0x1000>; 318 snps,idle_slope = <0x1000>; 319 snps,high_credit = <0x3e800>; 320 snps,low_credit = <0xffc18000>; 321 }; 322 323 queue3 { 324 snps,avb-algorithm; 325 snps,send_slope = <0x1000>; 326 snps,idle_slope = <0x1000>; 327 snps,high_credit = <0x3e800>; 328 snps,low_credit = <0xffc18000>; 329 }; 330 }; 331}; 332 333&i2c0 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&i2c0_default>; 336 337 status = "okay"; 338}; 339 340&i2c1 { 341 pinctrl-names = "default"; 342 pinctrl-0 = <&i2c1_default>; 343 344 status = "okay"; 345}; 346 347&i2c12 { 348 pinctrl-names = "default"; 349 pinctrl-0 = <&i2c12_default>; 350 351 status = "okay"; 352}; 353 354&i2c15 { 355 pinctrl-names = "default"; 356 pinctrl-0 = <&i2c15_default>; 357 358 status = "okay"; 359}; 360 361&i2c18 { 362 pinctrl-names = "default"; 363 pinctrl-0 = <&i2c18_default>; 364 365 status = "okay"; 366}; 367 368&pcie2a { 369 ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, 370 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, 371 <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; 372 373 perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; 374 wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; 375 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pcie2a_default>; 378 379 status = "okay"; 380}; 381 382&pcie2a_phy { 383 vdda-phy-supply = <&vreg_l11a>; 384 vdda-pll-supply = <&vreg_l3a>; 385 386 status = "okay"; 387}; 388 389&pcie3a { 390 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 391 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, 392 <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; 393 394 perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; 395 wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; 396 397 pinctrl-names = "default"; 398 pinctrl-0 = <&pcie3a_default>; 399 400 status = "okay"; 401}; 402 403&pcie3a_phy { 404 vdda-phy-supply = <&vreg_l11a>; 405 vdda-pll-supply = <&vreg_l3a>; 406 407 status = "okay"; 408}; 409 410&pmm8540a_rtc { 411 nvmem-cells = <&rtc_offset>; 412 nvmem-cell-names = "offset"; 413 414 status = "okay"; 415}; 416 417&pmm8540c_sdam_2 { 418 status = "okay"; 419 420 rtc_offset: rtc-offset@a0 { 421 reg = <0xa0 0x4>; 422 }; 423}; 424 425&qup0 { 426 status = "okay"; 427}; 428 429&qup1 { 430 status = "okay"; 431}; 432 433&qup2 { 434 status = "okay"; 435}; 436 437&remoteproc_nsp0 { 438 firmware-name = "qcom/sa8540p/cdsp0.mbn"; 439 status = "okay"; 440}; 441 442&remoteproc_nsp1 { 443 firmware-name = "qcom/sa8540p/cdsp1.mbn"; 444 status = "okay"; 445}; 446 447&uart17 { 448 compatible = "qcom,geni-debug-uart"; 449 status = "okay"; 450}; 451 452&ufs_mem_hc { 453 reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; 454 455 vcc-supply = <&vreg_l17c>; 456 vccq-supply = <&vreg_l6c>; 457 458 status = "okay"; 459}; 460 461&ufs_mem_phy { 462 vdda-phy-supply = <&vreg_l8g>; 463 vdda-pll-supply = <&vreg_l3g>; 464 465 status = "okay"; 466}; 467 468&usb_0 { 469 status = "okay"; 470}; 471 472&usb_0_dwc3 { 473 dr_mode = "peripheral"; 474}; 475 476&usb_0_hsphy { 477 vdda-pll-supply = <&vreg_l5a>; 478 vdda18-supply = <&vreg_l7a>; 479 vdda33-supply = <&vreg_l13a>; 480 481 status = "okay"; 482}; 483 484&usb_0_qmpphy { 485 vdda-phy-supply = <&vreg_l3a>; 486 vdda-pll-supply = <&vreg_l5a>; 487 488 status = "okay"; 489}; 490 491&usb_2_hsphy0 { 492 vdda-pll-supply = <&vreg_l5a>; 493 vdda18-supply = <&vreg_l7g>; 494 vdda33-supply = <&vreg_l13a>; 495 496 status = "okay"; 497}; 498 499&usb_2_qmpphy0 { 500 vdda-phy-supply = <&vreg_l3a>; 501 vdda-pll-supply = <&vreg_l5a>; 502 503 status = "okay"; 504}; 505 506&xo_board_clk { 507 clock-frequency = <38400000>; 508}; 509 510/* PINCTRL */ 511 512&tlmm { 513 ethernet0_default: ethernet0-default-state { 514 mdc-pins { 515 pins = "gpio175"; 516 function = "rgmii_0"; 517 drive-strength = <16>; 518 bias-pull-up; 519 }; 520 521 mdio-pins { 522 pins = "gpio176"; 523 function = "rgmii_0"; 524 drive-strength = <16>; 525 bias-pull-up; 526 }; 527 528 rgmii-tx-pins { 529 pins = "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188"; 530 function = "rgmii_0"; 531 drive-strength = <16>; 532 bias-pull-up; 533 }; 534 535 rgmii-rx-pins { 536 pins = "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182"; 537 function = "rgmii_0"; 538 drive-strength = <16>; 539 bias-disable; 540 }; 541 }; 542 543 ethernet1_default: ethernet1-default-state { 544 mdc-pins { 545 pins = "gpio97"; 546 function = "rgmii_1"; 547 drive-strength = <16>; 548 bias-pull-up; 549 }; 550 551 mdio-pins { 552 pins = "gpio98"; 553 function = "rgmii_1"; 554 drive-strength = <16>; 555 bias-pull-up; 556 }; 557 558 rgmii-tx-pins { 559 pins = "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110"; 560 function = "rgmii_1"; 561 drive-strength = <16>; 562 bias-pull-up; 563 }; 564 565 rgmii-rx-pins { 566 pins = "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104"; 567 function = "rgmii_1"; 568 drive-strength = <16>; 569 bias-disable; 570 }; 571 }; 572 573 i2c0_default: i2c0-default-state { 574 /* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */ 575 pins = "gpio135", "gpio136"; 576 function = "qup0"; 577 drive-strength = <2>; 578 bias-pull-up; 579 }; 580 581 i2c1_default: i2c1-default-state { 582 /* To PM40028B-F3EI PCIe switch */ 583 pins = "gpio158", "gpio159"; 584 function = "qup1"; 585 drive-strength = <2>; 586 bias-pull-up; 587 }; 588 589 i2c12_default: i2c12-default-state { 590 /* To Maxim max20411 */ 591 pins = "gpio0", "gpio1"; 592 function = "qup12"; 593 drive-strength = <2>; 594 bias-pull-up; 595 }; 596 597 i2c15_default: i2c15-default-state { 598 /* To display connector (SIP1 only) */ 599 pins = "gpio36", "gpio37"; 600 function = "qup15"; 601 drive-strength = <2>; 602 bias-pull-up; 603 }; 604 605 i2c18_default: i2c18-default-state { 606 /* To ASM330LHH IMU (SIP1 only) */ 607 pins = "gpio66", "gpio67"; 608 function = "qup18"; 609 drive-strength = <2>; 610 bias-pull-up; 611 }; 612 613 pcie2a_default: pcie2a-default-state { 614 perst-pins { 615 pins = "gpio143"; 616 function = "gpio"; 617 drive-strength = <2>; 618 bias-pull-down; 619 }; 620 621 clkreq-pins { 622 pins = "gpio142"; 623 function = "pcie2a_clkreq"; 624 drive-strength = <2>; 625 bias-pull-up; 626 }; 627 628 wake-pins { 629 pins = "gpio145"; 630 function = "gpio"; 631 drive-strength = <2>; 632 bias-pull-up; 633 }; 634 }; 635 636 pcie3a_default: pcie3a-default-state { 637 perst-pins { 638 pins = "gpio151"; 639 function = "gpio"; 640 drive-strength = <2>; 641 bias-pull-down; 642 }; 643 644 clkreq-pins { 645 pins = "gpio150"; 646 function = "pcie3a_clkreq"; 647 drive-strength = <2>; 648 bias-pull-up; 649 }; 650 651 wake-pins { 652 pins = "gpio56"; 653 function = "gpio"; 654 drive-strength = <2>; 655 bias-pull-up; 656 }; 657 }; 658}; 659