1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-qcs404.h> 8#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32768>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 CPU0: cpu@100 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x100>; 43 enable-method = "psci"; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 next-level-cache = <&L2_0>; 46 #cooling-cells = <2>; 47 clocks = <&apcs_glb>; 48 operating-points-v2 = <&cpu_opp_table>; 49 power-domains = <&cpr>; 50 power-domain-names = "cpr"; 51 }; 52 53 CPU1: cpu@101 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x101>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 next-level-cache = <&L2_0>; 60 #cooling-cells = <2>; 61 clocks = <&apcs_glb>; 62 operating-points-v2 = <&cpu_opp_table>; 63 power-domains = <&cpr>; 64 power-domain-names = "cpr"; 65 }; 66 67 CPU2: cpu@102 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x102>; 71 enable-method = "psci"; 72 cpu-idle-states = <&CPU_SLEEP_0>; 73 next-level-cache = <&L2_0>; 74 #cooling-cells = <2>; 75 clocks = <&apcs_glb>; 76 operating-points-v2 = <&cpu_opp_table>; 77 power-domains = <&cpr>; 78 power-domain-names = "cpr"; 79 }; 80 81 CPU3: cpu@103 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x103>; 85 enable-method = "psci"; 86 cpu-idle-states = <&CPU_SLEEP_0>; 87 next-level-cache = <&L2_0>; 88 #cooling-cells = <2>; 89 clocks = <&apcs_glb>; 90 operating-points-v2 = <&cpu_opp_table>; 91 power-domains = <&cpr>; 92 power-domain-names = "cpr"; 93 }; 94 95 L2_0: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 }; 100 101 idle-states { 102 entry-method = "psci"; 103 104 CPU_SLEEP_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 idle-state-name = "standalone-power-collapse"; 107 arm,psci-suspend-param = <0x40000003>; 108 entry-latency-us = <125>; 109 exit-latency-us = <180>; 110 min-residency-us = <595>; 111 local-timer-stop; 112 }; 113 }; 114 }; 115 116 cpu_opp_table: opp-table-cpu { 117 compatible = "operating-points-v2-kryo-cpu"; 118 opp-shared; 119 120 opp-1094400000 { 121 opp-hz = /bits/ 64 <1094400000>; 122 required-opps = <&cpr_opp1>; 123 }; 124 opp-1248000000 { 125 opp-hz = /bits/ 64 <1248000000>; 126 required-opps = <&cpr_opp2>; 127 }; 128 opp-1401600000 { 129 opp-hz = /bits/ 64 <1401600000>; 130 required-opps = <&cpr_opp3>; 131 }; 132 }; 133 134 cpr_opp_table: opp-table-cpr { 135 compatible = "operating-points-v2-qcom-level"; 136 137 cpr_opp1: opp1 { 138 opp-level = <1>; 139 qcom,opp-fuse-level = <1>; 140 }; 141 cpr_opp2: opp2 { 142 opp-level = <2>; 143 qcom,opp-fuse-level = <2>; 144 }; 145 cpr_opp3: opp3 { 146 opp-level = <3>; 147 qcom,opp-fuse-level = <3>; 148 }; 149 }; 150 151 firmware { 152 scm: scm { 153 compatible = "qcom,scm-qcs404", "qcom,scm"; 154 #reset-cells = <1>; 155 }; 156 }; 157 158 memory@80000000 { 159 device_type = "memory"; 160 /* We expect the bootloader to fill in the size */ 161 reg = <0 0x80000000 0 0>; 162 }; 163 164 psci { 165 compatible = "arm,psci-1.0"; 166 method = "smc"; 167 }; 168 169 rpm: remoteproc { 170 compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc"; 171 172 glink-edge { 173 compatible = "qcom,glink-rpm"; 174 175 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 176 qcom,rpm-msg-ram = <&rpm_msg_ram>; 177 mboxes = <&apcs_glb 0>; 178 179 rpm_requests: rpm-requests { 180 compatible = "qcom,rpm-qcs404"; 181 qcom,glink-channels = "rpm_requests"; 182 183 rpmcc: clock-controller { 184 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; 185 #clock-cells = <1>; 186 clocks = <&xo_board>; 187 clock-names = "xo"; 188 }; 189 190 rpmpd: power-controller { 191 compatible = "qcom,qcs404-rpmpd"; 192 #power-domain-cells = <1>; 193 operating-points-v2 = <&rpmpd_opp_table>; 194 195 rpmpd_opp_table: opp-table { 196 compatible = "operating-points-v2"; 197 198 rpmpd_opp_ret: opp1 { 199 opp-level = <16>; 200 }; 201 202 rpmpd_opp_ret_plus: opp2 { 203 opp-level = <32>; 204 }; 205 206 rpmpd_opp_min_svs: opp3 { 207 opp-level = <48>; 208 }; 209 210 rpmpd_opp_low_svs: opp4 { 211 opp-level = <64>; 212 }; 213 214 rpmpd_opp_svs: opp5 { 215 opp-level = <128>; 216 }; 217 218 rpmpd_opp_svs_plus: opp6 { 219 opp-level = <192>; 220 }; 221 222 rpmpd_opp_nom: opp7 { 223 opp-level = <256>; 224 }; 225 226 rpmpd_opp_nom_plus: opp8 { 227 opp-level = <320>; 228 }; 229 230 rpmpd_opp_turbo: opp9 { 231 opp-level = <384>; 232 }; 233 234 rpmpd_opp_turbo_no_cpr: opp10 { 235 opp-level = <416>; 236 }; 237 238 rpmpd_opp_turbo_plus: opp11 { 239 opp-level = <512>; 240 }; 241 }; 242 }; 243 }; 244 }; 245 }; 246 247 reserved-memory { 248 #address-cells = <2>; 249 #size-cells = <2>; 250 ranges; 251 252 tz_apps_mem: memory@85900000 { 253 reg = <0 0x85900000 0 0x500000>; 254 no-map; 255 }; 256 257 xbl_mem: memory@85e00000 { 258 reg = <0 0x85e00000 0 0x100000>; 259 no-map; 260 }; 261 262 smem_region: memory@85f00000 { 263 reg = <0 0x85f00000 0 0x200000>; 264 no-map; 265 }; 266 267 tz_mem: memory@86100000 { 268 reg = <0 0x86100000 0 0x300000>; 269 no-map; 270 }; 271 272 wlan_fw_mem: memory@86400000 { 273 reg = <0 0x86400000 0 0x1100000>; 274 no-map; 275 }; 276 277 adsp_fw_mem: memory@87500000 { 278 reg = <0 0x87500000 0 0x1a00000>; 279 no-map; 280 }; 281 282 cdsp_fw_mem: memory@88f00000 { 283 reg = <0 0x88f00000 0 0x600000>; 284 no-map; 285 }; 286 287 wlan_msa_mem: memory@89500000 { 288 reg = <0 0x89500000 0 0x100000>; 289 no-map; 290 }; 291 292 uefi_mem: memory@9f800000 { 293 reg = <0 0x9f800000 0 0x800000>; 294 no-map; 295 }; 296 }; 297 298 smem { 299 compatible = "qcom,smem"; 300 301 memory-region = <&smem_region>; 302 qcom,rpm-msg-ram = <&rpm_msg_ram>; 303 304 hwlocks = <&tcsr_mutex 3>; 305 }; 306 307 soc: soc@0 { 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges = <0 0 0 0xffffffff>; 311 compatible = "simple-bus"; 312 313 turingcc: clock-controller@800000 { 314 compatible = "qcom,qcs404-turingcc"; 315 reg = <0x00800000 0x30000>; 316 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 317 318 #clock-cells = <1>; 319 #reset-cells = <1>; 320 321 status = "disabled"; 322 }; 323 324 rpm_msg_ram: sram@60000 { 325 compatible = "qcom,rpm-msg-ram"; 326 reg = <0x00060000 0x6000>; 327 }; 328 329 usb3_phy: phy@78000 { 330 compatible = "qcom,usb-ss-28nm-phy"; 331 reg = <0x00078000 0x400>; 332 #phy-cells = <0>; 333 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 334 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 335 <&gcc GCC_USB3_PHY_PIPE_CLK>; 336 clock-names = "ref", "ahb", "pipe"; 337 resets = <&gcc GCC_USB3_PHY_BCR>, 338 <&gcc GCC_USB3PHY_PHY_BCR>; 339 reset-names = "com", "phy"; 340 status = "disabled"; 341 }; 342 343 usb2_phy_prim: phy@7a000 { 344 compatible = "qcom,usb-hs-28nm-femtophy"; 345 reg = <0x0007a000 0x200>; 346 #phy-cells = <0>; 347 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 348 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 349 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 350 clock-names = "ref", "ahb", "sleep"; 351 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, 352 <&gcc GCC_USB2A_PHY_BCR>; 353 reset-names = "phy", "por"; 354 status = "disabled"; 355 }; 356 357 usb2_phy_sec: phy@7c000 { 358 compatible = "qcom,usb-hs-28nm-femtophy"; 359 reg = <0x0007c000 0x200>; 360 #phy-cells = <0>; 361 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 362 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 363 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 364 clock-names = "ref", "ahb", "sleep"; 365 resets = <&gcc GCC_QUSB2_PHY_BCR>, 366 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 367 reset-names = "phy", "por"; 368 status = "disabled"; 369 }; 370 371 qfprom: qfprom@a4000 { 372 compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; 373 reg = <0x000a4000 0x1000>; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 cpr_efuse_speedbin: speedbin@13c { 377 reg = <0x13c 0x4>; 378 bits = <2 3>; 379 }; 380 381 tsens_s0_p1: s0-p1@1f8 { 382 reg = <0x1f8 0x1>; 383 bits = <0 6>; 384 }; 385 386 tsens_s0_p2: s0-p2@1f8 { 387 reg = <0x1f8 0x2>; 388 bits = <6 6>; 389 }; 390 391 tsens_s1_p1: s1-p1@1f9 { 392 reg = <0x1f9 0x2>; 393 bits = <4 6>; 394 }; 395 396 tsens_s1_p2: s1-p2@1fa { 397 reg = <0x1fa 0x1>; 398 bits = <2 6>; 399 }; 400 401 tsens_s2_p1: s2-p1@1fb { 402 reg = <0x1fb 0x1>; 403 bits = <0 6>; 404 }; 405 406 tsens_s2_p2: s2-p2@1fb { 407 reg = <0x1fb 0x2>; 408 bits = <6 6>; 409 }; 410 411 tsens_s3_p1: s3-p1@1fc { 412 reg = <0x1fc 0x2>; 413 bits = <4 6>; 414 }; 415 416 tsens_s3_p2: s3-p2@1fd { 417 reg = <0x1fd 0x1>; 418 bits = <2 6>; 419 }; 420 421 tsens_s4_p1: s4-p1@1fe { 422 reg = <0x1fe 0x1>; 423 bits = <0 6>; 424 }; 425 426 tsens_s4_p2: s4-p2@1fe { 427 reg = <0x1fe 0x2>; 428 bits = <6 6>; 429 }; 430 431 tsens_s5_p1: s5-p1@200 { 432 reg = <0x200 0x1>; 433 bits = <0 6>; 434 }; 435 436 tsens_s5_p2: s5-p2@200 { 437 reg = <0x200 0x2>; 438 bits = <6 6>; 439 }; 440 441 tsens_s6_p1: s6-p1@201 { 442 reg = <0x201 0x2>; 443 bits = <4 6>; 444 }; 445 446 tsens_s6_p2: s6-p2@202 { 447 reg = <0x202 0x1>; 448 bits = <2 6>; 449 }; 450 451 tsens_s7_p1: s7-p1@203 { 452 reg = <0x203 0x1>; 453 bits = <0 6>; 454 }; 455 456 tsens_s7_p2: s7-p2@203 { 457 reg = <0x203 0x2>; 458 bits = <6 6>; 459 }; 460 461 tsens_s8_p1: s8-p1@204 { 462 reg = <0x204 0x2>; 463 bits = <4 6>; 464 }; 465 466 tsens_s8_p2: s8-p2@205 { 467 reg = <0x205 0x1>; 468 bits = <2 6>; 469 }; 470 471 tsens_s9_p1: s9-p1@206 { 472 reg = <0x206 0x1>; 473 bits = <0 6>; 474 }; 475 476 tsens_s9_p2: s9-p2@206 { 477 reg = <0x206 0x2>; 478 bits = <6 6>; 479 }; 480 481 tsens_mode: mode@208 { 482 reg = <0x208 1>; 483 bits = <0 3>; 484 }; 485 486 tsens_base1: base1@208 { 487 reg = <0x208 2>; 488 bits = <3 8>; 489 }; 490 491 tsens_base2: base2@208 { 492 reg = <0x209 2>; 493 bits = <3 8>; 494 }; 495 496 cpr_efuse_quot_offset1: qoffset1@231 { 497 reg = <0x231 0x4>; 498 bits = <4 7>; 499 }; 500 cpr_efuse_quot_offset2: qoffset2@232 { 501 reg = <0x232 0x4>; 502 bits = <3 7>; 503 }; 504 cpr_efuse_quot_offset3: qoffset3@233 { 505 reg = <0x233 0x4>; 506 bits = <2 7>; 507 }; 508 cpr_efuse_init_voltage1: ivoltage1@229 { 509 reg = <0x229 0x4>; 510 bits = <4 6>; 511 }; 512 cpr_efuse_init_voltage2: ivoltage2@22a { 513 reg = <0x22a 0x4>; 514 bits = <2 6>; 515 }; 516 cpr_efuse_init_voltage3: ivoltage3@22b { 517 reg = <0x22b 0x4>; 518 bits = <0 6>; 519 }; 520 cpr_efuse_quot1: quot1@22b { 521 reg = <0x22b 0x4>; 522 bits = <6 12>; 523 }; 524 cpr_efuse_quot2: quot2@22d { 525 reg = <0x22d 0x4>; 526 bits = <2 12>; 527 }; 528 cpr_efuse_quot3: quot3@230 { 529 reg = <0x230 0x4>; 530 bits = <0 12>; 531 }; 532 cpr_efuse_ring1: ring1@228 { 533 reg = <0x228 0x4>; 534 bits = <0 3>; 535 }; 536 cpr_efuse_ring2: ring2@228 { 537 reg = <0x228 0x4>; 538 bits = <4 3>; 539 }; 540 cpr_efuse_ring3: ring3@229 { 541 reg = <0x229 0x4>; 542 bits = <0 3>; 543 }; 544 cpr_efuse_revision: revision@218 { 545 reg = <0x218 0x4>; 546 bits = <3 3>; 547 }; 548 }; 549 550 rng: rng@e3000 { 551 compatible = "qcom,prng-ee"; 552 reg = <0x000e3000 0x1000>; 553 clocks = <&gcc GCC_PRNG_AHB_CLK>; 554 clock-names = "core"; 555 }; 556 557 bimc: interconnect@400000 { 558 reg = <0x00400000 0x80000>; 559 compatible = "qcom,qcs404-bimc"; 560 #interconnect-cells = <1>; 561 }; 562 563 tsens: thermal-sensor@4a9000 { 564 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 565 reg = <0x004a9000 0x1000>, /* TM */ 566 <0x004a8000 0x1000>; /* SROT */ 567 nvmem-cells = <&tsens_mode>, 568 <&tsens_base1>, <&tsens_base2>, 569 <&tsens_s0_p1>, <&tsens_s0_p2>, 570 <&tsens_s1_p1>, <&tsens_s1_p2>, 571 <&tsens_s2_p1>, <&tsens_s2_p2>, 572 <&tsens_s3_p1>, <&tsens_s3_p2>, 573 <&tsens_s4_p1>, <&tsens_s4_p2>, 574 <&tsens_s5_p1>, <&tsens_s5_p2>, 575 <&tsens_s6_p1>, <&tsens_s6_p2>, 576 <&tsens_s7_p1>, <&tsens_s7_p2>, 577 <&tsens_s8_p1>, <&tsens_s8_p2>, 578 <&tsens_s9_p1>, <&tsens_s9_p2>; 579 nvmem-cell-names = "mode", 580 "base1", "base2", 581 "s0_p1", "s0_p2", 582 "s1_p1", "s1_p2", 583 "s2_p1", "s2_p2", 584 "s3_p1", "s3_p2", 585 "s4_p1", "s4_p2", 586 "s5_p1", "s5_p2", 587 "s6_p1", "s6_p2", 588 "s7_p1", "s7_p2", 589 "s8_p1", "s8_p2", 590 "s9_p1", "s9_p2"; 591 #qcom,sensors = <10>; 592 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 593 interrupt-names = "uplow"; 594 #thermal-sensor-cells = <1>; 595 }; 596 597 pcnoc: interconnect@500000 { 598 reg = <0x00500000 0x15080>; 599 compatible = "qcom,qcs404-pcnoc"; 600 #interconnect-cells = <1>; 601 }; 602 603 snoc: interconnect@580000 { 604 reg = <0x00580000 0x23080>; 605 compatible = "qcom,qcs404-snoc"; 606 #interconnect-cells = <1>; 607 }; 608 609 remoteproc_cdsp: remoteproc@b00000 { 610 compatible = "qcom,qcs404-cdsp-pas"; 611 reg = <0x00b00000 0x4040>; 612 613 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 614 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 615 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 616 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 617 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 618 interrupt-names = "wdog", "fatal", "ready", 619 "handover", "stop-ack"; 620 621 clocks = <&xo_board>; 622 clock-names = "xo"; 623 624 /* 625 * If the node was using the PIL binding, then include properties: 626 * clocks = <&xo_board>, 627 * <&gcc GCC_CDSP_CFG_AHB_CLK>, 628 * <&gcc GCC_CDSP_TBU_CLK>, 629 * <&gcc GCC_BIMC_CDSP_CLK>, 630 * <&turingcc TURING_WRAPPER_AON_CLK>, 631 * <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 632 * <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 633 * <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 634 * clock-names = "xo", 635 * "sway", 636 * "tbu", 637 * "bimc", 638 * "ahb_aon", 639 * "q6ss_slave", 640 * "q6ss_master", 641 * "q6_axim"; 642 * resets = <&gcc GCC_CDSP_RESTART>; 643 * reset-names = "restart"; 644 * qcom,halt-regs = <&tcsr 0x19004>; 645 */ 646 647 memory-region = <&cdsp_fw_mem>; 648 649 qcom,smem-states = <&cdsp_smp2p_out 0>; 650 qcom,smem-state-names = "stop"; 651 652 status = "disabled"; 653 654 glink-edge { 655 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 656 657 qcom,remote-pid = <5>; 658 mboxes = <&apcs_glb 12>; 659 660 label = "cdsp"; 661 }; 662 }; 663 664 usb3: usb@7678800 { 665 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 666 reg = <0x07678800 0x400>; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 ranges; 670 clocks = <&gcc GCC_USB30_MASTER_CLK>, 671 <&gcc GCC_SYS_NOC_USB3_CLK>, 672 <&gcc GCC_USB30_SLEEP_CLK>, 673 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 674 clock-names = "core", "iface", "sleep", "mock_utmi"; 675 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 676 <&gcc GCC_USB30_MASTER_CLK>; 677 assigned-clock-rates = <19200000>, <200000000>; 678 status = "disabled"; 679 680 usb3_dwc3: usb@7580000 { 681 compatible = "snps,dwc3"; 682 reg = <0x07580000 0xcd00>; 683 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 684 phys = <&usb2_phy_prim>, <&usb3_phy>; 685 phy-names = "usb2-phy", "usb3-phy"; 686 snps,has-lpm-erratum; 687 snps,hird-threshold = /bits/ 8 <0x10>; 688 snps,usb3_lpm_capable; 689 dr_mode = "otg"; 690 }; 691 }; 692 693 usb2: usb@79b8800 { 694 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 695 reg = <0x079b8800 0x400>; 696 #address-cells = <1>; 697 #size-cells = <1>; 698 ranges; 699 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, 700 <&gcc GCC_PCNOC_USB2_CLK>, 701 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, 702 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 703 clock-names = "core", "iface", "sleep", "mock_utmi"; 704 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 705 <&gcc GCC_USB_HS_SYSTEM_CLK>; 706 assigned-clock-rates = <19200000>, <133333333>; 707 status = "disabled"; 708 709 usb@78c0000 { 710 compatible = "snps,dwc3"; 711 reg = <0x078c0000 0xcc00>; 712 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 713 phys = <&usb2_phy_sec>; 714 phy-names = "usb2-phy"; 715 snps,has-lpm-erratum; 716 snps,hird-threshold = /bits/ 8 <0x10>; 717 snps,usb3_lpm_capable; 718 dr_mode = "peripheral"; 719 }; 720 }; 721 722 tlmm: pinctrl@1000000 { 723 compatible = "qcom,qcs404-pinctrl"; 724 reg = <0x01000000 0x200000>, 725 <0x01300000 0x200000>, 726 <0x07b00000 0x200000>; 727 reg-names = "south", "north", "east"; 728 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 729 gpio-ranges = <&tlmm 0 0 120>; 730 gpio-controller; 731 #gpio-cells = <2>; 732 interrupt-controller; 733 #interrupt-cells = <2>; 734 735 blsp1_i2c0_default: blsp1-i2c0-default-state { 736 pins = "gpio32", "gpio33"; 737 function = "blsp_i2c0"; 738 }; 739 740 blsp1_i2c1_default: blsp1-i2c1-default-state { 741 pins = "gpio24", "gpio25"; 742 function = "blsp_i2c1"; 743 }; 744 745 blsp1_i2c2_default: blsp1-i2c2-default-state { 746 sda-pins { 747 pins = "gpio19"; 748 function = "blsp_i2c_sda_a2"; 749 }; 750 751 scl-pins { 752 pins = "gpio20"; 753 function = "blsp_i2c_scl_a2"; 754 }; 755 }; 756 757 blsp1_i2c3_default: blsp1-i2c3-default-state { 758 pins = "gpio84", "gpio85"; 759 function = "blsp_i2c3"; 760 }; 761 762 blsp1_i2c4_default: blsp1-i2c4-default-state { 763 pins = "gpio117", "gpio118"; 764 function = "blsp_i2c4"; 765 }; 766 767 blsp1_uart0_default: blsp1-uart0-default-state { 768 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 769 function = "blsp_uart0"; 770 }; 771 772 blsp1_uart1_default: blsp1-uart1-default-state { 773 pins = "gpio22", "gpio23"; 774 function = "blsp_uart1"; 775 }; 776 777 blsp1_uart2_default: blsp1-uart2-default-state { 778 rx-pins { 779 pins = "gpio18"; 780 function = "blsp_uart_rx_a2"; 781 }; 782 783 tx-pins { 784 pins = "gpio17"; 785 function = "blsp_uart_tx_a2"; 786 }; 787 }; 788 789 blsp1_uart3_default: blsp1-uart3-default-state { 790 cts-pins { 791 pins = "gpio84"; 792 function = "blsp_uart3"; 793 }; 794 795 rts-tx-pins { 796 pins = "gpio85", "gpio82"; 797 function = "blsp_uart3"; 798 }; 799 800 rx-pins { 801 pins = "gpio83"; 802 function = "blsp_uart3"; 803 }; 804 }; 805 806 blsp2_i2c0_default: blsp2-i2c0-default-state { 807 pins = "gpio28", "gpio29"; 808 function = "blsp_i2c5"; 809 }; 810 811 blsp1_spi0_default: blsp1-spi0-default-state { 812 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 813 function = "blsp_spi0"; 814 }; 815 816 blsp1_spi1_default: blsp1-spi1-default-state { 817 mosi-pins { 818 pins = "gpio22"; 819 function = "blsp_spi_mosi_a1"; 820 }; 821 822 miso-pins { 823 pins = "gpio23"; 824 function = "blsp_spi_miso_a1"; 825 }; 826 827 cs-n-pins { 828 pins = "gpio24"; 829 function = "blsp_spi_cs_n_a1"; 830 }; 831 832 clk-pins { 833 pins = "gpio25"; 834 function = "blsp_spi_clk_a1"; 835 }; 836 }; 837 838 blsp1_spi2_default: blsp1-spi2-default-state { 839 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 840 function = "blsp_spi2"; 841 }; 842 843 blsp1_spi3_default: blsp1-spi3-default-state { 844 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 845 function = "blsp_spi3"; 846 }; 847 848 blsp1_spi4_default: blsp1-spi4-default-state { 849 pins = "gpio37", "gpio38", "gpio117", "gpio118"; 850 function = "blsp_spi4"; 851 }; 852 853 blsp2_spi0_default: blsp2-spi0-default-state { 854 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 855 function = "blsp_spi5"; 856 }; 857 858 blsp2_uart0_default: blsp2-uart0-default-state { 859 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 860 function = "blsp_uart5"; 861 }; 862 }; 863 864 gcc: clock-controller@1800000 { 865 compatible = "qcom,gcc-qcs404"; 866 reg = <0x01800000 0x80000>; 867 #clock-cells = <1>; 868 #reset-cells = <1>; 869 #power-domain-cells = <1>; 870 871 clocks = <&xo_board>, 872 <&sleep_clk>, 873 <&pcie_phy>, 874 <0>, 875 <0>, 876 <0>; 877 878 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 879 assigned-clock-rates = <19200000>; 880 }; 881 882 tcsr_mutex: hwlock@1905000 { 883 compatible = "qcom,tcsr-mutex"; 884 reg = <0x01905000 0x20000>; 885 #hwlock-cells = <1>; 886 }; 887 888 tcsr: syscon@1937000 { 889 compatible = "qcom,qcs404-tcsr", "syscon"; 890 reg = <0x01937000 0x25000>; 891 }; 892 893 sram@290000 { 894 compatible = "qcom,rpm-stats"; 895 reg = <0x00290000 0x10000>; 896 }; 897 898 spmi_bus: spmi@200f000 { 899 compatible = "qcom,spmi-pmic-arb"; 900 reg = <0x0200f000 0x001000>, 901 <0x02400000 0x800000>, 902 <0x02c00000 0x800000>, 903 <0x03800000 0x200000>, 904 <0x0200a000 0x002100>; 905 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 906 interrupt-names = "periph_irq"; 907 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 908 qcom,ee = <0>; 909 qcom,channel = <0>; 910 #address-cells = <2>; 911 #size-cells = <0>; 912 interrupt-controller; 913 #interrupt-cells = <4>; 914 }; 915 916 remoteproc_wcss: remoteproc@7400000 { 917 compatible = "qcom,qcs404-wcss-pas"; 918 reg = <0x07400000 0x4040>; 919 920 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 921 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 922 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 923 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 924 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 925 interrupt-names = "wdog", "fatal", "ready", 926 "handover", "stop-ack"; 927 928 clocks = <&xo_board>; 929 clock-names = "xo"; 930 931 memory-region = <&wlan_fw_mem>; 932 933 qcom,smem-states = <&wcss_smp2p_out 0>; 934 qcom,smem-state-names = "stop"; 935 936 status = "disabled"; 937 938 glink-edge { 939 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 940 941 qcom,remote-pid = <1>; 942 mboxes = <&apcs_glb 16>; 943 944 label = "wcss"; 945 }; 946 }; 947 948 pcie_phy: phy@7786000 { 949 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 950 reg = <0x07786000 0xb8>; 951 952 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 953 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 954 <&gcc GCC_PCIE_0_PIPE_ARES>; 955 reset-names = "phy", "pipe"; 956 957 clock-output-names = "pcie_0_pipe_clk"; 958 #clock-cells = <0>; 959 #phy-cells = <0>; 960 961 status = "disabled"; 962 }; 963 964 sdcc1: mmc@7804000 { 965 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 966 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 967 reg-names = "hc", "cqhci"; 968 969 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 971 interrupt-names = "hc_irq", "pwr_irq"; 972 973 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 974 <&gcc GCC_SDCC1_APPS_CLK>, 975 <&xo_board>; 976 clock-names = "iface", "core", "xo"; 977 978 status = "disabled"; 979 }; 980 981 blsp1_dma: dma-controller@7884000 { 982 compatible = "qcom,bam-v1.7.0"; 983 reg = <0x07884000 0x25000>; 984 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 986 clock-names = "bam_clk"; 987 #dma-cells = <1>; 988 qcom,ee = <0>; 989 status = "okay"; 990 }; 991 992 blsp1_uart0: serial@78af000 { 993 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 994 reg = <0x078af000 0x200>; 995 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 997 clock-names = "core", "iface"; 998 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 999 dma-names = "tx", "rx"; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&blsp1_uart0_default>; 1002 status = "disabled"; 1003 }; 1004 1005 blsp1_uart1: serial@78b0000 { 1006 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1007 reg = <0x078b0000 0x200>; 1008 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1010 clock-names = "core", "iface"; 1011 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1012 dma-names = "tx", "rx"; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&blsp1_uart1_default>; 1015 status = "disabled"; 1016 }; 1017 1018 blsp1_uart2: serial@78b1000 { 1019 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1020 reg = <0x078b1000 0x200>; 1021 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1023 clock-names = "core", "iface"; 1024 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1025 dma-names = "tx", "rx"; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&blsp1_uart2_default>; 1028 status = "okay"; 1029 }; 1030 1031 ethernet: ethernet@7a80000 { 1032 compatible = "qcom,qcs404-ethqos"; 1033 reg = <0x07a80000 0x10000>, 1034 <0x07a96000 0x100>; 1035 reg-names = "stmmaceth", "rgmii"; 1036 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 1037 clocks = <&gcc GCC_ETH_AXI_CLK>, 1038 <&gcc GCC_ETH_SLAVE_AHB_CLK>, 1039 <&gcc GCC_ETH_PTP_CLK>, 1040 <&gcc GCC_ETH_RGMII_CLK>; 1041 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1043 interrupt-names = "macirq", "eth_lpi"; 1044 1045 snps,tso; 1046 rx-fifo-depth = <4096>; 1047 tx-fifo-depth = <4096>; 1048 1049 status = "disabled"; 1050 }; 1051 1052 wifi: wifi@a000000 { 1053 compatible = "qcom,wcn3990-wifi"; 1054 reg = <0xa000000 0x800000>; 1055 reg-names = "membase"; 1056 memory-region = <&wlan_msa_mem>; 1057 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 1069 status = "disabled"; 1070 }; 1071 1072 blsp1_uart3: serial@78b2000 { 1073 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1074 reg = <0x078b2000 0x200>; 1075 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1077 clock-names = "core", "iface"; 1078 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1079 dma-names = "tx", "rx"; 1080 pinctrl-names = "default"; 1081 pinctrl-0 = <&blsp1_uart3_default>; 1082 status = "disabled"; 1083 }; 1084 1085 blsp1_i2c0: i2c@78b5000 { 1086 compatible = "qcom,i2c-qup-v2.2.1"; 1087 reg = <0x078b5000 0x600>; 1088 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1089 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, 1090 <&gcc GCC_BLSP1_AHB_CLK>; 1091 clock-names = "core", "iface"; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&blsp1_i2c0_default>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 blsp1_spi0: spi@78b5000 { 1100 compatible = "qcom,spi-qup-v2.2.1"; 1101 reg = <0x078b5000 0x600>; 1102 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, 1104 <&gcc GCC_BLSP1_AHB_CLK>; 1105 clock-names = "core", "iface"; 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&blsp1_spi0_default>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 blsp1_i2c1: i2c@78b6000 { 1114 compatible = "qcom,i2c-qup-v2.2.1"; 1115 reg = <0x078b6000 0x600>; 1116 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1118 <&gcc GCC_BLSP1_AHB_CLK>; 1119 clock-names = "core", "iface"; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&blsp1_i2c1_default>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 blsp1_spi1: spi@78b6000 { 1128 compatible = "qcom,spi-qup-v2.2.1"; 1129 reg = <0x078b6000 0x600>; 1130 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1132 <&gcc GCC_BLSP1_AHB_CLK>; 1133 clock-names = "core", "iface"; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&blsp1_spi1_default>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 status = "disabled"; 1139 }; 1140 1141 blsp1_i2c2: i2c@78b7000 { 1142 compatible = "qcom,i2c-qup-v2.2.1"; 1143 reg = <0x078b7000 0x600>; 1144 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1146 <&gcc GCC_BLSP1_AHB_CLK>; 1147 clock-names = "core", "iface"; 1148 pinctrl-names = "default"; 1149 pinctrl-0 = <&blsp1_i2c2_default>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 status = "disabled"; 1153 }; 1154 1155 blsp1_spi2: spi@78b7000 { 1156 compatible = "qcom,spi-qup-v2.2.1"; 1157 reg = <0x078b7000 0x600>; 1158 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1159 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1160 <&gcc GCC_BLSP1_AHB_CLK>; 1161 clock-names = "core", "iface"; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&blsp1_spi2_default>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 status = "disabled"; 1167 }; 1168 1169 blsp1_i2c3: i2c@78b8000 { 1170 compatible = "qcom,i2c-qup-v2.2.1"; 1171 reg = <0x078b8000 0x600>; 1172 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1173 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1174 <&gcc GCC_BLSP1_AHB_CLK>; 1175 clock-names = "core", "iface"; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&blsp1_i2c3_default>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 status = "disabled"; 1181 }; 1182 1183 blsp1_spi3: spi@78b8000 { 1184 compatible = "qcom,spi-qup-v2.2.1"; 1185 reg = <0x078b8000 0x600>; 1186 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1188 <&gcc GCC_BLSP1_AHB_CLK>; 1189 clock-names = "core", "iface"; 1190 pinctrl-names = "default"; 1191 pinctrl-0 = <&blsp1_spi3_default>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 blsp1_i2c4: i2c@78b9000 { 1198 compatible = "qcom,i2c-qup-v2.2.1"; 1199 reg = <0x078b9000 0x600>; 1200 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1202 <&gcc GCC_BLSP1_AHB_CLK>; 1203 clock-names = "core", "iface"; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&blsp1_i2c4_default>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 blsp1_spi4: spi@78b9000 { 1212 compatible = "qcom,spi-qup-v2.2.1"; 1213 reg = <0x078b9000 0x600>; 1214 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1216 <&gcc GCC_BLSP1_AHB_CLK>; 1217 clock-names = "core", "iface"; 1218 pinctrl-names = "default"; 1219 pinctrl-0 = <&blsp1_spi4_default>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 1225 blsp2_dma: dma-controller@7ac4000 { 1226 compatible = "qcom,bam-v1.7.0"; 1227 reg = <0x07ac4000 0x17000>; 1228 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1230 clock-names = "bam_clk"; 1231 #dma-cells = <1>; 1232 qcom,ee = <0>; 1233 status = "disabled"; 1234 }; 1235 1236 blsp2_uart0: serial@7aef000 { 1237 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1238 reg = <0x07aef000 0x200>; 1239 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1241 clock-names = "core", "iface"; 1242 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1243 dma-names = "tx", "rx"; 1244 pinctrl-names = "default"; 1245 pinctrl-0 = <&blsp2_uart0_default>; 1246 status = "disabled"; 1247 }; 1248 1249 blsp2_i2c0: i2c@7af5000 { 1250 compatible = "qcom,i2c-qup-v2.2.1"; 1251 reg = <0x07af5000 0x600>; 1252 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1253 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, 1254 <&gcc GCC_BLSP2_AHB_CLK>; 1255 clock-names = "core", "iface"; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&blsp2_i2c0_default>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 blsp2_spi0: spi@7af5000 { 1264 compatible = "qcom,spi-qup-v2.2.1"; 1265 reg = <0x07af5000 0x600>; 1266 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, 1268 <&gcc GCC_BLSP2_AHB_CLK>; 1269 clock-names = "core", "iface"; 1270 pinctrl-names = "default"; 1271 pinctrl-0 = <&blsp2_spi0_default>; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 sram@8600000 { 1278 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; 1279 reg = <0x08600000 0x1000>; 1280 1281 #address-cells = <1>; 1282 #size-cells = <1>; 1283 1284 ranges = <0 0x08600000 0x1000>; 1285 1286 pil-reloc@94c { 1287 compatible = "qcom,pil-reloc-info"; 1288 reg = <0x94c 0xc8>; 1289 }; 1290 }; 1291 1292 intc: interrupt-controller@b000000 { 1293 compatible = "qcom,msm-qgic2"; 1294 interrupt-controller; 1295 #interrupt-cells = <3>; 1296 reg = <0x0b000000 0x1000>, 1297 <0x0b002000 0x1000>; 1298 }; 1299 1300 apcs_glb: mailbox@b011000 { 1301 compatible = "qcom,qcs404-apcs-apps-global", 1302 "qcom,msm8916-apcs-kpss-global", "syscon"; 1303 reg = <0x0b011000 0x1000>; 1304 #mbox-cells = <1>; 1305 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 1306 clock-names = "pll", "aux"; 1307 #clock-cells = <0>; 1308 }; 1309 1310 apcs_hfpll: clock-controller@b016000 { 1311 compatible = "qcom,hfpll"; 1312 reg = <0x0b016000 0x30>; 1313 #clock-cells = <0>; 1314 clock-output-names = "apcs_hfpll"; 1315 clocks = <&xo_board>; 1316 clock-names = "xo"; 1317 }; 1318 1319 watchdog@b017000 { 1320 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1321 reg = <0x0b017000 0x1000>; 1322 clocks = <&sleep_clk>; 1323 }; 1324 1325 cpr: power-controller@b018000 { 1326 compatible = "qcom,qcs404-cpr", "qcom,cpr"; 1327 reg = <0x0b018000 0x1000>; 1328 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 1329 clocks = <&xo_board>; 1330 clock-names = "ref"; 1331 vdd-apc-supply = <&pms405_s3>; 1332 #power-domain-cells = <0>; 1333 operating-points-v2 = <&cpr_opp_table>; 1334 acc-syscon = <&tcsr>; 1335 1336 nvmem-cells = <&cpr_efuse_quot_offset1>, 1337 <&cpr_efuse_quot_offset2>, 1338 <&cpr_efuse_quot_offset3>, 1339 <&cpr_efuse_init_voltage1>, 1340 <&cpr_efuse_init_voltage2>, 1341 <&cpr_efuse_init_voltage3>, 1342 <&cpr_efuse_quot1>, 1343 <&cpr_efuse_quot2>, 1344 <&cpr_efuse_quot3>, 1345 <&cpr_efuse_ring1>, 1346 <&cpr_efuse_ring2>, 1347 <&cpr_efuse_ring3>, 1348 <&cpr_efuse_revision>; 1349 nvmem-cell-names = "cpr_quotient_offset1", 1350 "cpr_quotient_offset2", 1351 "cpr_quotient_offset3", 1352 "cpr_init_voltage1", 1353 "cpr_init_voltage2", 1354 "cpr_init_voltage3", 1355 "cpr_quotient1", 1356 "cpr_quotient2", 1357 "cpr_quotient3", 1358 "cpr_ring_osc1", 1359 "cpr_ring_osc2", 1360 "cpr_ring_osc3", 1361 "cpr_fuse_revision"; 1362 }; 1363 1364 timer@b120000 { 1365 #address-cells = <1>; 1366 #size-cells = <1>; 1367 ranges; 1368 compatible = "arm,armv7-timer-mem"; 1369 reg = <0x0b120000 0x1000>; 1370 clock-frequency = <19200000>; 1371 1372 frame@b121000 { 1373 frame-number = <0>; 1374 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1376 reg = <0x0b121000 0x1000>, 1377 <0x0b122000 0x1000>; 1378 }; 1379 1380 frame@b123000 { 1381 frame-number = <1>; 1382 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1383 reg = <0x0b123000 0x1000>; 1384 status = "disabled"; 1385 }; 1386 1387 frame@b124000 { 1388 frame-number = <2>; 1389 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1390 reg = <0x0b124000 0x1000>; 1391 status = "disabled"; 1392 }; 1393 1394 frame@b125000 { 1395 frame-number = <3>; 1396 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1397 reg = <0x0b125000 0x1000>; 1398 status = "disabled"; 1399 }; 1400 1401 frame@b126000 { 1402 frame-number = <4>; 1403 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1404 reg = <0x0b126000 0x1000>; 1405 status = "disabled"; 1406 }; 1407 1408 frame@b127000 { 1409 frame-number = <5>; 1410 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1411 reg = <0xb127000 0x1000>; 1412 status = "disabled"; 1413 }; 1414 1415 frame@b128000 { 1416 frame-number = <6>; 1417 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1418 reg = <0x0b128000 0x1000>; 1419 status = "disabled"; 1420 }; 1421 }; 1422 1423 remoteproc_adsp: remoteproc@c700000 { 1424 compatible = "qcom,qcs404-adsp-pas"; 1425 reg = <0x0c700000 0x4040>; 1426 1427 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 1428 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1429 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1430 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1431 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1432 interrupt-names = "wdog", "fatal", "ready", 1433 "handover", "stop-ack"; 1434 1435 clocks = <&xo_board>; 1436 clock-names = "xo"; 1437 1438 memory-region = <&adsp_fw_mem>; 1439 1440 qcom,smem-states = <&adsp_smp2p_out 0>; 1441 qcom,smem-state-names = "stop"; 1442 1443 status = "disabled"; 1444 1445 glink-edge { 1446 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1447 1448 qcom,remote-pid = <2>; 1449 mboxes = <&apcs_glb 8>; 1450 1451 label = "adsp"; 1452 }; 1453 }; 1454 1455 pcie: pcie@10000000 { 1456 compatible = "qcom,pcie-qcs404"; 1457 reg = <0x10000000 0xf1d>, 1458 <0x10000f20 0xa8>, 1459 <0x07780000 0x2000>, 1460 <0x10001000 0x2000>; 1461 reg-names = "dbi", "elbi", "parf", "config"; 1462 device_type = "pci"; 1463 linux,pci-domain = <0>; 1464 bus-range = <0x00 0xff>; 1465 num-lanes = <1>; 1466 #address-cells = <3>; 1467 #size-cells = <2>; 1468 1469 ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ 1470 <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ 1471 1472 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1473 interrupt-names = "msi"; 1474 #interrupt-cells = <1>; 1475 interrupt-map-mask = <0 0 0 0x7>; 1476 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1477 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1478 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1479 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1480 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1481 <&gcc GCC_PCIE_0_AUX_CLK>, 1482 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1483 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1484 clock-names = "iface", "aux", "master_bus", "slave_bus"; 1485 1486 resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, 1487 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, 1488 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, 1489 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, 1490 <&gcc GCC_PCIE_0_BCR>, 1491 <&gcc GCC_PCIE_0_AHB_ARES>; 1492 reset-names = "axi_m", 1493 "axi_s", 1494 "axi_m_sticky", 1495 "pipe_sticky", 1496 "pwr", 1497 "ahb"; 1498 1499 phys = <&pcie_phy>; 1500 phy-names = "pciephy"; 1501 1502 status = "disabled"; 1503 }; 1504 }; 1505 1506 timer { 1507 compatible = "arm,armv8-timer"; 1508 interrupts = <GIC_PPI 2 0xff08>, 1509 <GIC_PPI 3 0xff08>, 1510 <GIC_PPI 4 0xff08>, 1511 <GIC_PPI 1 0xff08>; 1512 }; 1513 1514 smp2p-adsp { 1515 compatible = "qcom,smp2p"; 1516 qcom,smem = <443>, <429>; 1517 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1518 mboxes = <&apcs_glb 10>; 1519 qcom,local-pid = <0>; 1520 qcom,remote-pid = <2>; 1521 1522 adsp_smp2p_out: master-kernel { 1523 qcom,entry-name = "master-kernel"; 1524 #qcom,smem-state-cells = <1>; 1525 }; 1526 1527 adsp_smp2p_in: slave-kernel { 1528 qcom,entry-name = "slave-kernel"; 1529 interrupt-controller; 1530 #interrupt-cells = <2>; 1531 }; 1532 }; 1533 1534 smp2p-cdsp { 1535 compatible = "qcom,smp2p"; 1536 qcom,smem = <94>, <432>; 1537 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1538 mboxes = <&apcs_glb 14>; 1539 qcom,local-pid = <0>; 1540 qcom,remote-pid = <5>; 1541 1542 cdsp_smp2p_out: master-kernel { 1543 qcom,entry-name = "master-kernel"; 1544 #qcom,smem-state-cells = <1>; 1545 }; 1546 1547 cdsp_smp2p_in: slave-kernel { 1548 qcom,entry-name = "slave-kernel"; 1549 interrupt-controller; 1550 #interrupt-cells = <2>; 1551 }; 1552 }; 1553 1554 smp2p-wcss { 1555 compatible = "qcom,smp2p"; 1556 qcom,smem = <435>, <428>; 1557 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1558 mboxes = <&apcs_glb 18>; 1559 qcom,local-pid = <0>; 1560 qcom,remote-pid = <1>; 1561 1562 wcss_smp2p_out: master-kernel { 1563 qcom,entry-name = "master-kernel"; 1564 #qcom,smem-state-cells = <1>; 1565 }; 1566 1567 wcss_smp2p_in: slave-kernel { 1568 qcom,entry-name = "slave-kernel"; 1569 interrupt-controller; 1570 #interrupt-cells = <2>; 1571 }; 1572 }; 1573 1574 thermal-zones { 1575 aoss-thermal { 1576 polling-delay-passive = <250>; 1577 polling-delay = <1000>; 1578 1579 thermal-sensors = <&tsens 0>; 1580 1581 trips { 1582 aoss_alert0: trip-point0 { 1583 temperature = <105000>; 1584 hysteresis = <2000>; 1585 type = "hot"; 1586 }; 1587 }; 1588 }; 1589 1590 q6-hvx-thermal { 1591 polling-delay-passive = <250>; 1592 polling-delay = <1000>; 1593 1594 thermal-sensors = <&tsens 1>; 1595 1596 trips { 1597 q6_hvx_alert0: trip-point0 { 1598 temperature = <105000>; 1599 hysteresis = <2000>; 1600 type = "hot"; 1601 }; 1602 }; 1603 }; 1604 1605 lpass-thermal { 1606 polling-delay-passive = <250>; 1607 polling-delay = <1000>; 1608 1609 thermal-sensors = <&tsens 2>; 1610 1611 trips { 1612 lpass_alert0: trip-point0 { 1613 temperature = <105000>; 1614 hysteresis = <2000>; 1615 type = "hot"; 1616 }; 1617 }; 1618 }; 1619 1620 wlan-thermal { 1621 polling-delay-passive = <250>; 1622 polling-delay = <1000>; 1623 1624 thermal-sensors = <&tsens 3>; 1625 1626 trips { 1627 wlan_alert0: trip-point0 { 1628 temperature = <105000>; 1629 hysteresis = <2000>; 1630 type = "hot"; 1631 }; 1632 }; 1633 }; 1634 1635 cluster-thermal { 1636 polling-delay-passive = <250>; 1637 polling-delay = <1000>; 1638 1639 thermal-sensors = <&tsens 4>; 1640 1641 trips { 1642 cluster_alert0: trip-point0 { 1643 temperature = <95000>; 1644 hysteresis = <2000>; 1645 type = "hot"; 1646 }; 1647 cluster_alert1: trip-point1 { 1648 temperature = <105000>; 1649 hysteresis = <2000>; 1650 type = "passive"; 1651 }; 1652 cluster_crit: cluster-crit { 1653 temperature = <120000>; 1654 hysteresis = <2000>; 1655 type = "critical"; 1656 }; 1657 }; 1658 cooling-maps { 1659 map0 { 1660 trip = <&cluster_alert1>; 1661 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1662 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1663 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1664 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1665 }; 1666 }; 1667 }; 1668 1669 cpu0-thermal { 1670 polling-delay-passive = <250>; 1671 polling-delay = <1000>; 1672 1673 thermal-sensors = <&tsens 5>; 1674 1675 trips { 1676 cpu0_alert0: trip-point0 { 1677 temperature = <95000>; 1678 hysteresis = <2000>; 1679 type = "hot"; 1680 }; 1681 cpu0_alert1: trip-point1 { 1682 temperature = <105000>; 1683 hysteresis = <2000>; 1684 type = "passive"; 1685 }; 1686 cpu0_crit: cpu-crit { 1687 temperature = <120000>; 1688 hysteresis = <2000>; 1689 type = "critical"; 1690 }; 1691 }; 1692 cooling-maps { 1693 map0 { 1694 trip = <&cpu0_alert1>; 1695 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1696 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1697 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1698 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1699 }; 1700 }; 1701 }; 1702 1703 cpu1-thermal { 1704 polling-delay-passive = <250>; 1705 polling-delay = <1000>; 1706 1707 thermal-sensors = <&tsens 6>; 1708 1709 trips { 1710 cpu1_alert0: trip-point0 { 1711 temperature = <95000>; 1712 hysteresis = <2000>; 1713 type = "hot"; 1714 }; 1715 cpu1_alert1: trip-point1 { 1716 temperature = <105000>; 1717 hysteresis = <2000>; 1718 type = "passive"; 1719 }; 1720 cpu1_crit: cpu-crit { 1721 temperature = <120000>; 1722 hysteresis = <2000>; 1723 type = "critical"; 1724 }; 1725 }; 1726 cooling-maps { 1727 map0 { 1728 trip = <&cpu1_alert1>; 1729 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1730 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1731 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1732 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1733 }; 1734 }; 1735 }; 1736 1737 cpu2-thermal { 1738 polling-delay-passive = <250>; 1739 polling-delay = <1000>; 1740 1741 thermal-sensors = <&tsens 7>; 1742 1743 trips { 1744 cpu2_alert0: trip-point0 { 1745 temperature = <95000>; 1746 hysteresis = <2000>; 1747 type = "hot"; 1748 }; 1749 cpu2_alert1: trip-point1 { 1750 temperature = <105000>; 1751 hysteresis = <2000>; 1752 type = "passive"; 1753 }; 1754 cpu2_crit: cpu-crit { 1755 temperature = <120000>; 1756 hysteresis = <2000>; 1757 type = "critical"; 1758 }; 1759 }; 1760 cooling-maps { 1761 map0 { 1762 trip = <&cpu2_alert1>; 1763 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1764 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1765 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1766 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1767 }; 1768 }; 1769 }; 1770 1771 cpu3-thermal { 1772 polling-delay-passive = <250>; 1773 polling-delay = <1000>; 1774 1775 thermal-sensors = <&tsens 8>; 1776 1777 trips { 1778 cpu3_alert0: trip-point0 { 1779 temperature = <95000>; 1780 hysteresis = <2000>; 1781 type = "hot"; 1782 }; 1783 cpu3_alert1: trip-point1 { 1784 temperature = <105000>; 1785 hysteresis = <2000>; 1786 type = "passive"; 1787 }; 1788 cpu3_crit: cpu-crit { 1789 temperature = <120000>; 1790 hysteresis = <2000>; 1791 type = "critical"; 1792 }; 1793 }; 1794 cooling-maps { 1795 map0 { 1796 trip = <&cpu3_alert1>; 1797 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1798 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1799 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1800 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1801 }; 1802 }; 1803 }; 1804 1805 gpu-thermal { 1806 polling-delay-passive = <250>; 1807 polling-delay = <1000>; 1808 1809 thermal-sensors = <&tsens 9>; 1810 1811 trips { 1812 gpu_alert0: trip-point0 { 1813 temperature = <95000>; 1814 hysteresis = <2000>; 1815 type = "hot"; 1816 }; 1817 }; 1818 }; 1819 }; 1820}; 1821