xref: /freebsd/sys/contrib/device-tree/src/arm64/qcom/msm8998.dtsi (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0) 
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8998.h>
6#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/firmware/qcom,scm.h>
10#include <dt-bindings/power/qcom-rpmpd.h>
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	qcom,msm-id = <292 0x0>;
17
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen { };
22
23	memory@80000000 {
24		device_type = "memory";
25		/* We expect the bootloader to fill in the reg */
26		reg = <0x0 0x80000000 0x0 0x0>;
27	};
28
29	reserved-memory {
30		#address-cells = <2>;
31		#size-cells = <2>;
32		ranges;
33
34		hyp_mem: memory@85800000 {
35			reg = <0x0 0x85800000 0x0 0x600000>;
36			no-map;
37		};
38
39		xbl_mem: memory@85e00000 {
40			reg = <0x0 0x85e00000 0x0 0x100000>;
41			no-map;
42		};
43
44		smem_mem: smem-mem@86000000 {
45			reg = <0x0 0x86000000 0x0 0x200000>;
46			no-map;
47		};
48
49		tz_mem: memory@86200000 {
50			reg = <0x0 0x86200000 0x0 0x2d00000>;
51			no-map;
52		};
53
54		rmtfs_mem: memory@88f00000 {
55			compatible = "qcom,rmtfs-mem";
56			reg = <0x0 0x88f00000 0x0 0x200000>;
57			no-map;
58
59			qcom,client-id = <1>;
60			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
61		};
62
63		spss_mem: memory@8ab00000 {
64			reg = <0x0 0x8ab00000 0x0 0x700000>;
65			no-map;
66		};
67
68		adsp_mem: memory@8b200000 {
69			reg = <0x0 0x8b200000 0x0 0x1a00000>;
70			no-map;
71		};
72
73		mpss_mem: memory@8cc00000 {
74			reg = <0x0 0x8cc00000 0x0 0x7000000>;
75			no-map;
76		};
77
78		venus_mem: memory@93c00000 {
79			reg = <0x0 0x93c00000 0x0 0x500000>;
80			no-map;
81		};
82
83		mba_mem: memory@94100000 {
84			reg = <0x0 0x94100000 0x0 0x200000>;
85			no-map;
86		};
87
88		slpi_mem: memory@94300000 {
89			reg = <0x0 0x94300000 0x0 0xf00000>;
90			no-map;
91		};
92
93		ipa_fw_mem: memory@95200000 {
94			reg = <0x0 0x95200000 0x0 0x10000>;
95			no-map;
96		};
97
98		ipa_gsi_mem: memory@95210000 {
99			reg = <0x0 0x95210000 0x0 0x5000>;
100			no-map;
101		};
102
103		gpu_mem: memory@95600000 {
104			reg = <0x0 0x95600000 0x0 0x100000>;
105			no-map;
106		};
107
108		wlan_msa_mem: memory@95700000 {
109			reg = <0x0 0x95700000 0x0 0x100000>;
110			no-map;
111		};
112
113		mdata_mem: mpss-metadata {
114			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115			size = <0x0 0x4000>;
116			no-map;
117		};
118	};
119
120	clocks {
121		xo: xo-board {
122			compatible = "fixed-clock";
123			#clock-cells = <0>;
124			clock-frequency = <19200000>;
125			clock-output-names = "xo_board";
126		};
127
128		sleep_clk: sleep-clk {
129			compatible = "fixed-clock";
130			#clock-cells = <0>;
131			clock-frequency = <32764>;
132		};
133	};
134
135	cpus {
136		#address-cells = <2>;
137		#size-cells = <0>;
138
139		CPU0: cpu@0 {
140			device_type = "cpu";
141			compatible = "qcom,kryo280";
142			reg = <0x0 0x0>;
143			enable-method = "psci";
144			capacity-dmips-mhz = <1024>;
145			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146			next-level-cache = <&L2_0>;
147			L2_0: l2-cache {
148				compatible = "cache";
149				cache-level = <2>;
150				cache-unified;
151			};
152		};
153
154		CPU1: cpu@1 {
155			device_type = "cpu";
156			compatible = "qcom,kryo280";
157			reg = <0x0 0x1>;
158			enable-method = "psci";
159			capacity-dmips-mhz = <1024>;
160			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161			next-level-cache = <&L2_0>;
162		};
163
164		CPU2: cpu@2 {
165			device_type = "cpu";
166			compatible = "qcom,kryo280";
167			reg = <0x0 0x2>;
168			enable-method = "psci";
169			capacity-dmips-mhz = <1024>;
170			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171			next-level-cache = <&L2_0>;
172		};
173
174		CPU3: cpu@3 {
175			device_type = "cpu";
176			compatible = "qcom,kryo280";
177			reg = <0x0 0x3>;
178			enable-method = "psci";
179			capacity-dmips-mhz = <1024>;
180			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181			next-level-cache = <&L2_0>;
182		};
183
184		CPU4: cpu@100 {
185			device_type = "cpu";
186			compatible = "qcom,kryo280";
187			reg = <0x0 0x100>;
188			enable-method = "psci";
189			capacity-dmips-mhz = <1536>;
190			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191			next-level-cache = <&L2_1>;
192			L2_1: l2-cache {
193				compatible = "cache";
194				cache-level = <2>;
195				cache-unified;
196			};
197		};
198
199		CPU5: cpu@101 {
200			device_type = "cpu";
201			compatible = "qcom,kryo280";
202			reg = <0x0 0x101>;
203			enable-method = "psci";
204			capacity-dmips-mhz = <1536>;
205			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206			next-level-cache = <&L2_1>;
207		};
208
209		CPU6: cpu@102 {
210			device_type = "cpu";
211			compatible = "qcom,kryo280";
212			reg = <0x0 0x102>;
213			enable-method = "psci";
214			capacity-dmips-mhz = <1536>;
215			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216			next-level-cache = <&L2_1>;
217		};
218
219		CPU7: cpu@103 {
220			device_type = "cpu";
221			compatible = "qcom,kryo280";
222			reg = <0x0 0x103>;
223			enable-method = "psci";
224			capacity-dmips-mhz = <1536>;
225			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226			next-level-cache = <&L2_1>;
227		};
228
229		cpu-map {
230			cluster0 {
231				core0 {
232					cpu = <&CPU0>;
233				};
234
235				core1 {
236					cpu = <&CPU1>;
237				};
238
239				core2 {
240					cpu = <&CPU2>;
241				};
242
243				core3 {
244					cpu = <&CPU3>;
245				};
246			};
247
248			cluster1 {
249				core0 {
250					cpu = <&CPU4>;
251				};
252
253				core1 {
254					cpu = <&CPU5>;
255				};
256
257				core2 {
258					cpu = <&CPU6>;
259				};
260
261				core3 {
262					cpu = <&CPU7>;
263				};
264			};
265		};
266
267		idle-states {
268			entry-method = "psci";
269
270			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271				compatible = "arm,idle-state";
272				idle-state-name = "little-retention";
273				/* CPU Retention (C2D), L2 Active */
274				arm,psci-suspend-param = <0x00000002>;
275				entry-latency-us = <81>;
276				exit-latency-us = <86>;
277				min-residency-us = <504>;
278			};
279
280			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281				compatible = "arm,idle-state";
282				idle-state-name = "little-power-collapse";
283				/* CPU + L2 Power Collapse (C3, D4) */
284				arm,psci-suspend-param = <0x40000003>;
285				entry-latency-us = <814>;
286				exit-latency-us = <4562>;
287				min-residency-us = <9183>;
288				local-timer-stop;
289			};
290
291			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292				compatible = "arm,idle-state";
293				idle-state-name = "big-retention";
294				/* CPU Retention (C2D), L2 Active */
295				arm,psci-suspend-param = <0x00000002>;
296				entry-latency-us = <79>;
297				exit-latency-us = <82>;
298				min-residency-us = <1302>;
299			};
300
301			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302				compatible = "arm,idle-state";
303				idle-state-name = "big-power-collapse";
304				/* CPU + L2 Power Collapse (C3, D4) */
305				arm,psci-suspend-param = <0x40000003>;
306				entry-latency-us = <724>;
307				exit-latency-us = <2027>;
308				min-residency-us = <9419>;
309				local-timer-stop;
310			};
311		};
312	};
313
314	firmware {
315		scm {
316			compatible = "qcom,scm-msm8998", "qcom,scm";
317		};
318	};
319
320	dsi_opp_table: opp-table-dsi {
321		compatible = "operating-points-v2";
322
323		opp-131250000 {
324			opp-hz = /bits/ 64 <131250000>;
325			required-opps = <&rpmpd_opp_low_svs>;
326		};
327
328		opp-210000000 {
329			opp-hz = /bits/ 64 <210000000>;
330			required-opps = <&rpmpd_opp_svs>;
331		};
332
333		opp-312500000 {
334			opp-hz = /bits/ 64 <312500000>;
335			required-opps = <&rpmpd_opp_nom>;
336		};
337	};
338
339	psci {
340		compatible = "arm,psci-1.0";
341		method = "smc";
342	};
343
344	rpm: remoteproc {
345		compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
346
347		glink-edge {
348			compatible = "qcom,glink-rpm";
349
350			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
351			qcom,rpm-msg-ram = <&rpm_msg_ram>;
352			mboxes = <&apcs_glb 0>;
353
354			rpm_requests: rpm-requests {
355				compatible = "qcom,rpm-msm8998";
356				qcom,glink-channels = "rpm_requests";
357
358				rpmcc: clock-controller {
359					compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
360					clocks = <&xo>;
361					clock-names = "xo";
362					#clock-cells = <1>;
363				};
364
365				rpmpd: power-controller {
366					compatible = "qcom,msm8998-rpmpd";
367					#power-domain-cells = <1>;
368					operating-points-v2 = <&rpmpd_opp_table>;
369
370					rpmpd_opp_table: opp-table {
371						compatible = "operating-points-v2";
372
373						rpmpd_opp_ret: opp1 {
374							opp-level = <RPM_SMD_LEVEL_RETENTION>;
375						};
376
377						rpmpd_opp_ret_plus: opp2 {
378							opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
379						};
380
381						rpmpd_opp_min_svs: opp3 {
382							opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
383						};
384
385						rpmpd_opp_low_svs: opp4 {
386							opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
387						};
388
389						rpmpd_opp_svs: opp5 {
390							opp-level = <RPM_SMD_LEVEL_SVS>;
391						};
392
393						rpmpd_opp_svs_plus: opp6 {
394							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
395						};
396
397						rpmpd_opp_nom: opp7 {
398							opp-level = <RPM_SMD_LEVEL_NOM>;
399						};
400
401						rpmpd_opp_nom_plus: opp8 {
402							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
403						};
404
405						rpmpd_opp_turbo: opp9 {
406							opp-level = <RPM_SMD_LEVEL_TURBO>;
407						};
408
409						rpmpd_opp_turbo_plus: opp10 {
410							opp-level = <RPM_SMD_LEVEL_BINNING>;
411						};
412					};
413				};
414			};
415		};
416	};
417
418	smem {
419		compatible = "qcom,smem";
420		memory-region = <&smem_mem>;
421		hwlocks = <&tcsr_mutex 3>;
422	};
423
424	smp2p-lpass {
425		compatible = "qcom,smp2p";
426		qcom,smem = <443>, <429>;
427
428		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429
430		mboxes = <&apcs_glb 10>;
431
432		qcom,local-pid = <0>;
433		qcom,remote-pid = <2>;
434
435		adsp_smp2p_out: master-kernel {
436			qcom,entry-name = "master-kernel";
437			#qcom,smem-state-cells = <1>;
438		};
439
440		adsp_smp2p_in: slave-kernel {
441			qcom,entry-name = "slave-kernel";
442
443			interrupt-controller;
444			#interrupt-cells = <2>;
445		};
446	};
447
448	smp2p-mpss {
449		compatible = "qcom,smp2p";
450		qcom,smem = <435>, <428>;
451		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452		mboxes = <&apcs_glb 14>;
453		qcom,local-pid = <0>;
454		qcom,remote-pid = <1>;
455
456		modem_smp2p_out: master-kernel {
457			qcom,entry-name = "master-kernel";
458			#qcom,smem-state-cells = <1>;
459		};
460
461		modem_smp2p_in: slave-kernel {
462			qcom,entry-name = "slave-kernel";
463			interrupt-controller;
464			#interrupt-cells = <2>;
465		};
466	};
467
468	smp2p-slpi {
469		compatible = "qcom,smp2p";
470		qcom,smem = <481>, <430>;
471		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472		mboxes = <&apcs_glb 26>;
473		qcom,local-pid = <0>;
474		qcom,remote-pid = <3>;
475
476		slpi_smp2p_out: master-kernel {
477			qcom,entry-name = "master-kernel";
478			#qcom,smem-state-cells = <1>;
479		};
480
481		slpi_smp2p_in: slave-kernel {
482			qcom,entry-name = "slave-kernel";
483			interrupt-controller;
484			#interrupt-cells = <2>;
485		};
486	};
487
488	thermal-zones {
489		cpu0-thermal {
490			polling-delay-passive = <250>;
491			polling-delay = <1000>;
492
493			thermal-sensors = <&tsens0 1>;
494
495			trips {
496				cpu0_alert0: trip-point0 {
497					temperature = <75000>;
498					hysteresis = <2000>;
499					type = "passive";
500				};
501
502				cpu0_crit: cpu-crit {
503					temperature = <110000>;
504					hysteresis = <2000>;
505					type = "critical";
506				};
507			};
508		};
509
510		cpu1-thermal {
511			polling-delay-passive = <250>;
512			polling-delay = <1000>;
513
514			thermal-sensors = <&tsens0 2>;
515
516			trips {
517				cpu1_alert0: trip-point0 {
518					temperature = <75000>;
519					hysteresis = <2000>;
520					type = "passive";
521				};
522
523				cpu1_crit: cpu-crit {
524					temperature = <110000>;
525					hysteresis = <2000>;
526					type = "critical";
527				};
528			};
529		};
530
531		cpu2-thermal {
532			polling-delay-passive = <250>;
533			polling-delay = <1000>;
534
535			thermal-sensors = <&tsens0 3>;
536
537			trips {
538				cpu2_alert0: trip-point0 {
539					temperature = <75000>;
540					hysteresis = <2000>;
541					type = "passive";
542				};
543
544				cpu2_crit: cpu-crit {
545					temperature = <110000>;
546					hysteresis = <2000>;
547					type = "critical";
548				};
549			};
550		};
551
552		cpu3-thermal {
553			polling-delay-passive = <250>;
554			polling-delay = <1000>;
555
556			thermal-sensors = <&tsens0 4>;
557
558			trips {
559				cpu3_alert0: trip-point0 {
560					temperature = <75000>;
561					hysteresis = <2000>;
562					type = "passive";
563				};
564
565				cpu3_crit: cpu-crit {
566					temperature = <110000>;
567					hysteresis = <2000>;
568					type = "critical";
569				};
570			};
571		};
572
573		cpu4-thermal {
574			polling-delay-passive = <250>;
575			polling-delay = <1000>;
576
577			thermal-sensors = <&tsens0 7>;
578
579			trips {
580				cpu4_alert0: trip-point0 {
581					temperature = <75000>;
582					hysteresis = <2000>;
583					type = "passive";
584				};
585
586				cpu4_crit: cpu-crit {
587					temperature = <110000>;
588					hysteresis = <2000>;
589					type = "critical";
590				};
591			};
592		};
593
594		cpu5-thermal {
595			polling-delay-passive = <250>;
596			polling-delay = <1000>;
597
598			thermal-sensors = <&tsens0 8>;
599
600			trips {
601				cpu5_alert0: trip-point0 {
602					temperature = <75000>;
603					hysteresis = <2000>;
604					type = "passive";
605				};
606
607				cpu5_crit: cpu-crit {
608					temperature = <110000>;
609					hysteresis = <2000>;
610					type = "critical";
611				};
612			};
613		};
614
615		cpu6-thermal {
616			polling-delay-passive = <250>;
617			polling-delay = <1000>;
618
619			thermal-sensors = <&tsens0 9>;
620
621			trips {
622				cpu6_alert0: trip-point0 {
623					temperature = <75000>;
624					hysteresis = <2000>;
625					type = "passive";
626				};
627
628				cpu6_crit: cpu-crit {
629					temperature = <110000>;
630					hysteresis = <2000>;
631					type = "critical";
632				};
633			};
634		};
635
636		cpu7-thermal {
637			polling-delay-passive = <250>;
638			polling-delay = <1000>;
639
640			thermal-sensors = <&tsens0 10>;
641
642			trips {
643				cpu7_alert0: trip-point0 {
644					temperature = <75000>;
645					hysteresis = <2000>;
646					type = "passive";
647				};
648
649				cpu7_crit: cpu-crit {
650					temperature = <110000>;
651					hysteresis = <2000>;
652					type = "critical";
653				};
654			};
655		};
656
657		gpu-bottom-thermal {
658			polling-delay-passive = <250>;
659			polling-delay = <1000>;
660
661			thermal-sensors = <&tsens0 12>;
662
663			trips {
664				gpu1_alert0: trip-point0 {
665					temperature = <90000>;
666					hysteresis = <2000>;
667					type = "hot";
668				};
669			};
670		};
671
672		gpu-top-thermal {
673			polling-delay-passive = <250>;
674			polling-delay = <1000>;
675
676			thermal-sensors = <&tsens0 13>;
677
678			trips {
679				gpu2_alert0: trip-point0 {
680					temperature = <90000>;
681					hysteresis = <2000>;
682					type = "hot";
683				};
684			};
685		};
686
687		clust0-mhm-thermal {
688			polling-delay-passive = <250>;
689			polling-delay = <1000>;
690
691			thermal-sensors = <&tsens0 5>;
692
693			trips {
694				cluster0_mhm_alert0: trip-point0 {
695					temperature = <90000>;
696					hysteresis = <2000>;
697					type = "hot";
698				};
699			};
700		};
701
702		clust1-mhm-thermal {
703			polling-delay-passive = <250>;
704			polling-delay = <1000>;
705
706			thermal-sensors = <&tsens0 6>;
707
708			trips {
709				cluster1_mhm_alert0: trip-point0 {
710					temperature = <90000>;
711					hysteresis = <2000>;
712					type = "hot";
713				};
714			};
715		};
716
717		cluster1-l2-thermal {
718			polling-delay-passive = <250>;
719			polling-delay = <1000>;
720
721			thermal-sensors = <&tsens0 11>;
722
723			trips {
724				cluster1_l2_alert0: trip-point0 {
725					temperature = <90000>;
726					hysteresis = <2000>;
727					type = "hot";
728				};
729			};
730		};
731
732		modem-thermal {
733			polling-delay-passive = <250>;
734			polling-delay = <1000>;
735
736			thermal-sensors = <&tsens1 1>;
737
738			trips {
739				modem_alert0: trip-point0 {
740					temperature = <90000>;
741					hysteresis = <2000>;
742					type = "hot";
743				};
744			};
745		};
746
747		mem-thermal {
748			polling-delay-passive = <250>;
749			polling-delay = <1000>;
750
751			thermal-sensors = <&tsens1 2>;
752
753			trips {
754				mem_alert0: trip-point0 {
755					temperature = <90000>;
756					hysteresis = <2000>;
757					type = "hot";
758				};
759			};
760		};
761
762		wlan-thermal {
763			polling-delay-passive = <250>;
764			polling-delay = <1000>;
765
766			thermal-sensors = <&tsens1 3>;
767
768			trips {
769				wlan_alert0: trip-point0 {
770					temperature = <90000>;
771					hysteresis = <2000>;
772					type = "hot";
773				};
774			};
775		};
776
777		q6-dsp-thermal {
778			polling-delay-passive = <250>;
779			polling-delay = <1000>;
780
781			thermal-sensors = <&tsens1 4>;
782
783			trips {
784				q6_dsp_alert0: trip-point0 {
785					temperature = <90000>;
786					hysteresis = <2000>;
787					type = "hot";
788				};
789			};
790		};
791
792		camera-thermal {
793			polling-delay-passive = <250>;
794			polling-delay = <1000>;
795
796			thermal-sensors = <&tsens1 5>;
797
798			trips {
799				camera_alert0: trip-point0 {
800					temperature = <90000>;
801					hysteresis = <2000>;
802					type = "hot";
803				};
804			};
805		};
806
807		multimedia-thermal {
808			polling-delay-passive = <250>;
809			polling-delay = <1000>;
810
811			thermal-sensors = <&tsens1 6>;
812
813			trips {
814				multimedia_alert0: trip-point0 {
815					temperature = <90000>;
816					hysteresis = <2000>;
817					type = "hot";
818				};
819			};
820		};
821	};
822
823	timer {
824		compatible = "arm,armv8-timer";
825		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
826			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
827			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
828			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
829	};
830
831	soc: soc@0 {
832		#address-cells = <1>;
833		#size-cells = <1>;
834		ranges = <0 0 0 0xffffffff>;
835		compatible = "simple-bus";
836
837		gcc: clock-controller@100000 {
838			compatible = "qcom,gcc-msm8998";
839			#clock-cells = <1>;
840			#reset-cells = <1>;
841			#power-domain-cells = <1>;
842			reg = <0x00100000 0xb0000>;
843
844			clock-names = "xo", "sleep_clk";
845			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
846
847			/*
848			 * The hypervisor typically configures the memory region where these clocks
849			 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
850			 * these clocks on a device with such configuration (e.g. because they are
851			 * enabled but unused during boot-up), the device will most likely decide
852			 * to reboot.
853			 * In light of that, we are conservative here and we list all such clocks
854			 * as protected. The board dts (or a user-supplied dts) can override the
855			 * list of protected clocks if it differs from the norm, and it is in fact
856			 * desired for the HLOS to manage these clocks
857			 */
858			protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
859					   <SSC_XO>,
860					   <SSC_CNOC_AHBS_CLK>;
861		};
862
863		rpm_msg_ram: sram@778000 {
864			compatible = "qcom,rpm-msg-ram";
865			reg = <0x00778000 0x7000>;
866		};
867
868		qfprom: qfprom@784000 {
869			compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
870			reg = <0x00784000 0x621c>;
871			#address-cells = <1>;
872			#size-cells = <1>;
873
874			qusb2_hstx_trim: hstx-trim@23a {
875				reg = <0x23a 0x1>;
876				bits = <0 4>;
877			};
878		};
879
880		tsens0: thermal@10ab000 {
881			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
882			reg = <0x010ab000 0x1000>, /* TM */
883			      <0x010aa000 0x1000>; /* SROT */
884			#qcom,sensors = <14>;
885			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
886				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
887			interrupt-names = "uplow", "critical";
888			#thermal-sensor-cells = <1>;
889		};
890
891		tsens1: thermal@10ae000 {
892			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
893			reg = <0x010ae000 0x1000>, /* TM */
894			      <0x010ad000 0x1000>; /* SROT */
895			#qcom,sensors = <8>;
896			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
897				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
898			interrupt-names = "uplow", "critical";
899			#thermal-sensor-cells = <1>;
900		};
901
902		anoc1_smmu: iommu@1680000 {
903			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
904			reg = <0x01680000 0x10000>;
905			#iommu-cells = <1>;
906
907			#global-interrupts = <0>;
908			interrupts =
909				<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
910				<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
911				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
912				<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
913				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
914				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
915		};
916
917		anoc2_smmu: iommu@16c0000 {
918			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
919			reg = <0x016c0000 0x40000>;
920			#iommu-cells = <1>;
921
922			#global-interrupts = <0>;
923			interrupts =
924				<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
925				<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
926				<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
927				<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
928				<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
929				<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
930				<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
931				<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
932				<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
933				<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
934		};
935
936		pcie0: pcie@1c00000 {
937			compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
938			reg = <0x01c00000 0x2000>,
939			      <0x1b000000 0xf1d>,
940			      <0x1b000f20 0xa8>,
941			      <0x1b100000 0x100000>;
942			reg-names = "parf", "dbi", "elbi", "config";
943			device_type = "pci";
944			linux,pci-domain = <0>;
945			bus-range = <0x00 0xff>;
946			#address-cells = <3>;
947			#size-cells = <2>;
948			num-lanes = <1>;
949			phys = <&pcie_phy>;
950			phy-names = "pciephy";
951			status = "disabled";
952
953			ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
954				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
955
956			#interrupt-cells = <1>;
957			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
958			interrupt-names = "msi";
959			interrupt-map-mask = <0 0 0 0x7>;
960			interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
961					<0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
962					<0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
963					<0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
964
965			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
966				 <&gcc GCC_PCIE_0_AUX_CLK>,
967				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
968				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
969				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
970			clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
971
972			power-domains = <&gcc PCIE_0_GDSC>;
973			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
974			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
975		};
976
977		pcie_phy: phy@1c06000 {
978			compatible = "qcom,msm8998-qmp-pcie-phy";
979			reg = <0x01c06000 0x1000>;
980			status = "disabled";
981
982			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
983				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
984				 <&gcc GCC_PCIE_CLKREF_CLK>,
985				 <&gcc GCC_PCIE_0_PIPE_CLK>;
986			clock-names = "aux",
987				      "cfg_ahb",
988				      "ref",
989				      "pipe";
990
991			clock-output-names = "pcie_0_pipe_clk_src";
992			#clock-cells = <0>;
993
994			#phy-cells = <0>;
995
996			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
997			reset-names = "phy", "common";
998
999			vdda-phy-supply = <&vreg_l1a_0p875>;
1000			vdda-pll-supply = <&vreg_l2a_1p2>;
1001		};
1002
1003		ufshc: ufshc@1da4000 {
1004			compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1005			reg = <0x01da4000 0x2500>;
1006			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1007			phys = <&ufsphy>;
1008			phy-names = "ufsphy";
1009			lanes-per-direction = <2>;
1010			power-domains = <&gcc UFS_GDSC>;
1011			status = "disabled";
1012			#reset-cells = <1>;
1013
1014			clock-names =
1015				"core_clk",
1016				"bus_aggr_clk",
1017				"iface_clk",
1018				"core_clk_unipro",
1019				"ref_clk",
1020				"tx_lane0_sync_clk",
1021				"rx_lane0_sync_clk",
1022				"rx_lane1_sync_clk";
1023			clocks =
1024				<&gcc GCC_UFS_AXI_CLK>,
1025				<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1026				<&gcc GCC_UFS_AHB_CLK>,
1027				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1028				<&rpmcc RPM_SMD_LN_BB_CLK1>,
1029				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1030				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1031				<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1032			freq-table-hz =
1033				<50000000 200000000>,
1034				<0 0>,
1035				<0 0>,
1036				<37500000 150000000>,
1037				<0 0>,
1038				<0 0>,
1039				<0 0>,
1040				<0 0>;
1041
1042			resets = <&gcc GCC_UFS_BCR>;
1043			reset-names = "rst";
1044		};
1045
1046		ufsphy: phy@1da7000 {
1047			compatible = "qcom,msm8998-qmp-ufs-phy";
1048			reg = <0x01da7000 0x1000>;
1049
1050			clock-names =
1051				"ref",
1052				"ref_aux";
1053			clocks =
1054				<&gcc GCC_UFS_CLKREF_CLK>,
1055				<&gcc GCC_UFS_PHY_AUX_CLK>;
1056
1057			reset-names = "ufsphy";
1058			resets = <&ufshc 0>;
1059
1060			#phy-cells = <0>;
1061			status = "disabled";
1062		};
1063
1064		tcsr_mutex: hwlock@1f40000 {
1065			compatible = "qcom,tcsr-mutex";
1066			reg = <0x01f40000 0x20000>;
1067			#hwlock-cells = <1>;
1068		};
1069
1070		tcsr_regs_1: syscon@1f60000 {
1071			compatible = "qcom,msm8998-tcsr", "syscon";
1072			reg = <0x01f60000 0x20000>;
1073		};
1074
1075		tlmm: pinctrl@3400000 {
1076			compatible = "qcom,msm8998-pinctrl";
1077			reg = <0x03400000 0xc00000>;
1078			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1079			gpio-ranges = <&tlmm 0 0 150>;
1080			gpio-controller;
1081			#gpio-cells = <2>;
1082			interrupt-controller;
1083			#interrupt-cells = <2>;
1084
1085			sdc2_on: sdc2-on-state {
1086				clk-pins {
1087					pins = "sdc2_clk";
1088					drive-strength = <16>;
1089					bias-disable;
1090				};
1091
1092				cmd-pins {
1093					pins = "sdc2_cmd";
1094					drive-strength = <10>;
1095					bias-pull-up;
1096				};
1097
1098				data-pins {
1099					pins = "sdc2_data";
1100					drive-strength = <10>;
1101					bias-pull-up;
1102				};
1103			};
1104
1105			sdc2_off: sdc2-off-state {
1106				clk-pins {
1107					pins = "sdc2_clk";
1108					drive-strength = <2>;
1109					bias-disable;
1110				};
1111
1112				cmd-pins {
1113					pins = "sdc2_cmd";
1114					drive-strength = <2>;
1115					bias-pull-up;
1116				};
1117
1118				data-pins {
1119					pins = "sdc2_data";
1120					drive-strength = <2>;
1121					bias-pull-up;
1122				};
1123			};
1124
1125			sdc2_cd: sdc2-cd-state {
1126				pins = "gpio95";
1127				function = "gpio";
1128				bias-pull-up;
1129				drive-strength = <2>;
1130			};
1131
1132			blsp1_uart3_on: blsp1-uart3-on-state {
1133				tx-pins {
1134					pins = "gpio45";
1135					function = "blsp_uart3_a";
1136					drive-strength = <2>;
1137					bias-disable;
1138				};
1139
1140				rx-pins {
1141					pins = "gpio46";
1142					function = "blsp_uart3_a";
1143					drive-strength = <2>;
1144					bias-disable;
1145				};
1146
1147				cts-pins {
1148					pins = "gpio47";
1149					function = "blsp_uart3_a";
1150					drive-strength = <2>;
1151					bias-disable;
1152				};
1153
1154				rfr-pins {
1155					pins = "gpio48";
1156					function = "blsp_uart3_a";
1157					drive-strength = <2>;
1158					bias-disable;
1159				};
1160			};
1161
1162			blsp1_i2c1_default: blsp1-i2c1-default-state {
1163				pins = "gpio2", "gpio3";
1164				function = "blsp_i2c1";
1165				drive-strength = <2>;
1166				bias-disable;
1167			};
1168
1169			blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1170				pins = "gpio2", "gpio3";
1171				function = "blsp_i2c1";
1172				drive-strength = <2>;
1173				bias-pull-up;
1174			};
1175
1176			blsp1_i2c2_default: blsp1-i2c2-default-state {
1177				pins = "gpio32", "gpio33";
1178				function = "blsp_i2c2";
1179				drive-strength = <2>;
1180				bias-disable;
1181			};
1182
1183			blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1184				pins = "gpio32", "gpio33";
1185				function = "blsp_i2c2";
1186				drive-strength = <2>;
1187				bias-pull-up;
1188			};
1189
1190			blsp1_i2c3_default: blsp1-i2c3-default-state {
1191				pins = "gpio47", "gpio48";
1192				function = "blsp_i2c3";
1193				drive-strength = <2>;
1194				bias-disable;
1195			};
1196
1197			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1198				pins = "gpio47", "gpio48";
1199				function = "blsp_i2c3";
1200				drive-strength = <2>;
1201				bias-pull-up;
1202			};
1203
1204			blsp1_i2c4_default: blsp1-i2c4-default-state {
1205				pins = "gpio10", "gpio11";
1206				function = "blsp_i2c4";
1207				drive-strength = <2>;
1208				bias-disable;
1209			};
1210
1211			blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1212				pins = "gpio10", "gpio11";
1213				function = "blsp_i2c4";
1214				drive-strength = <2>;
1215				bias-pull-up;
1216			};
1217
1218			blsp1_i2c5_default: blsp1-i2c5-default-state {
1219				pins = "gpio87", "gpio88";
1220				function = "blsp_i2c5";
1221				drive-strength = <2>;
1222				bias-disable;
1223			};
1224
1225			blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1226				pins = "gpio87", "gpio88";
1227				function = "blsp_i2c5";
1228				drive-strength = <2>;
1229				bias-pull-up;
1230			};
1231
1232			blsp1_i2c6_default: blsp1-i2c6-default-state {
1233				pins = "gpio43", "gpio44";
1234				function = "blsp_i2c6";
1235				drive-strength = <2>;
1236				bias-disable;
1237			};
1238
1239			blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1240				pins = "gpio43", "gpio44";
1241				function = "blsp_i2c6";
1242				drive-strength = <2>;
1243				bias-pull-up;
1244			};
1245
1246			blsp1_spi_b_default: blsp1-spi-b-default-state {
1247				pins = "gpio23", "gpio28";
1248				function = "blsp1_spi_b";
1249				drive-strength = <6>;
1250				bias-disable;
1251			};
1252
1253			blsp1_spi1_default: blsp1-spi1-default-state {
1254				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1255				function = "blsp_spi1";
1256				drive-strength = <6>;
1257				bias-disable;
1258			};
1259
1260			blsp1_spi2_default: blsp1-spi2-default-state {
1261				pins = "gpio31", "gpio34", "gpio32", "gpio33";
1262				function = "blsp_spi2";
1263				drive-strength = <6>;
1264				bias-disable;
1265			};
1266
1267			blsp1_spi3_default: blsp1-spi3-default-state {
1268				pins = "gpio45", "gpio46", "gpio47", "gpio48";
1269				function = "blsp_spi2";
1270				drive-strength = <6>;
1271				bias-disable;
1272			};
1273
1274			blsp1_spi4_default: blsp1-spi4-default-state {
1275				pins = "gpio8", "gpio9", "gpio10", "gpio11";
1276				function = "blsp_spi4";
1277				drive-strength = <6>;
1278				bias-disable;
1279			};
1280
1281			blsp1_spi5_default: blsp1-spi5-default-state {
1282				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1283				function = "blsp_spi5";
1284				drive-strength = <6>;
1285				bias-disable;
1286			};
1287
1288			blsp1_spi6_default: blsp1-spi6-default-state {
1289				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1290				function = "blsp_spi6";
1291				drive-strength = <6>;
1292				bias-disable;
1293			};
1294
1295
1296			/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1297			blsp2_i2c1_default: blsp2-i2c1-default-state {
1298				pins = "gpio55", "gpio56";
1299				function = "blsp_i2c7";
1300				drive-strength = <2>;
1301				bias-disable;
1302			};
1303
1304			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1305				pins = "gpio55", "gpio56";
1306				function = "blsp_i2c7";
1307				drive-strength = <2>;
1308				bias-pull-up;
1309			};
1310
1311			blsp2_i2c2_default: blsp2-i2c2-default-state {
1312				pins = "gpio6", "gpio7";
1313				function = "blsp_i2c8";
1314				drive-strength = <2>;
1315				bias-disable;
1316			};
1317
1318			blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1319				pins = "gpio6", "gpio7";
1320				function = "blsp_i2c8";
1321				drive-strength = <2>;
1322				bias-pull-up;
1323			};
1324
1325			blsp2_i2c3_default: blsp2-i2c3-default-state {
1326				pins = "gpio51", "gpio52";
1327				function = "blsp_i2c9";
1328				drive-strength = <2>;
1329				bias-disable;
1330			};
1331
1332			blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1333				pins = "gpio51", "gpio52";
1334				function = "blsp_i2c9";
1335				drive-strength = <2>;
1336				bias-pull-up;
1337			};
1338
1339			blsp2_i2c4_default: blsp2-i2c4-default-state {
1340				pins = "gpio67", "gpio68";
1341				function = "blsp_i2c10";
1342				drive-strength = <2>;
1343				bias-disable;
1344			};
1345
1346			blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1347				pins = "gpio67", "gpio68";
1348				function = "blsp_i2c10";
1349				drive-strength = <2>;
1350				bias-pull-up;
1351			};
1352
1353			blsp2_i2c5_default: blsp2-i2c5-default-state {
1354				pins = "gpio60", "gpio61";
1355				function = "blsp_i2c11";
1356				drive-strength = <2>;
1357				bias-disable;
1358			};
1359
1360			blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1361				pins = "gpio60", "gpio61";
1362				function = "blsp_i2c11";
1363				drive-strength = <2>;
1364				bias-pull-up;
1365			};
1366
1367			blsp2_i2c6_default: blsp2-i2c6-default-state {
1368				pins = "gpio83", "gpio84";
1369				function = "blsp_i2c12";
1370				drive-strength = <2>;
1371				bias-disable;
1372			};
1373
1374			blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1375				pins = "gpio83", "gpio84";
1376				function = "blsp_i2c12";
1377				drive-strength = <2>;
1378				bias-pull-up;
1379			};
1380
1381			blsp2_spi1_default: blsp2-spi1-default-state {
1382				pins = "gpio53", "gpio54", "gpio55", "gpio56";
1383				function = "blsp_spi7";
1384				drive-strength = <6>;
1385				bias-disable;
1386			};
1387
1388			blsp2_spi2_default: blsp2-spi2-default-state {
1389				pins = "gpio4", "gpio5", "gpio6", "gpio7";
1390				function = "blsp_spi8";
1391				drive-strength = <6>;
1392				bias-disable;
1393			};
1394
1395			blsp2_spi3_default: blsp2-spi3-default-state {
1396				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1397				function = "blsp_spi9";
1398				drive-strength = <6>;
1399				bias-disable;
1400			};
1401
1402			blsp2_spi4_default: blsp2-spi4-default-state {
1403				pins = "gpio65", "gpio66", "gpio67", "gpio68";
1404				function = "blsp_spi10";
1405				drive-strength = <6>;
1406				bias-disable;
1407			};
1408
1409			blsp2_spi5_default: blsp2-spi5-default-state {
1410				pins = "gpio58", "gpio59", "gpio60", "gpio61";
1411				function = "blsp_spi11";
1412				drive-strength = <6>;
1413				bias-disable;
1414			};
1415
1416			blsp2_spi6_default: blsp2-spi6-default-state {
1417				pins = "gpio81", "gpio82", "gpio83", "gpio84";
1418				function = "blsp_spi12";
1419				drive-strength = <6>;
1420				bias-disable;
1421			};
1422		};
1423
1424		remoteproc_mss: remoteproc@4080000 {
1425			compatible = "qcom,msm8998-mss-pil";
1426			reg = <0x04080000 0x100>, <0x04180000 0x20>;
1427			reg-names = "qdsp6", "rmb";
1428
1429			interrupts-extended =
1430				<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1431				<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1432				<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1433				<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1434				<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1435				<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1436			interrupt-names = "wdog", "fatal", "ready",
1437					  "handover", "stop-ack",
1438					  "shutdown-ack";
1439
1440			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1441				 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1442				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1443				 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1444				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1445				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1446				 <&rpmcc RPM_SMD_QDSS_CLK>,
1447				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1448			clock-names = "iface", "bus", "mem", "gpll0_mss",
1449				      "snoc_axi", "mnoc_axi", "qdss", "xo";
1450
1451			qcom,smem-states = <&modem_smp2p_out 0>;
1452			qcom,smem-state-names = "stop";
1453
1454			resets = <&gcc GCC_MSS_RESTART>;
1455			reset-names = "mss_restart";
1456
1457			qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1458
1459			power-domains = <&rpmpd MSM8998_VDDCX>,
1460					<&rpmpd MSM8998_VDDMX>;
1461			power-domain-names = "cx", "mx";
1462
1463			status = "disabled";
1464
1465			mba {
1466				memory-region = <&mba_mem>;
1467			};
1468
1469			mpss {
1470				memory-region = <&mpss_mem>;
1471			};
1472
1473			metadata {
1474				memory-region = <&mdata_mem>;
1475			};
1476
1477			glink-edge {
1478				interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1479				label = "modem";
1480				qcom,remote-pid = <1>;
1481				mboxes = <&apcs_glb 15>;
1482			};
1483		};
1484
1485		adreno_gpu: gpu@5000000 {
1486			compatible = "qcom,adreno-540.1", "qcom,adreno";
1487			reg = <0x05000000 0x40000>;
1488			reg-names = "kgsl_3d0_reg_memory";
1489
1490			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1491				<&gpucc RBBMTIMER_CLK>,
1492				<&gcc GCC_BIMC_GFX_CLK>,
1493				<&gcc GCC_GPU_BIMC_GFX_CLK>,
1494				<&gpucc RBCPR_CLK>,
1495				<&gpucc GFX3D_CLK>;
1496			clock-names = "iface",
1497				"rbbmtimer",
1498				"mem",
1499				"mem_iface",
1500				"rbcpr",
1501				"core";
1502
1503			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1504			iommus = <&adreno_smmu 0>;
1505			operating-points-v2 = <&gpu_opp_table>;
1506			power-domains = <&rpmpd MSM8998_VDDMX>;
1507			status = "disabled";
1508
1509			gpu_opp_table: opp-table {
1510				compatible = "operating-points-v2";
1511				opp-710000097 {
1512					opp-hz = /bits/ 64 <710000097>;
1513					opp-level = <RPM_SMD_LEVEL_TURBO>;
1514					opp-supported-hw = <0xff>;
1515				};
1516
1517				opp-670000048 {
1518					opp-hz = /bits/ 64 <670000048>;
1519					opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1520					opp-supported-hw = <0xff>;
1521				};
1522
1523				opp-596000097 {
1524					opp-hz = /bits/ 64 <596000097>;
1525					opp-level = <RPM_SMD_LEVEL_NOM>;
1526					opp-supported-hw = <0xff>;
1527				};
1528
1529				opp-515000097 {
1530					opp-hz = /bits/ 64 <515000097>;
1531					opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1532					opp-supported-hw = <0xff>;
1533				};
1534
1535				opp-414000000 {
1536					opp-hz = /bits/ 64 <414000000>;
1537					opp-level = <RPM_SMD_LEVEL_SVS>;
1538					opp-supported-hw = <0xff>;
1539				};
1540
1541				opp-342000000 {
1542					opp-hz = /bits/ 64 <342000000>;
1543					opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1544					opp-supported-hw = <0xff>;
1545				};
1546
1547				opp-257000000 {
1548					opp-hz = /bits/ 64 <257000000>;
1549					opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1550					opp-supported-hw = <0xff>;
1551				};
1552			};
1553		};
1554
1555		adreno_smmu: iommu@5040000 {
1556			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1557			reg = <0x05040000 0x10000>;
1558			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1559				 <&gcc GCC_BIMC_GFX_CLK>,
1560				 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1561			clock-names = "iface", "mem", "mem_iface";
1562
1563			#global-interrupts = <0>;
1564			#iommu-cells = <1>;
1565			interrupts =
1566				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1567				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1568				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1569			/*
1570			 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1571			 * GPU-CX for SMMU but we need both of them up for Adreno.
1572			 * Contemporarily, we also need to manage the VDDMX rpmpd
1573			 * domain in the Adreno driver.
1574			 * Enable GPU CX/GX GDSCs here so that we can manage the
1575			 * SoC VDDMX RPM Power Domain in the Adreno driver.
1576			 */
1577			power-domains = <&gpucc GPU_GX_GDSC>;
1578			status = "disabled";
1579		};
1580
1581		gpucc: clock-controller@5065000 {
1582			compatible = "qcom,msm8998-gpucc";
1583			#clock-cells = <1>;
1584			#reset-cells = <1>;
1585			#power-domain-cells = <1>;
1586			reg = <0x05065000 0x9000>;
1587
1588			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1589				 <&gcc GCC_GPU_GPLL0_CLK>;
1590			clock-names = "xo",
1591				      "gpll0";
1592		};
1593
1594		remoteproc_slpi: remoteproc@5800000 {
1595			compatible = "qcom,msm8998-slpi-pas";
1596			reg = <0x05800000 0x4040>;
1597
1598			interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1599					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1600					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1601					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1602					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1603			interrupt-names = "wdog", "fatal", "ready",
1604					  "handover", "stop-ack";
1605
1606			px-supply = <&vreg_lvs2a_1p8>;
1607
1608			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1609			clock-names = "xo";
1610
1611			memory-region = <&slpi_mem>;
1612
1613			qcom,smem-states = <&slpi_smp2p_out 0>;
1614			qcom,smem-state-names = "stop";
1615
1616			power-domains = <&rpmpd MSM8998_SSCCX>;
1617			power-domain-names = "ssc_cx";
1618
1619			status = "disabled";
1620
1621			glink-edge {
1622				interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1623				label = "dsps";
1624				qcom,remote-pid = <3>;
1625				mboxes = <&apcs_glb 27>;
1626			};
1627		};
1628
1629		stm: stm@6002000 {
1630			compatible = "arm,coresight-stm", "arm,primecell";
1631			reg = <0x06002000 0x1000>,
1632			      <0x16280000 0x180000>;
1633			reg-names = "stm-base", "stm-stimulus-base";
1634			status = "disabled";
1635
1636			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1637			clock-names = "apb_pclk", "atclk";
1638
1639			out-ports {
1640				port {
1641					stm_out: endpoint {
1642						remote-endpoint = <&funnel0_in7>;
1643					};
1644				};
1645			};
1646		};
1647
1648		funnel1: funnel@6041000 {
1649			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1650			reg = <0x06041000 0x1000>;
1651			status = "disabled";
1652
1653			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1654			clock-names = "apb_pclk", "atclk";
1655
1656			out-ports {
1657				port {
1658					funnel0_out: endpoint {
1659						remote-endpoint =
1660						  <&merge_funnel_in0>;
1661					};
1662				};
1663			};
1664
1665			in-ports {
1666				#address-cells = <1>;
1667				#size-cells = <0>;
1668
1669				port@7 {
1670					reg = <7>;
1671					funnel0_in7: endpoint {
1672						remote-endpoint = <&stm_out>;
1673					};
1674				};
1675			};
1676		};
1677
1678		funnel2: funnel@6042000 {
1679			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1680			reg = <0x06042000 0x1000>;
1681			status = "disabled";
1682
1683			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1684			clock-names = "apb_pclk", "atclk";
1685
1686			out-ports {
1687				port {
1688					funnel1_out: endpoint {
1689						remote-endpoint =
1690						  <&merge_funnel_in1>;
1691					};
1692				};
1693			};
1694
1695			in-ports {
1696				#address-cells = <1>;
1697				#size-cells = <0>;
1698
1699				port@6 {
1700					reg = <6>;
1701					funnel1_in6: endpoint {
1702						remote-endpoint =
1703						  <&apss_merge_funnel_out>;
1704					};
1705				};
1706			};
1707		};
1708
1709		funnel3: funnel@6045000 {
1710			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1711			reg = <0x06045000 0x1000>;
1712			status = "disabled";
1713
1714			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1715			clock-names = "apb_pclk", "atclk";
1716
1717			out-ports {
1718				port {
1719					merge_funnel_out: endpoint {
1720						remote-endpoint =
1721						  <&etf_in>;
1722					};
1723				};
1724			};
1725
1726			in-ports {
1727				#address-cells = <1>;
1728				#size-cells = <0>;
1729
1730				port@0 {
1731					reg = <0>;
1732					merge_funnel_in0: endpoint {
1733						remote-endpoint =
1734						  <&funnel0_out>;
1735					};
1736				};
1737
1738				port@1 {
1739					reg = <1>;
1740					merge_funnel_in1: endpoint {
1741						remote-endpoint =
1742						  <&funnel1_out>;
1743					};
1744				};
1745			};
1746		};
1747
1748		replicator1: replicator@6046000 {
1749			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1750			reg = <0x06046000 0x1000>;
1751			status = "disabled";
1752
1753			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1754			clock-names = "apb_pclk", "atclk";
1755
1756			out-ports {
1757				port {
1758					replicator_out: endpoint {
1759						remote-endpoint = <&etr_in>;
1760					};
1761				};
1762			};
1763
1764			in-ports {
1765				port {
1766					replicator_in: endpoint {
1767						remote-endpoint = <&etf_out>;
1768					};
1769				};
1770			};
1771		};
1772
1773		etf: etf@6047000 {
1774			compatible = "arm,coresight-tmc", "arm,primecell";
1775			reg = <0x06047000 0x1000>;
1776			status = "disabled";
1777
1778			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1779			clock-names = "apb_pclk", "atclk";
1780
1781			out-ports {
1782				port {
1783					etf_out: endpoint {
1784						remote-endpoint =
1785						  <&replicator_in>;
1786					};
1787				};
1788			};
1789
1790			in-ports {
1791				port {
1792					etf_in: endpoint {
1793						remote-endpoint =
1794						  <&merge_funnel_out>;
1795					};
1796				};
1797			};
1798		};
1799
1800		etr: etr@6048000 {
1801			compatible = "arm,coresight-tmc", "arm,primecell";
1802			reg = <0x06048000 0x1000>;
1803			status = "disabled";
1804
1805			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1806			clock-names = "apb_pclk", "atclk";
1807			arm,scatter-gather;
1808
1809			in-ports {
1810				port {
1811					etr_in: endpoint {
1812						remote-endpoint =
1813						  <&replicator_out>;
1814					};
1815				};
1816			};
1817		};
1818
1819		etm1: etm@7840000 {
1820			compatible = "arm,coresight-etm4x", "arm,primecell";
1821			reg = <0x07840000 0x1000>;
1822			status = "disabled";
1823
1824			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1825			clock-names = "apb_pclk", "atclk";
1826
1827			cpu = <&CPU0>;
1828
1829			out-ports {
1830				port {
1831					etm0_out: endpoint {
1832						remote-endpoint =
1833						  <&apss_funnel_in0>;
1834					};
1835				};
1836			};
1837		};
1838
1839		etm2: etm@7940000 {
1840			compatible = "arm,coresight-etm4x", "arm,primecell";
1841			reg = <0x07940000 0x1000>;
1842			status = "disabled";
1843
1844			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1845			clock-names = "apb_pclk", "atclk";
1846
1847			cpu = <&CPU1>;
1848
1849			out-ports {
1850				port {
1851					etm1_out: endpoint {
1852						remote-endpoint =
1853						  <&apss_funnel_in1>;
1854					};
1855				};
1856			};
1857		};
1858
1859		etm3: etm@7a40000 {
1860			compatible = "arm,coresight-etm4x", "arm,primecell";
1861			reg = <0x07a40000 0x1000>;
1862			status = "disabled";
1863
1864			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1865			clock-names = "apb_pclk", "atclk";
1866
1867			cpu = <&CPU2>;
1868
1869			out-ports {
1870				port {
1871					etm2_out: endpoint {
1872						remote-endpoint =
1873						  <&apss_funnel_in2>;
1874					};
1875				};
1876			};
1877		};
1878
1879		etm4: etm@7b40000 {
1880			compatible = "arm,coresight-etm4x", "arm,primecell";
1881			reg = <0x07b40000 0x1000>;
1882			status = "disabled";
1883
1884			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1885			clock-names = "apb_pclk", "atclk";
1886
1887			cpu = <&CPU3>;
1888
1889			out-ports {
1890				port {
1891					etm3_out: endpoint {
1892						remote-endpoint =
1893						  <&apss_funnel_in3>;
1894					};
1895				};
1896			};
1897		};
1898
1899		funnel4: funnel@7b60000 { /* APSS Funnel */
1900			compatible = "arm,coresight-etm4x", "arm,primecell";
1901			reg = <0x07b60000 0x1000>;
1902			status = "disabled";
1903
1904			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1905			clock-names = "apb_pclk", "atclk";
1906
1907			out-ports {
1908				port {
1909					apss_funnel_out: endpoint {
1910						remote-endpoint =
1911						  <&apss_merge_funnel_in>;
1912					};
1913				};
1914			};
1915
1916			in-ports {
1917				#address-cells = <1>;
1918				#size-cells = <0>;
1919
1920				port@0 {
1921					reg = <0>;
1922					apss_funnel_in0: endpoint {
1923						remote-endpoint =
1924						  <&etm0_out>;
1925					};
1926				};
1927
1928				port@1 {
1929					reg = <1>;
1930					apss_funnel_in1: endpoint {
1931						remote-endpoint =
1932						  <&etm1_out>;
1933					};
1934				};
1935
1936				port@2 {
1937					reg = <2>;
1938					apss_funnel_in2: endpoint {
1939						remote-endpoint =
1940						  <&etm2_out>;
1941					};
1942				};
1943
1944				port@3 {
1945					reg = <3>;
1946					apss_funnel_in3: endpoint {
1947						remote-endpoint =
1948						  <&etm3_out>;
1949					};
1950				};
1951
1952				port@4 {
1953					reg = <4>;
1954					apss_funnel_in4: endpoint {
1955						remote-endpoint =
1956						  <&etm4_out>;
1957					};
1958				};
1959
1960				port@5 {
1961					reg = <5>;
1962					apss_funnel_in5: endpoint {
1963						remote-endpoint =
1964						  <&etm5_out>;
1965					};
1966				};
1967
1968				port@6 {
1969					reg = <6>;
1970					apss_funnel_in6: endpoint {
1971						remote-endpoint =
1972						  <&etm6_out>;
1973					};
1974				};
1975
1976				port@7 {
1977					reg = <7>;
1978					apss_funnel_in7: endpoint {
1979						remote-endpoint =
1980						  <&etm7_out>;
1981					};
1982				};
1983			};
1984		};
1985
1986		funnel5: funnel@7b70000 {
1987			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1988			reg = <0x07b70000 0x1000>;
1989			status = "disabled";
1990
1991			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1992			clock-names = "apb_pclk", "atclk";
1993
1994			out-ports {
1995				port {
1996					apss_merge_funnel_out: endpoint {
1997						remote-endpoint =
1998						  <&funnel1_in6>;
1999					};
2000				};
2001			};
2002
2003			in-ports {
2004				port {
2005					apss_merge_funnel_in: endpoint {
2006						remote-endpoint =
2007						  <&apss_funnel_out>;
2008					};
2009				};
2010			};
2011		};
2012
2013		etm5: etm@7c40000 {
2014			compatible = "arm,coresight-etm4x", "arm,primecell";
2015			reg = <0x07c40000 0x1000>;
2016			status = "disabled";
2017
2018			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2019			clock-names = "apb_pclk", "atclk";
2020
2021			cpu = <&CPU4>;
2022
2023			out-ports {
2024				port {
2025					etm4_out: endpoint {
2026						remote-endpoint = <&apss_funnel_in4>;
2027					};
2028				};
2029			};
2030		};
2031
2032		etm6: etm@7d40000 {
2033			compatible = "arm,coresight-etm4x", "arm,primecell";
2034			reg = <0x07d40000 0x1000>;
2035			status = "disabled";
2036
2037			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2038			clock-names = "apb_pclk", "atclk";
2039
2040			cpu = <&CPU5>;
2041
2042			out-ports {
2043				port {
2044					etm5_out: endpoint {
2045						remote-endpoint = <&apss_funnel_in5>;
2046					};
2047				};
2048			};
2049		};
2050
2051		etm7: etm@7e40000 {
2052			compatible = "arm,coresight-etm4x", "arm,primecell";
2053			reg = <0x07e40000 0x1000>;
2054			status = "disabled";
2055
2056			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2057			clock-names = "apb_pclk", "atclk";
2058
2059			cpu = <&CPU6>;
2060
2061			out-ports {
2062				port {
2063					etm6_out: endpoint {
2064						remote-endpoint = <&apss_funnel_in6>;
2065					};
2066				};
2067			};
2068		};
2069
2070		etm8: etm@7f40000 {
2071			compatible = "arm,coresight-etm4x", "arm,primecell";
2072			reg = <0x07f40000 0x1000>;
2073			status = "disabled";
2074
2075			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2076			clock-names = "apb_pclk", "atclk";
2077
2078			cpu = <&CPU7>;
2079
2080			out-ports {
2081				port {
2082					etm7_out: endpoint {
2083						remote-endpoint = <&apss_funnel_in7>;
2084					};
2085				};
2086			};
2087		};
2088
2089		sram@290000 {
2090			compatible = "qcom,rpm-stats";
2091			reg = <0x00290000 0x10000>;
2092		};
2093
2094		spmi_bus: spmi@800f000 {
2095			compatible = "qcom,spmi-pmic-arb";
2096			reg = <0x0800f000 0x1000>,
2097			      <0x08400000 0x1000000>,
2098			      <0x09400000 0x1000000>,
2099			      <0x0a400000 0x220000>,
2100			      <0x0800a000 0x3000>;
2101			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2102			interrupt-names = "periph_irq";
2103			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2104			qcom,ee = <0>;
2105			qcom,channel = <0>;
2106			#address-cells = <2>;
2107			#size-cells = <0>;
2108			interrupt-controller;
2109			#interrupt-cells = <4>;
2110		};
2111
2112		usb3: usb@a8f8800 {
2113			compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2114			reg = <0x0a8f8800 0x400>;
2115			status = "disabled";
2116			#address-cells = <1>;
2117			#size-cells = <1>;
2118			ranges;
2119
2120			clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2121				 <&gcc GCC_USB30_MASTER_CLK>,
2122				 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2123				 <&gcc GCC_USB30_SLEEP_CLK>,
2124				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2125			clock-names = "cfg_noc",
2126				      "core",
2127				      "iface",
2128				      "sleep",
2129				      "mock_utmi";
2130
2131			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2132					  <&gcc GCC_USB30_MASTER_CLK>;
2133			assigned-clock-rates = <19200000>, <120000000>;
2134
2135			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2136				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2137			interrupt-names = "hs_phy_irq", "ss_phy_irq";
2138
2139			power-domains = <&gcc USB_30_GDSC>;
2140
2141			resets = <&gcc GCC_USB_30_BCR>;
2142
2143			usb3_dwc3: usb@a800000 {
2144				compatible = "snps,dwc3";
2145				reg = <0x0a800000 0xcd00>;
2146				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2147				snps,dis_u2_susphy_quirk;
2148				snps,dis_enblslpm_quirk;
2149				phys = <&qusb2phy>, <&usb3phy>;
2150				phy-names = "usb2-phy", "usb3-phy";
2151				snps,has-lpm-erratum;
2152				snps,hird-threshold = /bits/ 8 <0x10>;
2153			};
2154		};
2155
2156		usb3phy: phy@c010000 {
2157			compatible = "qcom,msm8998-qmp-usb3-phy";
2158			reg = <0x0c010000 0x1000>;
2159
2160			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2161				 <&gcc GCC_USB3_CLKREF_CLK>,
2162				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2163				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
2164			clock-names = "aux",
2165				      "ref",
2166				      "cfg_ahb",
2167				      "pipe";
2168			clock-output-names = "usb3_phy_pipe_clk_src";
2169			#clock-cells = <0>;
2170			#phy-cells = <0>;
2171
2172			resets = <&gcc GCC_USB3_PHY_BCR>,
2173				 <&gcc GCC_USB3PHY_PHY_BCR>;
2174			reset-names = "phy",
2175				      "phy_phy";
2176
2177			status = "disabled";
2178		};
2179
2180		qusb2phy: phy@c012000 {
2181			compatible = "qcom,msm8998-qusb2-phy";
2182			reg = <0x0c012000 0x2a8>;
2183			status = "disabled";
2184			#phy-cells = <0>;
2185
2186			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2187				 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2188			clock-names = "cfg_ahb", "ref";
2189
2190			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2191
2192			nvmem-cells = <&qusb2_hstx_trim>;
2193		};
2194
2195		sdhc2: mmc@c0a4900 {
2196			compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2197			reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2198			reg-names = "hc", "core";
2199
2200			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2201				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2202			interrupt-names = "hc_irq", "pwr_irq";
2203
2204			clock-names = "iface", "core", "xo";
2205			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2206				 <&gcc GCC_SDCC2_APPS_CLK>,
2207				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2208			bus-width = <4>;
2209			status = "disabled";
2210		};
2211
2212		blsp1_dma: dma-controller@c144000 {
2213			compatible = "qcom,bam-v1.7.0";
2214			reg = <0x0c144000 0x25000>;
2215			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2216			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2217			clock-names = "bam_clk";
2218			#dma-cells = <1>;
2219			qcom,ee = <0>;
2220			qcom,controlled-remotely;
2221			num-channels = <18>;
2222			qcom,num-ees = <4>;
2223		};
2224
2225		blsp1_uart3: serial@c171000 {
2226			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2227			reg = <0x0c171000 0x1000>;
2228			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2229			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2230				 <&gcc GCC_BLSP1_AHB_CLK>;
2231			clock-names = "core", "iface";
2232			dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2233			dma-names = "tx", "rx";
2234			pinctrl-names = "default";
2235			pinctrl-0 = <&blsp1_uart3_on>;
2236			status = "disabled";
2237		};
2238
2239		blsp1_i2c1: i2c@c175000 {
2240			compatible = "qcom,i2c-qup-v2.2.1";
2241			reg = <0x0c175000 0x600>;
2242			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2243
2244			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2245				 <&gcc GCC_BLSP1_AHB_CLK>;
2246			clock-names = "core", "iface";
2247			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2248			dma-names = "tx", "rx";
2249			pinctrl-names = "default", "sleep";
2250			pinctrl-0 = <&blsp1_i2c1_default>;
2251			pinctrl-1 = <&blsp1_i2c1_sleep>;
2252			clock-frequency = <400000>;
2253
2254			status = "disabled";
2255			#address-cells = <1>;
2256			#size-cells = <0>;
2257		};
2258
2259		blsp1_i2c2: i2c@c176000 {
2260			compatible = "qcom,i2c-qup-v2.2.1";
2261			reg = <0x0c176000 0x600>;
2262			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2263
2264			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2265				 <&gcc GCC_BLSP1_AHB_CLK>;
2266			clock-names = "core", "iface";
2267			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2268			dma-names = "tx", "rx";
2269			pinctrl-names = "default", "sleep";
2270			pinctrl-0 = <&blsp1_i2c2_default>;
2271			pinctrl-1 = <&blsp1_i2c2_sleep>;
2272			clock-frequency = <400000>;
2273
2274			status = "disabled";
2275			#address-cells = <1>;
2276			#size-cells = <0>;
2277		};
2278
2279		blsp1_i2c3: i2c@c177000 {
2280			compatible = "qcom,i2c-qup-v2.2.1";
2281			reg = <0x0c177000 0x600>;
2282			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2283
2284			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2285				 <&gcc GCC_BLSP1_AHB_CLK>;
2286			clock-names = "core", "iface";
2287			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2288			dma-names = "tx", "rx";
2289			pinctrl-names = "default", "sleep";
2290			pinctrl-0 = <&blsp1_i2c3_default>;
2291			pinctrl-1 = <&blsp1_i2c3_sleep>;
2292			clock-frequency = <400000>;
2293
2294			status = "disabled";
2295			#address-cells = <1>;
2296			#size-cells = <0>;
2297		};
2298
2299		blsp1_i2c4: i2c@c178000 {
2300			compatible = "qcom,i2c-qup-v2.2.1";
2301			reg = <0x0c178000 0x600>;
2302			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2303
2304			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2305				 <&gcc GCC_BLSP1_AHB_CLK>;
2306			clock-names = "core", "iface";
2307			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2308			dma-names = "tx", "rx";
2309			pinctrl-names = "default", "sleep";
2310			pinctrl-0 = <&blsp1_i2c4_default>;
2311			pinctrl-1 = <&blsp1_i2c4_sleep>;
2312			clock-frequency = <400000>;
2313
2314			status = "disabled";
2315			#address-cells = <1>;
2316			#size-cells = <0>;
2317		};
2318
2319		blsp1_i2c5: i2c@c179000 {
2320			compatible = "qcom,i2c-qup-v2.2.1";
2321			reg = <0x0c179000 0x600>;
2322			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2323
2324			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2325				 <&gcc GCC_BLSP1_AHB_CLK>;
2326			clock-names = "core", "iface";
2327			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2328			dma-names = "tx", "rx";
2329			pinctrl-names = "default", "sleep";
2330			pinctrl-0 = <&blsp1_i2c5_default>;
2331			pinctrl-1 = <&blsp1_i2c5_sleep>;
2332			clock-frequency = <400000>;
2333
2334			status = "disabled";
2335			#address-cells = <1>;
2336			#size-cells = <0>;
2337		};
2338
2339		blsp1_i2c6: i2c@c17a000 {
2340			compatible = "qcom,i2c-qup-v2.2.1";
2341			reg = <0x0c17a000 0x600>;
2342			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2343
2344			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2345				 <&gcc GCC_BLSP1_AHB_CLK>;
2346			clock-names = "core", "iface";
2347			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2348			dma-names = "tx", "rx";
2349			pinctrl-names = "default", "sleep";
2350			pinctrl-0 = <&blsp1_i2c6_default>;
2351			pinctrl-1 = <&blsp1_i2c6_sleep>;
2352			clock-frequency = <400000>;
2353
2354			status = "disabled";
2355			#address-cells = <1>;
2356			#size-cells = <0>;
2357		};
2358
2359		blsp1_spi1: spi@c175000 {
2360			compatible = "qcom,spi-qup-v2.2.1";
2361			reg = <0x0c175000 0x600>;
2362			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2363
2364			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2365				 <&gcc GCC_BLSP1_AHB_CLK>;
2366			clock-names = "core", "iface";
2367			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2368			dma-names = "tx", "rx";
2369			pinctrl-names = "default";
2370			pinctrl-0 = <&blsp1_spi1_default>;
2371
2372			status = "disabled";
2373			#address-cells = <1>;
2374			#size-cells = <0>;
2375		};
2376
2377		blsp1_spi2: spi@c176000 {
2378			compatible = "qcom,spi-qup-v2.2.1";
2379			reg = <0x0c176000 0x600>;
2380			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2381
2382			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2383				 <&gcc GCC_BLSP1_AHB_CLK>;
2384			clock-names = "core", "iface";
2385			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2386			dma-names = "tx", "rx";
2387			pinctrl-names = "default";
2388			pinctrl-0 = <&blsp1_spi2_default>;
2389
2390			status = "disabled";
2391			#address-cells = <1>;
2392			#size-cells = <0>;
2393		};
2394
2395		blsp1_spi3: spi@c177000 {
2396			compatible = "qcom,spi-qup-v2.2.1";
2397			reg = <0x0c177000 0x600>;
2398			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2399
2400			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2401				 <&gcc GCC_BLSP1_AHB_CLK>;
2402			clock-names = "core", "iface";
2403			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2404			dma-names = "tx", "rx";
2405			pinctrl-names = "default";
2406			pinctrl-0 = <&blsp1_spi3_default>;
2407
2408			status = "disabled";
2409			#address-cells = <1>;
2410			#size-cells = <0>;
2411		};
2412
2413		blsp1_spi4: spi@c178000 {
2414			compatible = "qcom,spi-qup-v2.2.1";
2415			reg = <0x0c178000 0x600>;
2416			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2417
2418			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2419				 <&gcc GCC_BLSP1_AHB_CLK>;
2420			clock-names = "core", "iface";
2421			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2422			dma-names = "tx", "rx";
2423			pinctrl-names = "default";
2424			pinctrl-0 = <&blsp1_spi4_default>;
2425
2426			status = "disabled";
2427			#address-cells = <1>;
2428			#size-cells = <0>;
2429		};
2430
2431		blsp1_spi5: spi@c179000 {
2432			compatible = "qcom,spi-qup-v2.2.1";
2433			reg = <0x0c179000 0x600>;
2434			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2435
2436			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2437				 <&gcc GCC_BLSP1_AHB_CLK>;
2438			clock-names = "core", "iface";
2439			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2440			dma-names = "tx", "rx";
2441			pinctrl-names = "default";
2442			pinctrl-0 = <&blsp1_spi5_default>;
2443
2444			status = "disabled";
2445			#address-cells = <1>;
2446			#size-cells = <0>;
2447		};
2448
2449		blsp1_spi6: spi@c17a000 {
2450			compatible = "qcom,spi-qup-v2.2.1";
2451			reg = <0x0c17a000 0x600>;
2452			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2453
2454			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2455				 <&gcc GCC_BLSP1_AHB_CLK>;
2456			clock-names = "core", "iface";
2457			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2458			dma-names = "tx", "rx";
2459			pinctrl-names = "default";
2460			pinctrl-0 = <&blsp1_spi6_default>;
2461
2462			status = "disabled";
2463			#address-cells = <1>;
2464			#size-cells = <0>;
2465		};
2466
2467		blsp2_dma: dma-controller@c184000 {
2468			compatible = "qcom,bam-v1.7.0";
2469			reg = <0x0c184000 0x25000>;
2470			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2471			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2472			clock-names = "bam_clk";
2473			#dma-cells = <1>;
2474			qcom,ee = <0>;
2475			qcom,controlled-remotely;
2476			num-channels = <18>;
2477			qcom,num-ees = <4>;
2478		};
2479
2480		blsp2_uart1: serial@c1b0000 {
2481			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2482			reg = <0x0c1b0000 0x1000>;
2483			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2484			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2485				 <&gcc GCC_BLSP2_AHB_CLK>;
2486			clock-names = "core", "iface";
2487			status = "disabled";
2488		};
2489
2490		blsp2_i2c1: i2c@c1b5000 {
2491			compatible = "qcom,i2c-qup-v2.2.1";
2492			reg = <0x0c1b5000 0x600>;
2493			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2494
2495			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2496				 <&gcc GCC_BLSP2_AHB_CLK>;
2497			clock-names = "core", "iface";
2498			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2499			dma-names = "tx", "rx";
2500			pinctrl-names = "default", "sleep";
2501			pinctrl-0 = <&blsp2_i2c1_default>;
2502			pinctrl-1 = <&blsp2_i2c1_sleep>;
2503			clock-frequency = <400000>;
2504
2505			status = "disabled";
2506			#address-cells = <1>;
2507			#size-cells = <0>;
2508		};
2509
2510		blsp2_i2c2: i2c@c1b6000 {
2511			compatible = "qcom,i2c-qup-v2.2.1";
2512			reg = <0x0c1b6000 0x600>;
2513			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2514
2515			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2516				 <&gcc GCC_BLSP2_AHB_CLK>;
2517			clock-names = "core", "iface";
2518			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2519			dma-names = "tx", "rx";
2520			pinctrl-names = "default", "sleep";
2521			pinctrl-0 = <&blsp2_i2c2_default>;
2522			pinctrl-1 = <&blsp2_i2c2_sleep>;
2523			clock-frequency = <400000>;
2524
2525			status = "disabled";
2526			#address-cells = <1>;
2527			#size-cells = <0>;
2528		};
2529
2530		blsp2_i2c3: i2c@c1b7000 {
2531			compatible = "qcom,i2c-qup-v2.2.1";
2532			reg = <0x0c1b7000 0x600>;
2533			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2534
2535			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2536				 <&gcc GCC_BLSP2_AHB_CLK>;
2537			clock-names = "core", "iface";
2538			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2539			dma-names = "tx", "rx";
2540			pinctrl-names = "default", "sleep";
2541			pinctrl-0 = <&blsp2_i2c3_default>;
2542			pinctrl-1 = <&blsp2_i2c3_sleep>;
2543			clock-frequency = <400000>;
2544
2545			status = "disabled";
2546			#address-cells = <1>;
2547			#size-cells = <0>;
2548		};
2549
2550		blsp2_i2c4: i2c@c1b8000 {
2551			compatible = "qcom,i2c-qup-v2.2.1";
2552			reg = <0x0c1b8000 0x600>;
2553			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2554
2555			clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2556				 <&gcc GCC_BLSP2_AHB_CLK>;
2557			clock-names = "core", "iface";
2558			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2559			dma-names = "tx", "rx";
2560			pinctrl-names = "default", "sleep";
2561			pinctrl-0 = <&blsp2_i2c4_default>;
2562			pinctrl-1 = <&blsp2_i2c4_sleep>;
2563			clock-frequency = <400000>;
2564
2565			status = "disabled";
2566			#address-cells = <1>;
2567			#size-cells = <0>;
2568		};
2569
2570		blsp2_i2c5: i2c@c1b9000 {
2571			compatible = "qcom,i2c-qup-v2.2.1";
2572			reg = <0x0c1b9000 0x600>;
2573			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2574
2575			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2576				 <&gcc GCC_BLSP2_AHB_CLK>;
2577			clock-names = "core", "iface";
2578			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2579			dma-names = "tx", "rx";
2580			pinctrl-names = "default", "sleep";
2581			pinctrl-0 = <&blsp2_i2c5_default>;
2582			pinctrl-1 = <&blsp2_i2c5_sleep>;
2583			clock-frequency = <400000>;
2584
2585			status = "disabled";
2586			#address-cells = <1>;
2587			#size-cells = <0>;
2588		};
2589
2590		blsp2_i2c6: i2c@c1ba000 {
2591			compatible = "qcom,i2c-qup-v2.2.1";
2592			reg = <0x0c1ba000 0x600>;
2593			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2594
2595			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2596				 <&gcc GCC_BLSP2_AHB_CLK>;
2597			clock-names = "core", "iface";
2598			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2599			dma-names = "tx", "rx";
2600			pinctrl-names = "default", "sleep";
2601			pinctrl-0 = <&blsp2_i2c6_default>;
2602			pinctrl-1 = <&blsp2_i2c6_sleep>;
2603			clock-frequency = <400000>;
2604
2605			status = "disabled";
2606			#address-cells = <1>;
2607			#size-cells = <0>;
2608		};
2609
2610		blsp2_spi1: spi@c1b5000 {
2611			compatible = "qcom,spi-qup-v2.2.1";
2612			reg = <0x0c1b5000 0x600>;
2613			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2614
2615			clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2616				 <&gcc GCC_BLSP2_AHB_CLK>;
2617			clock-names = "core", "iface";
2618			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2619			dma-names = "tx", "rx";
2620			pinctrl-names = "default";
2621			pinctrl-0 = <&blsp2_spi1_default>;
2622
2623			status = "disabled";
2624			#address-cells = <1>;
2625			#size-cells = <0>;
2626		};
2627
2628		blsp2_spi2: spi@c1b6000 {
2629			compatible = "qcom,spi-qup-v2.2.1";
2630			reg = <0x0c1b6000 0x600>;
2631			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2632
2633			clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2634				 <&gcc GCC_BLSP2_AHB_CLK>;
2635			clock-names = "core", "iface";
2636			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2637			dma-names = "tx", "rx";
2638			pinctrl-names = "default";
2639			pinctrl-0 = <&blsp2_spi2_default>;
2640
2641			status = "disabled";
2642			#address-cells = <1>;
2643			#size-cells = <0>;
2644		};
2645
2646		blsp2_spi3: spi@c1b7000 {
2647			compatible = "qcom,spi-qup-v2.2.1";
2648			reg = <0x0c1b7000 0x600>;
2649			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2650
2651			clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2652				 <&gcc GCC_BLSP2_AHB_CLK>;
2653			clock-names = "core", "iface";
2654			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2655			dma-names = "tx", "rx";
2656			pinctrl-names = "default";
2657			pinctrl-0 = <&blsp2_spi3_default>;
2658
2659			status = "disabled";
2660			#address-cells = <1>;
2661			#size-cells = <0>;
2662		};
2663
2664		blsp2_spi4: spi@c1b8000 {
2665			compatible = "qcom,spi-qup-v2.2.1";
2666			reg = <0x0c1b8000 0x600>;
2667			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2668
2669			clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2670				 <&gcc GCC_BLSP2_AHB_CLK>;
2671			clock-names = "core", "iface";
2672			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2673			dma-names = "tx", "rx";
2674			pinctrl-names = "default";
2675			pinctrl-0 = <&blsp2_spi4_default>;
2676
2677			status = "disabled";
2678			#address-cells = <1>;
2679			#size-cells = <0>;
2680		};
2681
2682		blsp2_spi5: spi@c1b9000 {
2683			compatible = "qcom,spi-qup-v2.2.1";
2684			reg = <0x0c1b9000 0x600>;
2685			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2686
2687			clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2688				 <&gcc GCC_BLSP2_AHB_CLK>;
2689			clock-names = "core", "iface";
2690			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2691			dma-names = "tx", "rx";
2692			pinctrl-names = "default";
2693			pinctrl-0 = <&blsp2_spi5_default>;
2694
2695			status = "disabled";
2696			#address-cells = <1>;
2697			#size-cells = <0>;
2698		};
2699
2700		blsp2_spi6: spi@c1ba000 {
2701			compatible = "qcom,spi-qup-v2.2.1";
2702			reg = <0x0c1ba000 0x600>;
2703			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2704
2705			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2706				 <&gcc GCC_BLSP2_AHB_CLK>;
2707			clock-names = "core", "iface";
2708			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2709			dma-names = "tx", "rx";
2710			pinctrl-names = "default";
2711			pinctrl-0 = <&blsp2_spi6_default>;
2712
2713			status = "disabled";
2714			#address-cells = <1>;
2715			#size-cells = <0>;
2716		};
2717
2718		mmcc: clock-controller@c8c0000 {
2719			compatible = "qcom,mmcc-msm8998";
2720			#clock-cells = <1>;
2721			#reset-cells = <1>;
2722			#power-domain-cells = <1>;
2723			reg = <0xc8c0000 0x40000>;
2724
2725			clock-names = "xo",
2726				      "gpll0",
2727				      "dsi0dsi",
2728				      "dsi0byte",
2729				      "dsi1dsi",
2730				      "dsi1byte",
2731				      "hdmipll",
2732				      "dplink",
2733				      "dpvco",
2734				      "gpll0_div";
2735			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2736				 <&gcc GCC_MMSS_GPLL0_CLK>,
2737				 <&mdss_dsi0_phy 1>,
2738				 <&mdss_dsi0_phy 0>,
2739				 <&mdss_dsi1_phy 1>,
2740				 <&mdss_dsi1_phy 0>,
2741				 <0>,
2742				 <0>,
2743				 <0>,
2744				 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
2745		};
2746
2747		mdss: display-subsystem@c900000 {
2748			compatible = "qcom,msm8998-mdss";
2749			reg = <0x0c900000 0x1000>;
2750			reg-names = "mdss";
2751
2752			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2753			interrupt-controller;
2754			#interrupt-cells = <1>;
2755
2756			clocks = <&mmcc MDSS_AHB_CLK>,
2757				 <&mmcc MDSS_AXI_CLK>,
2758				 <&mmcc MDSS_MDP_CLK>;
2759			clock-names = "iface",
2760				      "bus",
2761				      "core";
2762
2763			power-domains = <&mmcc MDSS_GDSC>;
2764			iommus = <&mmss_smmu 0>;
2765
2766			#address-cells = <1>;
2767			#size-cells = <1>;
2768			ranges;
2769
2770			status = "disabled";
2771
2772			mdss_mdp: display-controller@c901000 {
2773				compatible = "qcom,msm8998-dpu";
2774				reg = <0x0c901000 0x8f000>,
2775				      <0x0c9a8e00 0xf0>,
2776				      <0x0c9b0000 0x2008>,
2777				      <0x0c9b8000 0x1040>;
2778				reg-names = "mdp",
2779					    "regdma",
2780					    "vbif",
2781					    "vbif_nrt";
2782
2783				interrupt-parent = <&mdss>;
2784				interrupts = <0>;
2785
2786				clocks = <&mmcc MDSS_AHB_CLK>,
2787					 <&mmcc MDSS_AXI_CLK>,
2788					 <&mmcc MNOC_AHB_CLK>,
2789					 <&mmcc MDSS_MDP_CLK>,
2790					 <&mmcc MDSS_VSYNC_CLK>;
2791				clock-names = "iface",
2792					      "bus",
2793					      "mnoc",
2794					      "core",
2795					      "vsync";
2796
2797				assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2798				assigned-clock-rates = <19200000>;
2799
2800				operating-points-v2 = <&mdp_opp_table>;
2801				power-domains = <&rpmpd MSM8998_VDDMX>;
2802
2803				mdp_opp_table: opp-table {
2804					compatible = "operating-points-v2";
2805
2806					opp-171430000 {
2807						opp-hz = /bits/ 64 <171430000>;
2808						required-opps = <&rpmpd_opp_low_svs>;
2809					};
2810
2811					opp-275000000 {
2812						opp-hz = /bits/ 64 <275000000>;
2813						required-opps = <&rpmpd_opp_svs>;
2814					};
2815
2816					opp-330000000 {
2817						opp-hz = /bits/ 64 <330000000>;
2818						required-opps = <&rpmpd_opp_nom>;
2819					};
2820
2821					opp-412500000 {
2822						opp-hz = /bits/ 64 <412500000>;
2823						required-opps = <&rpmpd_opp_turbo>;
2824					};
2825				};
2826
2827				ports {
2828					#address-cells = <1>;
2829					#size-cells = <0>;
2830
2831					port@0 {
2832						reg = <0>;
2833
2834						dpu_intf1_out: endpoint {
2835							remote-endpoint = <&mdss_dsi0_in>;
2836						};
2837					};
2838
2839					port@1 {
2840						reg = <1>;
2841
2842						dpu_intf2_out: endpoint {
2843							remote-endpoint = <&mdss_dsi1_in>;
2844						};
2845					};
2846				};
2847			};
2848
2849			mdss_dsi0: dsi@c994000 {
2850				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2851				reg = <0x0c994000 0x400>;
2852				reg-names = "dsi_ctrl";
2853
2854				interrupt-parent = <&mdss>;
2855				interrupts = <4>;
2856
2857				clocks = <&mmcc MDSS_BYTE0_CLK>,
2858					 <&mmcc MDSS_BYTE0_INTF_CLK>,
2859					 <&mmcc MDSS_PCLK0_CLK>,
2860					 <&mmcc MDSS_ESC0_CLK>,
2861					 <&mmcc MDSS_AHB_CLK>,
2862					 <&mmcc MDSS_AXI_CLK>;
2863				clock-names = "byte",
2864					      "byte_intf",
2865					      "pixel",
2866					      "core",
2867					      "iface",
2868					      "bus";
2869				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2870						  <&mmcc PCLK0_CLK_SRC>;
2871				assigned-clock-parents = <&mdss_dsi0_phy 0>,
2872							 <&mdss_dsi0_phy 1>;
2873
2874				operating-points-v2 = <&dsi_opp_table>;
2875				power-domains = <&rpmpd MSM8998_VDDCX>;
2876
2877				phys = <&mdss_dsi0_phy>;
2878				phy-names = "dsi";
2879
2880				#address-cells = <1>;
2881				#size-cells = <0>;
2882
2883				status = "disabled";
2884
2885				ports {
2886					#address-cells = <1>;
2887					#size-cells = <0>;
2888
2889					port@0 {
2890						reg = <0>;
2891
2892						mdss_dsi0_in: endpoint {
2893							remote-endpoint = <&dpu_intf1_out>;
2894						};
2895					};
2896
2897					port@1 {
2898						reg = <1>;
2899
2900						mdss_dsi0_out: endpoint {
2901						};
2902					};
2903				};
2904			};
2905
2906			mdss_dsi0_phy: phy@c994400 {
2907				compatible = "qcom,dsi-phy-10nm-8998";
2908				reg = <0x0c994400 0x200>,
2909				      <0x0c994600 0x280>,
2910				      <0x0c994a00 0x1e0>;
2911				reg-names = "dsi_phy",
2912					    "dsi_phy_lane",
2913					    "dsi_pll";
2914
2915				clocks = <&mmcc MDSS_AHB_CLK>,
2916					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2917				clock-names = "iface", "ref";
2918
2919				#clock-cells = <1>;
2920				#phy-cells = <0>;
2921
2922				status = "disabled";
2923			};
2924
2925			mdss_dsi1: dsi@c996000 {
2926				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2927				reg = <0x0c996000 0x400>;
2928				reg-names = "dsi_ctrl";
2929
2930				interrupt-parent = <&mdss>;
2931				interrupts = <5>;
2932
2933				clocks = <&mmcc MDSS_BYTE1_CLK>,
2934					 <&mmcc MDSS_BYTE1_INTF_CLK>,
2935					 <&mmcc MDSS_PCLK1_CLK>,
2936					 <&mmcc MDSS_ESC1_CLK>,
2937					 <&mmcc MDSS_AHB_CLK>,
2938					 <&mmcc MDSS_AXI_CLK>;
2939				clock-names = "byte",
2940					      "byte_intf",
2941					      "pixel",
2942					      "core",
2943					      "iface",
2944					      "bus";
2945				assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2946						  <&mmcc PCLK1_CLK_SRC>;
2947				assigned-clock-parents = <&mdss_dsi1_phy 0>,
2948							 <&mdss_dsi1_phy 1>;
2949
2950				operating-points-v2 = <&dsi_opp_table>;
2951				power-domains = <&rpmpd MSM8998_VDDCX>;
2952
2953				phys = <&mdss_dsi1_phy>;
2954				phy-names = "dsi";
2955
2956				#address-cells = <1>;
2957				#size-cells = <0>;
2958
2959				status = "disabled";
2960
2961				ports {
2962					#address-cells = <1>;
2963					#size-cells = <0>;
2964
2965					port@0 {
2966						reg = <0>;
2967
2968						mdss_dsi1_in: endpoint {
2969							remote-endpoint = <&dpu_intf2_out>;
2970						};
2971					};
2972
2973					port@1 {
2974						reg = <1>;
2975
2976						mdss_dsi1_out: endpoint {
2977						};
2978					};
2979				};
2980			};
2981
2982			mdss_dsi1_phy: phy@c996400 {
2983				compatible = "qcom,dsi-phy-10nm-8998";
2984				reg = <0x0c996400 0x200>,
2985				      <0x0c996600 0x280>,
2986				      <0x0c996a00 0x10e>;
2987				reg-names = "dsi_phy",
2988					    "dsi_phy_lane",
2989					    "dsi_pll";
2990
2991				clocks = <&mmcc MDSS_AHB_CLK>,
2992					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2993				clock-names = "iface",
2994					      "ref";
2995
2996				#clock-cells = <1>;
2997				#phy-cells = <0>;
2998
2999				status = "disabled";
3000			};
3001		};
3002
3003		mmss_smmu: iommu@cd00000 {
3004			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3005			reg = <0x0cd00000 0x40000>;
3006			#iommu-cells = <1>;
3007
3008			clocks = <&mmcc MNOC_AHB_CLK>,
3009				 <&mmcc BIMC_SMMU_AHB_CLK>,
3010				 <&mmcc BIMC_SMMU_AXI_CLK>;
3011			clock-names = "iface-mm",
3012				      "iface-smmu",
3013				      "bus-smmu";
3014
3015			#global-interrupts = <0>;
3016			interrupts =
3017				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3018				<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3019				<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3020				<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3021				<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3022				<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3023				<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3024				<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3025				<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3026				<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3027				<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3028				<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3029				<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3030				<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3031				<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3032				<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3033				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3034				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3035				<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3036				<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3037
3038			power-domains = <&mmcc BIMC_SMMU_GDSC>;
3039		};
3040
3041		remoteproc_adsp: remoteproc@17300000 {
3042			compatible = "qcom,msm8998-adsp-pas";
3043			reg = <0x17300000 0x4040>;
3044
3045			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3046					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3047					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3048					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3049					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3050			interrupt-names = "wdog", "fatal", "ready",
3051					  "handover", "stop-ack";
3052
3053			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3054			clock-names = "xo";
3055
3056			memory-region = <&adsp_mem>;
3057
3058			qcom,smem-states = <&adsp_smp2p_out 0>;
3059			qcom,smem-state-names = "stop";
3060
3061			power-domains = <&rpmpd MSM8998_VDDCX>;
3062			power-domain-names = "cx";
3063
3064			status = "disabled";
3065
3066			glink-edge {
3067				interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3068				label = "lpass";
3069				qcom,remote-pid = <2>;
3070				mboxes = <&apcs_glb 9>;
3071			};
3072		};
3073
3074		apcs_glb: mailbox@17911000 {
3075			compatible = "qcom,msm8998-apcs-hmss-global",
3076				     "qcom,msm8994-apcs-kpss-global";
3077			reg = <0x17911000 0x1000>;
3078
3079			#mbox-cells = <1>;
3080		};
3081
3082		timer@17920000 {
3083			#address-cells = <1>;
3084			#size-cells = <1>;
3085			ranges;
3086			compatible = "arm,armv7-timer-mem";
3087			reg = <0x17920000 0x1000>;
3088
3089			frame@17921000 {
3090				frame-number = <0>;
3091				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3092					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3093				reg = <0x17921000 0x1000>,
3094				      <0x17922000 0x1000>;
3095			};
3096
3097			frame@17923000 {
3098				frame-number = <1>;
3099				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3100				reg = <0x17923000 0x1000>;
3101				status = "disabled";
3102			};
3103
3104			frame@17924000 {
3105				frame-number = <2>;
3106				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3107				reg = <0x17924000 0x1000>;
3108				status = "disabled";
3109			};
3110
3111			frame@17925000 {
3112				frame-number = <3>;
3113				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3114				reg = <0x17925000 0x1000>;
3115				status = "disabled";
3116			};
3117
3118			frame@17926000 {
3119				frame-number = <4>;
3120				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3121				reg = <0x17926000 0x1000>;
3122				status = "disabled";
3123			};
3124
3125			frame@17927000 {
3126				frame-number = <5>;
3127				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3128				reg = <0x17927000 0x1000>;
3129				status = "disabled";
3130			};
3131
3132			frame@17928000 {
3133				frame-number = <6>;
3134				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3135				reg = <0x17928000 0x1000>;
3136				status = "disabled";
3137			};
3138		};
3139
3140		intc: interrupt-controller@17a00000 {
3141			compatible = "arm,gic-v3";
3142			reg = <0x17a00000 0x10000>,       /* GICD */
3143			      <0x17b00000 0x100000>;      /* GICR * 8 */
3144			#interrupt-cells = <3>;
3145			#address-cells = <1>;
3146			#size-cells = <1>;
3147			ranges;
3148			interrupt-controller;
3149			#redistributor-regions = <1>;
3150			redistributor-stride = <0x0 0x20000>;
3151			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3152		};
3153
3154		wifi: wifi@18800000 {
3155			compatible = "qcom,wcn3990-wifi";
3156			status = "disabled";
3157			reg = <0x18800000 0x800000>;
3158			reg-names = "membase";
3159			memory-region = <&wlan_msa_mem>;
3160			clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3161			clock-names = "cxo_ref_clk_pin";
3162			interrupts =
3163				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3164				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3165				<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3166				<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3167				<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3168				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3169				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3170				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3171				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3172				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3173				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3174				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3175			iommus = <&anoc2_smmu 0x1900>,
3176				 <&anoc2_smmu 0x1901>;
3177			qcom,snoc-host-cap-8bit-quirk;
3178		};
3179	};
3180};
3181