1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/power/qcom-rpmpd.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 qcom,msm-id = <292 0x0>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 memory@80000000 { 23 device_type = "memory"; 24 /* We expect the bootloader to fill in the reg */ 25 reg = <0x0 0x80000000 0x0 0x0>; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 hyp_mem: memory@85800000 { 34 reg = <0x0 0x85800000 0x0 0x600000>; 35 no-map; 36 }; 37 38 xbl_mem: memory@85e00000 { 39 reg = <0x0 0x85e00000 0x0 0x100000>; 40 no-map; 41 }; 42 43 smem_mem: smem-mem@86000000 { 44 reg = <0x0 0x86000000 0x0 0x200000>; 45 no-map; 46 }; 47 48 tz_mem: memory@86200000 { 49 reg = <0x0 0x86200000 0x0 0x2d00000>; 50 no-map; 51 }; 52 53 rmtfs_mem: memory@88f00000 { 54 compatible = "qcom,rmtfs-mem"; 55 reg = <0x0 0x88f00000 0x0 0x200000>; 56 no-map; 57 58 qcom,client-id = <1>; 59 qcom,vmid = <15>; 60 }; 61 62 spss_mem: memory@8ab00000 { 63 reg = <0x0 0x8ab00000 0x0 0x700000>; 64 no-map; 65 }; 66 67 adsp_mem: memory@8b200000 { 68 reg = <0x0 0x8b200000 0x0 0x1a00000>; 69 no-map; 70 }; 71 72 mpss_mem: memory@8cc00000 { 73 reg = <0x0 0x8cc00000 0x0 0x7000000>; 74 no-map; 75 }; 76 77 venus_mem: memory@93c00000 { 78 reg = <0x0 0x93c00000 0x0 0x500000>; 79 no-map; 80 }; 81 82 mba_mem: memory@94100000 { 83 reg = <0x0 0x94100000 0x0 0x200000>; 84 no-map; 85 }; 86 87 slpi_mem: memory@94300000 { 88 reg = <0x0 0x94300000 0x0 0xf00000>; 89 no-map; 90 }; 91 92 ipa_fw_mem: memory@95200000 { 93 reg = <0x0 0x95200000 0x0 0x10000>; 94 no-map; 95 }; 96 97 ipa_gsi_mem: memory@95210000 { 98 reg = <0x0 0x95210000 0x0 0x5000>; 99 no-map; 100 }; 101 102 gpu_mem: memory@95600000 { 103 reg = <0x0 0x95600000 0x0 0x100000>; 104 no-map; 105 }; 106 107 wlan_msa_mem: memory@95700000 { 108 reg = <0x0 0x95700000 0x0 0x100000>; 109 no-map; 110 }; 111 112 mdata_mem: mpss-metadata { 113 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 114 size = <0x0 0x4000>; 115 no-map; 116 }; 117 }; 118 119 clocks { 120 xo: xo-board { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <19200000>; 124 clock-output-names = "xo_board"; 125 }; 126 127 sleep_clk: sleep-clk { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <32764>; 131 }; 132 }; 133 134 cpus { 135 #address-cells = <2>; 136 #size-cells = <0>; 137 138 CPU0: cpu@0 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo280"; 141 reg = <0x0 0x0>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1024>; 144 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 145 next-level-cache = <&L2_0>; 146 L2_0: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 }; 151 }; 152 153 CPU1: cpu@1 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo280"; 156 reg = <0x0 0x1>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <1024>; 159 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 160 next-level-cache = <&L2_0>; 161 }; 162 163 CPU2: cpu@2 { 164 device_type = "cpu"; 165 compatible = "qcom,kryo280"; 166 reg = <0x0 0x2>; 167 enable-method = "psci"; 168 capacity-dmips-mhz = <1024>; 169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 170 next-level-cache = <&L2_0>; 171 }; 172 173 CPU3: cpu@3 { 174 device_type = "cpu"; 175 compatible = "qcom,kryo280"; 176 reg = <0x0 0x3>; 177 enable-method = "psci"; 178 capacity-dmips-mhz = <1024>; 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 180 next-level-cache = <&L2_0>; 181 }; 182 183 CPU4: cpu@100 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo280"; 186 reg = <0x0 0x100>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1536>; 189 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 190 next-level-cache = <&L2_1>; 191 L2_1: l2-cache { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-unified; 195 }; 196 }; 197 198 CPU5: cpu@101 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo280"; 201 reg = <0x0 0x101>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1536>; 204 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 205 next-level-cache = <&L2_1>; 206 }; 207 208 CPU6: cpu@102 { 209 device_type = "cpu"; 210 compatible = "qcom,kryo280"; 211 reg = <0x0 0x102>; 212 enable-method = "psci"; 213 capacity-dmips-mhz = <1536>; 214 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 215 next-level-cache = <&L2_1>; 216 }; 217 218 CPU7: cpu@103 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo280"; 221 reg = <0x0 0x103>; 222 enable-method = "psci"; 223 capacity-dmips-mhz = <1536>; 224 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 225 next-level-cache = <&L2_1>; 226 }; 227 228 cpu-map { 229 cluster0 { 230 core0 { 231 cpu = <&CPU0>; 232 }; 233 234 core1 { 235 cpu = <&CPU1>; 236 }; 237 238 core2 { 239 cpu = <&CPU2>; 240 }; 241 242 core3 { 243 cpu = <&CPU3>; 244 }; 245 }; 246 247 cluster1 { 248 core0 { 249 cpu = <&CPU4>; 250 }; 251 252 core1 { 253 cpu = <&CPU5>; 254 }; 255 256 core2 { 257 cpu = <&CPU6>; 258 }; 259 260 core3 { 261 cpu = <&CPU7>; 262 }; 263 }; 264 }; 265 266 idle-states { 267 entry-method = "psci"; 268 269 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 270 compatible = "arm,idle-state"; 271 idle-state-name = "little-retention"; 272 /* CPU Retention (C2D), L2 Active */ 273 arm,psci-suspend-param = <0x00000002>; 274 entry-latency-us = <81>; 275 exit-latency-us = <86>; 276 min-residency-us = <504>; 277 }; 278 279 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "little-power-collapse"; 282 /* CPU + L2 Power Collapse (C3, D4) */ 283 arm,psci-suspend-param = <0x40000003>; 284 entry-latency-us = <814>; 285 exit-latency-us = <4562>; 286 min-residency-us = <9183>; 287 local-timer-stop; 288 }; 289 290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 idle-state-name = "big-retention"; 293 /* CPU Retention (C2D), L2 Active */ 294 arm,psci-suspend-param = <0x00000002>; 295 entry-latency-us = <79>; 296 exit-latency-us = <82>; 297 min-residency-us = <1302>; 298 }; 299 300 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "big-power-collapse"; 303 /* CPU + L2 Power Collapse (C3, D4) */ 304 arm,psci-suspend-param = <0x40000003>; 305 entry-latency-us = <724>; 306 exit-latency-us = <2027>; 307 min-residency-us = <9419>; 308 local-timer-stop; 309 }; 310 }; 311 }; 312 313 firmware { 314 scm { 315 compatible = "qcom,scm-msm8998", "qcom,scm"; 316 }; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 }; 323 324 rpm-glink { 325 compatible = "qcom,glink-rpm"; 326 327 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 328 qcom,rpm-msg-ram = <&rpm_msg_ram>; 329 mboxes = <&apcs_glb 0>; 330 331 rpm_requests: rpm-requests { 332 compatible = "qcom,rpm-msm8998"; 333 qcom,glink-channels = "rpm_requests"; 334 335 rpmcc: clock-controller { 336 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 337 #clock-cells = <1>; 338 }; 339 340 rpmpd: power-controller { 341 compatible = "qcom,msm8998-rpmpd"; 342 #power-domain-cells = <1>; 343 operating-points-v2 = <&rpmpd_opp_table>; 344 345 rpmpd_opp_table: opp-table { 346 compatible = "operating-points-v2"; 347 348 rpmpd_opp_ret: opp1 { 349 opp-level = <RPM_SMD_LEVEL_RETENTION>; 350 }; 351 352 rpmpd_opp_ret_plus: opp2 { 353 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 354 }; 355 356 rpmpd_opp_min_svs: opp3 { 357 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 358 }; 359 360 rpmpd_opp_low_svs: opp4 { 361 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 362 }; 363 364 rpmpd_opp_svs: opp5 { 365 opp-level = <RPM_SMD_LEVEL_SVS>; 366 }; 367 368 rpmpd_opp_svs_plus: opp6 { 369 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 370 }; 371 372 rpmpd_opp_nom: opp7 { 373 opp-level = <RPM_SMD_LEVEL_NOM>; 374 }; 375 376 rpmpd_opp_nom_plus: opp8 { 377 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 378 }; 379 380 rpmpd_opp_turbo: opp9 { 381 opp-level = <RPM_SMD_LEVEL_TURBO>; 382 }; 383 384 rpmpd_opp_turbo_plus: opp10 { 385 opp-level = <RPM_SMD_LEVEL_BINNING>; 386 }; 387 }; 388 }; 389 }; 390 }; 391 392 smem { 393 compatible = "qcom,smem"; 394 memory-region = <&smem_mem>; 395 hwlocks = <&tcsr_mutex 3>; 396 }; 397 398 smp2p-lpass { 399 compatible = "qcom,smp2p"; 400 qcom,smem = <443>, <429>; 401 402 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 403 404 mboxes = <&apcs_glb 10>; 405 406 qcom,local-pid = <0>; 407 qcom,remote-pid = <2>; 408 409 adsp_smp2p_out: master-kernel { 410 qcom,entry-name = "master-kernel"; 411 #qcom,smem-state-cells = <1>; 412 }; 413 414 adsp_smp2p_in: slave-kernel { 415 qcom,entry-name = "slave-kernel"; 416 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 }; 420 }; 421 422 smp2p-mpss { 423 compatible = "qcom,smp2p"; 424 qcom,smem = <435>, <428>; 425 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 426 mboxes = <&apcs_glb 14>; 427 qcom,local-pid = <0>; 428 qcom,remote-pid = <1>; 429 430 modem_smp2p_out: master-kernel { 431 qcom,entry-name = "master-kernel"; 432 #qcom,smem-state-cells = <1>; 433 }; 434 435 modem_smp2p_in: slave-kernel { 436 qcom,entry-name = "slave-kernel"; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 }; 440 }; 441 442 smp2p-slpi { 443 compatible = "qcom,smp2p"; 444 qcom,smem = <481>, <430>; 445 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 446 mboxes = <&apcs_glb 26>; 447 qcom,local-pid = <0>; 448 qcom,remote-pid = <3>; 449 450 slpi_smp2p_out: master-kernel { 451 qcom,entry-name = "master-kernel"; 452 #qcom,smem-state-cells = <1>; 453 }; 454 455 slpi_smp2p_in: slave-kernel { 456 qcom,entry-name = "slave-kernel"; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 }; 460 }; 461 462 thermal-zones { 463 cpu0-thermal { 464 polling-delay-passive = <250>; 465 polling-delay = <1000>; 466 467 thermal-sensors = <&tsens0 1>; 468 469 trips { 470 cpu0_alert0: trip-point0 { 471 temperature = <75000>; 472 hysteresis = <2000>; 473 type = "passive"; 474 }; 475 476 cpu0_crit: cpu-crit { 477 temperature = <110000>; 478 hysteresis = <2000>; 479 type = "critical"; 480 }; 481 }; 482 }; 483 484 cpu1-thermal { 485 polling-delay-passive = <250>; 486 polling-delay = <1000>; 487 488 thermal-sensors = <&tsens0 2>; 489 490 trips { 491 cpu1_alert0: trip-point0 { 492 temperature = <75000>; 493 hysteresis = <2000>; 494 type = "passive"; 495 }; 496 497 cpu1_crit: cpu-crit { 498 temperature = <110000>; 499 hysteresis = <2000>; 500 type = "critical"; 501 }; 502 }; 503 }; 504 505 cpu2-thermal { 506 polling-delay-passive = <250>; 507 polling-delay = <1000>; 508 509 thermal-sensors = <&tsens0 3>; 510 511 trips { 512 cpu2_alert0: trip-point0 { 513 temperature = <75000>; 514 hysteresis = <2000>; 515 type = "passive"; 516 }; 517 518 cpu2_crit: cpu-crit { 519 temperature = <110000>; 520 hysteresis = <2000>; 521 type = "critical"; 522 }; 523 }; 524 }; 525 526 cpu3-thermal { 527 polling-delay-passive = <250>; 528 polling-delay = <1000>; 529 530 thermal-sensors = <&tsens0 4>; 531 532 trips { 533 cpu3_alert0: trip-point0 { 534 temperature = <75000>; 535 hysteresis = <2000>; 536 type = "passive"; 537 }; 538 539 cpu3_crit: cpu-crit { 540 temperature = <110000>; 541 hysteresis = <2000>; 542 type = "critical"; 543 }; 544 }; 545 }; 546 547 cpu4-thermal { 548 polling-delay-passive = <250>; 549 polling-delay = <1000>; 550 551 thermal-sensors = <&tsens0 7>; 552 553 trips { 554 cpu4_alert0: trip-point0 { 555 temperature = <75000>; 556 hysteresis = <2000>; 557 type = "passive"; 558 }; 559 560 cpu4_crit: cpu-crit { 561 temperature = <110000>; 562 hysteresis = <2000>; 563 type = "critical"; 564 }; 565 }; 566 }; 567 568 cpu5-thermal { 569 polling-delay-passive = <250>; 570 polling-delay = <1000>; 571 572 thermal-sensors = <&tsens0 8>; 573 574 trips { 575 cpu5_alert0: trip-point0 { 576 temperature = <75000>; 577 hysteresis = <2000>; 578 type = "passive"; 579 }; 580 581 cpu5_crit: cpu-crit { 582 temperature = <110000>; 583 hysteresis = <2000>; 584 type = "critical"; 585 }; 586 }; 587 }; 588 589 cpu6-thermal { 590 polling-delay-passive = <250>; 591 polling-delay = <1000>; 592 593 thermal-sensors = <&tsens0 9>; 594 595 trips { 596 cpu6_alert0: trip-point0 { 597 temperature = <75000>; 598 hysteresis = <2000>; 599 type = "passive"; 600 }; 601 602 cpu6_crit: cpu-crit { 603 temperature = <110000>; 604 hysteresis = <2000>; 605 type = "critical"; 606 }; 607 }; 608 }; 609 610 cpu7-thermal { 611 polling-delay-passive = <250>; 612 polling-delay = <1000>; 613 614 thermal-sensors = <&tsens0 10>; 615 616 trips { 617 cpu7_alert0: trip-point0 { 618 temperature = <75000>; 619 hysteresis = <2000>; 620 type = "passive"; 621 }; 622 623 cpu7_crit: cpu-crit { 624 temperature = <110000>; 625 hysteresis = <2000>; 626 type = "critical"; 627 }; 628 }; 629 }; 630 631 gpu-bottom-thermal { 632 polling-delay-passive = <250>; 633 polling-delay = <1000>; 634 635 thermal-sensors = <&tsens0 12>; 636 637 trips { 638 gpu1_alert0: trip-point0 { 639 temperature = <90000>; 640 hysteresis = <2000>; 641 type = "hot"; 642 }; 643 }; 644 }; 645 646 gpu-top-thermal { 647 polling-delay-passive = <250>; 648 polling-delay = <1000>; 649 650 thermal-sensors = <&tsens0 13>; 651 652 trips { 653 gpu2_alert0: trip-point0 { 654 temperature = <90000>; 655 hysteresis = <2000>; 656 type = "hot"; 657 }; 658 }; 659 }; 660 661 clust0-mhm-thermal { 662 polling-delay-passive = <250>; 663 polling-delay = <1000>; 664 665 thermal-sensors = <&tsens0 5>; 666 667 trips { 668 cluster0_mhm_alert0: trip-point0 { 669 temperature = <90000>; 670 hysteresis = <2000>; 671 type = "hot"; 672 }; 673 }; 674 }; 675 676 clust1-mhm-thermal { 677 polling-delay-passive = <250>; 678 polling-delay = <1000>; 679 680 thermal-sensors = <&tsens0 6>; 681 682 trips { 683 cluster1_mhm_alert0: trip-point0 { 684 temperature = <90000>; 685 hysteresis = <2000>; 686 type = "hot"; 687 }; 688 }; 689 }; 690 691 cluster1-l2-thermal { 692 polling-delay-passive = <250>; 693 polling-delay = <1000>; 694 695 thermal-sensors = <&tsens0 11>; 696 697 trips { 698 cluster1_l2_alert0: trip-point0 { 699 temperature = <90000>; 700 hysteresis = <2000>; 701 type = "hot"; 702 }; 703 }; 704 }; 705 706 modem-thermal { 707 polling-delay-passive = <250>; 708 polling-delay = <1000>; 709 710 thermal-sensors = <&tsens1 1>; 711 712 trips { 713 modem_alert0: trip-point0 { 714 temperature = <90000>; 715 hysteresis = <2000>; 716 type = "hot"; 717 }; 718 }; 719 }; 720 721 mem-thermal { 722 polling-delay-passive = <250>; 723 polling-delay = <1000>; 724 725 thermal-sensors = <&tsens1 2>; 726 727 trips { 728 mem_alert0: trip-point0 { 729 temperature = <90000>; 730 hysteresis = <2000>; 731 type = "hot"; 732 }; 733 }; 734 }; 735 736 wlan-thermal { 737 polling-delay-passive = <250>; 738 polling-delay = <1000>; 739 740 thermal-sensors = <&tsens1 3>; 741 742 trips { 743 wlan_alert0: trip-point0 { 744 temperature = <90000>; 745 hysteresis = <2000>; 746 type = "hot"; 747 }; 748 }; 749 }; 750 751 q6-dsp-thermal { 752 polling-delay-passive = <250>; 753 polling-delay = <1000>; 754 755 thermal-sensors = <&tsens1 4>; 756 757 trips { 758 q6_dsp_alert0: trip-point0 { 759 temperature = <90000>; 760 hysteresis = <2000>; 761 type = "hot"; 762 }; 763 }; 764 }; 765 766 camera-thermal { 767 polling-delay-passive = <250>; 768 polling-delay = <1000>; 769 770 thermal-sensors = <&tsens1 5>; 771 772 trips { 773 camera_alert0: trip-point0 { 774 temperature = <90000>; 775 hysteresis = <2000>; 776 type = "hot"; 777 }; 778 }; 779 }; 780 781 multimedia-thermal { 782 polling-delay-passive = <250>; 783 polling-delay = <1000>; 784 785 thermal-sensors = <&tsens1 6>; 786 787 trips { 788 multimedia_alert0: trip-point0 { 789 temperature = <90000>; 790 hysteresis = <2000>; 791 type = "hot"; 792 }; 793 }; 794 }; 795 }; 796 797 timer { 798 compatible = "arm,armv8-timer"; 799 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 800 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 801 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 802 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 803 }; 804 805 soc: soc { 806 #address-cells = <1>; 807 #size-cells = <1>; 808 ranges = <0 0 0 0xffffffff>; 809 compatible = "simple-bus"; 810 811 gcc: clock-controller@100000 { 812 compatible = "qcom,gcc-msm8998"; 813 #clock-cells = <1>; 814 #reset-cells = <1>; 815 #power-domain-cells = <1>; 816 reg = <0x00100000 0xb0000>; 817 818 clock-names = "xo", "sleep_clk"; 819 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 820 821 /* 822 * The hypervisor typically configures the memory region where these clocks 823 * reside as read-only for the HLOS. If the HLOS tried to enable or disable 824 * these clocks on a device with such configuration (e.g. because they are 825 * enabled but unused during boot-up), the device will most likely decide 826 * to reboot. 827 * In light of that, we are conservative here and we list all such clocks 828 * as protected. The board dts (or a user-supplied dts) can override the 829 * list of protected clocks if it differs from the norm, and it is in fact 830 * desired for the HLOS to manage these clocks 831 */ 832 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>, 833 <SSC_XO>, 834 <SSC_CNOC_AHBS_CLK>; 835 }; 836 837 rpm_msg_ram: sram@778000 { 838 compatible = "qcom,rpm-msg-ram"; 839 reg = <0x00778000 0x7000>; 840 }; 841 842 qfprom: qfprom@784000 { 843 compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 844 reg = <0x00784000 0x621c>; 845 #address-cells = <1>; 846 #size-cells = <1>; 847 848 qusb2_hstx_trim: hstx-trim@23a { 849 reg = <0x23a 0x1>; 850 bits = <0 4>; 851 }; 852 }; 853 854 tsens0: thermal@10ab000 { 855 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 856 reg = <0x010ab000 0x1000>, /* TM */ 857 <0x010aa000 0x1000>; /* SROT */ 858 #qcom,sensors = <14>; 859 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "uplow", "critical"; 862 #thermal-sensor-cells = <1>; 863 }; 864 865 tsens1: thermal@10ae000 { 866 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 867 reg = <0x010ae000 0x1000>, /* TM */ 868 <0x010ad000 0x1000>; /* SROT */ 869 #qcom,sensors = <8>; 870 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 872 interrupt-names = "uplow", "critical"; 873 #thermal-sensor-cells = <1>; 874 }; 875 876 anoc1_smmu: iommu@1680000 { 877 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 878 reg = <0x01680000 0x10000>; 879 #iommu-cells = <1>; 880 881 #global-interrupts = <0>; 882 interrupts = 883 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 884 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 885 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 886 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 887 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 888 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 889 }; 890 891 anoc2_smmu: iommu@16c0000 { 892 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 893 reg = <0x016c0000 0x40000>; 894 #iommu-cells = <1>; 895 896 #global-interrupts = <0>; 897 interrupts = 898 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 899 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 900 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 901 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 902 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 903 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 904 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 905 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 906 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 907 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 908 }; 909 910 pcie0: pci@1c00000 { 911 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; 912 reg = <0x01c00000 0x2000>, 913 <0x1b000000 0xf1d>, 914 <0x1b000f20 0xa8>, 915 <0x1b100000 0x100000>; 916 reg-names = "parf", "dbi", "elbi", "config"; 917 device_type = "pci"; 918 linux,pci-domain = <0>; 919 bus-range = <0x00 0xff>; 920 #address-cells = <3>; 921 #size-cells = <2>; 922 num-lanes = <1>; 923 phys = <&pciephy>; 924 phy-names = "pciephy"; 925 status = "disabled"; 926 927 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 928 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 929 930 #interrupt-cells = <1>; 931 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 932 interrupt-names = "msi"; 933 interrupt-map-mask = <0 0 0 0x7>; 934 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 935 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 936 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 937 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 938 939 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 940 <&gcc GCC_PCIE_0_AUX_CLK>, 941 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 942 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 943 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 944 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; 945 946 power-domains = <&gcc PCIE_0_GDSC>; 947 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 948 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 949 }; 950 951 pcie_phy: phy@1c06000 { 952 compatible = "qcom,msm8998-qmp-pcie-phy"; 953 reg = <0x01c06000 0x18c>; 954 #address-cells = <1>; 955 #size-cells = <1>; 956 status = "disabled"; 957 ranges; 958 959 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 960 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 961 <&gcc GCC_PCIE_CLKREF_CLK>; 962 clock-names = "aux", "cfg_ahb", "ref"; 963 964 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 965 reset-names = "phy", "common"; 966 967 vdda-phy-supply = <&vreg_l1a_0p875>; 968 vdda-pll-supply = <&vreg_l2a_1p2>; 969 970 pciephy: phy@1c06800 { 971 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 972 #phy-cells = <0>; 973 974 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 975 clock-names = "pipe0"; 976 clock-output-names = "pcie_0_pipe_clk_src"; 977 #clock-cells = <0>; 978 }; 979 }; 980 981 ufshc: ufshc@1da4000 { 982 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 983 reg = <0x01da4000 0x2500>; 984 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 985 phys = <&ufsphy_lanes>; 986 phy-names = "ufsphy"; 987 lanes-per-direction = <2>; 988 power-domains = <&gcc UFS_GDSC>; 989 status = "disabled"; 990 #reset-cells = <1>; 991 992 clock-names = 993 "core_clk", 994 "bus_aggr_clk", 995 "iface_clk", 996 "core_clk_unipro", 997 "ref_clk", 998 "tx_lane0_sync_clk", 999 "rx_lane0_sync_clk", 1000 "rx_lane1_sync_clk"; 1001 clocks = 1002 <&gcc GCC_UFS_AXI_CLK>, 1003 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1004 <&gcc GCC_UFS_AHB_CLK>, 1005 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1006 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1007 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1008 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1009 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1010 freq-table-hz = 1011 <50000000 200000000>, 1012 <0 0>, 1013 <0 0>, 1014 <37500000 150000000>, 1015 <0 0>, 1016 <0 0>, 1017 <0 0>, 1018 <0 0>; 1019 1020 resets = <&gcc GCC_UFS_BCR>; 1021 reset-names = "rst"; 1022 }; 1023 1024 ufsphy: phy@1da7000 { 1025 compatible = "qcom,msm8998-qmp-ufs-phy"; 1026 reg = <0x01da7000 0x18c>; 1027 #address-cells = <1>; 1028 #size-cells = <1>; 1029 status = "disabled"; 1030 ranges; 1031 1032 clock-names = 1033 "ref", 1034 "ref_aux"; 1035 clocks = 1036 <&gcc GCC_UFS_CLKREF_CLK>, 1037 <&gcc GCC_UFS_PHY_AUX_CLK>; 1038 1039 reset-names = "ufsphy"; 1040 resets = <&ufshc 0>; 1041 1042 ufsphy_lanes: phy@1da7400 { 1043 reg = <0x01da7400 0x128>, 1044 <0x01da7600 0x1fc>, 1045 <0x01da7c00 0x1dc>, 1046 <0x01da7800 0x128>, 1047 <0x01da7a00 0x1fc>; 1048 #phy-cells = <0>; 1049 }; 1050 }; 1051 1052 tcsr_mutex: hwlock@1f40000 { 1053 compatible = "qcom,tcsr-mutex"; 1054 reg = <0x01f40000 0x20000>; 1055 #hwlock-cells = <1>; 1056 }; 1057 1058 tcsr_regs_1: syscon@1f60000 { 1059 compatible = "qcom,msm8998-tcsr", "syscon"; 1060 reg = <0x01f60000 0x20000>; 1061 }; 1062 1063 tlmm: pinctrl@3400000 { 1064 compatible = "qcom,msm8998-pinctrl"; 1065 reg = <0x03400000 0xc00000>; 1066 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1067 gpio-ranges = <&tlmm 0 0 150>; 1068 gpio-controller; 1069 #gpio-cells = <2>; 1070 interrupt-controller; 1071 #interrupt-cells = <2>; 1072 1073 sdc2_on: sdc2-on-state { 1074 clk-pins { 1075 pins = "sdc2_clk"; 1076 drive-strength = <16>; 1077 bias-disable; 1078 }; 1079 1080 cmd-pins { 1081 pins = "sdc2_cmd"; 1082 drive-strength = <10>; 1083 bias-pull-up; 1084 }; 1085 1086 data-pins { 1087 pins = "sdc2_data"; 1088 drive-strength = <10>; 1089 bias-pull-up; 1090 }; 1091 }; 1092 1093 sdc2_off: sdc2-off-state { 1094 clk-pins { 1095 pins = "sdc2_clk"; 1096 drive-strength = <2>; 1097 bias-disable; 1098 }; 1099 1100 cmd-pins { 1101 pins = "sdc2_cmd"; 1102 drive-strength = <2>; 1103 bias-pull-up; 1104 }; 1105 1106 data-pins { 1107 pins = "sdc2_data"; 1108 drive-strength = <2>; 1109 bias-pull-up; 1110 }; 1111 }; 1112 1113 sdc2_cd: sdc2-cd-state { 1114 pins = "gpio95"; 1115 function = "gpio"; 1116 bias-pull-up; 1117 drive-strength = <2>; 1118 }; 1119 1120 blsp1_uart3_on: blsp1-uart3-on-state { 1121 tx-pins { 1122 pins = "gpio45"; 1123 function = "blsp_uart3_a"; 1124 drive-strength = <2>; 1125 bias-disable; 1126 }; 1127 1128 rx-pins { 1129 pins = "gpio46"; 1130 function = "blsp_uart3_a"; 1131 drive-strength = <2>; 1132 bias-disable; 1133 }; 1134 1135 cts-pins { 1136 pins = "gpio47"; 1137 function = "blsp_uart3_a"; 1138 drive-strength = <2>; 1139 bias-disable; 1140 }; 1141 1142 rfr-pins { 1143 pins = "gpio48"; 1144 function = "blsp_uart3_a"; 1145 drive-strength = <2>; 1146 bias-disable; 1147 }; 1148 }; 1149 1150 blsp1_i2c1_default: blsp1-i2c1-default-state { 1151 pins = "gpio2", "gpio3"; 1152 function = "blsp_i2c1"; 1153 drive-strength = <2>; 1154 bias-disable; 1155 }; 1156 1157 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { 1158 pins = "gpio2", "gpio3"; 1159 function = "blsp_i2c1"; 1160 drive-strength = <2>; 1161 bias-pull-up; 1162 }; 1163 1164 blsp1_i2c2_default: blsp1-i2c2-default-state { 1165 pins = "gpio32", "gpio33"; 1166 function = "blsp_i2c2"; 1167 drive-strength = <2>; 1168 bias-disable; 1169 }; 1170 1171 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { 1172 pins = "gpio32", "gpio33"; 1173 function = "blsp_i2c2"; 1174 drive-strength = <2>; 1175 bias-pull-up; 1176 }; 1177 1178 blsp1_i2c3_default: blsp1-i2c3-default-state { 1179 pins = "gpio47", "gpio48"; 1180 function = "blsp_i2c3"; 1181 drive-strength = <2>; 1182 bias-disable; 1183 }; 1184 1185 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1186 pins = "gpio47", "gpio48"; 1187 function = "blsp_i2c3"; 1188 drive-strength = <2>; 1189 bias-pull-up; 1190 }; 1191 1192 blsp1_i2c4_default: blsp1-i2c4-default-state { 1193 pins = "gpio10", "gpio11"; 1194 function = "blsp_i2c4"; 1195 drive-strength = <2>; 1196 bias-disable; 1197 }; 1198 1199 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 1200 pins = "gpio10", "gpio11"; 1201 function = "blsp_i2c4"; 1202 drive-strength = <2>; 1203 bias-pull-up; 1204 }; 1205 1206 blsp1_i2c5_default: blsp1-i2c5-default-state { 1207 pins = "gpio87", "gpio88"; 1208 function = "blsp_i2c5"; 1209 drive-strength = <2>; 1210 bias-disable; 1211 }; 1212 1213 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { 1214 pins = "gpio87", "gpio88"; 1215 function = "blsp_i2c5"; 1216 drive-strength = <2>; 1217 bias-pull-up; 1218 }; 1219 1220 blsp1_i2c6_default: blsp1-i2c6-default-state { 1221 pins = "gpio43", "gpio44"; 1222 function = "blsp_i2c6"; 1223 drive-strength = <2>; 1224 bias-disable; 1225 }; 1226 1227 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1228 pins = "gpio43", "gpio44"; 1229 function = "blsp_i2c6"; 1230 drive-strength = <2>; 1231 bias-pull-up; 1232 }; 1233 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1234 blsp2_i2c1_default: blsp2-i2c1-default-state { 1235 pins = "gpio55", "gpio56"; 1236 function = "blsp_i2c7"; 1237 drive-strength = <2>; 1238 bias-disable; 1239 }; 1240 1241 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1242 pins = "gpio55", "gpio56"; 1243 function = "blsp_i2c7"; 1244 drive-strength = <2>; 1245 bias-pull-up; 1246 }; 1247 1248 blsp2_i2c2_default: blsp2-i2c2-default-state { 1249 pins = "gpio6", "gpio7"; 1250 function = "blsp_i2c8"; 1251 drive-strength = <2>; 1252 bias-disable; 1253 }; 1254 1255 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1256 pins = "gpio6", "gpio7"; 1257 function = "blsp_i2c8"; 1258 drive-strength = <2>; 1259 bias-pull-up; 1260 }; 1261 1262 blsp2_i2c3_default: blsp2-i2c3-default-state { 1263 pins = "gpio51", "gpio52"; 1264 function = "blsp_i2c9"; 1265 drive-strength = <2>; 1266 bias-disable; 1267 }; 1268 1269 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1270 pins = "gpio51", "gpio52"; 1271 function = "blsp_i2c9"; 1272 drive-strength = <2>; 1273 bias-pull-up; 1274 }; 1275 1276 blsp2_i2c4_default: blsp2-i2c4-default-state { 1277 pins = "gpio67", "gpio68"; 1278 function = "blsp_i2c10"; 1279 drive-strength = <2>; 1280 bias-disable; 1281 }; 1282 1283 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 1284 pins = "gpio67", "gpio68"; 1285 function = "blsp_i2c10"; 1286 drive-strength = <2>; 1287 bias-pull-up; 1288 }; 1289 1290 blsp2_i2c5_default: blsp2-i2c5-default-state { 1291 pins = "gpio60", "gpio61"; 1292 function = "blsp_i2c11"; 1293 drive-strength = <2>; 1294 bias-disable; 1295 }; 1296 1297 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1298 pins = "gpio60", "gpio61"; 1299 function = "blsp_i2c11"; 1300 drive-strength = <2>; 1301 bias-pull-up; 1302 }; 1303 1304 blsp2_i2c6_default: blsp2-i2c6-default-state { 1305 pins = "gpio83", "gpio84"; 1306 function = "blsp_i2c12"; 1307 drive-strength = <2>; 1308 bias-disable; 1309 }; 1310 1311 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1312 pins = "gpio83", "gpio84"; 1313 function = "blsp_i2c12"; 1314 drive-strength = <2>; 1315 bias-pull-up; 1316 }; 1317 }; 1318 1319 remoteproc_mss: remoteproc@4080000 { 1320 compatible = "qcom,msm8998-mss-pil"; 1321 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1322 reg-names = "qdsp6", "rmb"; 1323 1324 interrupts-extended = 1325 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1326 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1327 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1328 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1329 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1330 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1331 interrupt-names = "wdog", "fatal", "ready", 1332 "handover", "stop-ack", 1333 "shutdown-ack"; 1334 1335 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1336 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1337 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1338 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1339 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1340 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1341 <&rpmcc RPM_SMD_QDSS_CLK>, 1342 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1343 clock-names = "iface", "bus", "mem", "gpll0_mss", 1344 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1345 1346 qcom,smem-states = <&modem_smp2p_out 0>; 1347 qcom,smem-state-names = "stop"; 1348 1349 resets = <&gcc GCC_MSS_RESTART>; 1350 reset-names = "mss_restart"; 1351 1352 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1353 1354 power-domains = <&rpmpd MSM8998_VDDCX>, 1355 <&rpmpd MSM8998_VDDMX>; 1356 power-domain-names = "cx", "mx"; 1357 1358 status = "disabled"; 1359 1360 mba { 1361 memory-region = <&mba_mem>; 1362 }; 1363 1364 mpss { 1365 memory-region = <&mpss_mem>; 1366 }; 1367 1368 metadata { 1369 memory-region = <&mdata_mem>; 1370 }; 1371 1372 glink-edge { 1373 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1374 label = "modem"; 1375 qcom,remote-pid = <1>; 1376 mboxes = <&apcs_glb 15>; 1377 }; 1378 }; 1379 1380 adreno_gpu: gpu@5000000 { 1381 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1382 reg = <0x05000000 0x40000>; 1383 reg-names = "kgsl_3d0_reg_memory"; 1384 1385 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1386 <&gpucc RBBMTIMER_CLK>, 1387 <&gcc GCC_BIMC_GFX_CLK>, 1388 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1389 <&gpucc RBCPR_CLK>, 1390 <&gpucc GFX3D_CLK>; 1391 clock-names = "iface", 1392 "rbbmtimer", 1393 "mem", 1394 "mem_iface", 1395 "rbcpr", 1396 "core"; 1397 1398 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1399 iommus = <&adreno_smmu 0>; 1400 operating-points-v2 = <&gpu_opp_table>; 1401 power-domains = <&rpmpd MSM8998_VDDMX>; 1402 status = "disabled"; 1403 1404 gpu_opp_table: opp-table { 1405 compatible = "operating-points-v2"; 1406 opp-710000097 { 1407 opp-hz = /bits/ 64 <710000097>; 1408 opp-level = <RPM_SMD_LEVEL_TURBO>; 1409 opp-supported-hw = <0xff>; 1410 }; 1411 1412 opp-670000048 { 1413 opp-hz = /bits/ 64 <670000048>; 1414 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1415 opp-supported-hw = <0xff>; 1416 }; 1417 1418 opp-596000097 { 1419 opp-hz = /bits/ 64 <596000097>; 1420 opp-level = <RPM_SMD_LEVEL_NOM>; 1421 opp-supported-hw = <0xff>; 1422 }; 1423 1424 opp-515000097 { 1425 opp-hz = /bits/ 64 <515000097>; 1426 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1427 opp-supported-hw = <0xff>; 1428 }; 1429 1430 opp-414000000 { 1431 opp-hz = /bits/ 64 <414000000>; 1432 opp-level = <RPM_SMD_LEVEL_SVS>; 1433 opp-supported-hw = <0xff>; 1434 }; 1435 1436 opp-342000000 { 1437 opp-hz = /bits/ 64 <342000000>; 1438 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1439 opp-supported-hw = <0xff>; 1440 }; 1441 1442 opp-257000000 { 1443 opp-hz = /bits/ 64 <257000000>; 1444 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1445 opp-supported-hw = <0xff>; 1446 }; 1447 }; 1448 }; 1449 1450 adreno_smmu: iommu@5040000 { 1451 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1452 reg = <0x05040000 0x10000>; 1453 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1454 <&gcc GCC_BIMC_GFX_CLK>, 1455 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1456 clock-names = "iface", "mem", "mem_iface"; 1457 1458 #global-interrupts = <0>; 1459 #iommu-cells = <1>; 1460 interrupts = 1461 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1464 /* 1465 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1466 * GPU-CX for SMMU but we need both of them up for Adreno. 1467 * Contemporarily, we also need to manage the VDDMX rpmpd 1468 * domain in the Adreno driver. 1469 * Enable GPU CX/GX GDSCs here so that we can manage the 1470 * SoC VDDMX RPM Power Domain in the Adreno driver. 1471 */ 1472 power-domains = <&gpucc GPU_GX_GDSC>; 1473 status = "disabled"; 1474 }; 1475 1476 gpucc: clock-controller@5065000 { 1477 compatible = "qcom,msm8998-gpucc"; 1478 #clock-cells = <1>; 1479 #reset-cells = <1>; 1480 #power-domain-cells = <1>; 1481 reg = <0x05065000 0x9000>; 1482 1483 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1484 <&gcc GPLL0_OUT_MAIN>; 1485 clock-names = "xo", 1486 "gpll0"; 1487 }; 1488 1489 remoteproc_slpi: remoteproc@5800000 { 1490 compatible = "qcom,msm8998-slpi-pas"; 1491 reg = <0x05800000 0x4040>; 1492 1493 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1494 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1495 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1496 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1497 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1498 interrupt-names = "wdog", "fatal", "ready", 1499 "handover", "stop-ack"; 1500 1501 px-supply = <&vreg_lvs2a_1p8>; 1502 1503 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1504 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1505 clock-names = "xo", "aggre2"; 1506 1507 memory-region = <&slpi_mem>; 1508 1509 qcom,smem-states = <&slpi_smp2p_out 0>; 1510 qcom,smem-state-names = "stop"; 1511 1512 power-domains = <&rpmpd MSM8998_SSCCX>; 1513 power-domain-names = "ssc_cx"; 1514 1515 status = "disabled"; 1516 1517 glink-edge { 1518 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1519 label = "dsps"; 1520 qcom,remote-pid = <3>; 1521 mboxes = <&apcs_glb 27>; 1522 }; 1523 }; 1524 1525 stm: stm@6002000 { 1526 compatible = "arm,coresight-stm", "arm,primecell"; 1527 reg = <0x06002000 0x1000>, 1528 <0x16280000 0x180000>; 1529 reg-names = "stm-base", "stm-stimulus-base"; 1530 status = "disabled"; 1531 1532 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1533 clock-names = "apb_pclk", "atclk"; 1534 1535 out-ports { 1536 port { 1537 stm_out: endpoint { 1538 remote-endpoint = <&funnel0_in7>; 1539 }; 1540 }; 1541 }; 1542 }; 1543 1544 funnel1: funnel@6041000 { 1545 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1546 reg = <0x06041000 0x1000>; 1547 status = "disabled"; 1548 1549 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1550 clock-names = "apb_pclk", "atclk"; 1551 1552 out-ports { 1553 port { 1554 funnel0_out: endpoint { 1555 remote-endpoint = 1556 <&merge_funnel_in0>; 1557 }; 1558 }; 1559 }; 1560 1561 in-ports { 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 1565 port@7 { 1566 reg = <7>; 1567 funnel0_in7: endpoint { 1568 remote-endpoint = <&stm_out>; 1569 }; 1570 }; 1571 }; 1572 }; 1573 1574 funnel2: funnel@6042000 { 1575 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1576 reg = <0x06042000 0x1000>; 1577 status = "disabled"; 1578 1579 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1580 clock-names = "apb_pclk", "atclk"; 1581 1582 out-ports { 1583 port { 1584 funnel1_out: endpoint { 1585 remote-endpoint = 1586 <&merge_funnel_in1>; 1587 }; 1588 }; 1589 }; 1590 1591 in-ports { 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 1595 port@6 { 1596 reg = <6>; 1597 funnel1_in6: endpoint { 1598 remote-endpoint = 1599 <&apss_merge_funnel_out>; 1600 }; 1601 }; 1602 }; 1603 }; 1604 1605 funnel3: funnel@6045000 { 1606 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1607 reg = <0x06045000 0x1000>; 1608 status = "disabled"; 1609 1610 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1611 clock-names = "apb_pclk", "atclk"; 1612 1613 out-ports { 1614 port { 1615 merge_funnel_out: endpoint { 1616 remote-endpoint = 1617 <&etf_in>; 1618 }; 1619 }; 1620 }; 1621 1622 in-ports { 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 1626 port@0 { 1627 reg = <0>; 1628 merge_funnel_in0: endpoint { 1629 remote-endpoint = 1630 <&funnel0_out>; 1631 }; 1632 }; 1633 1634 port@1 { 1635 reg = <1>; 1636 merge_funnel_in1: endpoint { 1637 remote-endpoint = 1638 <&funnel1_out>; 1639 }; 1640 }; 1641 }; 1642 }; 1643 1644 replicator1: replicator@6046000 { 1645 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1646 reg = <0x06046000 0x1000>; 1647 status = "disabled"; 1648 1649 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1650 clock-names = "apb_pclk", "atclk"; 1651 1652 out-ports { 1653 port { 1654 replicator_out: endpoint { 1655 remote-endpoint = <&etr_in>; 1656 }; 1657 }; 1658 }; 1659 1660 in-ports { 1661 port { 1662 replicator_in: endpoint { 1663 remote-endpoint = <&etf_out>; 1664 }; 1665 }; 1666 }; 1667 }; 1668 1669 etf: etf@6047000 { 1670 compatible = "arm,coresight-tmc", "arm,primecell"; 1671 reg = <0x06047000 0x1000>; 1672 status = "disabled"; 1673 1674 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1675 clock-names = "apb_pclk", "atclk"; 1676 1677 out-ports { 1678 port { 1679 etf_out: endpoint { 1680 remote-endpoint = 1681 <&replicator_in>; 1682 }; 1683 }; 1684 }; 1685 1686 in-ports { 1687 port { 1688 etf_in: endpoint { 1689 remote-endpoint = 1690 <&merge_funnel_out>; 1691 }; 1692 }; 1693 }; 1694 }; 1695 1696 etr: etr@6048000 { 1697 compatible = "arm,coresight-tmc", "arm,primecell"; 1698 reg = <0x06048000 0x1000>; 1699 status = "disabled"; 1700 1701 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1702 clock-names = "apb_pclk", "atclk"; 1703 arm,scatter-gather; 1704 1705 in-ports { 1706 port { 1707 etr_in: endpoint { 1708 remote-endpoint = 1709 <&replicator_out>; 1710 }; 1711 }; 1712 }; 1713 }; 1714 1715 etm1: etm@7840000 { 1716 compatible = "arm,coresight-etm4x", "arm,primecell"; 1717 reg = <0x07840000 0x1000>; 1718 status = "disabled"; 1719 1720 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1721 clock-names = "apb_pclk", "atclk"; 1722 1723 cpu = <&CPU0>; 1724 1725 out-ports { 1726 port { 1727 etm0_out: endpoint { 1728 remote-endpoint = 1729 <&apss_funnel_in0>; 1730 }; 1731 }; 1732 }; 1733 }; 1734 1735 etm2: etm@7940000 { 1736 compatible = "arm,coresight-etm4x", "arm,primecell"; 1737 reg = <0x07940000 0x1000>; 1738 status = "disabled"; 1739 1740 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1741 clock-names = "apb_pclk", "atclk"; 1742 1743 cpu = <&CPU1>; 1744 1745 out-ports { 1746 port { 1747 etm1_out: endpoint { 1748 remote-endpoint = 1749 <&apss_funnel_in1>; 1750 }; 1751 }; 1752 }; 1753 }; 1754 1755 etm3: etm@7a40000 { 1756 compatible = "arm,coresight-etm4x", "arm,primecell"; 1757 reg = <0x07a40000 0x1000>; 1758 status = "disabled"; 1759 1760 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1761 clock-names = "apb_pclk", "atclk"; 1762 1763 cpu = <&CPU2>; 1764 1765 out-ports { 1766 port { 1767 etm2_out: endpoint { 1768 remote-endpoint = 1769 <&apss_funnel_in2>; 1770 }; 1771 }; 1772 }; 1773 }; 1774 1775 etm4: etm@7b40000 { 1776 compatible = "arm,coresight-etm4x", "arm,primecell"; 1777 reg = <0x07b40000 0x1000>; 1778 status = "disabled"; 1779 1780 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1781 clock-names = "apb_pclk", "atclk"; 1782 1783 cpu = <&CPU3>; 1784 1785 out-ports { 1786 port { 1787 etm3_out: endpoint { 1788 remote-endpoint = 1789 <&apss_funnel_in3>; 1790 }; 1791 }; 1792 }; 1793 }; 1794 1795 funnel4: funnel@7b60000 { /* APSS Funnel */ 1796 compatible = "arm,coresight-etm4x", "arm,primecell"; 1797 reg = <0x07b60000 0x1000>; 1798 status = "disabled"; 1799 1800 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1801 clock-names = "apb_pclk", "atclk"; 1802 1803 out-ports { 1804 port { 1805 apss_funnel_out: endpoint { 1806 remote-endpoint = 1807 <&apss_merge_funnel_in>; 1808 }; 1809 }; 1810 }; 1811 1812 in-ports { 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 1816 port@0 { 1817 reg = <0>; 1818 apss_funnel_in0: endpoint { 1819 remote-endpoint = 1820 <&etm0_out>; 1821 }; 1822 }; 1823 1824 port@1 { 1825 reg = <1>; 1826 apss_funnel_in1: endpoint { 1827 remote-endpoint = 1828 <&etm1_out>; 1829 }; 1830 }; 1831 1832 port@2 { 1833 reg = <2>; 1834 apss_funnel_in2: endpoint { 1835 remote-endpoint = 1836 <&etm2_out>; 1837 }; 1838 }; 1839 1840 port@3 { 1841 reg = <3>; 1842 apss_funnel_in3: endpoint { 1843 remote-endpoint = 1844 <&etm3_out>; 1845 }; 1846 }; 1847 1848 port@4 { 1849 reg = <4>; 1850 apss_funnel_in4: endpoint { 1851 remote-endpoint = 1852 <&etm4_out>; 1853 }; 1854 }; 1855 1856 port@5 { 1857 reg = <5>; 1858 apss_funnel_in5: endpoint { 1859 remote-endpoint = 1860 <&etm5_out>; 1861 }; 1862 }; 1863 1864 port@6 { 1865 reg = <6>; 1866 apss_funnel_in6: endpoint { 1867 remote-endpoint = 1868 <&etm6_out>; 1869 }; 1870 }; 1871 1872 port@7 { 1873 reg = <7>; 1874 apss_funnel_in7: endpoint { 1875 remote-endpoint = 1876 <&etm7_out>; 1877 }; 1878 }; 1879 }; 1880 }; 1881 1882 funnel5: funnel@7b70000 { 1883 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1884 reg = <0x07b70000 0x1000>; 1885 status = "disabled"; 1886 1887 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1888 clock-names = "apb_pclk", "atclk"; 1889 1890 out-ports { 1891 port { 1892 apss_merge_funnel_out: endpoint { 1893 remote-endpoint = 1894 <&funnel1_in6>; 1895 }; 1896 }; 1897 }; 1898 1899 in-ports { 1900 port { 1901 apss_merge_funnel_in: endpoint { 1902 remote-endpoint = 1903 <&apss_funnel_out>; 1904 }; 1905 }; 1906 }; 1907 }; 1908 1909 etm5: etm@7c40000 { 1910 compatible = "arm,coresight-etm4x", "arm,primecell"; 1911 reg = <0x07c40000 0x1000>; 1912 status = "disabled"; 1913 1914 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1915 clock-names = "apb_pclk", "atclk"; 1916 1917 cpu = <&CPU4>; 1918 1919 port { 1920 etm4_out: endpoint { 1921 remote-endpoint = <&apss_funnel_in4>; 1922 }; 1923 }; 1924 }; 1925 1926 etm6: etm@7d40000 { 1927 compatible = "arm,coresight-etm4x", "arm,primecell"; 1928 reg = <0x07d40000 0x1000>; 1929 status = "disabled"; 1930 1931 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1932 clock-names = "apb_pclk", "atclk"; 1933 1934 cpu = <&CPU5>; 1935 1936 port { 1937 etm5_out: endpoint { 1938 remote-endpoint = <&apss_funnel_in5>; 1939 }; 1940 }; 1941 }; 1942 1943 etm7: etm@7e40000 { 1944 compatible = "arm,coresight-etm4x", "arm,primecell"; 1945 reg = <0x07e40000 0x1000>; 1946 status = "disabled"; 1947 1948 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1949 clock-names = "apb_pclk", "atclk"; 1950 1951 cpu = <&CPU6>; 1952 1953 port { 1954 etm6_out: endpoint { 1955 remote-endpoint = <&apss_funnel_in6>; 1956 }; 1957 }; 1958 }; 1959 1960 etm8: etm@7f40000 { 1961 compatible = "arm,coresight-etm4x", "arm,primecell"; 1962 reg = <0x07f40000 0x1000>; 1963 status = "disabled"; 1964 1965 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1966 clock-names = "apb_pclk", "atclk"; 1967 1968 cpu = <&CPU7>; 1969 1970 port { 1971 etm7_out: endpoint { 1972 remote-endpoint = <&apss_funnel_in7>; 1973 }; 1974 }; 1975 }; 1976 1977 sram@290000 { 1978 compatible = "qcom,rpm-stats"; 1979 reg = <0x00290000 0x10000>; 1980 }; 1981 1982 spmi_bus: spmi@800f000 { 1983 compatible = "qcom,spmi-pmic-arb"; 1984 reg = <0x0800f000 0x1000>, 1985 <0x08400000 0x1000000>, 1986 <0x09400000 0x1000000>, 1987 <0x0a400000 0x220000>, 1988 <0x0800a000 0x3000>; 1989 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1990 interrupt-names = "periph_irq"; 1991 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1992 qcom,ee = <0>; 1993 qcom,channel = <0>; 1994 #address-cells = <2>; 1995 #size-cells = <0>; 1996 interrupt-controller; 1997 #interrupt-cells = <4>; 1998 }; 1999 2000 usb3: usb@a8f8800 { 2001 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2002 reg = <0x0a8f8800 0x400>; 2003 status = "disabled"; 2004 #address-cells = <1>; 2005 #size-cells = <1>; 2006 ranges; 2007 2008 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2009 <&gcc GCC_USB30_MASTER_CLK>, 2010 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2011 <&gcc GCC_USB30_SLEEP_CLK>, 2012 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2013 clock-names = "cfg_noc", 2014 "core", 2015 "iface", 2016 "sleep", 2017 "mock_utmi"; 2018 2019 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2020 <&gcc GCC_USB30_MASTER_CLK>; 2021 assigned-clock-rates = <19200000>, <120000000>; 2022 2023 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2024 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2025 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2026 2027 power-domains = <&gcc USB_30_GDSC>; 2028 2029 resets = <&gcc GCC_USB_30_BCR>; 2030 2031 usb3_dwc3: usb@a800000 { 2032 compatible = "snps,dwc3"; 2033 reg = <0x0a800000 0xcd00>; 2034 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2035 snps,dis_u2_susphy_quirk; 2036 snps,dis_enblslpm_quirk; 2037 phys = <&qusb2phy>, <&usb1_ssphy>; 2038 phy-names = "usb2-phy", "usb3-phy"; 2039 snps,has-lpm-erratum; 2040 snps,hird-threshold = /bits/ 8 <0x10>; 2041 }; 2042 }; 2043 2044 usb3phy: phy@c010000 { 2045 compatible = "qcom,msm8998-qmp-usb3-phy"; 2046 reg = <0x0c010000 0x18c>; 2047 status = "disabled"; 2048 #address-cells = <1>; 2049 #size-cells = <1>; 2050 ranges; 2051 2052 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2053 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2054 <&gcc GCC_USB3_CLKREF_CLK>; 2055 clock-names = "aux", "cfg_ahb", "ref"; 2056 2057 resets = <&gcc GCC_USB3_PHY_BCR>, 2058 <&gcc GCC_USB3PHY_PHY_BCR>; 2059 reset-names = "phy", "common"; 2060 2061 usb1_ssphy: phy@c010200 { 2062 reg = <0xc010200 0x128>, 2063 <0xc010400 0x200>, 2064 <0xc010c00 0x20c>, 2065 <0xc010600 0x128>, 2066 <0xc010800 0x200>; 2067 #phy-cells = <0>; 2068 #clock-cells = <0>; 2069 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2070 clock-names = "pipe0"; 2071 clock-output-names = "usb3_phy_pipe_clk_src"; 2072 }; 2073 }; 2074 2075 qusb2phy: phy@c012000 { 2076 compatible = "qcom,msm8998-qusb2-phy"; 2077 reg = <0x0c012000 0x2a8>; 2078 status = "disabled"; 2079 #phy-cells = <0>; 2080 2081 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2082 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2083 clock-names = "cfg_ahb", "ref"; 2084 2085 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2086 2087 nvmem-cells = <&qusb2_hstx_trim>; 2088 }; 2089 2090 sdhc2: mmc@c0a4900 { 2091 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; 2092 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2093 reg-names = "hc", "core"; 2094 2095 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2097 interrupt-names = "hc_irq", "pwr_irq"; 2098 2099 clock-names = "iface", "core", "xo"; 2100 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2101 <&gcc GCC_SDCC2_APPS_CLK>, 2102 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2103 bus-width = <4>; 2104 status = "disabled"; 2105 }; 2106 2107 blsp1_dma: dma-controller@c144000 { 2108 compatible = "qcom,bam-v1.7.0"; 2109 reg = <0x0c144000 0x25000>; 2110 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2111 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2112 clock-names = "bam_clk"; 2113 #dma-cells = <1>; 2114 qcom,ee = <0>; 2115 qcom,controlled-remotely; 2116 num-channels = <18>; 2117 qcom,num-ees = <4>; 2118 }; 2119 2120 blsp1_uart3: serial@c171000 { 2121 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2122 reg = <0x0c171000 0x1000>; 2123 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2124 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2125 <&gcc GCC_BLSP1_AHB_CLK>; 2126 clock-names = "core", "iface"; 2127 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2128 dma-names = "tx", "rx"; 2129 pinctrl-names = "default"; 2130 pinctrl-0 = <&blsp1_uart3_on>; 2131 status = "disabled"; 2132 }; 2133 2134 blsp1_i2c1: i2c@c175000 { 2135 compatible = "qcom,i2c-qup-v2.2.1"; 2136 reg = <0x0c175000 0x600>; 2137 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2138 2139 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2140 <&gcc GCC_BLSP1_AHB_CLK>; 2141 clock-names = "core", "iface"; 2142 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2143 dma-names = "tx", "rx"; 2144 pinctrl-names = "default", "sleep"; 2145 pinctrl-0 = <&blsp1_i2c1_default>; 2146 pinctrl-1 = <&blsp1_i2c1_sleep>; 2147 clock-frequency = <400000>; 2148 2149 status = "disabled"; 2150 #address-cells = <1>; 2151 #size-cells = <0>; 2152 }; 2153 2154 blsp1_i2c2: i2c@c176000 { 2155 compatible = "qcom,i2c-qup-v2.2.1"; 2156 reg = <0x0c176000 0x600>; 2157 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2158 2159 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2160 <&gcc GCC_BLSP1_AHB_CLK>; 2161 clock-names = "core", "iface"; 2162 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2163 dma-names = "tx", "rx"; 2164 pinctrl-names = "default", "sleep"; 2165 pinctrl-0 = <&blsp1_i2c2_default>; 2166 pinctrl-1 = <&blsp1_i2c2_sleep>; 2167 clock-frequency = <400000>; 2168 2169 status = "disabled"; 2170 #address-cells = <1>; 2171 #size-cells = <0>; 2172 }; 2173 2174 blsp1_i2c3: i2c@c177000 { 2175 compatible = "qcom,i2c-qup-v2.2.1"; 2176 reg = <0x0c177000 0x600>; 2177 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2178 2179 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2180 <&gcc GCC_BLSP1_AHB_CLK>; 2181 clock-names = "core", "iface"; 2182 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2183 dma-names = "tx", "rx"; 2184 pinctrl-names = "default", "sleep"; 2185 pinctrl-0 = <&blsp1_i2c3_default>; 2186 pinctrl-1 = <&blsp1_i2c3_sleep>; 2187 clock-frequency = <400000>; 2188 2189 status = "disabled"; 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 }; 2193 2194 blsp1_i2c4: i2c@c178000 { 2195 compatible = "qcom,i2c-qup-v2.2.1"; 2196 reg = <0x0c178000 0x600>; 2197 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2198 2199 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2200 <&gcc GCC_BLSP1_AHB_CLK>; 2201 clock-names = "core", "iface"; 2202 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2203 dma-names = "tx", "rx"; 2204 pinctrl-names = "default", "sleep"; 2205 pinctrl-0 = <&blsp1_i2c4_default>; 2206 pinctrl-1 = <&blsp1_i2c4_sleep>; 2207 clock-frequency = <400000>; 2208 2209 status = "disabled"; 2210 #address-cells = <1>; 2211 #size-cells = <0>; 2212 }; 2213 2214 blsp1_i2c5: i2c@c179000 { 2215 compatible = "qcom,i2c-qup-v2.2.1"; 2216 reg = <0x0c179000 0x600>; 2217 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2218 2219 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2220 <&gcc GCC_BLSP1_AHB_CLK>; 2221 clock-names = "core", "iface"; 2222 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2223 dma-names = "tx", "rx"; 2224 pinctrl-names = "default", "sleep"; 2225 pinctrl-0 = <&blsp1_i2c5_default>; 2226 pinctrl-1 = <&blsp1_i2c5_sleep>; 2227 clock-frequency = <400000>; 2228 2229 status = "disabled"; 2230 #address-cells = <1>; 2231 #size-cells = <0>; 2232 }; 2233 2234 blsp1_i2c6: i2c@c17a000 { 2235 compatible = "qcom,i2c-qup-v2.2.1"; 2236 reg = <0x0c17a000 0x600>; 2237 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2238 2239 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2240 <&gcc GCC_BLSP1_AHB_CLK>; 2241 clock-names = "core", "iface"; 2242 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2243 dma-names = "tx", "rx"; 2244 pinctrl-names = "default", "sleep"; 2245 pinctrl-0 = <&blsp1_i2c6_default>; 2246 pinctrl-1 = <&blsp1_i2c6_sleep>; 2247 clock-frequency = <400000>; 2248 2249 status = "disabled"; 2250 #address-cells = <1>; 2251 #size-cells = <0>; 2252 }; 2253 2254 blsp2_dma: dma-controller@c184000 { 2255 compatible = "qcom,bam-v1.7.0"; 2256 reg = <0x0c184000 0x25000>; 2257 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2258 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2259 clock-names = "bam_clk"; 2260 #dma-cells = <1>; 2261 qcom,ee = <0>; 2262 qcom,controlled-remotely; 2263 num-channels = <18>; 2264 qcom,num-ees = <4>; 2265 }; 2266 2267 blsp2_uart1: serial@c1b0000 { 2268 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2269 reg = <0x0c1b0000 0x1000>; 2270 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2271 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2272 <&gcc GCC_BLSP2_AHB_CLK>; 2273 clock-names = "core", "iface"; 2274 status = "disabled"; 2275 }; 2276 2277 blsp2_i2c1: i2c@c1b5000 { 2278 compatible = "qcom,i2c-qup-v2.2.1"; 2279 reg = <0x0c1b5000 0x600>; 2280 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2281 2282 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2283 <&gcc GCC_BLSP2_AHB_CLK>; 2284 clock-names = "core", "iface"; 2285 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2286 dma-names = "tx", "rx"; 2287 pinctrl-names = "default", "sleep"; 2288 pinctrl-0 = <&blsp2_i2c1_default>; 2289 pinctrl-1 = <&blsp2_i2c1_sleep>; 2290 clock-frequency = <400000>; 2291 2292 status = "disabled"; 2293 #address-cells = <1>; 2294 #size-cells = <0>; 2295 }; 2296 2297 blsp2_i2c2: i2c@c1b6000 { 2298 compatible = "qcom,i2c-qup-v2.2.1"; 2299 reg = <0x0c1b6000 0x600>; 2300 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2301 2302 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2303 <&gcc GCC_BLSP2_AHB_CLK>; 2304 clock-names = "core", "iface"; 2305 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2306 dma-names = "tx", "rx"; 2307 pinctrl-names = "default", "sleep"; 2308 pinctrl-0 = <&blsp2_i2c2_default>; 2309 pinctrl-1 = <&blsp2_i2c2_sleep>; 2310 clock-frequency = <400000>; 2311 2312 status = "disabled"; 2313 #address-cells = <1>; 2314 #size-cells = <0>; 2315 }; 2316 2317 blsp2_i2c3: i2c@c1b7000 { 2318 compatible = "qcom,i2c-qup-v2.2.1"; 2319 reg = <0x0c1b7000 0x600>; 2320 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2321 2322 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2323 <&gcc GCC_BLSP2_AHB_CLK>; 2324 clock-names = "core", "iface"; 2325 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2326 dma-names = "tx", "rx"; 2327 pinctrl-names = "default", "sleep"; 2328 pinctrl-0 = <&blsp2_i2c3_default>; 2329 pinctrl-1 = <&blsp2_i2c3_sleep>; 2330 clock-frequency = <400000>; 2331 2332 status = "disabled"; 2333 #address-cells = <1>; 2334 #size-cells = <0>; 2335 }; 2336 2337 blsp2_i2c4: i2c@c1b8000 { 2338 compatible = "qcom,i2c-qup-v2.2.1"; 2339 reg = <0x0c1b8000 0x600>; 2340 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2341 2342 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2343 <&gcc GCC_BLSP2_AHB_CLK>; 2344 clock-names = "core", "iface"; 2345 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2346 dma-names = "tx", "rx"; 2347 pinctrl-names = "default", "sleep"; 2348 pinctrl-0 = <&blsp2_i2c4_default>; 2349 pinctrl-1 = <&blsp2_i2c4_sleep>; 2350 clock-frequency = <400000>; 2351 2352 status = "disabled"; 2353 #address-cells = <1>; 2354 #size-cells = <0>; 2355 }; 2356 2357 blsp2_i2c5: i2c@c1b9000 { 2358 compatible = "qcom,i2c-qup-v2.2.1"; 2359 reg = <0x0c1b9000 0x600>; 2360 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2361 2362 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2363 <&gcc GCC_BLSP2_AHB_CLK>; 2364 clock-names = "core", "iface"; 2365 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2366 dma-names = "tx", "rx"; 2367 pinctrl-names = "default", "sleep"; 2368 pinctrl-0 = <&blsp2_i2c5_default>; 2369 pinctrl-1 = <&blsp2_i2c5_sleep>; 2370 clock-frequency = <400000>; 2371 2372 status = "disabled"; 2373 #address-cells = <1>; 2374 #size-cells = <0>; 2375 }; 2376 2377 blsp2_i2c6: i2c@c1ba000 { 2378 compatible = "qcom,i2c-qup-v2.2.1"; 2379 reg = <0x0c1ba000 0x600>; 2380 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2381 2382 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2383 <&gcc GCC_BLSP2_AHB_CLK>; 2384 clock-names = "core", "iface"; 2385 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2386 dma-names = "tx", "rx"; 2387 pinctrl-names = "default", "sleep"; 2388 pinctrl-0 = <&blsp2_i2c6_default>; 2389 pinctrl-1 = <&blsp2_i2c6_sleep>; 2390 clock-frequency = <400000>; 2391 2392 status = "disabled"; 2393 #address-cells = <1>; 2394 #size-cells = <0>; 2395 }; 2396 2397 mmcc: clock-controller@c8c0000 { 2398 compatible = "qcom,mmcc-msm8998"; 2399 #clock-cells = <1>; 2400 #reset-cells = <1>; 2401 #power-domain-cells = <1>; 2402 reg = <0xc8c0000 0x40000>; 2403 2404 clock-names = "xo", 2405 "gpll0", 2406 "dsi0dsi", 2407 "dsi0byte", 2408 "dsi1dsi", 2409 "dsi1byte", 2410 "hdmipll", 2411 "dplink", 2412 "dpvco"; 2413 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2414 <&gcc GCC_MMSS_GPLL0_CLK>, 2415 <0>, 2416 <0>, 2417 <0>, 2418 <0>, 2419 <0>, 2420 <0>, 2421 <0>; 2422 }; 2423 2424 mmss_smmu: iommu@cd00000 { 2425 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 2426 reg = <0x0cd00000 0x40000>; 2427 #iommu-cells = <1>; 2428 2429 clocks = <&mmcc MNOC_AHB_CLK>, 2430 <&mmcc BIMC_SMMU_AHB_CLK>, 2431 <&rpmcc RPM_SMD_MMAXI_CLK>, 2432 <&mmcc BIMC_SMMU_AXI_CLK>; 2433 clock-names = "iface-mm", "iface-smmu", 2434 "bus-mm", "bus-smmu"; 2435 2436 #global-interrupts = <0>; 2437 interrupts = 2438 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2454 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2455 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2458 }; 2459 2460 remoteproc_adsp: remoteproc@17300000 { 2461 compatible = "qcom,msm8998-adsp-pas"; 2462 reg = <0x17300000 0x4040>; 2463 2464 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2465 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2466 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2467 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2468 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2469 interrupt-names = "wdog", "fatal", "ready", 2470 "handover", "stop-ack"; 2471 2472 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2473 clock-names = "xo"; 2474 2475 memory-region = <&adsp_mem>; 2476 2477 qcom,smem-states = <&adsp_smp2p_out 0>; 2478 qcom,smem-state-names = "stop"; 2479 2480 power-domains = <&rpmpd MSM8998_VDDCX>; 2481 power-domain-names = "cx"; 2482 2483 status = "disabled"; 2484 2485 glink-edge { 2486 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2487 label = "lpass"; 2488 qcom,remote-pid = <2>; 2489 mboxes = <&apcs_glb 9>; 2490 }; 2491 }; 2492 2493 apcs_glb: mailbox@17911000 { 2494 compatible = "qcom,msm8998-apcs-hmss-global", 2495 "qcom,msm8994-apcs-kpss-global"; 2496 reg = <0x17911000 0x1000>; 2497 2498 #mbox-cells = <1>; 2499 }; 2500 2501 timer@17920000 { 2502 #address-cells = <1>; 2503 #size-cells = <1>; 2504 ranges; 2505 compatible = "arm,armv7-timer-mem"; 2506 reg = <0x17920000 0x1000>; 2507 2508 frame@17921000 { 2509 frame-number = <0>; 2510 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2512 reg = <0x17921000 0x1000>, 2513 <0x17922000 0x1000>; 2514 }; 2515 2516 frame@17923000 { 2517 frame-number = <1>; 2518 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2519 reg = <0x17923000 0x1000>; 2520 status = "disabled"; 2521 }; 2522 2523 frame@17924000 { 2524 frame-number = <2>; 2525 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2526 reg = <0x17924000 0x1000>; 2527 status = "disabled"; 2528 }; 2529 2530 frame@17925000 { 2531 frame-number = <3>; 2532 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2533 reg = <0x17925000 0x1000>; 2534 status = "disabled"; 2535 }; 2536 2537 frame@17926000 { 2538 frame-number = <4>; 2539 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2540 reg = <0x17926000 0x1000>; 2541 status = "disabled"; 2542 }; 2543 2544 frame@17927000 { 2545 frame-number = <5>; 2546 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2547 reg = <0x17927000 0x1000>; 2548 status = "disabled"; 2549 }; 2550 2551 frame@17928000 { 2552 frame-number = <6>; 2553 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2554 reg = <0x17928000 0x1000>; 2555 status = "disabled"; 2556 }; 2557 }; 2558 2559 intc: interrupt-controller@17a00000 { 2560 compatible = "arm,gic-v3"; 2561 reg = <0x17a00000 0x10000>, /* GICD */ 2562 <0x17b00000 0x100000>; /* GICR * 8 */ 2563 #interrupt-cells = <3>; 2564 #address-cells = <1>; 2565 #size-cells = <1>; 2566 ranges; 2567 interrupt-controller; 2568 #redistributor-regions = <1>; 2569 redistributor-stride = <0x0 0x20000>; 2570 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2571 }; 2572 2573 wifi: wifi@18800000 { 2574 compatible = "qcom,wcn3990-wifi"; 2575 status = "disabled"; 2576 reg = <0x18800000 0x800000>; 2577 reg-names = "membase"; 2578 memory-region = <&wlan_msa_mem>; 2579 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2580 clock-names = "cxo_ref_clk_pin"; 2581 interrupts = 2582 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2583 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2594 iommus = <&anoc2_smmu 0x1900>, 2595 <&anoc2_smmu 0x1901>; 2596 qcom,snoc-host-cap-8bit-quirk; 2597 }; 2598 }; 2599}; 2600