1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * OnePlus 5(T) (cheeseburger / dumpling) common device tree source based on msm8998-mtp.dtsi 4 * 5 * Copyright (c) 2021, Jami Kettunen <jamipkettunen@gmail.com> 6 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 13#include "msm8998.dtsi" 14#include "pm8005.dtsi" 15#include "pm8998.dtsi" 16#include "pmi8998.dtsi" 17 18/ { 19 /* Required for bootloader to select correct board */ 20 qcom,msm-id = <292 0x20001>; /* 8998 v2.1 */ 21 22 chosen { 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 27 /* Use display framebuffer setup by the UEFI XBL bootloader for simplefb */ 28 framebuffer0: framebuffer@9d400000 { 29 compatible = "simple-framebuffer"; 30 reg = <0x0 0x9d400000 0x0 0x2400000>; 31 width = <1080>; 32 height = <1920>; 33 stride = <(1080 * 4)>; 34 format = "a8r8g8b8"; 35 /* 36 * That's a lot of clocks, but it's necessary due 37 * to unused clk cleanup & no panel driver yet.. 38 */ 39 clocks = <&mmcc MDSS_AHB_CLK>, 40 <&mmcc MDSS_AXI_CLK>, 41 <&mmcc MDSS_VSYNC_CLK>, 42 <&mmcc MDSS_MDP_CLK>, 43 <&mmcc MDSS_BYTE0_CLK>, 44 <&mmcc MDSS_BYTE0_INTF_CLK>, 45 <&mmcc MDSS_PCLK0_CLK>, 46 <&mmcc MDSS_ESC0_CLK>; 47 power-domains = <&mmcc MDSS_GDSC>; 48 }; 49 }; 50 51 reserved-memory { 52 /* Bootloader display framebuffer region */ 53 cont_splash_mem: memory@9d400000 { 54 reg = <0x0 0x9d400000 0x0 0x2400000>; 55 no-map; 56 }; 57 58 /* For getting crash logs using Android downstream kernels */ 59 ramoops@ac000000 { 60 compatible = "ramoops"; 61 reg = <0x0 0xac000000 0x0 0x200000>; 62 console-size = <0x80000>; 63 pmsg-size = <0x40000>; 64 record-size = <0x8000>; 65 ftrace-size = <0x20000>; 66 }; 67 68 /* 69 * The following memory regions on downstream are "dynamically allocated" 70 * but given the same addresses every time. Hard code them as these addresses 71 * are where the OnePlus signed firmware expects them to be. 72 */ 73 ipa_fws_region: ipa@f6800000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x0 0xf6800000 0x0 0x5000>; 76 no-map; 77 }; 78 zap_shader_region: gpu@f6900000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x0 0xf6900000 0x0 0x2000>; 81 no-map; 82 }; 83 }; 84 85 gpio-keys { 86 compatible = "gpio-keys"; 87 label = "Volume buttons"; 88 autorepeat; 89 90 pinctrl-names = "default"; 91 pinctrl-0 = <&vol_keys_default>; 92 93 button-vol-down { 94 label = "Volume down"; 95 gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; 96 linux,code = <KEY_VOLUMEDOWN>; 97 debounce-interval = <15>; 98 wakeup-source; 99 }; 100 101 button-vol-up { 102 label = "Volume up"; 103 gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; 104 linux,code = <KEY_VOLUMEUP>; 105 debounce-interval = <15>; 106 wakeup-source; 107 }; 108 }; 109 110 gpio-hall-sensor { 111 compatible = "gpio-keys"; 112 label = "Hall effect sensor"; 113 114 pinctrl-names = "default"; 115 pinctrl-0 = <&hall_sensor_default>; 116 117 event-hall-sensor { 118 label = "Hall Effect Sensor"; 119 gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; 120 linux,input-type = <EV_SW>; 121 linux,code = <SW_LID>; 122 linux,can-disable; 123 wakeup-source; 124 }; 125 }; 126 127 vph_pwr: vph-pwr-regulator { 128 compatible = "regulator-fixed"; 129 regulator-name = "vph_pwr"; 130 regulator-always-on; 131 regulator-boot-on; 132 }; 133}; 134 135/* 136 * OnePlus' ADSP firmware requires 30 MiB in total, so increase the adsp_mem 137 * region by 4 MiB to account for this while relocating the other now 138 * conflicting memory nodes accordingly. 139 */ 140&adsp_mem { 141 reg = <0x0 0x8b200000 0x0 0x1e00000>; 142}; 143&mpss_mem { 144 reg = <0x0 0x8d000000 0x0 0x7000000>; 145}; 146&venus_mem { 147 reg = <0x0 0x94000000 0x0 0x500000>; 148}; 149&mba_mem { 150 reg = <0x0 0x94500000 0x0 0x200000>; 151}; 152&slpi_mem { 153 reg = <0x0 0x94700000 0x0 0xf00000>; 154}; 155&ipa_fw_mem { 156 reg = <0x0 0x95600000 0x0 0x10000>; 157}; 158&ipa_gsi_mem { 159 reg = <0x0 0x95610000 0x0 0x5000>; 160}; 161&gpu_mem { 162 reg = <0x0 0x95615000 0x0 0x100000>; 163}; 164&wlan_msa_mem { 165 reg = <0x0 0x95715000 0x0 0x100000>; 166}; 167 168&blsp1_i2c5 { 169 status = "okay"; 170 171 touchscreen@20 { 172 compatible = "syna,rmi4-i2c"; 173 reg = <0x20>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 interrupt-parent = <&tlmm>; 178 interrupts = <125 IRQ_TYPE_EDGE_FALLING>; 179 180 pinctrl-names = "default"; 181 pinctrl-0 = <&ts_int_active &ts_reset_active>; 182 183 vdd-supply = <&vreg_l28_3p0>; 184 vio-supply = <&vreg_l6a_1p8>; 185 186 syna,reset-delay-ms = <20>; 187 syna,startup-delay-ms = <20>; 188 189 rmi4-f01@1 { 190 reg = <0x01>; 191 syna,nosleep-mode = <1>; 192 }; 193 194 rmi4_f12: rmi4-f12@12 { 195 reg = <0x12>; 196 syna,rezero-wait-ms = <20>; 197 syna,sensor-type = <1>; 198 touchscreen-x-mm = <68>; 199 touchscreen-y-mm = <122>; 200 }; 201 }; 202}; 203 204&blsp1_i2c6 { 205 status = "okay"; 206 207 nfc@28 { 208 compatible = "nxp,nxp-nci-i2c"; 209 reg = <0x28>; 210 211 interrupt-parent = <&tlmm>; 212 interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; 213 214 enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; 215 216 pinctrl-names = "default"; 217 pinctrl-0 = <&nfc_int_active &nfc_enable_active>; 218 }; 219}; 220 221&blsp1_uart3 { 222 status = "okay"; 223 224 bluetooth { 225 compatible = "qcom,wcn3990-bt"; 226 227 vddio-supply = <&vreg_s4a_1p8>; 228 vddxo-supply = <&vreg_l7a_1p8>; 229 vddrf-supply = <&vreg_l17a_1p3>; 230 vddch0-supply = <&vreg_l25a_3p3>; 231 max-speed = <3200000>; 232 }; 233}; 234 235&blsp1_uart3_on { 236 rx-pins { 237 /delete-property/ bias-disable; 238 /* 239 * Configure a pull-up on 46 (RX). This is needed to 240 * avoid garbage data when the TX pin of the Bluetooth 241 * module is in tri-state (module powered off or not 242 * driving the signal yet). 243 */ 244 bias-pull-up; 245 }; 246 247 cts-pins { 248 /delete-property/ bias-disable; 249 /* 250 * Configure a pull-down on 47 (CTS) to match the pull 251 * of the Bluetooth module. 252 */ 253 bias-pull-down; 254 }; 255}; 256 257&blsp2_uart1 { 258 status = "okay"; 259}; 260 261&pm8005_regulators { 262 /* VDD_GFX supply */ 263 pm8005_s1: s1 { 264 regulator-min-microvolt = <524000>; 265 regulator-max-microvolt = <1100000>; 266 regulator-enable-ramp-delay = <500>; 267 /* Hack until we rig up the gpu consumer */ 268 regulator-always-on; 269 }; 270}; 271 272&pm8998_gpios { 273 vol_keys_default: vol-keys-state { 274 pins = "gpio5", "gpio6"; 275 function = "normal"; 276 bias-pull-up; 277 input-enable; 278 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; 279 }; 280}; 281 282&pmi8998_rradc { 283 status = "okay"; 284}; 285 286&qusb2phy { 287 status = "okay"; 288 289 vdd-supply = <&vreg_l1a_0p875>; 290 vdda-pll-supply = <&vreg_l12a_1p8>; 291 vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; 292}; 293 294&rpm_requests { 295 regulators-0 { 296 compatible = "qcom,rpm-pm8998-regulators"; 297 298 vdd_s1-supply = <&vph_pwr>; 299 vdd_s2-supply = <&vph_pwr>; 300 vdd_s3-supply = <&vph_pwr>; 301 vdd_s4-supply = <&vph_pwr>; 302 vdd_s5-supply = <&vph_pwr>; 303 vdd_s6-supply = <&vph_pwr>; 304 vdd_s7-supply = <&vph_pwr>; 305 vdd_s8-supply = <&vph_pwr>; 306 vdd_s9-supply = <&vph_pwr>; 307 vdd_s10-supply = <&vph_pwr>; 308 vdd_s11-supply = <&vph_pwr>; 309 vdd_s12-supply = <&vph_pwr>; 310 vdd_s13-supply = <&vph_pwr>; 311 vdd_l1_l27-supply = <&vreg_s7a_1p025>; 312 vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; 313 vdd_l3_l11-supply = <&vreg_s7a_1p025>; 314 vdd_l4_l5-supply = <&vreg_s7a_1p025>; 315 vdd_l6-supply = <&vreg_s5a_2p04>; 316 vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; 317 vdd_l9-supply = <&vreg_bob>; 318 vdd_l10_l23_l25-supply = <&vreg_bob>; 319 vdd_l13_l19_l21-supply = <&vreg_bob>; 320 vdd_l16_l28-supply = <&vreg_bob>; 321 vdd_l18_l22-supply = <&vreg_bob>; 322 vdd_l20_l24-supply = <&vreg_bob>; 323 vdd_l26-supply = <&vreg_s3a_1p35>; 324 vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; 325 326 vreg_s3a_1p35: s3 { 327 regulator-min-microvolt = <1352000>; 328 regulator-max-microvolt = <1352000>; 329 }; 330 331 vreg_s4a_1p8: s4 { 332 regulator-min-microvolt = <1800000>; 333 regulator-max-microvolt = <1800000>; 334 regulator-allow-set-load; 335 }; 336 337 vreg_s5a_2p04: s5 { 338 regulator-min-microvolt = <1904000>; 339 regulator-max-microvolt = <2040000>; 340 }; 341 342 vreg_s7a_1p025: s7 { 343 regulator-min-microvolt = <900000>; 344 regulator-max-microvolt = <1028000>; 345 }; 346 347 vreg_l1a_0p875: l1 { 348 regulator-min-microvolt = <880000>; 349 regulator-max-microvolt = <880000>; 350 }; 351 352 vreg_l2a_1p2: l2 { 353 regulator-min-microvolt = <1200000>; 354 regulator-max-microvolt = <1200000>; 355 }; 356 357 vreg_l3a_1p0: l3 { 358 regulator-min-microvolt = <1000000>; 359 regulator-max-microvolt = <1000000>; 360 }; 361 362 vreg_l5a_0p8: l5 { 363 regulator-min-microvolt = <800000>; 364 regulator-max-microvolt = <800000>; 365 }; 366 367 vreg_l6a_1p8: l6 { 368 regulator-min-microvolt = <1808000>; 369 regulator-max-microvolt = <1808000>; 370 }; 371 372 vreg_l7a_1p8: l7 { 373 regulator-min-microvolt = <1800000>; 374 regulator-max-microvolt = <1800000>; 375 }; 376 377 vreg_l8a_1p2: l8 { 378 regulator-min-microvolt = <1200000>; 379 regulator-max-microvolt = <1200000>; 380 }; 381 382 vreg_l9a_1p8: l9 { 383 regulator-min-microvolt = <1808000>; 384 regulator-max-microvolt = <2960000>; 385 }; 386 387 vreg_l10a_1p8: l10 { 388 regulator-min-microvolt = <1808000>; 389 regulator-max-microvolt = <2960000>; 390 }; 391 392 vreg_l11a_1p0: l11 { 393 regulator-min-microvolt = <1000000>; 394 regulator-max-microvolt = <1000000>; 395 }; 396 397 vreg_l12a_1p8: l12 { 398 regulator-min-microvolt = <1800000>; 399 regulator-max-microvolt = <1800000>; 400 }; 401 402 vreg_l13a_2p95: l13 { 403 regulator-min-microvolt = <1808000>; 404 regulator-max-microvolt = <2960000>; 405 }; 406 407 vreg_l14a_1p88: l14 { 408 regulator-min-microvolt = <1880000>; 409 regulator-max-microvolt = <1880000>; 410 }; 411 412 vreg_l15a_1p8: l15 { 413 regulator-min-microvolt = <1800000>; 414 regulator-max-microvolt = <1800000>; 415 }; 416 417 vreg_l16a_2p7: l16 { 418 regulator-min-microvolt = <2704000>; 419 regulator-max-microvolt = <2704000>; 420 }; 421 422 vreg_l17a_1p3: l17 { 423 regulator-min-microvolt = <1304000>; 424 regulator-max-microvolt = <1304000>; 425 }; 426 427 vreg_l18a_2p7: l18 { 428 regulator-min-microvolt = <2704000>; 429 regulator-max-microvolt = <2704000>; 430 }; 431 432 vreg_l19a_3p0: l19 { 433 regulator-min-microvolt = <3008000>; 434 regulator-max-microvolt = <3008000>; 435 }; 436 437 vreg_l20a_2p95: l20 { 438 regulator-min-microvolt = <2960000>; 439 regulator-max-microvolt = <2960000>; 440 regulator-allow-set-load; 441 }; 442 vreg_l21a_2p95: l21 { 443 regulator-min-microvolt = <2960000>; 444 regulator-max-microvolt = <2960000>; 445 regulator-system-load = <800000>; 446 regulator-allow-set-load; 447 }; 448 449 vreg_l22a_2p85: l22 { 450 regulator-min-microvolt = <2864000>; 451 regulator-max-microvolt = <2864000>; 452 }; 453 454 vreg_l23a_3p3: l23 { 455 regulator-min-microvolt = <3312000>; 456 regulator-max-microvolt = <3312000>; 457 }; 458 459 vreg_l24a_3p075: l24 { 460 regulator-min-microvolt = <3088000>; 461 regulator-max-microvolt = <3088000>; 462 }; 463 464 vreg_l25a_3p3: l25 { 465 regulator-min-microvolt = <3104000>; 466 regulator-max-microvolt = <3312000>; 467 }; 468 469 vreg_l26a_1p2: l26 { 470 regulator-min-microvolt = <1200000>; 471 regulator-max-microvolt = <1200000>; 472 regulator-allow-set-load; 473 }; 474 475 vreg_l28_3p0: l28 { 476 regulator-min-microvolt = <3008000>; 477 regulator-max-microvolt = <3008000>; 478 }; 479 480 vreg_lvs1a_1p8: lvs1 { }; 481 vreg_lvs2a_1p8: lvs2 { }; 482 }; 483 484 regulators-1 { 485 compatible = "qcom,rpm-pmi8998-regulators"; 486 487 vdd_bob-supply = <&vph_pwr>; 488 489 vreg_bob: bob { 490 regulator-min-microvolt = <3312000>; 491 regulator-max-microvolt = <3600000>; 492 }; 493 }; 494}; 495 496&tlmm { 497 gpio-reserved-ranges = <0 4>, <81 4>; 498 499 hall_sensor_default: hall-sensor-default-state { 500 pins = "gpio124"; 501 function = "gpio"; 502 drive-strength = <2>; 503 bias-disable; 504 }; 505 506 ts_int_active: ts-int-active-state { 507 pins = "gpio125"; 508 function = "gpio"; 509 drive-strength = <8>; 510 bias-pull-up; 511 }; 512 513 ts_reset_active: ts-reset-active-state { 514 pins = "gpio89"; 515 function = "gpio"; 516 drive-strength = <8>; 517 bias-pull-up; 518 }; 519 520 nfc_int_active: nfc-int-active-state { 521 pins = "gpio92"; 522 function = "gpio"; 523 drive-strength = <6>; 524 bias-pull-up; 525 }; 526 527 nfc_enable_active: nfc-enable-active-state { 528 pins = "gpio12", "gpio116"; 529 function = "gpio"; 530 drive-strength = <6>; 531 bias-pull-up; 532 }; 533}; 534 535&ufshc { 536 status = "okay"; 537 538 vcc-supply = <&vreg_l20a_2p95>; 539 vccq-supply = <&vreg_l26a_1p2>; 540 vccq2-supply = <&vreg_s4a_1p8>; 541 vcc-max-microamp = <750000>; 542 vccq-max-microamp = <560000>; 543 vccq2-max-microamp = <750000>; 544}; 545 546&ufsphy { 547 status = "okay"; 548 549 vdda-phy-supply = <&vreg_l1a_0p875>; 550 vdda-pll-supply = <&vreg_l2a_1p2>; 551 vddp-ref-clk-supply = <&vreg_l26a_1p2>; 552}; 553 554&usb3 { 555 status = "okay"; 556 557 /* Disable USB3 clock requirement as the device only supports USB2 */ 558 qcom,select-utmi-as-pipe-clk; 559}; 560 561&usb3_dwc3 { 562 /* Drop the unused USB 3 PHY */ 563 phys = <&qusb2phy>; 564 phy-names = "usb2-phy"; 565 566 /* Fastest mode for USB 2 */ 567 maximum-speed = "high-speed"; 568 569 /* Force to peripheral until we can switch modes */ 570 dr_mode = "peripheral"; 571}; 572 573&wifi { 574 /* Leave disabled until MSS is functional */ 575 vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; 576 vdd-1.8-xo-supply = <&vreg_l7a_1p8>; 577 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; 578 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; 579}; 580