1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/soc/qcom,apr.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 cpu-idle-states = <&CPU_SLEEP_0>; 50 capacity-dmips-mhz = <1024>; 51 clocks = <&kryocc 0>; 52 operating-points-v2 = <&cluster0_opp>; 53 #cooling-cells = <2>; 54 next-level-cache = <&L2_0>; 55 L2_0: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 cache-unified; 59 }; 60 }; 61 62 CPU1: cpu@1 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo"; 65 reg = <0x0 0x1>; 66 enable-method = "psci"; 67 cpu-idle-states = <&CPU_SLEEP_0>; 68 capacity-dmips-mhz = <1024>; 69 clocks = <&kryocc 0>; 70 operating-points-v2 = <&cluster0_opp>; 71 #cooling-cells = <2>; 72 next-level-cache = <&L2_0>; 73 }; 74 75 CPU2: cpu@100 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo"; 78 reg = <0x0 0x100>; 79 enable-method = "psci"; 80 cpu-idle-states = <&CPU_SLEEP_0>; 81 capacity-dmips-mhz = <1024>; 82 clocks = <&kryocc 1>; 83 operating-points-v2 = <&cluster1_opp>; 84 #cooling-cells = <2>; 85 next-level-cache = <&L2_1>; 86 L2_1: l2-cache { 87 compatible = "cache"; 88 cache-level = <2>; 89 cache-unified; 90 }; 91 }; 92 93 CPU3: cpu@101 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo"; 96 reg = <0x0 0x101>; 97 enable-method = "psci"; 98 cpu-idle-states = <&CPU_SLEEP_0>; 99 capacity-dmips-mhz = <1024>; 100 clocks = <&kryocc 1>; 101 operating-points-v2 = <&cluster1_opp>; 102 #cooling-cells = <2>; 103 next-level-cache = <&L2_1>; 104 }; 105 106 cpu-map { 107 cluster0 { 108 core0 { 109 cpu = <&CPU0>; 110 }; 111 112 core1 { 113 cpu = <&CPU1>; 114 }; 115 }; 116 117 cluster1 { 118 core0 { 119 cpu = <&CPU2>; 120 }; 121 122 core1 { 123 cpu = <&CPU3>; 124 }; 125 }; 126 }; 127 128 idle-states { 129 entry-method = "psci"; 130 131 CPU_SLEEP_0: cpu-sleep-0 { 132 compatible = "arm,idle-state"; 133 idle-state-name = "standalone-power-collapse"; 134 arm,psci-suspend-param = <0x00000004>; 135 entry-latency-us = <130>; 136 exit-latency-us = <80>; 137 min-residency-us = <300>; 138 }; 139 }; 140 }; 141 142 cluster0_opp: opp-table-cluster0 { 143 compatible = "operating-points-v2-kryo-cpu"; 144 nvmem-cells = <&speedbin_efuse>; 145 opp-shared; 146 147 /* Nominal fmax for now */ 148 opp-307200000 { 149 opp-hz = /bits/ 64 <307200000>; 150 opp-supported-hw = <0xf>; 151 clock-latency-ns = <200000>; 152 }; 153 opp-422400000 { 154 opp-hz = /bits/ 64 <422400000>; 155 opp-supported-hw = <0xf>; 156 clock-latency-ns = <200000>; 157 }; 158 opp-480000000 { 159 opp-hz = /bits/ 64 <480000000>; 160 opp-supported-hw = <0xf>; 161 clock-latency-ns = <200000>; 162 }; 163 opp-556800000 { 164 opp-hz = /bits/ 64 <556800000>; 165 opp-supported-hw = <0xf>; 166 clock-latency-ns = <200000>; 167 }; 168 opp-652800000 { 169 opp-hz = /bits/ 64 <652800000>; 170 opp-supported-hw = <0xf>; 171 clock-latency-ns = <200000>; 172 }; 173 opp-729600000 { 174 opp-hz = /bits/ 64 <729600000>; 175 opp-supported-hw = <0xf>; 176 clock-latency-ns = <200000>; 177 }; 178 opp-844800000 { 179 opp-hz = /bits/ 64 <844800000>; 180 opp-supported-hw = <0xf>; 181 clock-latency-ns = <200000>; 182 }; 183 opp-960000000 { 184 opp-hz = /bits/ 64 <960000000>; 185 opp-supported-hw = <0xf>; 186 clock-latency-ns = <200000>; 187 }; 188 opp-1036800000 { 189 opp-hz = /bits/ 64 <1036800000>; 190 opp-supported-hw = <0xf>; 191 clock-latency-ns = <200000>; 192 }; 193 opp-1113600000 { 194 opp-hz = /bits/ 64 <1113600000>; 195 opp-supported-hw = <0xf>; 196 clock-latency-ns = <200000>; 197 }; 198 opp-1190400000 { 199 opp-hz = /bits/ 64 <1190400000>; 200 opp-supported-hw = <0xf>; 201 clock-latency-ns = <200000>; 202 }; 203 opp-1228800000 { 204 opp-hz = /bits/ 64 <1228800000>; 205 opp-supported-hw = <0xf>; 206 clock-latency-ns = <200000>; 207 }; 208 opp-1324800000 { 209 opp-hz = /bits/ 64 <1324800000>; 210 opp-supported-hw = <0xd>; 211 clock-latency-ns = <200000>; 212 }; 213 opp-1363200000 { 214 opp-hz = /bits/ 64 <1363200000>; 215 opp-supported-hw = <0x2>; 216 clock-latency-ns = <200000>; 217 }; 218 opp-1401600000 { 219 opp-hz = /bits/ 64 <1401600000>; 220 opp-supported-hw = <0xd>; 221 clock-latency-ns = <200000>; 222 }; 223 opp-1478400000 { 224 opp-hz = /bits/ 64 <1478400000>; 225 opp-supported-hw = <0x9>; 226 clock-latency-ns = <200000>; 227 }; 228 opp-1497600000 { 229 opp-hz = /bits/ 64 <1497600000>; 230 opp-supported-hw = <0x04>; 231 clock-latency-ns = <200000>; 232 }; 233 opp-1593600000 { 234 opp-hz = /bits/ 64 <1593600000>; 235 opp-supported-hw = <0x9>; 236 clock-latency-ns = <200000>; 237 }; 238 }; 239 240 cluster1_opp: opp-table-cluster1 { 241 compatible = "operating-points-v2-kryo-cpu"; 242 nvmem-cells = <&speedbin_efuse>; 243 opp-shared; 244 245 /* Nominal fmax for now */ 246 opp-307200000 { 247 opp-hz = /bits/ 64 <307200000>; 248 opp-supported-hw = <0xf>; 249 clock-latency-ns = <200000>; 250 }; 251 opp-403200000 { 252 opp-hz = /bits/ 64 <403200000>; 253 opp-supported-hw = <0xf>; 254 clock-latency-ns = <200000>; 255 }; 256 opp-480000000 { 257 opp-hz = /bits/ 64 <480000000>; 258 opp-supported-hw = <0xf>; 259 clock-latency-ns = <200000>; 260 }; 261 opp-556800000 { 262 opp-hz = /bits/ 64 <556800000>; 263 opp-supported-hw = <0xf>; 264 clock-latency-ns = <200000>; 265 }; 266 opp-652800000 { 267 opp-hz = /bits/ 64 <652800000>; 268 opp-supported-hw = <0xf>; 269 clock-latency-ns = <200000>; 270 }; 271 opp-729600000 { 272 opp-hz = /bits/ 64 <729600000>; 273 opp-supported-hw = <0xf>; 274 clock-latency-ns = <200000>; 275 }; 276 opp-806400000 { 277 opp-hz = /bits/ 64 <806400000>; 278 opp-supported-hw = <0xf>; 279 clock-latency-ns = <200000>; 280 }; 281 opp-883200000 { 282 opp-hz = /bits/ 64 <883200000>; 283 opp-supported-hw = <0xf>; 284 clock-latency-ns = <200000>; 285 }; 286 opp-940800000 { 287 opp-hz = /bits/ 64 <940800000>; 288 opp-supported-hw = <0xf>; 289 clock-latency-ns = <200000>; 290 }; 291 opp-1036800000 { 292 opp-hz = /bits/ 64 <1036800000>; 293 opp-supported-hw = <0xf>; 294 clock-latency-ns = <200000>; 295 }; 296 opp-1113600000 { 297 opp-hz = /bits/ 64 <1113600000>; 298 opp-supported-hw = <0xf>; 299 clock-latency-ns = <200000>; 300 }; 301 opp-1190400000 { 302 opp-hz = /bits/ 64 <1190400000>; 303 opp-supported-hw = <0xf>; 304 clock-latency-ns = <200000>; 305 }; 306 opp-1248000000 { 307 opp-hz = /bits/ 64 <1248000000>; 308 opp-supported-hw = <0xf>; 309 clock-latency-ns = <200000>; 310 }; 311 opp-1324800000 { 312 opp-hz = /bits/ 64 <1324800000>; 313 opp-supported-hw = <0xf>; 314 clock-latency-ns = <200000>; 315 }; 316 opp-1401600000 { 317 opp-hz = /bits/ 64 <1401600000>; 318 opp-supported-hw = <0xf>; 319 clock-latency-ns = <200000>; 320 }; 321 opp-1478400000 { 322 opp-hz = /bits/ 64 <1478400000>; 323 opp-supported-hw = <0xf>; 324 clock-latency-ns = <200000>; 325 }; 326 opp-1555200000 { 327 opp-hz = /bits/ 64 <1555200000>; 328 opp-supported-hw = <0xf>; 329 clock-latency-ns = <200000>; 330 }; 331 opp-1632000000 { 332 opp-hz = /bits/ 64 <1632000000>; 333 opp-supported-hw = <0xf>; 334 clock-latency-ns = <200000>; 335 }; 336 opp-1708800000 { 337 opp-hz = /bits/ 64 <1708800000>; 338 opp-supported-hw = <0xf>; 339 clock-latency-ns = <200000>; 340 }; 341 opp-1785600000 { 342 opp-hz = /bits/ 64 <1785600000>; 343 opp-supported-hw = <0xf>; 344 clock-latency-ns = <200000>; 345 }; 346 opp-1804800000 { 347 opp-hz = /bits/ 64 <1804800000>; 348 opp-supported-hw = <0xe>; 349 clock-latency-ns = <200000>; 350 }; 351 opp-1824000000 { 352 opp-hz = /bits/ 64 <1824000000>; 353 opp-supported-hw = <0x1>; 354 clock-latency-ns = <200000>; 355 }; 356 opp-1900800000 { 357 opp-hz = /bits/ 64 <1900800000>; 358 opp-supported-hw = <0x4>; 359 clock-latency-ns = <200000>; 360 }; 361 opp-1920000000 { 362 opp-hz = /bits/ 64 <1920000000>; 363 opp-supported-hw = <0x1>; 364 clock-latency-ns = <200000>; 365 }; 366 opp-1996800000 { 367 opp-hz = /bits/ 64 <1996800000>; 368 opp-supported-hw = <0x1>; 369 clock-latency-ns = <200000>; 370 }; 371 opp-2073600000 { 372 opp-hz = /bits/ 64 <2073600000>; 373 opp-supported-hw = <0x1>; 374 clock-latency-ns = <200000>; 375 }; 376 opp-2150400000 { 377 opp-hz = /bits/ 64 <2150400000>; 378 opp-supported-hw = <0x1>; 379 clock-latency-ns = <200000>; 380 }; 381 }; 382 383 firmware { 384 scm { 385 compatible = "qcom,scm-msm8996", "qcom,scm"; 386 qcom,dload-mode = <&tcsr_2 0x13000>; 387 }; 388 }; 389 390 memory@80000000 { 391 device_type = "memory"; 392 /* We expect the bootloader to fill in the reg */ 393 reg = <0x0 0x80000000 0x0 0x0>; 394 }; 395 396 psci { 397 compatible = "arm,psci-1.0"; 398 method = "smc"; 399 }; 400 401 reserved-memory { 402 #address-cells = <2>; 403 #size-cells = <2>; 404 ranges; 405 406 hyp_mem: memory@85800000 { 407 reg = <0x0 0x85800000 0x0 0x600000>; 408 no-map; 409 }; 410 411 xbl_mem: memory@85e00000 { 412 reg = <0x0 0x85e00000 0x0 0x200000>; 413 no-map; 414 }; 415 416 smem_mem: smem-mem@86000000 { 417 reg = <0x0 0x86000000 0x0 0x200000>; 418 no-map; 419 }; 420 421 tz_mem: memory@86200000 { 422 reg = <0x0 0x86200000 0x0 0x2600000>; 423 no-map; 424 }; 425 426 rmtfs_mem: rmtfs { 427 compatible = "qcom,rmtfs-mem"; 428 429 size = <0x0 0x200000>; 430 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 431 no-map; 432 433 qcom,client-id = <1>; 434 qcom,vmid = <15>; 435 }; 436 437 mpss_mem: mpss@88800000 { 438 reg = <0x0 0x88800000 0x0 0x6200000>; 439 no-map; 440 }; 441 442 adsp_mem: adsp@8ea00000 { 443 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 444 no-map; 445 }; 446 447 slpi_mem: slpi@90500000 { 448 reg = <0x0 0x90500000 0x0 0xa00000>; 449 no-map; 450 }; 451 452 gpu_mem: gpu@90f00000 { 453 compatible = "shared-dma-pool"; 454 reg = <0x0 0x90f00000 0x0 0x100000>; 455 no-map; 456 }; 457 458 venus_mem: venus@91000000 { 459 reg = <0x0 0x91000000 0x0 0x500000>; 460 no-map; 461 }; 462 463 mba_mem: mba@91500000 { 464 reg = <0x0 0x91500000 0x0 0x200000>; 465 no-map; 466 }; 467 468 mdata_mem: mpss-metadata { 469 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 470 size = <0x0 0x4000>; 471 no-map; 472 }; 473 }; 474 475 rpm-glink { 476 compatible = "qcom,glink-rpm"; 477 478 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 479 480 qcom,rpm-msg-ram = <&rpm_msg_ram>; 481 482 mboxes = <&apcs_glb 0>; 483 484 rpm_requests: rpm-requests { 485 compatible = "qcom,rpm-msm8996"; 486 qcom,glink-channels = "rpm_requests"; 487 488 rpmcc: clock-controller { 489 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 490 #clock-cells = <1>; 491 clocks = <&xo_board>; 492 clock-names = "xo"; 493 }; 494 495 rpmpd: power-controller { 496 compatible = "qcom,msm8996-rpmpd"; 497 #power-domain-cells = <1>; 498 operating-points-v2 = <&rpmpd_opp_table>; 499 500 rpmpd_opp_table: opp-table { 501 compatible = "operating-points-v2"; 502 503 rpmpd_opp1: opp1 { 504 opp-level = <1>; 505 }; 506 507 rpmpd_opp2: opp2 { 508 opp-level = <2>; 509 }; 510 511 rpmpd_opp3: opp3 { 512 opp-level = <3>; 513 }; 514 515 rpmpd_opp4: opp4 { 516 opp-level = <4>; 517 }; 518 519 rpmpd_opp5: opp5 { 520 opp-level = <5>; 521 }; 522 523 rpmpd_opp6: opp6 { 524 opp-level = <6>; 525 }; 526 }; 527 }; 528 }; 529 }; 530 531 smem { 532 compatible = "qcom,smem"; 533 memory-region = <&smem_mem>; 534 hwlocks = <&tcsr_mutex 3>; 535 }; 536 537 smp2p-adsp { 538 compatible = "qcom,smp2p"; 539 qcom,smem = <443>, <429>; 540 541 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 542 543 mboxes = <&apcs_glb 10>; 544 545 qcom,local-pid = <0>; 546 qcom,remote-pid = <2>; 547 548 adsp_smp2p_out: master-kernel { 549 qcom,entry-name = "master-kernel"; 550 #qcom,smem-state-cells = <1>; 551 }; 552 553 adsp_smp2p_in: slave-kernel { 554 qcom,entry-name = "slave-kernel"; 555 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 }; 559 }; 560 561 smp2p-mpss { 562 compatible = "qcom,smp2p"; 563 qcom,smem = <435>, <428>; 564 565 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 566 567 mboxes = <&apcs_glb 14>; 568 569 qcom,local-pid = <0>; 570 qcom,remote-pid = <1>; 571 572 mpss_smp2p_out: master-kernel { 573 qcom,entry-name = "master-kernel"; 574 #qcom,smem-state-cells = <1>; 575 }; 576 577 mpss_smp2p_in: slave-kernel { 578 qcom,entry-name = "slave-kernel"; 579 580 interrupt-controller; 581 #interrupt-cells = <2>; 582 }; 583 }; 584 585 smp2p-slpi { 586 compatible = "qcom,smp2p"; 587 qcom,smem = <481>, <430>; 588 589 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 590 591 mboxes = <&apcs_glb 26>; 592 593 qcom,local-pid = <0>; 594 qcom,remote-pid = <3>; 595 596 slpi_smp2p_out: master-kernel { 597 qcom,entry-name = "master-kernel"; 598 #qcom,smem-state-cells = <1>; 599 }; 600 601 slpi_smp2p_in: slave-kernel { 602 qcom,entry-name = "slave-kernel"; 603 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 }; 607 }; 608 609 soc: soc { 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges = <0 0 0 0xffffffff>; 613 compatible = "simple-bus"; 614 615 pcie_phy: phy-wrapper@34000 { 616 compatible = "qcom,msm8996-qmp-pcie-phy"; 617 reg = <0x00034000 0x488>; 618 #address-cells = <1>; 619 #size-cells = <1>; 620 ranges = <0x0 0x00034000 0x4000>; 621 622 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 623 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 624 <&gcc GCC_PCIE_CLKREF_CLK>; 625 clock-names = "aux", "cfg_ahb", "ref"; 626 627 resets = <&gcc GCC_PCIE_PHY_BCR>, 628 <&gcc GCC_PCIE_PHY_COM_BCR>, 629 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 630 reset-names = "phy", "common", "cfg"; 631 632 status = "disabled"; 633 634 pciephy_0: phy@1000 { 635 reg = <0x1000 0x130>, 636 <0x1200 0x200>, 637 <0x1400 0x1dc>; 638 639 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 640 clock-names = "pipe0"; 641 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 642 reset-names = "lane0"; 643 644 #clock-cells = <0>; 645 clock-output-names = "pcie_0_pipe_clk_src"; 646 647 #phy-cells = <0>; 648 }; 649 650 pciephy_1: phy@2000 { 651 reg = <0x2000 0x130>, 652 <0x2200 0x200>, 653 <0x2400 0x1dc>; 654 655 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 656 clock-names = "pipe1"; 657 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 658 reset-names = "lane1"; 659 660 #clock-cells = <0>; 661 clock-output-names = "pcie_1_pipe_clk_src"; 662 663 #phy-cells = <0>; 664 }; 665 666 pciephy_2: phy@3000 { 667 reg = <0x3000 0x130>, 668 <0x3200 0x200>, 669 <0x3400 0x1dc>; 670 671 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 672 clock-names = "pipe2"; 673 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 674 reset-names = "lane2"; 675 676 #clock-cells = <0>; 677 clock-output-names = "pcie_2_pipe_clk_src"; 678 679 #phy-cells = <0>; 680 }; 681 }; 682 683 rpm_msg_ram: sram@68000 { 684 compatible = "qcom,rpm-msg-ram"; 685 reg = <0x00068000 0x6000>; 686 }; 687 688 qfprom@74000 { 689 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 690 reg = <0x00074000 0x8ff>; 691 #address-cells = <1>; 692 #size-cells = <1>; 693 694 qusb2p_hstx_trim: hstx_trim@24e { 695 reg = <0x24e 0x2>; 696 bits = <5 4>; 697 }; 698 699 qusb2s_hstx_trim: hstx_trim@24f { 700 reg = <0x24f 0x1>; 701 bits = <1 4>; 702 }; 703 704 speedbin_efuse: speedbin@133 { 705 reg = <0x133 0x1>; 706 bits = <5 3>; 707 }; 708 }; 709 710 rng: rng@83000 { 711 compatible = "qcom,prng-ee"; 712 reg = <0x00083000 0x1000>; 713 clocks = <&gcc GCC_PRNG_AHB_CLK>; 714 clock-names = "core"; 715 }; 716 717 gcc: clock-controller@300000 { 718 compatible = "qcom,gcc-msm8996"; 719 #clock-cells = <1>; 720 #reset-cells = <1>; 721 #power-domain-cells = <1>; 722 reg = <0x00300000 0x90000>; 723 724 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 725 <&rpmcc RPM_SMD_LN_BB_CLK>, 726 <&sleep_clk>, 727 <&pciephy_0>, 728 <&pciephy_1>, 729 <&pciephy_2>, 730 <&ssusb_phy_0>, 731 <&ufsphy_lane 0>, 732 <&ufsphy_lane 1>, 733 <&ufsphy_lane 2>; 734 clock-names = "cxo", 735 "cxo2", 736 "sleep_clk", 737 "pcie_0_pipe_clk_src", 738 "pcie_1_pipe_clk_src", 739 "pcie_2_pipe_clk_src", 740 "usb3_phy_pipe_clk_src", 741 "ufs_rx_symbol_0_clk_src", 742 "ufs_rx_symbol_1_clk_src", 743 "ufs_tx_symbol_0_clk_src"; 744 }; 745 746 bimc: interconnect@408000 { 747 compatible = "qcom,msm8996-bimc"; 748 reg = <0x00408000 0x5a000>; 749 #interconnect-cells = <1>; 750 clock-names = "bus", "bus_a"; 751 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 752 <&rpmcc RPM_SMD_BIMC_A_CLK>; 753 }; 754 755 tsens0: thermal-sensor@4a9000 { 756 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 757 reg = <0x004a9000 0x1000>, /* TM */ 758 <0x004a8000 0x1000>; /* SROT */ 759 #qcom,sensors = <13>; 760 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-names = "uplow", "critical"; 763 #thermal-sensor-cells = <1>; 764 }; 765 766 tsens1: thermal-sensor@4ad000 { 767 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 768 reg = <0x004ad000 0x1000>, /* TM */ 769 <0x004ac000 0x1000>; /* SROT */ 770 #qcom,sensors = <8>; 771 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 773 interrupt-names = "uplow", "critical"; 774 #thermal-sensor-cells = <1>; 775 }; 776 777 cryptobam: dma-controller@644000 { 778 compatible = "qcom,bam-v1.7.0"; 779 reg = <0x00644000 0x24000>; 780 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&gcc GCC_CE1_CLK>; 782 clock-names = "bam_clk"; 783 #dma-cells = <1>; 784 qcom,ee = <0>; 785 qcom,controlled-remotely; 786 }; 787 788 crypto: crypto@67a000 { 789 compatible = "qcom,crypto-v5.4"; 790 reg = <0x0067a000 0x6000>; 791 clocks = <&gcc GCC_CE1_AHB_CLK>, 792 <&gcc GCC_CE1_AXI_CLK>, 793 <&gcc GCC_CE1_CLK>; 794 clock-names = "iface", "bus", "core"; 795 dmas = <&cryptobam 6>, <&cryptobam 7>; 796 dma-names = "rx", "tx"; 797 }; 798 799 cnoc: interconnect@500000 { 800 compatible = "qcom,msm8996-cnoc"; 801 reg = <0x00500000 0x1000>; 802 #interconnect-cells = <1>; 803 clock-names = "bus", "bus_a"; 804 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 805 <&rpmcc RPM_SMD_CNOC_A_CLK>; 806 }; 807 808 snoc: interconnect@524000 { 809 compatible = "qcom,msm8996-snoc"; 810 reg = <0x00524000 0x1c000>; 811 #interconnect-cells = <1>; 812 clock-names = "bus", "bus_a"; 813 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 814 <&rpmcc RPM_SMD_SNOC_A_CLK>; 815 }; 816 817 a0noc: interconnect@543000 { 818 compatible = "qcom,msm8996-a0noc"; 819 reg = <0x00543000 0x6000>; 820 #interconnect-cells = <1>; 821 clock-names = "aggre0_snoc_axi", 822 "aggre0_cnoc_ahb", 823 "aggre0_noc_mpu_cfg"; 824 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 825 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 826 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 827 power-domains = <&gcc AGGRE0_NOC_GDSC>; 828 }; 829 830 a1noc: interconnect@562000 { 831 compatible = "qcom,msm8996-a1noc"; 832 reg = <0x00562000 0x5000>; 833 #interconnect-cells = <1>; 834 clock-names = "bus", "bus_a"; 835 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 836 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 837 }; 838 839 a2noc: interconnect@583000 { 840 compatible = "qcom,msm8996-a2noc"; 841 reg = <0x00583000 0x7000>; 842 #interconnect-cells = <1>; 843 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; 844 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 845 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 846 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 847 <&gcc GCC_UFS_AXI_CLK>; 848 }; 849 850 mnoc: interconnect@5a4000 { 851 compatible = "qcom,msm8996-mnoc"; 852 reg = <0x005a4000 0x1c000>; 853 #interconnect-cells = <1>; 854 clock-names = "bus", "bus_a", "iface"; 855 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 856 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 857 <&mmcc AHB_CLK_SRC>; 858 }; 859 860 pnoc: interconnect@5c0000 { 861 compatible = "qcom,msm8996-pnoc"; 862 reg = <0x005c0000 0x3000>; 863 #interconnect-cells = <1>; 864 clock-names = "bus", "bus_a"; 865 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 866 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 867 }; 868 869 tcsr_mutex: hwlock@740000 { 870 compatible = "qcom,tcsr-mutex"; 871 reg = <0x00740000 0x20000>; 872 #hwlock-cells = <1>; 873 }; 874 875 tcsr_1: syscon@760000 { 876 compatible = "qcom,tcsr-msm8996", "syscon"; 877 reg = <0x00760000 0x20000>; 878 }; 879 880 tcsr_2: syscon@7a0000 { 881 compatible = "qcom,tcsr-msm8996", "syscon"; 882 reg = <0x007a0000 0x18000>; 883 }; 884 885 mmcc: clock-controller@8c0000 { 886 compatible = "qcom,mmcc-msm8996"; 887 #clock-cells = <1>; 888 #reset-cells = <1>; 889 #power-domain-cells = <1>; 890 reg = <0x008c0000 0x40000>; 891 clocks = <&xo_board>, 892 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 893 <&gcc GPLL0>, 894 <&dsi0_phy 1>, 895 <&dsi0_phy 0>, 896 <&dsi1_phy 1>, 897 <&dsi1_phy 0>, 898 <&hdmi_phy>; 899 clock-names = "xo", 900 "gcc_mmss_noc_cfg_ahb_clk", 901 "gpll0", 902 "dsi0pll", 903 "dsi0pllbyte", 904 "dsi1pll", 905 "dsi1pllbyte", 906 "hdmipll"; 907 assigned-clocks = <&mmcc MMPLL9_PLL>, 908 <&mmcc MMPLL1_PLL>, 909 <&mmcc MMPLL3_PLL>, 910 <&mmcc MMPLL4_PLL>, 911 <&mmcc MMPLL5_PLL>; 912 assigned-clock-rates = <624000000>, 913 <810000000>, 914 <980000000>, 915 <960000000>, 916 <825000000>; 917 }; 918 919 mdss: display-subsystem@900000 { 920 compatible = "qcom,mdss"; 921 922 reg = <0x00900000 0x1000>, 923 <0x009b0000 0x1040>, 924 <0x009b8000 0x1040>; 925 reg-names = "mdss_phys", 926 "vbif_phys", 927 "vbif_nrt_phys"; 928 929 power-domains = <&mmcc MDSS_GDSC>; 930 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 931 932 interrupt-controller; 933 #interrupt-cells = <1>; 934 935 clocks = <&mmcc MDSS_AHB_CLK>, 936 <&mmcc MDSS_MDP_CLK>; 937 clock-names = "iface", "core"; 938 939 #address-cells = <1>; 940 #size-cells = <1>; 941 ranges; 942 943 status = "disabled"; 944 945 mdp: display-controller@901000 { 946 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 947 reg = <0x00901000 0x90000>; 948 reg-names = "mdp_phys"; 949 950 interrupt-parent = <&mdss>; 951 interrupts = <0>; 952 953 clocks = <&mmcc MDSS_AHB_CLK>, 954 <&mmcc MDSS_AXI_CLK>, 955 <&mmcc MDSS_MDP_CLK>, 956 <&mmcc SMMU_MDP_AXI_CLK>, 957 <&mmcc MDSS_VSYNC_CLK>; 958 clock-names = "iface", 959 "bus", 960 "core", 961 "iommu", 962 "vsync"; 963 964 iommus = <&mdp_smmu 0>; 965 966 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 967 <&mmcc MDSS_VSYNC_CLK>; 968 assigned-clock-rates = <300000000>, 969 <19200000>; 970 971 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 972 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 973 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 974 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 975 976 ports { 977 #address-cells = <1>; 978 #size-cells = <0>; 979 980 port@0 { 981 reg = <0>; 982 mdp5_intf3_out: endpoint { 983 remote-endpoint = <&hdmi_in>; 984 }; 985 }; 986 987 port@1 { 988 reg = <1>; 989 mdp5_intf1_out: endpoint { 990 remote-endpoint = <&dsi0_in>; 991 }; 992 }; 993 994 port@2 { 995 reg = <2>; 996 mdp5_intf2_out: endpoint { 997 remote-endpoint = <&dsi1_in>; 998 }; 999 }; 1000 }; 1001 }; 1002 1003 dsi0: dsi@994000 { 1004 compatible = "qcom,msm8996-dsi-ctrl", 1005 "qcom,mdss-dsi-ctrl"; 1006 reg = <0x00994000 0x400>; 1007 reg-names = "dsi_ctrl"; 1008 1009 interrupt-parent = <&mdss>; 1010 interrupts = <4>; 1011 1012 clocks = <&mmcc MDSS_MDP_CLK>, 1013 <&mmcc MDSS_BYTE0_CLK>, 1014 <&mmcc MDSS_AHB_CLK>, 1015 <&mmcc MDSS_AXI_CLK>, 1016 <&mmcc MMSS_MISC_AHB_CLK>, 1017 <&mmcc MDSS_PCLK0_CLK>, 1018 <&mmcc MDSS_ESC0_CLK>; 1019 clock-names = "mdp_core", 1020 "byte", 1021 "iface", 1022 "bus", 1023 "core_mmss", 1024 "pixel", 1025 "core"; 1026 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1027 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1028 1029 phys = <&dsi0_phy>; 1030 status = "disabled"; 1031 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 ports { 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 1039 port@0 { 1040 reg = <0>; 1041 dsi0_in: endpoint { 1042 remote-endpoint = <&mdp5_intf1_out>; 1043 }; 1044 }; 1045 1046 port@1 { 1047 reg = <1>; 1048 dsi0_out: endpoint { 1049 }; 1050 }; 1051 }; 1052 }; 1053 1054 dsi0_phy: phy@994400 { 1055 compatible = "qcom,dsi-phy-14nm"; 1056 reg = <0x00994400 0x100>, 1057 <0x00994500 0x300>, 1058 <0x00994800 0x188>; 1059 reg-names = "dsi_phy", 1060 "dsi_phy_lane", 1061 "dsi_pll"; 1062 1063 #clock-cells = <1>; 1064 #phy-cells = <0>; 1065 1066 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1067 clock-names = "iface", "ref"; 1068 status = "disabled"; 1069 }; 1070 1071 dsi1: dsi@996000 { 1072 compatible = "qcom,msm8996-dsi-ctrl", 1073 "qcom,mdss-dsi-ctrl"; 1074 reg = <0x00996000 0x400>; 1075 reg-names = "dsi_ctrl"; 1076 1077 interrupt-parent = <&mdss>; 1078 interrupts = <4>; 1079 1080 clocks = <&mmcc MDSS_MDP_CLK>, 1081 <&mmcc MDSS_BYTE1_CLK>, 1082 <&mmcc MDSS_AHB_CLK>, 1083 <&mmcc MDSS_AXI_CLK>, 1084 <&mmcc MMSS_MISC_AHB_CLK>, 1085 <&mmcc MDSS_PCLK1_CLK>, 1086 <&mmcc MDSS_ESC1_CLK>; 1087 clock-names = "mdp_core", 1088 "byte", 1089 "iface", 1090 "bus", 1091 "core_mmss", 1092 "pixel", 1093 "core"; 1094 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1095 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 1096 1097 phys = <&dsi1_phy>; 1098 status = "disabled"; 1099 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 1103 ports { 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 1107 port@0 { 1108 reg = <0>; 1109 dsi1_in: endpoint { 1110 remote-endpoint = <&mdp5_intf2_out>; 1111 }; 1112 }; 1113 1114 port@1 { 1115 reg = <1>; 1116 dsi1_out: endpoint { 1117 }; 1118 }; 1119 }; 1120 }; 1121 1122 dsi1_phy: phy@996400 { 1123 compatible = "qcom,dsi-phy-14nm"; 1124 reg = <0x00996400 0x100>, 1125 <0x00996500 0x300>, 1126 <0x00996800 0x188>; 1127 reg-names = "dsi_phy", 1128 "dsi_phy_lane", 1129 "dsi_pll"; 1130 1131 #clock-cells = <1>; 1132 #phy-cells = <0>; 1133 1134 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1135 clock-names = "iface", "ref"; 1136 status = "disabled"; 1137 }; 1138 1139 hdmi: hdmi-tx@9a0000 { 1140 compatible = "qcom,hdmi-tx-8996"; 1141 reg = <0x009a0000 0x50c>, 1142 <0x00070000 0x6158>, 1143 <0x009e0000 0xfff>; 1144 reg-names = "core_physical", 1145 "qfprom_physical", 1146 "hdcp_physical"; 1147 1148 interrupt-parent = <&mdss>; 1149 interrupts = <8>; 1150 1151 clocks = <&mmcc MDSS_MDP_CLK>, 1152 <&mmcc MDSS_AHB_CLK>, 1153 <&mmcc MDSS_HDMI_CLK>, 1154 <&mmcc MDSS_HDMI_AHB_CLK>, 1155 <&mmcc MDSS_EXTPCLK_CLK>; 1156 clock-names = 1157 "mdp_core", 1158 "iface", 1159 "core", 1160 "alt_iface", 1161 "extp"; 1162 1163 phys = <&hdmi_phy>; 1164 #sound-dai-cells = <1>; 1165 1166 status = "disabled"; 1167 1168 ports { 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 1172 port@0 { 1173 reg = <0>; 1174 hdmi_in: endpoint { 1175 remote-endpoint = <&mdp5_intf3_out>; 1176 }; 1177 }; 1178 }; 1179 }; 1180 1181 hdmi_phy: phy@9a0600 { 1182 #phy-cells = <0>; 1183 compatible = "qcom,hdmi-phy-8996"; 1184 reg = <0x009a0600 0x1c4>, 1185 <0x009a0a00 0x124>, 1186 <0x009a0c00 0x124>, 1187 <0x009a0e00 0x124>, 1188 <0x009a1000 0x124>, 1189 <0x009a1200 0x0c8>; 1190 reg-names = "hdmi_pll", 1191 "hdmi_tx_l0", 1192 "hdmi_tx_l1", 1193 "hdmi_tx_l2", 1194 "hdmi_tx_l3", 1195 "hdmi_phy"; 1196 1197 clocks = <&mmcc MDSS_AHB_CLK>, 1198 <&gcc GCC_HDMI_CLKREF_CLK>, 1199 <&xo_board>; 1200 clock-names = "iface", 1201 "ref", 1202 "xo"; 1203 1204 #clock-cells = <0>; 1205 1206 status = "disabled"; 1207 }; 1208 }; 1209 1210 gpu: gpu@b00000 { 1211 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1212 1213 reg = <0x00b00000 0x3f000>; 1214 reg-names = "kgsl_3d0_reg_memory"; 1215 1216 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1217 1218 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1219 <&mmcc GPU_AHB_CLK>, 1220 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1221 <&gcc GCC_BIMC_GFX_CLK>, 1222 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1223 1224 clock-names = "core", 1225 "iface", 1226 "rbbmtimer", 1227 "mem", 1228 "mem_iface"; 1229 1230 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1231 interconnect-names = "gfx-mem"; 1232 1233 power-domains = <&mmcc GPU_GX_GDSC>; 1234 iommus = <&adreno_smmu 0>; 1235 1236 nvmem-cells = <&speedbin_efuse>; 1237 nvmem-cell-names = "speed_bin"; 1238 1239 operating-points-v2 = <&gpu_opp_table>; 1240 1241 status = "disabled"; 1242 1243 #cooling-cells = <2>; 1244 1245 gpu_opp_table: opp-table { 1246 compatible = "operating-points-v2"; 1247 1248 /* 1249 * 624Mhz is only available on speed bins 0 and 3. 1250 * 560Mhz is only available on speed bins 0, 2 and 3. 1251 * All the rest are available on all bins of the hardware. 1252 */ 1253 opp-624000000 { 1254 opp-hz = /bits/ 64 <624000000>; 1255 opp-supported-hw = <0x09>; 1256 }; 1257 opp-560000000 { 1258 opp-hz = /bits/ 64 <560000000>; 1259 opp-supported-hw = <0x0d>; 1260 }; 1261 opp-510000000 { 1262 opp-hz = /bits/ 64 <510000000>; 1263 opp-supported-hw = <0xff>; 1264 }; 1265 opp-401800000 { 1266 opp-hz = /bits/ 64 <401800000>; 1267 opp-supported-hw = <0xff>; 1268 }; 1269 opp-315000000 { 1270 opp-hz = /bits/ 64 <315000000>; 1271 opp-supported-hw = <0xff>; 1272 }; 1273 opp-214000000 { 1274 opp-hz = /bits/ 64 <214000000>; 1275 opp-supported-hw = <0xff>; 1276 }; 1277 opp-133000000 { 1278 opp-hz = /bits/ 64 <133000000>; 1279 opp-supported-hw = <0xff>; 1280 }; 1281 }; 1282 1283 zap-shader { 1284 memory-region = <&gpu_mem>; 1285 }; 1286 }; 1287 1288 tlmm: pinctrl@1010000 { 1289 compatible = "qcom,msm8996-pinctrl"; 1290 reg = <0x01010000 0x300000>; 1291 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1292 gpio-controller; 1293 gpio-ranges = <&tlmm 0 0 150>; 1294 #gpio-cells = <2>; 1295 interrupt-controller; 1296 #interrupt-cells = <2>; 1297 1298 blsp1_spi1_default: blsp1-spi1-default-state { 1299 spi-pins { 1300 pins = "gpio0", "gpio1", "gpio3"; 1301 function = "blsp_spi1"; 1302 drive-strength = <12>; 1303 bias-disable; 1304 }; 1305 1306 cs-pins { 1307 pins = "gpio2"; 1308 function = "gpio"; 1309 drive-strength = <16>; 1310 bias-disable; 1311 output-high; 1312 }; 1313 }; 1314 1315 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1316 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1317 function = "gpio"; 1318 drive-strength = <2>; 1319 bias-pull-down; 1320 }; 1321 1322 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1323 pins = "gpio4", "gpio5"; 1324 function = "blsp_uart8"; 1325 drive-strength = <16>; 1326 bias-disable; 1327 }; 1328 1329 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1330 pins = "gpio4", "gpio5"; 1331 function = "gpio"; 1332 drive-strength = <2>; 1333 bias-disable; 1334 }; 1335 1336 blsp2_i2c2_default: blsp2-i2c2-state { 1337 pins = "gpio6", "gpio7"; 1338 function = "blsp_i2c8"; 1339 drive-strength = <16>; 1340 bias-disable; 1341 }; 1342 1343 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1344 pins = "gpio6", "gpio7"; 1345 function = "gpio"; 1346 drive-strength = <2>; 1347 bias-disable; 1348 }; 1349 1350 blsp1_i2c6_default: blsp1-i2c6-state { 1351 pins = "gpio27", "gpio28"; 1352 function = "blsp_i2c6"; 1353 drive-strength = <16>; 1354 bias-disable; 1355 }; 1356 1357 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1358 pins = "gpio27", "gpio28"; 1359 function = "gpio"; 1360 drive-strength = <2>; 1361 bias-pull-up; 1362 }; 1363 1364 cci0_default: cci0-default-state { 1365 pins = "gpio17", "gpio18"; 1366 function = "cci_i2c"; 1367 drive-strength = <16>; 1368 bias-disable; 1369 }; 1370 1371 camera0_state_on: 1372 camera_rear_default: camera-rear-default-state { 1373 camera0_mclk: mclk0-pins { 1374 pins = "gpio13"; 1375 function = "cam_mclk"; 1376 drive-strength = <16>; 1377 bias-disable; 1378 }; 1379 1380 camera0_rst: rst-pins { 1381 pins = "gpio25"; 1382 function = "gpio"; 1383 drive-strength = <16>; 1384 bias-disable; 1385 }; 1386 1387 camera0_pwdn: pwdn-pins { 1388 pins = "gpio26"; 1389 function = "gpio"; 1390 drive-strength = <16>; 1391 bias-disable; 1392 }; 1393 }; 1394 1395 cci1_default: cci1-default-state { 1396 pins = "gpio19", "gpio20"; 1397 function = "cci_i2c"; 1398 drive-strength = <16>; 1399 bias-disable; 1400 }; 1401 1402 camera1_state_on: 1403 camera_board_default: camera-board-default-state { 1404 mclk1-pins { 1405 pins = "gpio14"; 1406 function = "cam_mclk"; 1407 drive-strength = <16>; 1408 bias-disable; 1409 }; 1410 1411 pwdn-pins { 1412 pins = "gpio98"; 1413 function = "gpio"; 1414 drive-strength = <16>; 1415 bias-disable; 1416 }; 1417 1418 rst-pins { 1419 pins = "gpio104"; 1420 function = "gpio"; 1421 drive-strength = <16>; 1422 bias-disable; 1423 }; 1424 }; 1425 1426 camera2_state_on: 1427 camera_front_default: camera-front-default-state { 1428 camera2_mclk: mclk2-pins { 1429 pins = "gpio15"; 1430 function = "cam_mclk"; 1431 drive-strength = <16>; 1432 bias-disable; 1433 }; 1434 1435 camera2_rst: rst-pins { 1436 pins = "gpio23"; 1437 function = "gpio"; 1438 drive-strength = <16>; 1439 bias-disable; 1440 }; 1441 1442 pwdn-pins { 1443 pins = "gpio133"; 1444 function = "gpio"; 1445 drive-strength = <16>; 1446 bias-disable; 1447 }; 1448 }; 1449 1450 pcie0_state_on: pcie0-state-on-state { 1451 perst-pins { 1452 pins = "gpio35"; 1453 function = "gpio"; 1454 drive-strength = <2>; 1455 bias-pull-down; 1456 }; 1457 1458 clkreq-pins { 1459 pins = "gpio36"; 1460 function = "pci_e0"; 1461 drive-strength = <2>; 1462 bias-pull-up; 1463 }; 1464 1465 wake-pins { 1466 pins = "gpio37"; 1467 function = "gpio"; 1468 drive-strength = <2>; 1469 bias-pull-up; 1470 }; 1471 }; 1472 1473 pcie0_state_off: pcie0-state-off-state { 1474 perst-pins { 1475 pins = "gpio35"; 1476 function = "gpio"; 1477 drive-strength = <2>; 1478 bias-pull-down; 1479 }; 1480 1481 clkreq-pins { 1482 pins = "gpio36"; 1483 function = "gpio"; 1484 drive-strength = <2>; 1485 bias-disable; 1486 }; 1487 1488 wake-pins { 1489 pins = "gpio37"; 1490 function = "gpio"; 1491 drive-strength = <2>; 1492 bias-disable; 1493 }; 1494 }; 1495 1496 blsp1_uart2_default: blsp1-uart2-default-state { 1497 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1498 function = "blsp_uart2"; 1499 drive-strength = <16>; 1500 bias-disable; 1501 }; 1502 1503 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1504 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1505 function = "gpio"; 1506 drive-strength = <2>; 1507 bias-disable; 1508 }; 1509 1510 blsp1_i2c3_default: blsp1-i2c3-default-state { 1511 pins = "gpio47", "gpio48"; 1512 function = "blsp_i2c3"; 1513 drive-strength = <16>; 1514 bias-disable; 1515 }; 1516 1517 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1518 pins = "gpio47", "gpio48"; 1519 function = "gpio"; 1520 drive-strength = <2>; 1521 bias-disable; 1522 }; 1523 1524 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1525 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1526 function = "blsp_uart9"; 1527 drive-strength = <16>; 1528 bias-disable; 1529 }; 1530 1531 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1532 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1533 function = "blsp_uart9"; 1534 drive-strength = <2>; 1535 bias-disable; 1536 }; 1537 1538 blsp2_i2c3_default: blsp2-i2c3-state-state { 1539 pins = "gpio51", "gpio52"; 1540 function = "blsp_i2c9"; 1541 drive-strength = <16>; 1542 bias-disable; 1543 }; 1544 1545 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1546 pins = "gpio51", "gpio52"; 1547 function = "gpio"; 1548 drive-strength = <2>; 1549 bias-disable; 1550 }; 1551 1552 wcd_intr_default: wcd-intr-default-state { 1553 pins = "gpio54"; 1554 function = "gpio"; 1555 drive-strength = <2>; 1556 bias-pull-down; 1557 }; 1558 1559 blsp2_i2c1_default: blsp2-i2c1-state { 1560 pins = "gpio55", "gpio56"; 1561 function = "blsp_i2c7"; 1562 drive-strength = <16>; 1563 bias-disable; 1564 }; 1565 1566 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1567 pins = "gpio55", "gpio56"; 1568 function = "gpio"; 1569 drive-strength = <2>; 1570 bias-disable; 1571 }; 1572 1573 blsp2_i2c5_default: blsp2-i2c5-state { 1574 pins = "gpio60", "gpio61"; 1575 function = "blsp_i2c11"; 1576 drive-strength = <2>; 1577 bias-disable; 1578 }; 1579 1580 /* Sleep state for BLSP2_I2C5 is missing.. */ 1581 1582 cdc_reset_active: cdc-reset-active-state { 1583 pins = "gpio64"; 1584 function = "gpio"; 1585 drive-strength = <16>; 1586 bias-pull-down; 1587 output-high; 1588 }; 1589 1590 cdc_reset_sleep: cdc-reset-sleep-state { 1591 pins = "gpio64"; 1592 function = "gpio"; 1593 drive-strength = <16>; 1594 bias-disable; 1595 output-low; 1596 }; 1597 1598 blsp2_spi6_default: blsp2-spi6-default-state { 1599 spi-pins { 1600 pins = "gpio85", "gpio86", "gpio88"; 1601 function = "blsp_spi12"; 1602 drive-strength = <12>; 1603 bias-disable; 1604 }; 1605 1606 cs-pins { 1607 pins = "gpio87"; 1608 function = "gpio"; 1609 drive-strength = <16>; 1610 bias-disable; 1611 output-high; 1612 }; 1613 }; 1614 1615 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1616 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1617 function = "gpio"; 1618 drive-strength = <2>; 1619 bias-pull-down; 1620 }; 1621 1622 blsp2_i2c6_default: blsp2-i2c6-state { 1623 pins = "gpio87", "gpio88"; 1624 function = "blsp_i2c12"; 1625 drive-strength = <16>; 1626 bias-disable; 1627 }; 1628 1629 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1630 pins = "gpio87", "gpio88"; 1631 function = "gpio"; 1632 drive-strength = <2>; 1633 bias-disable; 1634 }; 1635 1636 pcie1_state_on: pcie1-on-state { 1637 perst-pins { 1638 pins = "gpio130"; 1639 function = "gpio"; 1640 drive-strength = <2>; 1641 bias-pull-down; 1642 }; 1643 1644 clkreq-pins { 1645 pins = "gpio131"; 1646 function = "pci_e1"; 1647 drive-strength = <2>; 1648 bias-pull-up; 1649 }; 1650 1651 wake-pins { 1652 pins = "gpio132"; 1653 function = "gpio"; 1654 drive-strength = <2>; 1655 bias-pull-down; 1656 }; 1657 }; 1658 1659 pcie1_state_off: pcie1-off-state { 1660 /* Perst is missing? */ 1661 clkreq-pins { 1662 pins = "gpio131"; 1663 function = "gpio"; 1664 drive-strength = <2>; 1665 bias-disable; 1666 }; 1667 1668 wake-pins { 1669 pins = "gpio132"; 1670 function = "gpio"; 1671 drive-strength = <2>; 1672 bias-disable; 1673 }; 1674 }; 1675 1676 pcie2_state_on: pcie2-on-state { 1677 perst-pins { 1678 pins = "gpio114"; 1679 function = "gpio"; 1680 drive-strength = <2>; 1681 bias-pull-down; 1682 }; 1683 1684 clkreq-pins { 1685 pins = "gpio115"; 1686 function = "pci_e2"; 1687 drive-strength = <2>; 1688 bias-pull-up; 1689 }; 1690 1691 wake-pins { 1692 pins = "gpio116"; 1693 function = "gpio"; 1694 drive-strength = <2>; 1695 bias-pull-down; 1696 }; 1697 }; 1698 1699 pcie2_state_off: pcie2-off-state { 1700 /* Perst is missing? */ 1701 clkreq-pins { 1702 pins = "gpio115"; 1703 function = "gpio"; 1704 drive-strength = <2>; 1705 bias-disable; 1706 }; 1707 1708 wake-pins { 1709 pins = "gpio116"; 1710 function = "gpio"; 1711 drive-strength = <2>; 1712 bias-disable; 1713 }; 1714 }; 1715 1716 sdc1_state_on: sdc1-on-state { 1717 clk-pins { 1718 pins = "sdc1_clk"; 1719 bias-disable; 1720 drive-strength = <16>; 1721 }; 1722 1723 cmd-pins { 1724 pins = "sdc1_cmd"; 1725 bias-pull-up; 1726 drive-strength = <10>; 1727 }; 1728 1729 data-pins { 1730 pins = "sdc1_data"; 1731 bias-pull-up; 1732 drive-strength = <10>; 1733 }; 1734 1735 rclk-pins { 1736 pins = "sdc1_rclk"; 1737 bias-pull-down; 1738 }; 1739 }; 1740 1741 sdc1_state_off: sdc1-off-state { 1742 clk-pins { 1743 pins = "sdc1_clk"; 1744 bias-disable; 1745 drive-strength = <2>; 1746 }; 1747 1748 cmd-pins { 1749 pins = "sdc1_cmd"; 1750 bias-pull-up; 1751 drive-strength = <2>; 1752 }; 1753 1754 data-pins { 1755 pins = "sdc1_data"; 1756 bias-pull-up; 1757 drive-strength = <2>; 1758 }; 1759 1760 rclk-pins { 1761 pins = "sdc1_rclk"; 1762 bias-pull-down; 1763 }; 1764 }; 1765 1766 sdc2_state_on: sdc2-on-state { 1767 clk-pins { 1768 pins = "sdc2_clk"; 1769 bias-disable; 1770 drive-strength = <16>; 1771 }; 1772 1773 cmd-pins { 1774 pins = "sdc2_cmd"; 1775 bias-pull-up; 1776 drive-strength = <10>; 1777 }; 1778 1779 data-pins { 1780 pins = "sdc2_data"; 1781 bias-pull-up; 1782 drive-strength = <10>; 1783 }; 1784 }; 1785 1786 sdc2_state_off: sdc2-off-state { 1787 clk-pins { 1788 pins = "sdc2_clk"; 1789 bias-disable; 1790 drive-strength = <2>; 1791 }; 1792 1793 cmd-pins { 1794 pins = "sdc2_cmd"; 1795 bias-pull-up; 1796 drive-strength = <2>; 1797 }; 1798 1799 data-pins { 1800 pins = "sdc2_data"; 1801 bias-pull-up; 1802 drive-strength = <2>; 1803 }; 1804 }; 1805 }; 1806 1807 sram@290000 { 1808 compatible = "qcom,rpm-stats"; 1809 reg = <0x00290000 0x10000>; 1810 }; 1811 1812 spmi_bus: spmi@400f000 { 1813 compatible = "qcom,spmi-pmic-arb"; 1814 reg = <0x0400f000 0x1000>, 1815 <0x04400000 0x800000>, 1816 <0x04c00000 0x800000>, 1817 <0x05800000 0x200000>, 1818 <0x0400a000 0x002100>; 1819 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1820 interrupt-names = "periph_irq"; 1821 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1822 qcom,ee = <0>; 1823 qcom,channel = <0>; 1824 #address-cells = <2>; 1825 #size-cells = <0>; 1826 interrupt-controller; 1827 #interrupt-cells = <4>; 1828 }; 1829 1830 bus@0 { 1831 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1832 compatible = "simple-pm-bus"; 1833 #address-cells = <1>; 1834 #size-cells = <1>; 1835 ranges; 1836 1837 pcie0: pcie@600000 { 1838 compatible = "qcom,pcie-msm8996"; 1839 status = "disabled"; 1840 power-domains = <&gcc PCIE0_GDSC>; 1841 bus-range = <0x00 0xff>; 1842 num-lanes = <1>; 1843 1844 reg = <0x00600000 0x2000>, 1845 <0x0c000000 0xf1d>, 1846 <0x0c000f20 0xa8>, 1847 <0x0c100000 0x100000>; 1848 reg-names = "parf", "dbi", "elbi","config"; 1849 1850 phys = <&pciephy_0>; 1851 phy-names = "pciephy"; 1852 1853 #address-cells = <3>; 1854 #size-cells = <2>; 1855 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 1856 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1857 1858 device_type = "pci"; 1859 1860 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1861 interrupt-names = "msi"; 1862 #interrupt-cells = <1>; 1863 interrupt-map-mask = <0 0 0 0x7>; 1864 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1865 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1866 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1867 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1868 1869 pinctrl-names = "default", "sleep"; 1870 pinctrl-0 = <&pcie0_state_on>; 1871 pinctrl-1 = <&pcie0_state_off>; 1872 1873 linux,pci-domain = <0>; 1874 1875 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1876 <&gcc GCC_PCIE_0_AUX_CLK>, 1877 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1878 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1879 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1880 1881 clock-names = "pipe", 1882 "aux", 1883 "cfg", 1884 "bus_master", 1885 "bus_slave"; 1886 }; 1887 1888 pcie1: pcie@608000 { 1889 compatible = "qcom,pcie-msm8996"; 1890 power-domains = <&gcc PCIE1_GDSC>; 1891 bus-range = <0x00 0xff>; 1892 num-lanes = <1>; 1893 1894 status = "disabled"; 1895 1896 reg = <0x00608000 0x2000>, 1897 <0x0d000000 0xf1d>, 1898 <0x0d000f20 0xa8>, 1899 <0x0d100000 0x100000>; 1900 1901 reg-names = "parf", "dbi", "elbi","config"; 1902 1903 phys = <&pciephy_1>; 1904 phy-names = "pciephy"; 1905 1906 #address-cells = <3>; 1907 #size-cells = <2>; 1908 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 1909 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1910 1911 device_type = "pci"; 1912 1913 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1914 interrupt-names = "msi"; 1915 #interrupt-cells = <1>; 1916 interrupt-map-mask = <0 0 0 0x7>; 1917 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1918 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1919 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1920 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1921 1922 pinctrl-names = "default", "sleep"; 1923 pinctrl-0 = <&pcie1_state_on>; 1924 pinctrl-1 = <&pcie1_state_off>; 1925 1926 linux,pci-domain = <1>; 1927 1928 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1929 <&gcc GCC_PCIE_1_AUX_CLK>, 1930 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1931 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1932 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1933 1934 clock-names = "pipe", 1935 "aux", 1936 "cfg", 1937 "bus_master", 1938 "bus_slave"; 1939 }; 1940 1941 pcie2: pcie@610000 { 1942 compatible = "qcom,pcie-msm8996"; 1943 power-domains = <&gcc PCIE2_GDSC>; 1944 bus-range = <0x00 0xff>; 1945 num-lanes = <1>; 1946 status = "disabled"; 1947 reg = <0x00610000 0x2000>, 1948 <0x0e000000 0xf1d>, 1949 <0x0e000f20 0xa8>, 1950 <0x0e100000 0x100000>; 1951 1952 reg-names = "parf", "dbi", "elbi","config"; 1953 1954 phys = <&pciephy_2>; 1955 phy-names = "pciephy"; 1956 1957 #address-cells = <3>; 1958 #size-cells = <2>; 1959 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 1960 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1961 1962 device_type = "pci"; 1963 1964 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1965 interrupt-names = "msi"; 1966 #interrupt-cells = <1>; 1967 interrupt-map-mask = <0 0 0 0x7>; 1968 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1969 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1970 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1971 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1972 1973 pinctrl-names = "default", "sleep"; 1974 pinctrl-0 = <&pcie2_state_on>; 1975 pinctrl-1 = <&pcie2_state_off>; 1976 1977 linux,pci-domain = <2>; 1978 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1979 <&gcc GCC_PCIE_2_AUX_CLK>, 1980 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1981 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1982 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1983 1984 clock-names = "pipe", 1985 "aux", 1986 "cfg", 1987 "bus_master", 1988 "bus_slave"; 1989 }; 1990 }; 1991 1992 ufshc: ufshc@624000 { 1993 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 1994 "jedec,ufs-2.0"; 1995 reg = <0x00624000 0x2500>; 1996 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1997 1998 phys = <&ufsphy_lane>; 1999 phy-names = "ufsphy"; 2000 2001 power-domains = <&gcc UFS_GDSC>; 2002 2003 clock-names = 2004 "core_clk_src", 2005 "core_clk", 2006 "bus_clk", 2007 "bus_aggr_clk", 2008 "iface_clk", 2009 "core_clk_unipro_src", 2010 "core_clk_unipro", 2011 "core_clk_ice", 2012 "ref_clk", 2013 "tx_lane0_sync_clk", 2014 "rx_lane0_sync_clk"; 2015 clocks = 2016 <&gcc UFS_AXI_CLK_SRC>, 2017 <&gcc GCC_UFS_AXI_CLK>, 2018 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2019 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2020 <&gcc GCC_UFS_AHB_CLK>, 2021 <&gcc UFS_ICE_CORE_CLK_SRC>, 2022 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2023 <&gcc GCC_UFS_ICE_CORE_CLK>, 2024 <&rpmcc RPM_SMD_LN_BB_CLK>, 2025 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2026 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2027 freq-table-hz = 2028 <100000000 200000000>, 2029 <0 0>, 2030 <0 0>, 2031 <0 0>, 2032 <0 0>, 2033 <150000000 300000000>, 2034 <0 0>, 2035 <0 0>, 2036 <0 0>, 2037 <0 0>, 2038 <0 0>; 2039 2040 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2041 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2042 interconnect-names = "ufs-ddr", "cpu-ufs"; 2043 2044 lanes-per-direction = <1>; 2045 #reset-cells = <1>; 2046 status = "disabled"; 2047 }; 2048 2049 ufsphy: phy@627000 { 2050 compatible = "qcom,msm8996-qmp-ufs-phy"; 2051 reg = <0x00627000 0x1c4>; 2052 #address-cells = <1>; 2053 #size-cells = <1>; 2054 ranges; 2055 2056 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2057 clock-names = "ref"; 2058 2059 resets = <&ufshc 0>; 2060 reset-names = "ufsphy"; 2061 status = "disabled"; 2062 2063 ufsphy_lane: phy@627400 { 2064 reg = <0x627400 0x12c>, 2065 <0x627600 0x200>, 2066 <0x627c00 0x1b4>; 2067 #clock-cells = <1>; 2068 #phy-cells = <0>; 2069 }; 2070 }; 2071 2072 camss: camss@a00000 { 2073 compatible = "qcom,msm8996-camss"; 2074 reg = <0x00a34000 0x1000>, 2075 <0x00a00030 0x4>, 2076 <0x00a35000 0x1000>, 2077 <0x00a00038 0x4>, 2078 <0x00a36000 0x1000>, 2079 <0x00a00040 0x4>, 2080 <0x00a30000 0x100>, 2081 <0x00a30400 0x100>, 2082 <0x00a30800 0x100>, 2083 <0x00a30c00 0x100>, 2084 <0x00a31000 0x500>, 2085 <0x00a00020 0x10>, 2086 <0x00a10000 0x1000>, 2087 <0x00a14000 0x1000>; 2088 reg-names = "csiphy0", 2089 "csiphy0_clk_mux", 2090 "csiphy1", 2091 "csiphy1_clk_mux", 2092 "csiphy2", 2093 "csiphy2_clk_mux", 2094 "csid0", 2095 "csid1", 2096 "csid2", 2097 "csid3", 2098 "ispif", 2099 "csi_clk_mux", 2100 "vfe0", 2101 "vfe1"; 2102 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2103 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2104 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2105 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2106 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2107 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2108 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2109 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2110 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2111 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2112 interrupt-names = "csiphy0", 2113 "csiphy1", 2114 "csiphy2", 2115 "csid0", 2116 "csid1", 2117 "csid2", 2118 "csid3", 2119 "ispif", 2120 "vfe0", 2121 "vfe1"; 2122 power-domains = <&mmcc VFE0_GDSC>, 2123 <&mmcc VFE1_GDSC>; 2124 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2125 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2126 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2127 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2128 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2129 <&mmcc CAMSS_CSI0_AHB_CLK>, 2130 <&mmcc CAMSS_CSI0_CLK>, 2131 <&mmcc CAMSS_CSI0PHY_CLK>, 2132 <&mmcc CAMSS_CSI0PIX_CLK>, 2133 <&mmcc CAMSS_CSI0RDI_CLK>, 2134 <&mmcc CAMSS_CSI1_AHB_CLK>, 2135 <&mmcc CAMSS_CSI1_CLK>, 2136 <&mmcc CAMSS_CSI1PHY_CLK>, 2137 <&mmcc CAMSS_CSI1PIX_CLK>, 2138 <&mmcc CAMSS_CSI1RDI_CLK>, 2139 <&mmcc CAMSS_CSI2_AHB_CLK>, 2140 <&mmcc CAMSS_CSI2_CLK>, 2141 <&mmcc CAMSS_CSI2PHY_CLK>, 2142 <&mmcc CAMSS_CSI2PIX_CLK>, 2143 <&mmcc CAMSS_CSI2RDI_CLK>, 2144 <&mmcc CAMSS_CSI3_AHB_CLK>, 2145 <&mmcc CAMSS_CSI3_CLK>, 2146 <&mmcc CAMSS_CSI3PHY_CLK>, 2147 <&mmcc CAMSS_CSI3PIX_CLK>, 2148 <&mmcc CAMSS_CSI3RDI_CLK>, 2149 <&mmcc CAMSS_AHB_CLK>, 2150 <&mmcc CAMSS_VFE0_CLK>, 2151 <&mmcc CAMSS_CSI_VFE0_CLK>, 2152 <&mmcc CAMSS_VFE0_AHB_CLK>, 2153 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2154 <&mmcc CAMSS_VFE1_CLK>, 2155 <&mmcc CAMSS_CSI_VFE1_CLK>, 2156 <&mmcc CAMSS_VFE1_AHB_CLK>, 2157 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2158 <&mmcc CAMSS_VFE_AHB_CLK>, 2159 <&mmcc CAMSS_VFE_AXI_CLK>; 2160 clock-names = "top_ahb", 2161 "ispif_ahb", 2162 "csiphy0_timer", 2163 "csiphy1_timer", 2164 "csiphy2_timer", 2165 "csi0_ahb", 2166 "csi0", 2167 "csi0_phy", 2168 "csi0_pix", 2169 "csi0_rdi", 2170 "csi1_ahb", 2171 "csi1", 2172 "csi1_phy", 2173 "csi1_pix", 2174 "csi1_rdi", 2175 "csi2_ahb", 2176 "csi2", 2177 "csi2_phy", 2178 "csi2_pix", 2179 "csi2_rdi", 2180 "csi3_ahb", 2181 "csi3", 2182 "csi3_phy", 2183 "csi3_pix", 2184 "csi3_rdi", 2185 "ahb", 2186 "vfe0", 2187 "csi_vfe0", 2188 "vfe0_ahb", 2189 "vfe0_stream", 2190 "vfe1", 2191 "csi_vfe1", 2192 "vfe1_ahb", 2193 "vfe1_stream", 2194 "vfe_ahb", 2195 "vfe_axi"; 2196 iommus = <&vfe_smmu 0>, 2197 <&vfe_smmu 1>, 2198 <&vfe_smmu 2>, 2199 <&vfe_smmu 3>; 2200 status = "disabled"; 2201 ports { 2202 #address-cells = <1>; 2203 #size-cells = <0>; 2204 }; 2205 }; 2206 2207 cci: cci@a0c000 { 2208 compatible = "qcom,msm8996-cci"; 2209 #address-cells = <1>; 2210 #size-cells = <0>; 2211 reg = <0xa0c000 0x1000>; 2212 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2213 power-domains = <&mmcc CAMSS_GDSC>; 2214 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2215 <&mmcc CAMSS_CCI_AHB_CLK>, 2216 <&mmcc CAMSS_CCI_CLK>, 2217 <&mmcc CAMSS_AHB_CLK>; 2218 clock-names = "camss_top_ahb", 2219 "cci_ahb", 2220 "cci", 2221 "camss_ahb"; 2222 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2223 <&mmcc CAMSS_CCI_CLK>; 2224 assigned-clock-rates = <80000000>, <37500000>; 2225 pinctrl-names = "default"; 2226 pinctrl-0 = <&cci0_default &cci1_default>; 2227 status = "disabled"; 2228 2229 cci_i2c0: i2c-bus@0 { 2230 reg = <0>; 2231 clock-frequency = <400000>; 2232 #address-cells = <1>; 2233 #size-cells = <0>; 2234 }; 2235 2236 cci_i2c1: i2c-bus@1 { 2237 reg = <1>; 2238 clock-frequency = <400000>; 2239 #address-cells = <1>; 2240 #size-cells = <0>; 2241 }; 2242 }; 2243 2244 adreno_smmu: iommu@b40000 { 2245 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2246 reg = <0x00b40000 0x10000>; 2247 2248 #global-interrupts = <1>; 2249 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2252 #iommu-cells = <1>; 2253 2254 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2255 <&mmcc GPU_AHB_CLK>; 2256 clock-names = "bus", "iface"; 2257 2258 power-domains = <&mmcc GPU_GDSC>; 2259 }; 2260 2261 venus: video-codec@c00000 { 2262 compatible = "qcom,msm8996-venus"; 2263 reg = <0x00c00000 0xff000>; 2264 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2265 power-domains = <&mmcc VENUS_GDSC>; 2266 clocks = <&mmcc VIDEO_CORE_CLK>, 2267 <&mmcc VIDEO_AHB_CLK>, 2268 <&mmcc VIDEO_AXI_CLK>, 2269 <&mmcc VIDEO_MAXI_CLK>; 2270 clock-names = "core", "iface", "bus", "mbus"; 2271 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2272 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2273 interconnect-names = "video-mem", "cpu-cfg"; 2274 iommus = <&venus_smmu 0x00>, 2275 <&venus_smmu 0x01>, 2276 <&venus_smmu 0x0a>, 2277 <&venus_smmu 0x07>, 2278 <&venus_smmu 0x0e>, 2279 <&venus_smmu 0x0f>, 2280 <&venus_smmu 0x08>, 2281 <&venus_smmu 0x09>, 2282 <&venus_smmu 0x0b>, 2283 <&venus_smmu 0x0c>, 2284 <&venus_smmu 0x0d>, 2285 <&venus_smmu 0x10>, 2286 <&venus_smmu 0x11>, 2287 <&venus_smmu 0x21>, 2288 <&venus_smmu 0x28>, 2289 <&venus_smmu 0x29>, 2290 <&venus_smmu 0x2b>, 2291 <&venus_smmu 0x2c>, 2292 <&venus_smmu 0x2d>, 2293 <&venus_smmu 0x31>; 2294 memory-region = <&venus_mem>; 2295 status = "disabled"; 2296 2297 video-decoder { 2298 compatible = "venus-decoder"; 2299 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2300 clock-names = "core"; 2301 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2302 }; 2303 2304 video-encoder { 2305 compatible = "venus-encoder"; 2306 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2307 clock-names = "core"; 2308 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2309 }; 2310 }; 2311 2312 mdp_smmu: iommu@d00000 { 2313 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2314 reg = <0x00d00000 0x10000>; 2315 2316 #global-interrupts = <1>; 2317 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2318 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2319 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2320 #iommu-cells = <1>; 2321 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2322 <&mmcc SMMU_MDP_AHB_CLK>; 2323 clock-names = "bus", "iface"; 2324 2325 power-domains = <&mmcc MDSS_GDSC>; 2326 }; 2327 2328 venus_smmu: iommu@d40000 { 2329 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2330 reg = <0x00d40000 0x20000>; 2331 #global-interrupts = <1>; 2332 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2333 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2340 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2341 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2342 <&mmcc SMMU_VIDEO_AHB_CLK>; 2343 clock-names = "bus", "iface"; 2344 #iommu-cells = <1>; 2345 status = "okay"; 2346 }; 2347 2348 vfe_smmu: iommu@da0000 { 2349 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2350 reg = <0x00da0000 0x10000>; 2351 2352 #global-interrupts = <1>; 2353 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2356 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2357 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2358 <&mmcc SMMU_VFE_AHB_CLK>; 2359 clock-names = "bus", "iface"; 2360 #iommu-cells = <1>; 2361 }; 2362 2363 lpass_q6_smmu: iommu@1600000 { 2364 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2365 reg = <0x01600000 0x20000>; 2366 #iommu-cells = <1>; 2367 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2368 2369 #global-interrupts = <1>; 2370 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2380 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2383 2384 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2385 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2386 clock-names = "bus", "iface"; 2387 }; 2388 2389 slpi_pil: remoteproc@1c00000 { 2390 compatible = "qcom,msm8996-slpi-pil"; 2391 reg = <0x01c00000 0x4000>; 2392 2393 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2394 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2395 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2396 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2397 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2398 interrupt-names = "wdog", 2399 "fatal", 2400 "ready", 2401 "handover", 2402 "stop-ack"; 2403 2404 clocks = <&xo_board>, 2405 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2406 clock-names = "xo", "aggre2"; 2407 2408 memory-region = <&slpi_mem>; 2409 2410 qcom,smem-states = <&slpi_smp2p_out 0>; 2411 qcom,smem-state-names = "stop"; 2412 2413 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2414 power-domain-names = "ssc_cx"; 2415 2416 status = "disabled"; 2417 2418 smd-edge { 2419 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2420 2421 label = "dsps"; 2422 mboxes = <&apcs_glb 25>; 2423 qcom,smd-edge = <3>; 2424 qcom,remote-pid = <3>; 2425 }; 2426 }; 2427 2428 mss_pil: remoteproc@2080000 { 2429 compatible = "qcom,msm8996-mss-pil"; 2430 reg = <0x2080000 0x100>, 2431 <0x2180000 0x020>; 2432 reg-names = "qdsp6", "rmb"; 2433 2434 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2435 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2436 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2437 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2438 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2439 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2440 interrupt-names = "wdog", "fatal", "ready", 2441 "handover", "stop-ack", 2442 "shutdown-ack"; 2443 2444 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2445 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2446 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2447 <&xo_board>, 2448 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2449 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2450 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2451 <&rpmcc RPM_SMD_PCNOC_CLK>, 2452 <&rpmcc RPM_SMD_QDSS_CLK>; 2453 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2454 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2455 2456 resets = <&gcc GCC_MSS_RESTART>; 2457 reset-names = "mss_restart"; 2458 2459 power-domains = <&rpmpd MSM8996_VDDCX>, 2460 <&rpmpd MSM8996_VDDMX>; 2461 power-domain-names = "cx", "mx"; 2462 2463 qcom,smem-states = <&mpss_smp2p_out 0>; 2464 qcom,smem-state-names = "stop"; 2465 2466 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2467 2468 status = "disabled"; 2469 2470 mba { 2471 memory-region = <&mba_mem>; 2472 }; 2473 2474 mpss { 2475 memory-region = <&mpss_mem>; 2476 }; 2477 2478 metadata { 2479 memory-region = <&mdata_mem>; 2480 }; 2481 2482 smd-edge { 2483 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2484 2485 label = "mpss"; 2486 mboxes = <&apcs_glb 12>; 2487 qcom,smd-edge = <0>; 2488 qcom,remote-pid = <1>; 2489 }; 2490 }; 2491 2492 stm@3002000 { 2493 compatible = "arm,coresight-stm", "arm,primecell"; 2494 reg = <0x3002000 0x1000>, 2495 <0x8280000 0x180000>; 2496 reg-names = "stm-base", "stm-stimulus-base"; 2497 2498 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2499 clock-names = "apb_pclk", "atclk"; 2500 2501 out-ports { 2502 port { 2503 stm_out: endpoint { 2504 remote-endpoint = 2505 <&funnel0_in>; 2506 }; 2507 }; 2508 }; 2509 }; 2510 2511 tpiu@3020000 { 2512 compatible = "arm,coresight-tpiu", "arm,primecell"; 2513 reg = <0x3020000 0x1000>; 2514 2515 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2516 clock-names = "apb_pclk", "atclk"; 2517 2518 in-ports { 2519 port { 2520 tpiu_in: endpoint { 2521 remote-endpoint = 2522 <&replicator_out1>; 2523 }; 2524 }; 2525 }; 2526 }; 2527 2528 funnel@3021000 { 2529 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2530 reg = <0x3021000 0x1000>; 2531 2532 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2533 clock-names = "apb_pclk", "atclk"; 2534 2535 in-ports { 2536 #address-cells = <1>; 2537 #size-cells = <0>; 2538 2539 port@7 { 2540 reg = <7>; 2541 funnel0_in: endpoint { 2542 remote-endpoint = 2543 <&stm_out>; 2544 }; 2545 }; 2546 }; 2547 2548 out-ports { 2549 port { 2550 funnel0_out: endpoint { 2551 remote-endpoint = 2552 <&merge_funnel_in0>; 2553 }; 2554 }; 2555 }; 2556 }; 2557 2558 funnel@3022000 { 2559 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2560 reg = <0x3022000 0x1000>; 2561 2562 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2563 clock-names = "apb_pclk", "atclk"; 2564 2565 in-ports { 2566 #address-cells = <1>; 2567 #size-cells = <0>; 2568 2569 port@6 { 2570 reg = <6>; 2571 funnel1_in: endpoint { 2572 remote-endpoint = 2573 <&apss_merge_funnel_out>; 2574 }; 2575 }; 2576 }; 2577 2578 out-ports { 2579 port { 2580 funnel1_out: endpoint { 2581 remote-endpoint = 2582 <&merge_funnel_in1>; 2583 }; 2584 }; 2585 }; 2586 }; 2587 2588 funnel@3023000 { 2589 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2590 reg = <0x3023000 0x1000>; 2591 2592 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2593 clock-names = "apb_pclk", "atclk"; 2594 2595 2596 out-ports { 2597 port { 2598 funnel2_out: endpoint { 2599 remote-endpoint = 2600 <&merge_funnel_in2>; 2601 }; 2602 }; 2603 }; 2604 }; 2605 2606 funnel@3025000 { 2607 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2608 reg = <0x3025000 0x1000>; 2609 2610 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2611 clock-names = "apb_pclk", "atclk"; 2612 2613 in-ports { 2614 #address-cells = <1>; 2615 #size-cells = <0>; 2616 2617 port@0 { 2618 reg = <0>; 2619 merge_funnel_in0: endpoint { 2620 remote-endpoint = 2621 <&funnel0_out>; 2622 }; 2623 }; 2624 2625 port@1 { 2626 reg = <1>; 2627 merge_funnel_in1: endpoint { 2628 remote-endpoint = 2629 <&funnel1_out>; 2630 }; 2631 }; 2632 2633 port@2 { 2634 reg = <2>; 2635 merge_funnel_in2: endpoint { 2636 remote-endpoint = 2637 <&funnel2_out>; 2638 }; 2639 }; 2640 }; 2641 2642 out-ports { 2643 port { 2644 merge_funnel_out: endpoint { 2645 remote-endpoint = 2646 <&etf_in>; 2647 }; 2648 }; 2649 }; 2650 }; 2651 2652 replicator@3026000 { 2653 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2654 reg = <0x3026000 0x1000>; 2655 2656 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2657 clock-names = "apb_pclk", "atclk"; 2658 2659 in-ports { 2660 port { 2661 replicator_in: endpoint { 2662 remote-endpoint = 2663 <&etf_out>; 2664 }; 2665 }; 2666 }; 2667 2668 out-ports { 2669 #address-cells = <1>; 2670 #size-cells = <0>; 2671 2672 port@0 { 2673 reg = <0>; 2674 replicator_out0: endpoint { 2675 remote-endpoint = 2676 <&etr_in>; 2677 }; 2678 }; 2679 2680 port@1 { 2681 reg = <1>; 2682 replicator_out1: endpoint { 2683 remote-endpoint = 2684 <&tpiu_in>; 2685 }; 2686 }; 2687 }; 2688 }; 2689 2690 etf@3027000 { 2691 compatible = "arm,coresight-tmc", "arm,primecell"; 2692 reg = <0x3027000 0x1000>; 2693 2694 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2695 clock-names = "apb_pclk", "atclk"; 2696 2697 in-ports { 2698 port { 2699 etf_in: endpoint { 2700 remote-endpoint = 2701 <&merge_funnel_out>; 2702 }; 2703 }; 2704 }; 2705 2706 out-ports { 2707 port { 2708 etf_out: endpoint { 2709 remote-endpoint = 2710 <&replicator_in>; 2711 }; 2712 }; 2713 }; 2714 }; 2715 2716 etr@3028000 { 2717 compatible = "arm,coresight-tmc", "arm,primecell"; 2718 reg = <0x3028000 0x1000>; 2719 2720 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2721 clock-names = "apb_pclk", "atclk"; 2722 arm,scatter-gather; 2723 2724 in-ports { 2725 port { 2726 etr_in: endpoint { 2727 remote-endpoint = 2728 <&replicator_out0>; 2729 }; 2730 }; 2731 }; 2732 }; 2733 2734 debug@3810000 { 2735 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2736 reg = <0x3810000 0x1000>; 2737 2738 clocks = <&rpmcc RPM_QDSS_CLK>; 2739 clock-names = "apb_pclk"; 2740 2741 cpu = <&CPU0>; 2742 }; 2743 2744 etm@3840000 { 2745 compatible = "arm,coresight-etm4x", "arm,primecell"; 2746 reg = <0x3840000 0x1000>; 2747 2748 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2749 clock-names = "apb_pclk", "atclk"; 2750 2751 cpu = <&CPU0>; 2752 2753 out-ports { 2754 port { 2755 etm0_out: endpoint { 2756 remote-endpoint = 2757 <&apss_funnel0_in0>; 2758 }; 2759 }; 2760 }; 2761 }; 2762 2763 debug@3910000 { 2764 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2765 reg = <0x3910000 0x1000>; 2766 2767 clocks = <&rpmcc RPM_QDSS_CLK>; 2768 clock-names = "apb_pclk"; 2769 2770 cpu = <&CPU1>; 2771 }; 2772 2773 etm@3940000 { 2774 compatible = "arm,coresight-etm4x", "arm,primecell"; 2775 reg = <0x3940000 0x1000>; 2776 2777 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2778 clock-names = "apb_pclk", "atclk"; 2779 2780 cpu = <&CPU1>; 2781 2782 out-ports { 2783 port { 2784 etm1_out: endpoint { 2785 remote-endpoint = 2786 <&apss_funnel0_in1>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 funnel@39b0000 { /* APSS Funnel 0 */ 2793 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2794 reg = <0x39b0000 0x1000>; 2795 2796 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2797 clock-names = "apb_pclk", "atclk"; 2798 2799 in-ports { 2800 #address-cells = <1>; 2801 #size-cells = <0>; 2802 2803 port@0 { 2804 reg = <0>; 2805 apss_funnel0_in0: endpoint { 2806 remote-endpoint = <&etm0_out>; 2807 }; 2808 }; 2809 2810 port@1 { 2811 reg = <1>; 2812 apss_funnel0_in1: endpoint { 2813 remote-endpoint = <&etm1_out>; 2814 }; 2815 }; 2816 }; 2817 2818 out-ports { 2819 port { 2820 apss_funnel0_out: endpoint { 2821 remote-endpoint = 2822 <&apss_merge_funnel_in0>; 2823 }; 2824 }; 2825 }; 2826 }; 2827 2828 debug@3a10000 { 2829 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2830 reg = <0x3a10000 0x1000>; 2831 2832 clocks = <&rpmcc RPM_QDSS_CLK>; 2833 clock-names = "apb_pclk"; 2834 2835 cpu = <&CPU2>; 2836 }; 2837 2838 etm@3a40000 { 2839 compatible = "arm,coresight-etm4x", "arm,primecell"; 2840 reg = <0x3a40000 0x1000>; 2841 2842 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2843 clock-names = "apb_pclk", "atclk"; 2844 2845 cpu = <&CPU2>; 2846 2847 out-ports { 2848 port { 2849 etm2_out: endpoint { 2850 remote-endpoint = 2851 <&apss_funnel1_in0>; 2852 }; 2853 }; 2854 }; 2855 }; 2856 2857 debug@3b10000 { 2858 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2859 reg = <0x3b10000 0x1000>; 2860 2861 clocks = <&rpmcc RPM_QDSS_CLK>; 2862 clock-names = "apb_pclk"; 2863 2864 cpu = <&CPU3>; 2865 }; 2866 2867 etm@3b40000 { 2868 compatible = "arm,coresight-etm4x", "arm,primecell"; 2869 reg = <0x3b40000 0x1000>; 2870 2871 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2872 clock-names = "apb_pclk", "atclk"; 2873 2874 cpu = <&CPU3>; 2875 2876 out-ports { 2877 port { 2878 etm3_out: endpoint { 2879 remote-endpoint = 2880 <&apss_funnel1_in1>; 2881 }; 2882 }; 2883 }; 2884 }; 2885 2886 funnel@3bb0000 { /* APSS Funnel 1 */ 2887 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2888 reg = <0x3bb0000 0x1000>; 2889 2890 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2891 clock-names = "apb_pclk", "atclk"; 2892 2893 in-ports { 2894 #address-cells = <1>; 2895 #size-cells = <0>; 2896 2897 port@0 { 2898 reg = <0>; 2899 apss_funnel1_in0: endpoint { 2900 remote-endpoint = <&etm2_out>; 2901 }; 2902 }; 2903 2904 port@1 { 2905 reg = <1>; 2906 apss_funnel1_in1: endpoint { 2907 remote-endpoint = <&etm3_out>; 2908 }; 2909 }; 2910 }; 2911 2912 out-ports { 2913 port { 2914 apss_funnel1_out: endpoint { 2915 remote-endpoint = 2916 <&apss_merge_funnel_in1>; 2917 }; 2918 }; 2919 }; 2920 }; 2921 2922 funnel@3bc0000 { 2923 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2924 reg = <0x3bc0000 0x1000>; 2925 2926 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2927 clock-names = "apb_pclk", "atclk"; 2928 2929 in-ports { 2930 #address-cells = <1>; 2931 #size-cells = <0>; 2932 2933 port@0 { 2934 reg = <0>; 2935 apss_merge_funnel_in0: endpoint { 2936 remote-endpoint = 2937 <&apss_funnel0_out>; 2938 }; 2939 }; 2940 2941 port@1 { 2942 reg = <1>; 2943 apss_merge_funnel_in1: endpoint { 2944 remote-endpoint = 2945 <&apss_funnel1_out>; 2946 }; 2947 }; 2948 }; 2949 2950 out-ports { 2951 port { 2952 apss_merge_funnel_out: endpoint { 2953 remote-endpoint = 2954 <&funnel1_in>; 2955 }; 2956 }; 2957 }; 2958 }; 2959 2960 kryocc: clock-controller@6400000 { 2961 compatible = "qcom,msm8996-apcc"; 2962 reg = <0x06400000 0x90000>; 2963 2964 clock-names = "xo", "sys_apcs_aux"; 2965 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 2966 2967 #clock-cells = <1>; 2968 }; 2969 2970 usb3: usb@6af8800 { 2971 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 2972 reg = <0x06af8800 0x400>; 2973 #address-cells = <1>; 2974 #size-cells = <1>; 2975 ranges; 2976 2977 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2978 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2979 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2980 2981 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 2982 <&gcc GCC_USB30_MASTER_CLK>, 2983 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 2984 <&gcc GCC_USB30_SLEEP_CLK>, 2985 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2986 clock-names = "cfg_noc", 2987 "core", 2988 "iface", 2989 "sleep", 2990 "mock_utmi"; 2991 2992 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2993 <&gcc GCC_USB30_MASTER_CLK>; 2994 assigned-clock-rates = <19200000>, <120000000>; 2995 2996 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 2997 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 2998 interconnect-names = "usb-ddr", "apps-usb"; 2999 3000 power-domains = <&gcc USB30_GDSC>; 3001 status = "disabled"; 3002 3003 usb3_dwc3: usb@6a00000 { 3004 compatible = "snps,dwc3"; 3005 reg = <0x06a00000 0xcc00>; 3006 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 3007 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 3008 phy-names = "usb2-phy", "usb3-phy"; 3009 snps,hird-threshold = /bits/ 8 <0>; 3010 snps,dis_u2_susphy_quirk; 3011 snps,dis_enblslpm_quirk; 3012 snps,is-utmi-l1-suspend; 3013 tx-fifo-resize; 3014 }; 3015 }; 3016 3017 usb3phy: phy@7410000 { 3018 compatible = "qcom,msm8996-qmp-usb3-phy"; 3019 reg = <0x07410000 0x1c4>; 3020 #address-cells = <1>; 3021 #size-cells = <1>; 3022 ranges; 3023 3024 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3025 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3026 <&gcc GCC_USB3_CLKREF_CLK>; 3027 clock-names = "aux", "cfg_ahb", "ref"; 3028 3029 resets = <&gcc GCC_USB3_PHY_BCR>, 3030 <&gcc GCC_USB3PHY_PHY_BCR>; 3031 reset-names = "phy", "common"; 3032 status = "disabled"; 3033 3034 ssusb_phy_0: phy@7410200 { 3035 reg = <0x07410200 0x200>, 3036 <0x07410400 0x130>, 3037 <0x07410600 0x1a8>; 3038 #phy-cells = <0>; 3039 3040 #clock-cells = <0>; 3041 clock-output-names = "usb3_phy_pipe_clk_src"; 3042 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 3043 clock-names = "pipe0"; 3044 }; 3045 }; 3046 3047 hsusb_phy1: phy@7411000 { 3048 compatible = "qcom,msm8996-qusb2-phy"; 3049 reg = <0x07411000 0x180>; 3050 #phy-cells = <0>; 3051 3052 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3053 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3054 clock-names = "cfg_ahb", "ref"; 3055 3056 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3057 nvmem-cells = <&qusb2p_hstx_trim>; 3058 status = "disabled"; 3059 }; 3060 3061 hsusb_phy2: phy@7412000 { 3062 compatible = "qcom,msm8996-qusb2-phy"; 3063 reg = <0x07412000 0x180>; 3064 #phy-cells = <0>; 3065 3066 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3067 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3068 clock-names = "cfg_ahb", "ref"; 3069 3070 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3071 nvmem-cells = <&qusb2s_hstx_trim>; 3072 status = "disabled"; 3073 }; 3074 3075 sdhc1: mmc@7464900 { 3076 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3077 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3078 reg-names = "hc", "core"; 3079 3080 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3082 interrupt-names = "hc_irq", "pwr_irq"; 3083 3084 clock-names = "iface", "core", "xo"; 3085 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3086 <&gcc GCC_SDCC1_APPS_CLK>, 3087 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3088 resets = <&gcc GCC_SDCC1_BCR>; 3089 3090 pinctrl-names = "default", "sleep"; 3091 pinctrl-0 = <&sdc1_state_on>; 3092 pinctrl-1 = <&sdc1_state_off>; 3093 3094 bus-width = <8>; 3095 non-removable; 3096 status = "disabled"; 3097 }; 3098 3099 sdhc2: mmc@74a4900 { 3100 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3101 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3102 reg-names = "hc", "core"; 3103 3104 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3106 interrupt-names = "hc_irq", "pwr_irq"; 3107 3108 clock-names = "iface", "core", "xo"; 3109 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3110 <&gcc GCC_SDCC2_APPS_CLK>, 3111 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3112 resets = <&gcc GCC_SDCC2_BCR>; 3113 3114 pinctrl-names = "default", "sleep"; 3115 pinctrl-0 = <&sdc2_state_on>; 3116 pinctrl-1 = <&sdc2_state_off>; 3117 3118 bus-width = <4>; 3119 status = "disabled"; 3120 }; 3121 3122 blsp1_dma: dma-controller@7544000 { 3123 compatible = "qcom,bam-v1.7.0"; 3124 reg = <0x07544000 0x2b000>; 3125 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3126 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3127 clock-names = "bam_clk"; 3128 qcom,controlled-remotely; 3129 #dma-cells = <1>; 3130 qcom,ee = <0>; 3131 }; 3132 3133 blsp1_uart2: serial@7570000 { 3134 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3135 reg = <0x07570000 0x1000>; 3136 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3137 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3138 <&gcc GCC_BLSP1_AHB_CLK>; 3139 clock-names = "core", "iface"; 3140 pinctrl-names = "default", "sleep"; 3141 pinctrl-0 = <&blsp1_uart2_default>; 3142 pinctrl-1 = <&blsp1_uart2_sleep>; 3143 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3144 dma-names = "tx", "rx"; 3145 status = "disabled"; 3146 }; 3147 3148 blsp1_spi1: spi@7575000 { 3149 compatible = "qcom,spi-qup-v2.2.1"; 3150 reg = <0x07575000 0x600>; 3151 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3152 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3153 <&gcc GCC_BLSP1_AHB_CLK>; 3154 clock-names = "core", "iface"; 3155 pinctrl-names = "default", "sleep"; 3156 pinctrl-0 = <&blsp1_spi1_default>; 3157 pinctrl-1 = <&blsp1_spi1_sleep>; 3158 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3159 dma-names = "tx", "rx"; 3160 #address-cells = <1>; 3161 #size-cells = <0>; 3162 status = "disabled"; 3163 }; 3164 3165 blsp1_i2c3: i2c@7577000 { 3166 compatible = "qcom,i2c-qup-v2.2.1"; 3167 reg = <0x07577000 0x1000>; 3168 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3169 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3170 <&gcc GCC_BLSP1_AHB_CLK>; 3171 clock-names = "core", "iface"; 3172 pinctrl-names = "default", "sleep"; 3173 pinctrl-0 = <&blsp1_i2c3_default>; 3174 pinctrl-1 = <&blsp1_i2c3_sleep>; 3175 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3176 dma-names = "tx", "rx"; 3177 #address-cells = <1>; 3178 #size-cells = <0>; 3179 status = "disabled"; 3180 }; 3181 3182 blsp1_i2c6: i2c@757a000 { 3183 compatible = "qcom,i2c-qup-v2.2.1"; 3184 reg = <0x757a000 0x1000>; 3185 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3186 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3187 <&gcc GCC_BLSP1_AHB_CLK>; 3188 clock-names = "core", "iface"; 3189 pinctrl-names = "default", "sleep"; 3190 pinctrl-0 = <&blsp1_i2c6_default>; 3191 pinctrl-1 = <&blsp1_i2c6_sleep>; 3192 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3193 dma-names = "tx", "rx"; 3194 #address-cells = <1>; 3195 #size-cells = <0>; 3196 status = "disabled"; 3197 }; 3198 3199 blsp2_dma: dma-controller@7584000 { 3200 compatible = "qcom,bam-v1.7.0"; 3201 reg = <0x07584000 0x2b000>; 3202 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3203 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3204 clock-names = "bam_clk"; 3205 qcom,controlled-remotely; 3206 #dma-cells = <1>; 3207 qcom,ee = <0>; 3208 }; 3209 3210 blsp2_uart2: serial@75b0000 { 3211 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3212 reg = <0x075b0000 0x1000>; 3213 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3214 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3215 <&gcc GCC_BLSP2_AHB_CLK>; 3216 clock-names = "core", "iface"; 3217 status = "disabled"; 3218 }; 3219 3220 blsp2_uart3: serial@75b1000 { 3221 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3222 reg = <0x075b1000 0x1000>; 3223 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3224 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3225 <&gcc GCC_BLSP2_AHB_CLK>; 3226 clock-names = "core", "iface"; 3227 status = "disabled"; 3228 }; 3229 3230 blsp2_i2c1: i2c@75b5000 { 3231 compatible = "qcom,i2c-qup-v2.2.1"; 3232 reg = <0x075b5000 0x1000>; 3233 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3234 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3235 <&gcc GCC_BLSP2_AHB_CLK>; 3236 clock-names = "core", "iface"; 3237 pinctrl-names = "default", "sleep"; 3238 pinctrl-0 = <&blsp2_i2c1_default>; 3239 pinctrl-1 = <&blsp2_i2c1_sleep>; 3240 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3241 dma-names = "tx", "rx"; 3242 #address-cells = <1>; 3243 #size-cells = <0>; 3244 status = "disabled"; 3245 }; 3246 3247 blsp2_i2c2: i2c@75b6000 { 3248 compatible = "qcom,i2c-qup-v2.2.1"; 3249 reg = <0x075b6000 0x1000>; 3250 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3251 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3252 <&gcc GCC_BLSP2_AHB_CLK>; 3253 clock-names = "core", "iface"; 3254 pinctrl-names = "default", "sleep"; 3255 pinctrl-0 = <&blsp2_i2c2_default>; 3256 pinctrl-1 = <&blsp2_i2c2_sleep>; 3257 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3258 dma-names = "tx", "rx"; 3259 #address-cells = <1>; 3260 #size-cells = <0>; 3261 status = "disabled"; 3262 }; 3263 3264 blsp2_i2c3: i2c@75b7000 { 3265 compatible = "qcom,i2c-qup-v2.2.1"; 3266 reg = <0x075b7000 0x1000>; 3267 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3268 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3269 <&gcc GCC_BLSP2_AHB_CLK>; 3270 clock-names = "core", "iface"; 3271 clock-frequency = <400000>; 3272 pinctrl-names = "default", "sleep"; 3273 pinctrl-0 = <&blsp2_i2c3_default>; 3274 pinctrl-1 = <&blsp2_i2c3_sleep>; 3275 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3276 dma-names = "tx", "rx"; 3277 #address-cells = <1>; 3278 #size-cells = <0>; 3279 status = "disabled"; 3280 }; 3281 3282 blsp2_i2c5: i2c@75b9000 { 3283 compatible = "qcom,i2c-qup-v2.2.1"; 3284 reg = <0x75b9000 0x1000>; 3285 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3286 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3287 <&gcc GCC_BLSP2_AHB_CLK>; 3288 clock-names = "core", "iface"; 3289 pinctrl-names = "default"; 3290 pinctrl-0 = <&blsp2_i2c5_default>; 3291 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3292 dma-names = "tx", "rx"; 3293 #address-cells = <1>; 3294 #size-cells = <0>; 3295 status = "disabled"; 3296 }; 3297 3298 blsp2_i2c6: i2c@75ba000 { 3299 compatible = "qcom,i2c-qup-v2.2.1"; 3300 reg = <0x75ba000 0x1000>; 3301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3302 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3303 <&gcc GCC_BLSP2_AHB_CLK>; 3304 clock-names = "core", "iface"; 3305 pinctrl-names = "default", "sleep"; 3306 pinctrl-0 = <&blsp2_i2c6_default>; 3307 pinctrl-1 = <&blsp2_i2c6_sleep>; 3308 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3309 dma-names = "tx", "rx"; 3310 #address-cells = <1>; 3311 #size-cells = <0>; 3312 status = "disabled"; 3313 }; 3314 3315 blsp2_spi6: spi@75ba000 { 3316 compatible = "qcom,spi-qup-v2.2.1"; 3317 reg = <0x075ba000 0x600>; 3318 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3319 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3320 <&gcc GCC_BLSP2_AHB_CLK>; 3321 clock-names = "core", "iface"; 3322 pinctrl-names = "default", "sleep"; 3323 pinctrl-0 = <&blsp2_spi6_default>; 3324 pinctrl-1 = <&blsp2_spi6_sleep>; 3325 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3326 dma-names = "tx", "rx"; 3327 #address-cells = <1>; 3328 #size-cells = <0>; 3329 status = "disabled"; 3330 }; 3331 3332 usb2: usb@76f8800 { 3333 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3334 reg = <0x076f8800 0x400>; 3335 #address-cells = <1>; 3336 #size-cells = <1>; 3337 ranges; 3338 3339 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3340 <&gcc GCC_USB20_MASTER_CLK>, 3341 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3342 <&gcc GCC_USB20_SLEEP_CLK>, 3343 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3344 clock-names = "cfg_noc", 3345 "core", 3346 "iface", 3347 "sleep", 3348 "mock_utmi"; 3349 3350 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3351 <&gcc GCC_USB20_MASTER_CLK>; 3352 assigned-clock-rates = <19200000>, <60000000>; 3353 3354 power-domains = <&gcc USB30_GDSC>; 3355 qcom,select-utmi-as-pipe-clk; 3356 status = "disabled"; 3357 3358 usb2_dwc3: usb@7600000 { 3359 compatible = "snps,dwc3"; 3360 reg = <0x07600000 0xcc00>; 3361 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 3362 phys = <&hsusb_phy2>; 3363 phy-names = "usb2-phy"; 3364 maximum-speed = "high-speed"; 3365 snps,dis_u2_susphy_quirk; 3366 snps,dis_enblslpm_quirk; 3367 }; 3368 }; 3369 3370 slimbam: dma-controller@9184000 { 3371 compatible = "qcom,bam-v1.7.0"; 3372 qcom,controlled-remotely; 3373 reg = <0x09184000 0x32000>; 3374 num-channels = <31>; 3375 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3376 #dma-cells = <1>; 3377 qcom,ee = <1>; 3378 qcom,num-ees = <2>; 3379 }; 3380 3381 slim_msm: slim-ngd@91c0000 { 3382 compatible = "qcom,slim-ngd-v1.5.0"; 3383 reg = <0x091c0000 0x2c000>; 3384 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3385 dmas = <&slimbam 3>, <&slimbam 4>; 3386 dma-names = "rx", "tx"; 3387 #address-cells = <1>; 3388 #size-cells = <0>; 3389 3390 status = "disabled"; 3391 }; 3392 3393 adsp_pil: remoteproc@9300000 { 3394 compatible = "qcom,msm8996-adsp-pil"; 3395 reg = <0x09300000 0x80000>; 3396 3397 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3398 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3399 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3400 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3401 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3402 interrupt-names = "wdog", "fatal", "ready", 3403 "handover", "stop-ack"; 3404 3405 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3406 clock-names = "xo"; 3407 3408 memory-region = <&adsp_mem>; 3409 3410 qcom,smem-states = <&adsp_smp2p_out 0>; 3411 qcom,smem-state-names = "stop"; 3412 3413 power-domains = <&rpmpd MSM8996_VDDCX>; 3414 power-domain-names = "cx"; 3415 3416 status = "disabled"; 3417 3418 smd-edge { 3419 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3420 3421 label = "lpass"; 3422 mboxes = <&apcs_glb 8>; 3423 qcom,smd-edge = <1>; 3424 qcom,remote-pid = <2>; 3425 3426 apr { 3427 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3428 compatible = "qcom,apr-v2"; 3429 qcom,smd-channels = "apr_audio_svc"; 3430 qcom,domain = <APR_DOMAIN_ADSP>; 3431 #address-cells = <1>; 3432 #size-cells = <0>; 3433 3434 service@3 { 3435 reg = <APR_SVC_ADSP_CORE>; 3436 compatible = "qcom,q6core"; 3437 }; 3438 3439 q6afe: service@4 { 3440 compatible = "qcom,q6afe"; 3441 reg = <APR_SVC_AFE>; 3442 q6afedai: dais { 3443 compatible = "qcom,q6afe-dais"; 3444 #address-cells = <1>; 3445 #size-cells = <0>; 3446 #sound-dai-cells = <1>; 3447 dai@1 { 3448 reg = <1>; 3449 }; 3450 }; 3451 }; 3452 3453 q6asm: service@7 { 3454 compatible = "qcom,q6asm"; 3455 reg = <APR_SVC_ASM>; 3456 q6asmdai: dais { 3457 compatible = "qcom,q6asm-dais"; 3458 #address-cells = <1>; 3459 #size-cells = <0>; 3460 #sound-dai-cells = <1>; 3461 iommus = <&lpass_q6_smmu 1>; 3462 }; 3463 }; 3464 3465 q6adm: service@8 { 3466 compatible = "qcom,q6adm"; 3467 reg = <APR_SVC_ADM>; 3468 q6routing: routing { 3469 compatible = "qcom,q6adm-routing"; 3470 #sound-dai-cells = <0>; 3471 }; 3472 }; 3473 }; 3474 }; 3475 }; 3476 3477 apcs_glb: mailbox@9820000 { 3478 compatible = "qcom,msm8996-apcs-hmss-global"; 3479 reg = <0x09820000 0x1000>; 3480 3481 #mbox-cells = <1>; 3482 #clock-cells = <0>; 3483 }; 3484 3485 timer@9840000 { 3486 #address-cells = <1>; 3487 #size-cells = <1>; 3488 ranges; 3489 compatible = "arm,armv7-timer-mem"; 3490 reg = <0x09840000 0x1000>; 3491 clock-frequency = <19200000>; 3492 3493 frame@9850000 { 3494 frame-number = <0>; 3495 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3497 reg = <0x09850000 0x1000>, 3498 <0x09860000 0x1000>; 3499 }; 3500 3501 frame@9870000 { 3502 frame-number = <1>; 3503 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3504 reg = <0x09870000 0x1000>; 3505 status = "disabled"; 3506 }; 3507 3508 frame@9880000 { 3509 frame-number = <2>; 3510 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3511 reg = <0x09880000 0x1000>; 3512 status = "disabled"; 3513 }; 3514 3515 frame@9890000 { 3516 frame-number = <3>; 3517 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3518 reg = <0x09890000 0x1000>; 3519 status = "disabled"; 3520 }; 3521 3522 frame@98a0000 { 3523 frame-number = <4>; 3524 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3525 reg = <0x098a0000 0x1000>; 3526 status = "disabled"; 3527 }; 3528 3529 frame@98b0000 { 3530 frame-number = <5>; 3531 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3532 reg = <0x098b0000 0x1000>; 3533 status = "disabled"; 3534 }; 3535 3536 frame@98c0000 { 3537 frame-number = <6>; 3538 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3539 reg = <0x098c0000 0x1000>; 3540 status = "disabled"; 3541 }; 3542 }; 3543 3544 saw3: syscon@9a10000 { 3545 compatible = "syscon"; 3546 reg = <0x09a10000 0x1000>; 3547 }; 3548 3549 cbf: clock-controller@9a11000 { 3550 compatible = "qcom,msm8996-cbf"; 3551 reg = <0x09a11000 0x10000>; 3552 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3553 #clock-cells = <0>; 3554 }; 3555 3556 intc: interrupt-controller@9bc0000 { 3557 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3558 #interrupt-cells = <3>; 3559 interrupt-controller; 3560 #redistributor-regions = <1>; 3561 redistributor-stride = <0x0 0x40000>; 3562 reg = <0x09bc0000 0x10000>, 3563 <0x09c00000 0x100000>; 3564 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3565 }; 3566 }; 3567 3568 sound: sound { 3569 }; 3570 3571 thermal-zones { 3572 cpu0-thermal { 3573 polling-delay-passive = <250>; 3574 polling-delay = <1000>; 3575 3576 thermal-sensors = <&tsens0 3>; 3577 3578 trips { 3579 cpu0_alert0: trip-point0 { 3580 temperature = <75000>; 3581 hysteresis = <2000>; 3582 type = "passive"; 3583 }; 3584 3585 cpu0_crit: cpu-crit { 3586 temperature = <110000>; 3587 hysteresis = <2000>; 3588 type = "critical"; 3589 }; 3590 }; 3591 }; 3592 3593 cpu1-thermal { 3594 polling-delay-passive = <250>; 3595 polling-delay = <1000>; 3596 3597 thermal-sensors = <&tsens0 5>; 3598 3599 trips { 3600 cpu1_alert0: trip-point0 { 3601 temperature = <75000>; 3602 hysteresis = <2000>; 3603 type = "passive"; 3604 }; 3605 3606 cpu1_crit: cpu-crit { 3607 temperature = <110000>; 3608 hysteresis = <2000>; 3609 type = "critical"; 3610 }; 3611 }; 3612 }; 3613 3614 cpu2-thermal { 3615 polling-delay-passive = <250>; 3616 polling-delay = <1000>; 3617 3618 thermal-sensors = <&tsens0 8>; 3619 3620 trips { 3621 cpu2_alert0: trip-point0 { 3622 temperature = <75000>; 3623 hysteresis = <2000>; 3624 type = "passive"; 3625 }; 3626 3627 cpu2_crit: cpu-crit { 3628 temperature = <110000>; 3629 hysteresis = <2000>; 3630 type = "critical"; 3631 }; 3632 }; 3633 }; 3634 3635 cpu3-thermal { 3636 polling-delay-passive = <250>; 3637 polling-delay = <1000>; 3638 3639 thermal-sensors = <&tsens0 10>; 3640 3641 trips { 3642 cpu3_alert0: trip-point0 { 3643 temperature = <75000>; 3644 hysteresis = <2000>; 3645 type = "passive"; 3646 }; 3647 3648 cpu3_crit: cpu-crit { 3649 temperature = <110000>; 3650 hysteresis = <2000>; 3651 type = "critical"; 3652 }; 3653 }; 3654 }; 3655 3656 gpu-top-thermal { 3657 polling-delay-passive = <250>; 3658 polling-delay = <1000>; 3659 3660 thermal-sensors = <&tsens1 6>; 3661 3662 trips { 3663 gpu1_alert0: trip-point0 { 3664 temperature = <90000>; 3665 hysteresis = <2000>; 3666 type = "passive"; 3667 }; 3668 }; 3669 3670 cooling-maps { 3671 map0 { 3672 trip = <&gpu1_alert0>; 3673 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3674 }; 3675 }; 3676 }; 3677 3678 gpu-bottom-thermal { 3679 polling-delay-passive = <250>; 3680 polling-delay = <1000>; 3681 3682 thermal-sensors = <&tsens1 7>; 3683 3684 trips { 3685 gpu2_alert0: trip-point0 { 3686 temperature = <90000>; 3687 hysteresis = <2000>; 3688 type = "passive"; 3689 }; 3690 }; 3691 3692 cooling-maps { 3693 map0 { 3694 trip = <&gpu2_alert0>; 3695 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3696 }; 3697 }; 3698 }; 3699 3700 m4m-thermal { 3701 polling-delay-passive = <250>; 3702 polling-delay = <1000>; 3703 3704 thermal-sensors = <&tsens0 1>; 3705 3706 trips { 3707 m4m_alert0: trip-point0 { 3708 temperature = <90000>; 3709 hysteresis = <2000>; 3710 type = "hot"; 3711 }; 3712 }; 3713 }; 3714 3715 l3-or-venus-thermal { 3716 polling-delay-passive = <250>; 3717 polling-delay = <1000>; 3718 3719 thermal-sensors = <&tsens0 2>; 3720 3721 trips { 3722 l3_or_venus_alert0: trip-point0 { 3723 temperature = <90000>; 3724 hysteresis = <2000>; 3725 type = "hot"; 3726 }; 3727 }; 3728 }; 3729 3730 cluster0-l2-thermal { 3731 polling-delay-passive = <250>; 3732 polling-delay = <1000>; 3733 3734 thermal-sensors = <&tsens0 7>; 3735 3736 trips { 3737 cluster0_l2_alert0: trip-point0 { 3738 temperature = <90000>; 3739 hysteresis = <2000>; 3740 type = "hot"; 3741 }; 3742 }; 3743 }; 3744 3745 cluster1-l2-thermal { 3746 polling-delay-passive = <250>; 3747 polling-delay = <1000>; 3748 3749 thermal-sensors = <&tsens0 12>; 3750 3751 trips { 3752 cluster1_l2_alert0: trip-point0 { 3753 temperature = <90000>; 3754 hysteresis = <2000>; 3755 type = "hot"; 3756 }; 3757 }; 3758 }; 3759 3760 camera-thermal { 3761 polling-delay-passive = <250>; 3762 polling-delay = <1000>; 3763 3764 thermal-sensors = <&tsens1 1>; 3765 3766 trips { 3767 camera_alert0: trip-point0 { 3768 temperature = <90000>; 3769 hysteresis = <2000>; 3770 type = "hot"; 3771 }; 3772 }; 3773 }; 3774 3775 q6-dsp-thermal { 3776 polling-delay-passive = <250>; 3777 polling-delay = <1000>; 3778 3779 thermal-sensors = <&tsens1 2>; 3780 3781 trips { 3782 q6_dsp_alert0: trip-point0 { 3783 temperature = <90000>; 3784 hysteresis = <2000>; 3785 type = "hot"; 3786 }; 3787 }; 3788 }; 3789 3790 mem-thermal { 3791 polling-delay-passive = <250>; 3792 polling-delay = <1000>; 3793 3794 thermal-sensors = <&tsens1 3>; 3795 3796 trips { 3797 mem_alert0: trip-point0 { 3798 temperature = <90000>; 3799 hysteresis = <2000>; 3800 type = "hot"; 3801 }; 3802 }; 3803 }; 3804 3805 modemtx-thermal { 3806 polling-delay-passive = <250>; 3807 polling-delay = <1000>; 3808 3809 thermal-sensors = <&tsens1 4>; 3810 3811 trips { 3812 modemtx_alert0: trip-point0 { 3813 temperature = <90000>; 3814 hysteresis = <2000>; 3815 type = "hot"; 3816 }; 3817 }; 3818 }; 3819 }; 3820 3821 timer { 3822 compatible = "arm,armv8-timer"; 3823 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3824 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3825 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3826 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3827 }; 3828}; 3829