1// SPDX-License-Identifier: BSD-3-Clause 2/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/clock/qcom,gcc-msm8953.h> 5#include <dt-bindings/clock/qcom,rpmcc.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/soc/qcom,apr.h> 10#include <dt-bindings/sound/qcom,q6afe.h> 11#include <dt-bindings/sound/qcom,q6asm.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 sleep_clk: sleep-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <32768>; 27 }; 28 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <19200000>; 33 clock-output-names = "xo"; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <0x0>; 45 enable-method = "psci"; 46 capacity-dmips-mhz = <1024>; 47 next-level-cache = <&L2_0>; 48 #cooling-cells = <2>; 49 }; 50 51 CPU1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x1>; 55 enable-method = "psci"; 56 capacity-dmips-mhz = <1024>; 57 next-level-cache = <&L2_0>; 58 #cooling-cells = <2>; 59 }; 60 61 CPU2: cpu@2 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x2>; 65 enable-method = "psci"; 66 capacity-dmips-mhz = <1024>; 67 next-level-cache = <&L2_0>; 68 #cooling-cells = <2>; 69 }; 70 71 CPU3: cpu@3 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x3>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <1024>; 77 next-level-cache = <&L2_0>; 78 #cooling-cells = <2>; 79 }; 80 81 CPU4: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x100>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <1024>; 87 next-level-cache = <&L2_1>; 88 #cooling-cells = <2>; 89 }; 90 91 CPU5: cpu@101 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x101>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <1024>; 97 next-level-cache = <&L2_1>; 98 #cooling-cells = <2>; 99 }; 100 101 CPU6: cpu@102 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x102>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <1024>; 107 next-level-cache = <&L2_1>; 108 #cooling-cells = <2>; 109 }; 110 111 CPU7: cpu@103 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53"; 114 reg = <0x103>; 115 enable-method = "psci"; 116 capacity-dmips-mhz = <1024>; 117 next-level-cache = <&L2_1>; 118 #cooling-cells = <2>; 119 }; 120 121 cpu-map { 122 cluster0 { 123 core0 { 124 cpu = <&CPU0>; 125 }; 126 core1 { 127 cpu = <&CPU1>; 128 }; 129 core2 { 130 cpu = <&CPU2>; 131 }; 132 core3 { 133 cpu = <&CPU3>; 134 }; 135 }; 136 137 cluster1 { 138 core0 { 139 cpu = <&CPU4>; 140 }; 141 core1 { 142 cpu = <&CPU5>; 143 }; 144 core2 { 145 cpu = <&CPU6>; 146 }; 147 core3 { 148 cpu = <&CPU7>; 149 }; 150 }; 151 }; 152 153 L2_0: l2-cache-0 { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 }; 158 159 L2_1: l2-cache-1 { 160 compatible = "cache"; 161 cache-level = <2>; 162 cache-unified; 163 }; 164 }; 165 166 firmware { 167 scm: scm { 168 compatible = "qcom,scm-msm8953", "qcom,scm"; 169 clocks = <&gcc GCC_CRYPTO_CLK>, 170 <&gcc GCC_CRYPTO_AXI_CLK>, 171 <&gcc GCC_CRYPTO_AHB_CLK>; 172 clock-names = "core", "bus", "iface"; 173 #reset-cells = <1>; 174 }; 175 }; 176 177 memory@10000000 { 178 device_type = "memory"; 179 /* We expect the bootloader to fill in the reg */ 180 reg = <0 0x10000000 0 0>; 181 }; 182 183 pmu { 184 compatible = "arm,cortex-a53-pmu"; 185 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 186 }; 187 188 psci { 189 compatible = "arm,psci-1.0"; 190 method = "smc"; 191 }; 192 193 rpm: remoteproc { 194 compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc"; 195 196 smd-edge { 197 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 198 qcom,ipc = <&apcs 8 0>; 199 qcom,smd-edge = <15>; 200 201 rpm_requests: rpm-requests { 202 compatible = "qcom,rpm-msm8953"; 203 qcom,smd-channels = "rpm_requests"; 204 205 rpmcc: clock-controller { 206 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; 207 clocks = <&xo_board>; 208 clock-names = "xo"; 209 #clock-cells = <1>; 210 }; 211 212 rpmpd: power-controller { 213 compatible = "qcom,msm8953-rpmpd"; 214 #power-domain-cells = <1>; 215 operating-points-v2 = <&rpmpd_opp_table>; 216 217 rpmpd_opp_table: opp-table { 218 compatible = "operating-points-v2"; 219 220 rpmpd_opp_ret: opp1 { 221 opp-level = <RPM_SMD_LEVEL_RETENTION>; 222 }; 223 224 rpmpd_opp_ret_plus: opp2 { 225 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 226 }; 227 228 rpmpd_opp_min_svs: opp3 { 229 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 230 }; 231 232 rpmpd_opp_low_svs: opp4 { 233 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 234 }; 235 236 rpmpd_opp_svs: opp5 { 237 opp-level = <RPM_SMD_LEVEL_SVS>; 238 }; 239 240 rpmpd_opp_svs_plus: opp6 { 241 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 242 }; 243 244 rpmpd_opp_nom: opp7 { 245 opp-level = <RPM_SMD_LEVEL_NOM>; 246 }; 247 248 rpmpd_opp_nom_plus: opp8 { 249 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 250 }; 251 252 rpmpd_opp_turbo: opp9 { 253 opp-level = <RPM_SMD_LEVEL_TURBO>; 254 }; 255 }; 256 }; 257 }; 258 }; 259 }; 260 261 reserved-memory { 262 #address-cells = <2>; 263 #size-cells = <2>; 264 ranges; 265 266 zap_shader_region: zap@81800000 { 267 compatible = "shared-dma-pool"; 268 reg = <0x0 0x81800000 0x0 0x2000>; 269 no-map; 270 }; 271 272 qseecom_mem: qseecom@85b00000 { 273 reg = <0x0 0x85b00000 0x0 0x800000>; 274 no-map; 275 }; 276 277 smem_mem: smem@86300000 { 278 compatible = "qcom,smem"; 279 reg = <0x0 0x86300000 0x0 0x100000>; 280 qcom,rpm-msg-ram = <&rpm_msg_ram>; 281 hwlocks = <&tcsr_mutex 3>; 282 no-map; 283 }; 284 285 reserved@86400000 { 286 reg = <0x0 0x86400000 0x0 0x400000>; 287 no-map; 288 }; 289 290 mpss_mem: mpss@86c00000 { 291 reg = <0x0 0x86c00000 0x0 0x6a00000>; 292 no-map; 293 }; 294 295 adsp_fw_mem: adsp@8d600000 { 296 reg = <0x0 0x8d600000 0x0 0x1100000>; 297 no-map; 298 }; 299 300 wcnss_fw_mem: wcnss@8e700000 { 301 reg = <0x0 0x8e700000 0x0 0x700000>; 302 no-map; 303 }; 304 305 dfps_data_mem: dfps-data@90000000 { 306 reg = <0 0x90000000 0 0x1000>; 307 no-map; 308 }; 309 310 cont_splash_mem: cont-splash@90001000 { 311 reg = <0x0 0x90001000 0x0 0x13ff000>; 312 no-map; 313 }; 314 315 venus_mem: venus@91400000 { 316 reg = <0x0 0x91400000 0x0 0x700000>; 317 no-map; 318 }; 319 320 mba_mem: mba@92000000 { 321 reg = <0x0 0x92000000 0x0 0x100000>; 322 no-map; 323 }; 324 325 rmtfs@f2d00000 { 326 compatible = "qcom,rmtfs-mem"; 327 reg = <0x0 0xf2d00000 0x0 0x180000>; 328 no-map; 329 330 qcom,client-id = <1>; 331 }; 332 }; 333 334 smp2p-adsp { 335 compatible = "qcom,smp2p"; 336 qcom,smem = <443>, <429>; 337 338 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 339 340 mboxes = <&apcs 10>; 341 342 qcom,local-pid = <0>; 343 qcom,remote-pid = <2>; 344 345 smp2p_adsp_out: master-kernel { 346 qcom,entry-name = "master-kernel"; 347 #qcom,smem-state-cells = <1>; 348 }; 349 350 smp2p_adsp_in: slave-kernel { 351 qcom,entry-name = "slave-kernel"; 352 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 }; 356 }; 357 358 smp2p-modem { 359 compatible = "qcom,smp2p"; 360 qcom,smem = <435>, <428>; 361 362 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 363 364 qcom,ipc = <&apcs 8 14>; 365 366 qcom,local-pid = <0>; 367 qcom,remote-pid = <1>; 368 369 smp2p_modem_out: master-kernel { 370 qcom,entry-name = "master-kernel"; 371 372 #qcom,smem-state-cells = <1>; 373 }; 374 375 smp2p_modem_in: slave-kernel { 376 qcom,entry-name = "slave-kernel"; 377 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 }; 381 }; 382 383 smp2p-wcnss { 384 compatible = "qcom,smp2p"; 385 qcom,smem = <451>, <431>; 386 387 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 388 389 qcom,ipc = <&apcs 8 18>; 390 391 qcom,local-pid = <0>; 392 qcom,remote-pid = <4>; 393 394 smp2p_wcnss_out: master-kernel { 395 qcom,entry-name = "master-kernel"; 396 397 #qcom,smem-state-cells = <1>; 398 }; 399 400 smp2p_wcnss_in: slave-kernel { 401 qcom,entry-name = "slave-kernel"; 402 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 }; 407 408 smsm { 409 compatible = "qcom,smsm"; 410 411 #address-cells = <1>; 412 #size-cells = <0>; 413 414 qcom,ipc-1 = <&apcs 8 13>; 415 qcom,ipc-3 = <&apcs 8 19>; 416 417 apps_smsm: apps@0 { 418 reg = <0>; 419 420 #qcom,smem-state-cells = <1>; 421 }; 422 423 modem_smsm: modem@1 { 424 reg = <1>; 425 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 426 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 431 wcnss_smsm: wcnss@6 { 432 reg = <6>; 433 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 434 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 }; 438 }; 439 440 soc: soc@0 { 441 #address-cells = <1>; 442 #size-cells = <1>; 443 ranges = <0 0 0 0xffffffff>; 444 compatible = "simple-bus"; 445 446 rpm_msg_ram: sram@60000 { 447 compatible = "qcom,rpm-msg-ram"; 448 reg = <0x00060000 0x8000>; 449 }; 450 451 hsusb_phy: phy@79000 { 452 compatible = "qcom,msm8953-qusb2-phy"; 453 reg = <0x00079000 0x180>; 454 #phy-cells = <0>; 455 456 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 457 <&gcc GCC_QUSB_REF_CLK>; 458 clock-names = "cfg_ahb", "ref"; 459 460 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; 461 462 resets = <&gcc GCC_QUSB2_PHY_BCR>; 463 464 status = "disabled"; 465 }; 466 467 rng@e3000 { 468 compatible = "qcom,prng"; 469 reg = <0x000e3000 0x1000>; 470 clocks = <&gcc GCC_PRNG_AHB_CLK>; 471 clock-names = "core"; 472 }; 473 474 tsens0: thermal-sensor@4a9000 { 475 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; 476 reg = <0x004a9000 0x1000>, /* TM */ 477 <0x004a8000 0x1000>; /* SROT */ 478 #qcom,sensors = <16>; 479 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "uplow", "critical"; 482 #thermal-sensor-cells = <1>; 483 }; 484 485 restart@4ab000 { 486 compatible = "qcom,pshold"; 487 reg = <0x004ab000 0x4>; 488 }; 489 490 tlmm: pinctrl@1000000 { 491 compatible = "qcom,msm8953-pinctrl"; 492 reg = <0x01000000 0x300000>; 493 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 494 gpio-controller; 495 gpio-ranges = <&tlmm 0 0 142>; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 500 uart_console_active: uart-console-active-state { 501 pins = "gpio4", "gpio5"; 502 function = "blsp_uart2"; 503 drive-strength = <2>; 504 bias-disable; 505 }; 506 507 uart_console_sleep: uart-console-sleep-state { 508 pins = "gpio4", "gpio5"; 509 function = "blsp_uart2"; 510 drive-strength = <2>; 511 bias-pull-down; 512 }; 513 514 sdc1_clk_on: sdc1-clk-on-state { 515 pins = "sdc1_clk"; 516 bias-disable; 517 drive-strength = <16>; 518 }; 519 520 sdc1_clk_off: sdc1-clk-off-state { 521 pins = "sdc1_clk"; 522 bias-disable; 523 drive-strength = <2>; 524 }; 525 526 sdc1_cmd_on: sdc1-cmd-on-state { 527 pins = "sdc1_cmd"; 528 bias-disable; 529 drive-strength = <10>; 530 }; 531 532 sdc1_cmd_off: sdc1-cmd-off-state { 533 pins = "sdc1_cmd"; 534 bias-disable; 535 drive-strength = <2>; 536 }; 537 538 sdc1_data_on: sdc1-data-on-state { 539 pins = "sdc1_data"; 540 bias-pull-up; 541 drive-strength = <10>; 542 }; 543 544 sdc1_data_off: sdc1-data-off-state { 545 pins = "sdc1_data"; 546 bias-pull-up; 547 drive-strength = <2>; 548 }; 549 550 sdc1_rclk_on: sdc1-rclk-on-state { 551 pins = "sdc1_rclk"; 552 bias-pull-down; 553 }; 554 555 sdc1_rclk_off: sdc1-rclk-off-state { 556 pins = "sdc1_rclk"; 557 bias-pull-down; 558 }; 559 560 sdc2_clk_on: sdc2-clk-on-state { 561 pins = "sdc2_clk"; 562 drive-strength = <16>; 563 bias-disable; 564 }; 565 566 sdc2_clk_off: sdc2-clk-off-state { 567 pins = "sdc2_clk"; 568 bias-disable; 569 drive-strength = <2>; 570 }; 571 572 sdc2_cmd_on: sdc2-cmd-on-state { 573 pins = "sdc2_cmd"; 574 bias-pull-up; 575 drive-strength = <10>; 576 }; 577 578 sdc2_cmd_off: sdc2-cmd-off-state { 579 pins = "sdc2_cmd"; 580 bias-pull-up; 581 drive-strength = <2>; 582 }; 583 584 sdc2_data_on: sdc2-data-on-state { 585 pins = "sdc2_data"; 586 bias-pull-up; 587 drive-strength = <10>; 588 }; 589 590 sdc2_data_off: sdc2-data-off-state { 591 pins = "sdc2_data"; 592 bias-pull-up; 593 drive-strength = <2>; 594 }; 595 596 sdc2_cd_on: cd-on-state { 597 pins = "gpio133"; 598 function = "gpio"; 599 drive-strength = <2>; 600 bias-pull-up; 601 }; 602 603 sdc2_cd_off: cd-off-state { 604 pins = "gpio133"; 605 function = "gpio"; 606 drive-strength = <2>; 607 bias-disable; 608 }; 609 610 gpio_key_default: gpio-key-default-state { 611 pins = "gpio85"; 612 function = "gpio"; 613 drive-strength = <2>; 614 bias-pull-up; 615 }; 616 617 i2c_1_default: i2c-1-default-state { 618 pins = "gpio2", "gpio3"; 619 function = "blsp_i2c1"; 620 drive-strength = <2>; 621 bias-disable; 622 }; 623 624 i2c_1_sleep: i2c-1-sleep-state { 625 pins = "gpio2", "gpio3"; 626 function = "gpio"; 627 drive-strength = <2>; 628 bias-disable; 629 }; 630 631 i2c_2_default: i2c-2-default-state { 632 pins = "gpio6", "gpio7"; 633 function = "blsp_i2c2"; 634 drive-strength = <2>; 635 bias-disable; 636 }; 637 638 i2c_2_sleep: i2c-2-sleep-state { 639 pins = "gpio6", "gpio7"; 640 function = "gpio"; 641 drive-strength = <2>; 642 bias-disable; 643 }; 644 645 i2c_3_default: i2c-3-default-state { 646 pins = "gpio10", "gpio11"; 647 function = "blsp_i2c3"; 648 drive-strength = <2>; 649 bias-disable; 650 }; 651 652 i2c_3_sleep: i2c-3-sleep-state { 653 pins = "gpio10", "gpio11"; 654 function = "gpio"; 655 drive-strength = <2>; 656 bias-disable; 657 }; 658 659 i2c_4_default: i2c-4-default-state { 660 pins = "gpio14", "gpio15"; 661 function = "blsp_i2c4"; 662 drive-strength = <2>; 663 bias-disable; 664 }; 665 666 i2c_4_sleep: i2c-4-sleep-state { 667 pins = "gpio14", "gpio15"; 668 function = "gpio"; 669 drive-strength = <2>; 670 bias-disable; 671 }; 672 673 i2c_5_default: i2c-5-default-state { 674 pins = "gpio18", "gpio19"; 675 function = "blsp_i2c5"; 676 drive-strength = <2>; 677 bias-disable; 678 }; 679 680 i2c_5_sleep: i2c-5-sleep-state { 681 pins = "gpio18", "gpio19"; 682 function = "gpio"; 683 drive-strength = <2>; 684 bias-disable; 685 }; 686 687 i2c_6_default: i2c-6-default-state { 688 pins = "gpio22", "gpio23"; 689 function = "blsp_i2c6"; 690 drive-strength = <2>; 691 bias-disable; 692 }; 693 694 i2c_6_sleep: i2c-6-sleep-state { 695 pins = "gpio22", "gpio23"; 696 function = "gpio"; 697 drive-strength = <2>; 698 bias-disable; 699 }; 700 701 i2c_7_default: i2c-7-default-state { 702 pins = "gpio135", "gpio136"; 703 function = "blsp_i2c7"; 704 drive-strength = <2>; 705 bias-disable; 706 }; 707 708 i2c_7_sleep: i2c-7-sleep-state { 709 pins = "gpio135", "gpio136"; 710 function = "gpio"; 711 drive-strength = <2>; 712 bias-disable; 713 }; 714 715 i2c_8_default: i2c-8-default-state { 716 pins = "gpio98", "gpio99"; 717 function = "blsp_i2c8"; 718 drive-strength = <2>; 719 bias-disable; 720 }; 721 722 i2c_8_sleep: i2c-8-sleep-state { 723 pins = "gpio98", "gpio99"; 724 function = "gpio"; 725 drive-strength = <2>; 726 bias-disable; 727 }; 728 729 spi_3_default: spi-3-default-state { 730 pins = "gpio10", "gpio11"; 731 function = "blsp_spi3"; 732 drive-strength = <2>; 733 bias-disable; 734 }; 735 736 spi_3_sleep: spi-3-sleep-state { 737 pins = "gpio10", "gpio11"; 738 function = "gpio"; 739 drive-strength = <2>; 740 bias-disable; 741 }; 742 743 spi_5_default: spi-5-default-state { 744 pins = "gpio18", "gpio19"; 745 function = "blsp_spi5"; 746 drive-strength = <2>; 747 bias-disable; 748 }; 749 750 spi_5_sleep: spi-5-sleep-state { 751 pins = "gpio18", "gpio19"; 752 function = "gpio"; 753 drive-strength = <2>; 754 bias-disable; 755 }; 756 757 spi_6_default: spi-6-default-state { 758 pins = "gpio22", "gpio23"; 759 function = "blsp_spi6"; 760 drive-strength = <2>; 761 bias-disable; 762 }; 763 764 spi_6_sleep: spi-6-sleep-state { 765 pins = "gpio22", "gpio23"; 766 function = "gpio"; 767 drive-strength = <2>; 768 bias-disable; 769 }; 770 771 wcnss_pin_a: wcnss-active-state { 772 773 wcss-wlan2-pins { 774 pins = "gpio76"; 775 function = "wcss_wlan2"; 776 drive-strength = <6>; 777 bias-pull-up; 778 }; 779 780 wcss-wlan1-pins { 781 pins = "gpio77"; 782 function = "wcss_wlan1"; 783 drive-strength = <6>; 784 bias-pull-up; 785 }; 786 787 wcss-wlan0-pins { 788 pins = "gpio78"; 789 function = "wcss_wlan0"; 790 drive-strength = <6>; 791 bias-pull-up; 792 }; 793 794 wcss-wlan-pins { 795 pins = "gpio79", "gpio80"; 796 function = "wcss_wlan"; 797 drive-strength = <6>; 798 bias-pull-up; 799 }; 800 }; 801 }; 802 803 gcc: clock-controller@1800000 { 804 compatible = "qcom,gcc-msm8953"; 805 reg = <0x01800000 0x80000>; 806 #clock-cells = <1>; 807 #reset-cells = <1>; 808 #power-domain-cells = <1>; 809 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 810 <&sleep_clk>, 811 <&mdss_dsi0_phy 1>, 812 <&mdss_dsi0_phy 0>, 813 <&mdss_dsi1_phy 1>, 814 <&mdss_dsi1_phy 0>; 815 clock-names = "xo", 816 "sleep", 817 "dsi0pll", 818 "dsi0pllbyte", 819 "dsi1pll", 820 "dsi1pllbyte"; 821 }; 822 823 tcsr_mutex: hwlock@1905000 { 824 compatible = "qcom,tcsr-mutex"; 825 reg = <0x01905000 0x20000>; 826 #hwlock-cells = <1>; 827 }; 828 829 tcsr: syscon@1937000 { 830 compatible = "qcom,tcsr-msm8953", "syscon"; 831 reg = <0x01937000 0x30000>; 832 }; 833 834 tcsr_phy_clk_scheme_sel: syscon@193f044 { 835 compatible = "qcom,tcsr-msm8953", "syscon"; 836 reg = <0x0193f044 0x4>; 837 }; 838 839 mdss: display-subsystem@1a00000 { 840 compatible = "qcom,mdss"; 841 842 reg = <0x01a00000 0x1000>, 843 <0x01ab0000 0x1040>; 844 reg-names = "mdss_phys", 845 "vbif_phys"; 846 847 power-domains = <&gcc MDSS_GDSC>; 848 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 849 850 interrupt-controller; 851 #interrupt-cells = <1>; 852 853 clocks = <&gcc GCC_MDSS_AHB_CLK>, 854 <&gcc GCC_MDSS_AXI_CLK>, 855 <&gcc GCC_MDSS_VSYNC_CLK>, 856 <&gcc GCC_MDSS_MDP_CLK>; 857 clock-names = "iface", 858 "bus", 859 "vsync", 860 "core"; 861 862 #address-cells = <1>; 863 #size-cells = <1>; 864 ranges; 865 866 status = "disabled"; 867 868 mdp: display-controller@1a01000 { 869 compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; 870 reg = <0x01a01000 0x89000>; 871 reg-names = "mdp_phys"; 872 873 interrupt-parent = <&mdss>; 874 interrupts = <0>; 875 876 power-domains = <&gcc MDSS_GDSC>; 877 878 clocks = <&gcc GCC_MDSS_AHB_CLK>, 879 <&gcc GCC_MDSS_AXI_CLK>, 880 <&gcc GCC_MDSS_MDP_CLK>, 881 <&gcc GCC_MDSS_VSYNC_CLK>; 882 clock-names = "iface", 883 "bus", 884 "core", 885 "vsync"; 886 887 iommus = <&apps_iommu 0x15>; 888 889 ports { 890 #address-cells = <1>; 891 #size-cells = <0>; 892 893 port@0 { 894 reg = <0>; 895 mdp5_intf1_out: endpoint { 896 remote-endpoint = <&mdss_dsi0_in>; 897 }; 898 }; 899 900 port@1 { 901 reg = <1>; 902 mdp5_intf2_out: endpoint { 903 remote-endpoint = <&mdss_dsi1_in>; 904 }; 905 }; 906 }; 907 }; 908 909 mdss_dsi0: dsi@1a94000 { 910 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 911 reg = <0x01a94000 0x400>; 912 reg-names = "dsi_ctrl"; 913 914 interrupt-parent = <&mdss>; 915 interrupts = <4>; 916 917 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 918 <&gcc PCLK0_CLK_SRC>; 919 assigned-clock-parents = <&mdss_dsi0_phy 0>, 920 <&mdss_dsi0_phy 1>; 921 922 clocks = <&gcc GCC_MDSS_MDP_CLK>, 923 <&gcc GCC_MDSS_AHB_CLK>, 924 <&gcc GCC_MDSS_AXI_CLK>, 925 <&gcc GCC_MDSS_BYTE0_CLK>, 926 <&gcc GCC_MDSS_PCLK0_CLK>, 927 <&gcc GCC_MDSS_ESC0_CLK>; 928 clock-names = "mdp_core", 929 "iface", 930 "bus", 931 "byte", 932 "pixel", 933 "core"; 934 935 phys = <&mdss_dsi0_phy>; 936 937 #address-cells = <1>; 938 #size-cells = <0>; 939 940 status = "disabled"; 941 942 ports { 943 #address-cells = <1>; 944 #size-cells = <0>; 945 946 port@0 { 947 reg = <0>; 948 mdss_dsi0_in: endpoint { 949 remote-endpoint = <&mdp5_intf1_out>; 950 }; 951 }; 952 953 port@1 { 954 reg = <1>; 955 mdss_dsi0_out: endpoint { 956 }; 957 }; 958 }; 959 }; 960 961 mdss_dsi0_phy: phy@1a94400 { 962 compatible = "qcom,dsi-phy-14nm-8953"; 963 reg = <0x01a94400 0x100>, 964 <0x01a94500 0x300>, 965 <0x01a94800 0x188>; 966 reg-names = "dsi_phy", 967 "dsi_phy_lane", 968 "dsi_pll"; 969 970 #clock-cells = <1>; 971 #phy-cells = <0>; 972 973 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 974 clock-names = "iface", "ref"; 975 976 status = "disabled"; 977 }; 978 979 mdss_dsi1: dsi@1a96000 { 980 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 981 reg = <0x01a96000 0x400>; 982 reg-names = "dsi_ctrl"; 983 984 interrupt-parent = <&mdss>; 985 interrupts = <5>; 986 987 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 988 <&gcc PCLK1_CLK_SRC>; 989 assigned-clock-parents = <&mdss_dsi1_phy 0>, 990 <&mdss_dsi1_phy 1>; 991 992 clocks = <&gcc GCC_MDSS_MDP_CLK>, 993 <&gcc GCC_MDSS_AHB_CLK>, 994 <&gcc GCC_MDSS_AXI_CLK>, 995 <&gcc GCC_MDSS_BYTE1_CLK>, 996 <&gcc GCC_MDSS_PCLK1_CLK>, 997 <&gcc GCC_MDSS_ESC1_CLK>; 998 clock-names = "mdp_core", 999 "iface", 1000 "bus", 1001 "byte", 1002 "pixel", 1003 "core"; 1004 1005 phys = <&mdss_dsi1_phy>; 1006 1007 status = "disabled"; 1008 1009 ports { 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 1013 port@0 { 1014 reg = <0>; 1015 mdss_dsi1_in: endpoint { 1016 remote-endpoint = <&mdp5_intf2_out>; 1017 }; 1018 }; 1019 1020 port@1 { 1021 reg = <1>; 1022 mdss_dsi1_out: endpoint { 1023 }; 1024 }; 1025 }; 1026 }; 1027 1028 mdss_dsi1_phy: phy@1a96400 { 1029 compatible = "qcom,dsi-phy-14nm-8953"; 1030 reg = <0x01a96400 0x100>, 1031 <0x01a96500 0x300>, 1032 <0x01a96800 0x188>; 1033 reg-names = "dsi_phy", 1034 "dsi_phy_lane", 1035 "dsi_pll"; 1036 1037 #clock-cells = <1>; 1038 #phy-cells = <0>; 1039 1040 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1041 clock-names = "iface", "ref"; 1042 1043 status = "disabled"; 1044 }; 1045 }; 1046 1047 apps_iommu: iommu@1e20000 { 1048 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; 1049 ranges = <0 0x01e20000 0x20000>; 1050 1051 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1052 <&gcc GCC_APSS_TCU_ASYNC_CLK>; 1053 clock-names = "iface", "bus"; 1054 1055 qcom,iommu-secure-id = <17>; 1056 1057 #address-cells = <1>; 1058 #iommu-cells = <1>; 1059 #size-cells = <1>; 1060 1061 /* VFE */ 1062 iommu-ctx@14000 { 1063 compatible = "qcom,msm-iommu-v1-ns"; 1064 reg = <0x14000 0x1000>; 1065 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1066 }; 1067 1068 /* MDP_0 */ 1069 iommu-ctx@15000 { 1070 compatible = "qcom,msm-iommu-v1-ns"; 1071 reg = <0x15000 0x1000>; 1072 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1073 }; 1074 1075 /* VENUS_NS */ 1076 iommu-ctx@16000 { 1077 compatible = "qcom,msm-iommu-v1-ns"; 1078 reg = <0x16000 0x1000>; 1079 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1080 }; 1081 }; 1082 1083 spmi_bus: spmi@200f000 { 1084 compatible = "qcom,spmi-pmic-arb"; 1085 reg = <0x0200f000 0x1000>, 1086 <0x02400000 0x800000>, 1087 <0x02c00000 0x800000>, 1088 <0x03800000 0x200000>, 1089 <0x0200a000 0x2100>; 1090 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1091 interrupt-names = "periph_irq"; 1092 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1093 qcom,ee = <0>; 1094 qcom,channel = <0>; 1095 interrupt-controller; 1096 1097 #interrupt-cells = <4>; 1098 #address-cells = <2>; 1099 #size-cells = <0>; 1100 }; 1101 1102 mpss: remoteproc@4080000 { 1103 compatible = "qcom,msm8953-mss-pil"; 1104 reg = <0x04080000 0x100>, 1105 <0x04020000 0x040>; 1106 reg-names = "qdsp6", "rmb"; 1107 1108 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1109 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1110 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1111 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1112 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>; 1113 interrupt-names = "wdog", "fatal", "ready", 1114 "handover", "stop-ack"; 1115 1116 power-domains = <&rpmpd MSM8953_VDDCX>, 1117 <&rpmpd MSM8953_VDDMX>, 1118 <&rpmpd MSM8953_VDDMD>; 1119 power-domain-names = "cx", "mx","mss"; 1120 1121 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1122 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1123 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1124 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1125 clock-names = "iface", "bus", "mem", "xo"; 1126 1127 qcom,smem-states = <&smp2p_modem_out 0>; 1128 qcom,smem-state-names = "stop"; 1129 1130 resets = <&gcc GCC_MSS_BCR>; 1131 reset-names = "mss_restart"; 1132 1133 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1134 1135 status = "disabled"; 1136 1137 mba { 1138 memory-region = <&mba_mem>; 1139 }; 1140 1141 mpss { 1142 memory-region = <&mpss_mem>; 1143 }; 1144 1145 smd-edge { 1146 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1147 1148 qcom,smd-edge = <0>; 1149 qcom,ipc = <&apcs 8 12>; 1150 qcom,remote-pid = <1>; 1151 1152 label = "modem"; 1153 }; 1154 }; 1155 1156 usb3: usb@70f8800 { 1157 compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; 1158 reg = <0x070f8800 0x400>; 1159 #address-cells = <1>; 1160 #size-cells = <1>; 1161 ranges; 1162 1163 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1165 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1166 1167 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 1168 <&gcc GCC_USB30_MASTER_CLK>, 1169 <&gcc GCC_PCNOC_USB3_AXI_CLK>, 1170 <&gcc GCC_USB30_SLEEP_CLK>, 1171 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1172 clock-names = "cfg_noc", 1173 "core", 1174 "iface", 1175 "sleep", 1176 "mock_utmi"; 1177 1178 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1179 <&gcc GCC_USB30_MASTER_CLK>; 1180 assigned-clock-rates = <19200000>, <133330000>; 1181 1182 power-domains = <&gcc USB30_GDSC>; 1183 1184 qcom,select-utmi-as-pipe-clk; 1185 1186 status = "disabled"; 1187 1188 usb3_dwc3: usb@7000000 { 1189 compatible = "snps,dwc3"; 1190 reg = <0x07000000 0xcc00>; 1191 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1192 phys = <&hsusb_phy>; 1193 phy-names = "usb2-phy"; 1194 1195 snps,usb2-gadget-lpm-disable; 1196 snps,dis-u1-entry-quirk; 1197 snps,dis-u2-entry-quirk; 1198 snps,is-utmi-l1-suspend; 1199 snps,hird-threshold = /bits/ 8 <0x00>; 1200 1201 maximum-speed = "high-speed"; 1202 }; 1203 }; 1204 1205 sdhc_1: mmc@7824900 { 1206 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1207 1208 reg = <0x07824900 0x500>, <0x07824000 0x800>; 1209 reg-names = "hc", "core"; 1210 1211 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1213 interrupt-names = "hc_irq", "pwr_irq"; 1214 1215 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1216 <&gcc GCC_SDCC1_APPS_CLK>, 1217 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1218 clock-names = "iface", "core", "xo"; 1219 1220 power-domains = <&rpmpd MSM8953_VDDCX>; 1221 operating-points-v2 = <&sdhc1_opp_table>; 1222 1223 pinctrl-names = "default", "sleep"; 1224 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 1225 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 1226 1227 mmc-hs400-1_8v; 1228 mmc-hs200-1_8v; 1229 mmc-ddr-1_8v; 1230 bus-width = <8>; 1231 non-removable; 1232 1233 status = "disabled"; 1234 1235 sdhc1_opp_table: opp-table-sdhc1 { 1236 compatible = "operating-points-v2"; 1237 1238 opp-25000000 { 1239 opp-hz = /bits/ 64 <25000000>; 1240 required-opps = <&rpmpd_opp_low_svs>; 1241 }; 1242 1243 opp-50000000 { 1244 opp-hz = /bits/ 64 <50000000>; 1245 required-opps = <&rpmpd_opp_svs>; 1246 }; 1247 1248 opp-100000000 { 1249 opp-hz = /bits/ 64 <100000000>; 1250 required-opps = <&rpmpd_opp_svs>; 1251 }; 1252 1253 opp-192000000 { 1254 opp-hz = /bits/ 64 <192000000>; 1255 required-opps = <&rpmpd_opp_nom>; 1256 }; 1257 1258 opp-384000000 { 1259 opp-hz = /bits/ 64 <384000000>; 1260 required-opps = <&rpmpd_opp_nom>; 1261 }; 1262 }; 1263 }; 1264 1265 sdhc_2: mmc@7864900 { 1266 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1267 1268 reg = <0x07864900 0x500>, <0x07864000 0x800>; 1269 reg-names = "hc", "core"; 1270 1271 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1273 interrupt-names = "hc_irq", "pwr_irq"; 1274 1275 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1276 <&gcc GCC_SDCC2_APPS_CLK>, 1277 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1278 clock-names = "iface", "core", "xo"; 1279 1280 power-domains = <&rpmpd MSM8953_VDDCX>; 1281 operating-points-v2 = <&sdhc2_opp_table>; 1282 1283 pinctrl-names = "default", "sleep"; 1284 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 1285 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 1286 1287 bus-width = <4>; 1288 1289 status = "disabled"; 1290 1291 sdhc2_opp_table: opp-table-sdhc2 { 1292 compatible = "operating-points-v2"; 1293 1294 opp-25000000 { 1295 opp-hz = /bits/ 64 <25000000>; 1296 required-opps = <&rpmpd_opp_low_svs>; 1297 }; 1298 1299 opp-50000000 { 1300 opp-hz = /bits/ 64 <50000000>; 1301 required-opps = <&rpmpd_opp_svs>; 1302 }; 1303 1304 opp-100000000 { 1305 opp-hz = /bits/ 64 <100000000>; 1306 required-opps = <&rpmpd_opp_svs>; 1307 }; 1308 1309 opp-177770000 { 1310 opp-hz = /bits/ 64 <177770000>; 1311 required-opps = <&rpmpd_opp_nom>; 1312 }; 1313 1314 opp-200000000 { 1315 opp-hz = /bits/ 64 <200000000>; 1316 required-opps = <&rpmpd_opp_nom>; 1317 }; 1318 }; 1319 }; 1320 1321 blsp1_dma: dma-controller@7884000 { 1322 compatible = "qcom,bam-v1.7.0"; 1323 reg = <0x07884000 0x1f000>; 1324 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1326 clock-names = "bam_clk"; 1327 num-channels = <12>; 1328 #dma-cells = <1>; 1329 qcom,ee = <0>; 1330 qcom,num-ees = <4>; 1331 qcom,controlled-remotely; 1332 }; 1333 1334 uart_0: serial@78af000 { 1335 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1336 reg = <0x078af000 0x200>; 1337 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1339 <&gcc GCC_BLSP1_AHB_CLK>; 1340 clock-names = "core", "iface"; 1341 1342 status = "disabled"; 1343 }; 1344 1345 i2c_1: i2c@78b5000 { 1346 compatible = "qcom,i2c-qup-v2.2.1"; 1347 reg = <0x078b5000 0x600>; 1348 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1349 clock-names = "core", "iface"; 1350 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1351 <&gcc GCC_BLSP1_AHB_CLK>; 1352 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1353 dma-names = "tx", "rx"; 1354 1355 pinctrl-names = "default", "sleep"; 1356 pinctrl-0 = <&i2c_1_default>; 1357 pinctrl-1 = <&i2c_1_sleep>; 1358 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 1362 status = "disabled"; 1363 }; 1364 1365 i2c_2: i2c@78b6000 { 1366 compatible = "qcom,i2c-qup-v2.2.1"; 1367 reg = <0x078b6000 0x600>; 1368 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1369 clock-names = "core", "iface"; 1370 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1371 <&gcc GCC_BLSP1_AHB_CLK>; 1372 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1373 dma-names = "tx", "rx"; 1374 1375 pinctrl-names = "default", "sleep"; 1376 pinctrl-0 = <&i2c_2_default>; 1377 pinctrl-1 = <&i2c_2_sleep>; 1378 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 1382 status = "disabled"; 1383 }; 1384 1385 i2c_3: i2c@78b7000 { 1386 compatible = "qcom,i2c-qup-v2.2.1"; 1387 reg = <0x078b7000 0x600>; 1388 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1389 clock-names = "core", "iface"; 1390 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1391 <&gcc GCC_BLSP1_AHB_CLK>; 1392 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1393 dma-names = "tx", "rx"; 1394 1395 pinctrl-names = "default", "sleep"; 1396 pinctrl-0 = <&i2c_3_default>; 1397 pinctrl-1 = <&i2c_3_sleep>; 1398 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 1402 status = "disabled"; 1403 }; 1404 1405 spi_3: spi@78b7000 { 1406 compatible = "qcom,spi-qup-v2.2.1"; 1407 reg = <0x078b7000 0x600>; 1408 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1409 clock-names = "core", "iface"; 1410 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1411 <&gcc GCC_BLSP1_AHB_CLK>; 1412 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1413 dma-names = "tx", "rx"; 1414 1415 pinctrl-names = "default", "sleep"; 1416 pinctrl-0 = <&spi_3_default>; 1417 pinctrl-1 = <&spi_3_sleep>; 1418 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 1422 status = "disabled"; 1423 }; 1424 1425 i2c_4: i2c@78b8000 { 1426 compatible = "qcom,i2c-qup-v2.2.1"; 1427 reg = <0x078b8000 0x600>; 1428 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1429 clock-names = "core", "iface"; 1430 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1431 <&gcc GCC_BLSP1_AHB_CLK>; 1432 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1433 dma-names = "tx", "rx"; 1434 1435 pinctrl-names = "default", "sleep"; 1436 pinctrl-0 = <&i2c_4_default>; 1437 pinctrl-1 = <&i2c_4_sleep>; 1438 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 1442 status = "disabled"; 1443 }; 1444 1445 blsp2_dma: dma-controller@7ac4000 { 1446 compatible = "qcom,bam-v1.7.0"; 1447 reg = <0x07ac4000 0x1f000>; 1448 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1449 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1450 clock-names = "bam_clk"; 1451 num-channels = <12>; 1452 #dma-cells = <1>; 1453 qcom,ee = <0>; 1454 qcom,num-ees = <4>; 1455 qcom,controlled-remotely; 1456 }; 1457 1458 i2c_5: i2c@7af5000 { 1459 compatible = "qcom,i2c-qup-v2.2.1"; 1460 reg = <0x07af5000 0x600>; 1461 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1462 clock-names = "core", "iface"; 1463 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1464 <&gcc GCC_BLSP2_AHB_CLK>; 1465 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1466 dma-names = "tx", "rx"; 1467 1468 pinctrl-names = "default", "sleep"; 1469 pinctrl-0 = <&i2c_5_default>; 1470 pinctrl-1 = <&i2c_5_sleep>; 1471 1472 #address-cells = <1>; 1473 #size-cells = <0>; 1474 1475 status = "disabled"; 1476 }; 1477 1478 spi_5: spi@7af5000 { 1479 compatible = "qcom,spi-qup-v2.2.1"; 1480 reg = <0x07af5000 0x600>; 1481 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1482 clock-names = "core", "iface"; 1483 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1484 <&gcc GCC_BLSP2_AHB_CLK>; 1485 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1486 dma-names = "tx", "rx"; 1487 1488 pinctrl-names = "default", "sleep"; 1489 pinctrl-0 = <&spi_5_default>; 1490 pinctrl-1 = <&spi_5_sleep>; 1491 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 1495 status = "disabled"; 1496 }; 1497 1498 i2c_6: i2c@7af6000 { 1499 compatible = "qcom,i2c-qup-v2.2.1"; 1500 reg = <0x07af6000 0x600>; 1501 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1502 clock-names = "core", "iface"; 1503 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1504 <&gcc GCC_BLSP2_AHB_CLK>; 1505 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1506 dma-names = "tx", "rx"; 1507 1508 pinctrl-names = "default", "sleep"; 1509 pinctrl-0 = <&i2c_6_default>; 1510 pinctrl-1 = <&i2c_6_sleep>; 1511 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 1515 status = "disabled"; 1516 }; 1517 1518 spi_6: spi@7af6000 { 1519 compatible = "qcom,spi-qup-v2.2.1"; 1520 reg = <0x07af6000 0x600>; 1521 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1522 clock-names = "core", "iface"; 1523 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1524 <&gcc GCC_BLSP2_AHB_CLK>; 1525 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1526 dma-names = "tx", "rx"; 1527 1528 pinctrl-names = "default", "sleep"; 1529 pinctrl-0 = <&spi_6_default>; 1530 pinctrl-1 = <&spi_6_sleep>; 1531 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 1535 status = "disabled"; 1536 }; 1537 1538 i2c_7: i2c@7af7000 { 1539 compatible = "qcom,i2c-qup-v2.2.1"; 1540 reg = <0x07af7000 0x600>; 1541 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1542 clock-names = "core", "iface"; 1543 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1544 <&gcc GCC_BLSP2_AHB_CLK>; 1545 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1546 dma-names = "tx", "rx"; 1547 1548 pinctrl-names = "default", "sleep"; 1549 pinctrl-0 = <&i2c_7_default>; 1550 pinctrl-1 = <&i2c_7_sleep>; 1551 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 1555 status = "disabled"; 1556 }; 1557 1558 i2c_8: i2c@7af8000 { 1559 compatible = "qcom,i2c-qup-v2.2.1"; 1560 reg = <0x07af8000 0x600>; 1561 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1562 clock-names = "core", "iface"; 1563 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1564 <&gcc GCC_BLSP2_AHB_CLK>; 1565 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1566 dma-names = "tx", "rx"; 1567 1568 pinctrl-names = "default", "sleep"; 1569 pinctrl-0 = <&i2c_8_default>; 1570 pinctrl-1 = <&i2c_8_sleep>; 1571 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 1575 status = "disabled"; 1576 }; 1577 1578 wcnss: remoteproc@a204000 { 1579 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1580 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1581 reg-names = "ccu", "dxe", "pmu"; 1582 1583 memory-region = <&wcnss_fw_mem>; 1584 1585 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1586 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>, 1587 <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>, 1588 <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>, 1589 <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>; 1590 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1591 1592 power-domains = <&rpmpd MSM8953_VDDCX>, 1593 <&rpmpd MSM8953_VDDMX>; 1594 power-domain-names = "cx", "mx"; 1595 1596 qcom,smem-states = <&smp2p_wcnss_out 0>; 1597 qcom,smem-state-names = "stop"; 1598 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&wcnss_pin_a>; 1601 1602 status = "disabled"; 1603 1604 wcnss_iris: iris { 1605 /* Separate chip, compatible is board-specific */ 1606 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1607 clock-names = "xo"; 1608 }; 1609 1610 smd-edge { 1611 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1612 1613 qcom,ipc = <&apcs 8 17>; 1614 qcom,smd-edge = <6>; 1615 qcom,remote-pid = <4>; 1616 1617 label = "pronto"; 1618 1619 wcnss_ctrl: wcnss { 1620 compatible = "qcom,wcnss"; 1621 qcom,smd-channels = "WCNSS_CTRL"; 1622 1623 qcom,mmio = <&wcnss>; 1624 1625 wcnss_bt: bluetooth { 1626 compatible = "qcom,wcnss-bt"; 1627 }; 1628 1629 wcnss_wifi: wifi { 1630 compatible = "qcom,wcnss-wlan"; 1631 1632 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1634 interrupt-names = "tx", "rx"; 1635 1636 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1637 qcom,smem-state-names = "tx-enable", 1638 "tx-rings-empty"; 1639 }; 1640 }; 1641 }; 1642 }; 1643 1644 intc: interrupt-controller@b000000 { 1645 compatible = "qcom,msm-qgic2"; 1646 interrupt-controller; 1647 #interrupt-cells = <3>; 1648 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 1649 }; 1650 1651 apcs: mailbox@b011000 { 1652 compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; 1653 reg = <0x0b011000 0x1000>; 1654 #mbox-cells = <1>; 1655 }; 1656 1657 timer@b120000 { 1658 compatible = "arm,armv7-timer-mem"; 1659 reg = <0x0b120000 0x1000>; 1660 #address-cells = <1>; 1661 #size-cells = <1>; 1662 ranges; 1663 1664 frame@b121000 { 1665 frame-number = <0>; 1666 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1668 reg = <0x0b121000 0x1000>, 1669 <0x0b122000 0x1000>; 1670 }; 1671 1672 frame@b123000 { 1673 frame-number = <1>; 1674 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1675 reg = <0x0b123000 0x1000>; 1676 status = "disabled"; 1677 }; 1678 1679 frame@b124000 { 1680 frame-number = <2>; 1681 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1682 reg = <0x0b124000 0x1000>; 1683 status = "disabled"; 1684 }; 1685 1686 frame@b125000 { 1687 frame-number = <3>; 1688 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1689 reg = <0x0b125000 0x1000>; 1690 status = "disabled"; 1691 }; 1692 1693 frame@b126000 { 1694 frame-number = <4>; 1695 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1696 reg = <0x0b126000 0x1000>; 1697 status = "disabled"; 1698 }; 1699 1700 frame@b127000 { 1701 frame-number = <5>; 1702 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1703 reg = <0x0b127000 0x1000>; 1704 status = "disabled"; 1705 }; 1706 1707 frame@b128000 { 1708 frame-number = <6>; 1709 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1710 reg = <0x0b128000 0x1000>; 1711 status = "disabled"; 1712 }; 1713 }; 1714 1715 lpass: remoteproc@c200000 { 1716 compatible = "qcom,msm8953-adsp-pil"; 1717 reg = <0x0c200000 0x100>; 1718 1719 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>, 1720 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1721 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1722 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1723 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1724 interrupt-names = "wdog", "fatal", "ready", 1725 "handover", "stop-ack"; 1726 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1727 clock-names = "xo"; 1728 1729 power-domains = <&rpmpd MSM8953_VDDCX>; 1730 power-domain-names = "cx"; 1731 1732 memory-region = <&adsp_fw_mem>; 1733 1734 qcom,smem-states = <&smp2p_adsp_out 0>; 1735 qcom,smem-state-names = "stop"; 1736 1737 status = "disabled"; 1738 1739 smd-edge { 1740 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1741 1742 label = "lpass"; 1743 mboxes = <&apcs 8>; 1744 qcom,smd-edge = <1>; 1745 qcom,remote-pid = <2>; 1746 1747 apr { 1748 compatible = "qcom,apr-v2"; 1749 qcom,smd-channels = "apr_audio_svc"; 1750 qcom,domain = <APR_DOMAIN_ADSP>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 1754 q6core: service@3 { 1755 reg = <APR_SVC_ADSP_CORE>; 1756 compatible = "qcom,q6core"; 1757 }; 1758 1759 q6afe: service@4 { 1760 compatible = "qcom,q6afe"; 1761 reg = <APR_SVC_AFE>; 1762 q6afedai: dais { 1763 compatible = "qcom,q6afe-dais"; 1764 #address-cells = <1>; 1765 #size-cells = <0>; 1766 #sound-dai-cells = <1>; 1767 1768 dai@16 { 1769 reg = <PRIMARY_MI2S_RX>; 1770 qcom,sd-lines = <0 1>; 1771 }; 1772 dai@20 { 1773 reg = <TERTIARY_MI2S_TX>; 1774 qcom,sd-lines = <0 1>; 1775 }; 1776 dai@127 { 1777 reg = <QUINARY_MI2S_RX>; 1778 qcom,sd-lines = <0>; 1779 }; 1780 }; 1781 1782 q6afecc: clock-controller { 1783 compatible = "qcom,q6afe-clocks"; 1784 #clock-cells = <2>; 1785 }; 1786 }; 1787 1788 q6asm: service@7 { 1789 compatible = "qcom,q6asm"; 1790 reg = <APR_SVC_ASM>; 1791 q6asmdai: dais { 1792 compatible = "qcom,q6asm-dais"; 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 #sound-dai-cells = <1>; 1796 1797 dai@0 { 1798 reg = <0>; 1799 direction = <Q6ASM_DAI_RX>; 1800 }; 1801 dai@1 { 1802 reg = <1>; 1803 direction = <Q6ASM_DAI_TX>; 1804 }; 1805 dai@2 { 1806 reg = <2>; 1807 direction = <Q6ASM_DAI_RX>; 1808 }; 1809 dai@3 { 1810 reg = <3>; 1811 direction = <Q6ASM_DAI_RX>; 1812 is-compress-dai; 1813 }; 1814 }; 1815 }; 1816 1817 q6adm: service@8 { 1818 compatible = "qcom,q6adm"; 1819 reg = <APR_SVC_ADM>; 1820 q6routing: routing { 1821 compatible = "qcom,q6adm-routing"; 1822 #sound-dai-cells = <0>; 1823 }; 1824 }; 1825 }; 1826 }; 1827 }; 1828 }; 1829 1830 thermal-zones { 1831 cpu0-thermal { 1832 polling-delay-passive = <250>; 1833 polling-delay = <1000>; 1834 thermal-sensors = <&tsens0 9>; 1835 trips { 1836 cpu0_alert: trip-point0 { 1837 temperature = <80000>; 1838 hysteresis = <2000>; 1839 type = "passive"; 1840 }; 1841 cpu0_crit: crit { 1842 temperature = <100000>; 1843 hysteresis = <2000>; 1844 type = "critical"; 1845 }; 1846 }; 1847 cooling-maps { 1848 map0 { 1849 trip = <&cpu0_alert>; 1850 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1851 }; 1852 }; 1853 }; 1854 cpu1-thermal { 1855 polling-delay-passive = <250>; 1856 polling-delay = <1000>; 1857 thermal-sensors = <&tsens0 10>; 1858 trips { 1859 cpu1_alert: trip-point0 { 1860 temperature = <80000>; 1861 hysteresis = <2000>; 1862 type = "passive"; 1863 }; 1864 cpu1_crit: crit { 1865 temperature = <100000>; 1866 hysteresis = <2000>; 1867 type = "critical"; 1868 }; 1869 }; 1870 cooling-maps { 1871 map0 { 1872 trip = <&cpu1_alert>; 1873 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1874 }; 1875 }; 1876 }; 1877 cpu2-thermal { 1878 polling-delay-passive = <250>; 1879 polling-delay = <1000>; 1880 thermal-sensors = <&tsens0 11>; 1881 trips { 1882 cpu2_alert: trip-point0 { 1883 temperature = <80000>; 1884 hysteresis = <2000>; 1885 type = "passive"; 1886 }; 1887 cpu2_crit: crit { 1888 temperature = <100000>; 1889 hysteresis = <2000>; 1890 type = "critical"; 1891 }; 1892 }; 1893 cooling-maps { 1894 map0 { 1895 trip = <&cpu2_alert>; 1896 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1897 }; 1898 }; 1899 }; 1900 cpu3-thermal { 1901 polling-delay-passive = <250>; 1902 polling-delay = <1000>; 1903 thermal-sensors = <&tsens0 12>; 1904 trips { 1905 cpu3_alert: trip-point0 { 1906 temperature = <80000>; 1907 hysteresis = <2000>; 1908 type = "passive"; 1909 }; 1910 cpu3_crit: crit { 1911 temperature = <100000>; 1912 hysteresis = <2000>; 1913 type = "critical"; 1914 }; 1915 }; 1916 cooling-maps { 1917 map0 { 1918 trip = <&cpu3_alert>; 1919 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1920 }; 1921 }; 1922 }; 1923 cpu4-thermal { 1924 polling-delay-passive = <250>; 1925 polling-delay = <1000>; 1926 thermal-sensors = <&tsens0 4>; 1927 trips { 1928 cpu4_alert: trip-point0 { 1929 temperature = <80000>; 1930 hysteresis = <2000>; 1931 type = "passive"; 1932 }; 1933 cpu4_crit: crit { 1934 temperature = <100000>; 1935 hysteresis = <2000>; 1936 type = "critical"; 1937 }; 1938 }; 1939 cooling-maps { 1940 map0 { 1941 trip = <&cpu4_alert>; 1942 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1943 }; 1944 }; 1945 }; 1946 cpu5-thermal { 1947 polling-delay-passive = <250>; 1948 polling-delay = <1000>; 1949 thermal-sensors = <&tsens0 5>; 1950 trips { 1951 cpu5_alert: trip-point0 { 1952 temperature = <80000>; 1953 hysteresis = <2000>; 1954 type = "passive"; 1955 }; 1956 cpu5_crit: crit { 1957 temperature = <100000>; 1958 hysteresis = <2000>; 1959 type = "critical"; 1960 }; 1961 }; 1962 cooling-maps { 1963 map0 { 1964 trip = <&cpu5_alert>; 1965 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1966 }; 1967 }; 1968 }; 1969 cpu6-thermal { 1970 polling-delay-passive = <250>; 1971 polling-delay = <1000>; 1972 thermal-sensors = <&tsens0 6>; 1973 trips { 1974 cpu6_alert: trip-point0 { 1975 temperature = <80000>; 1976 hysteresis = <2000>; 1977 type = "passive"; 1978 }; 1979 cpu6_crit: crit { 1980 temperature = <100000>; 1981 hysteresis = <2000>; 1982 type = "critical"; 1983 }; 1984 }; 1985 cooling-maps { 1986 map0 { 1987 trip = <&cpu6_alert>; 1988 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1989 }; 1990 }; 1991 }; 1992 cpu7-thermal { 1993 polling-delay-passive = <250>; 1994 polling-delay = <1000>; 1995 thermal-sensors = <&tsens0 7>; 1996 trips { 1997 cpu7_alert: trip-point0 { 1998 temperature = <80000>; 1999 hysteresis = <2000>; 2000 type = "passive"; 2001 }; 2002 cpu7_crit: crit { 2003 temperature = <100000>; 2004 hysteresis = <2000>; 2005 type = "critical"; 2006 }; 2007 }; 2008 cooling-maps { 2009 map0 { 2010 trip = <&cpu7_alert>; 2011 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2012 }; 2013 }; 2014 }; 2015 }; 2016 2017 timer { 2018 compatible = "arm,armv8-timer"; 2019 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2020 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2021 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2022 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2023 }; 2024}; 2025