1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 model = "Qualcomm Technologies, Inc. IPQ8074"; 14 compatible = "qcom,ipq8074"; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 sleep_clk: sleep_clk { 19 compatible = "fixed-clock"; 20 clock-frequency = <32768>; 21 #clock-cells = <0>; 22 }; 23 24 xo: xo { 25 compatible = "fixed-clock"; 26 clock-frequency = <19200000>; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 next-level-cache = <&L2_0>; 40 enable-method = "psci"; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 enable-method = "psci"; 47 reg = <0x1>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x3>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 L2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 cache-unified; 71 }; 72 }; 73 74 pmu { 75 compatible = "arm,cortex-a53-pmu"; 76 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 77 }; 78 79 psci { 80 compatible = "arm,psci-1.0"; 81 method = "smc"; 82 }; 83 84 reserved-memory { 85 #address-cells = <2>; 86 #size-cells = <2>; 87 ranges; 88 89 bootloader@4a600000 { 90 reg = <0x0 0x4a600000 0x0 0x400000>; 91 no-map; 92 }; 93 94 sbl@4aa00000 { 95 reg = <0x0 0x4aa00000 0x0 0x100000>; 96 no-map; 97 }; 98 99 smem@4ab00000 { 100 compatible = "qcom,smem"; 101 reg = <0x0 0x4ab00000 0x0 0x100000>; 102 no-map; 103 104 hwlocks = <&tcsr_mutex 3>; 105 }; 106 107 memory@4ac00000 { 108 reg = <0x0 0x4ac00000 0x0 0x400000>; 109 no-map; 110 }; 111 }; 112 113 firmware { 114 scm { 115 compatible = "qcom,scm-ipq8074", "qcom,scm"; 116 qcom,dload-mode = <&tcsr 0x6100>; 117 }; 118 }; 119 120 soc: soc@0 { 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0 0 0 0xffffffff>; 124 compatible = "simple-bus"; 125 126 ssphy_1: phy@58000 { 127 compatible = "qcom,ipq8074-qmp-usb3-phy"; 128 reg = <0x00058000 0x1000>; 129 130 clocks = <&gcc GCC_USB1_AUX_CLK>, 131 <&xo>, 132 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 133 <&gcc GCC_USB1_PIPE_CLK>; 134 clock-names = "aux", 135 "ref", 136 "cfg_ahb", 137 "pipe"; 138 clock-output-names = "usb3phy_1_cc_pipe_clk"; 139 #clock-cells = <0>; 140 #phy-cells = <0>; 141 142 resets = <&gcc GCC_USB1_PHY_BCR>, 143 <&gcc GCC_USB3PHY_1_PHY_BCR>; 144 reset-names = "phy", 145 "phy_phy"; 146 147 status = "disabled"; 148 }; 149 150 qusb_phy_1: phy@59000 { 151 compatible = "qcom,ipq8074-qusb2-phy"; 152 reg = <0x00059000 0x180>; 153 #phy-cells = <0>; 154 155 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 156 <&xo>; 157 clock-names = "cfg_ahb", "ref"; 158 159 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 160 status = "disabled"; 161 }; 162 163 ssphy_0: phy@78000 { 164 compatible = "qcom,ipq8074-qmp-usb3-phy"; 165 reg = <0x00078000 0x1000>; 166 167 clocks = <&gcc GCC_USB0_AUX_CLK>, 168 <&xo>, 169 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 170 <&gcc GCC_USB0_PIPE_CLK>; 171 clock-names = "aux", 172 "ref", 173 "cfg_ahb", 174 "pipe"; 175 clock-output-names = "usb3phy_0_cc_pipe_clk"; 176 #clock-cells = <0>; 177 #phy-cells = <0>; 178 179 resets = <&gcc GCC_USB0_PHY_BCR>, 180 <&gcc GCC_USB3PHY_0_PHY_BCR>; 181 reset-names = "phy", 182 "phy_phy"; 183 184 status = "disabled"; 185 }; 186 187 qusb_phy_0: phy@79000 { 188 compatible = "qcom,ipq8074-qusb2-phy"; 189 reg = <0x00079000 0x180>; 190 #phy-cells = <0>; 191 192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 193 <&xo>; 194 clock-names = "cfg_ahb", "ref"; 195 196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 197 status = "disabled"; 198 }; 199 200 pcie_qmp0: phy@84000 { 201 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 202 reg = <0x00084000 0x1000>; 203 204 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 205 <&gcc GCC_PCIE0_AHB_CLK>, 206 <&gcc GCC_PCIE0_PIPE_CLK>; 207 clock-names = "aux", 208 "cfg_ahb", 209 "pipe"; 210 211 clock-output-names = "pcie20_phy0_pipe_clk"; 212 #clock-cells = <0>; 213 214 #phy-cells = <0>; 215 216 resets = <&gcc GCC_PCIE0_PHY_BCR>, 217 <&gcc GCC_PCIE0PHY_PHY_BCR>; 218 reset-names = "phy", 219 "common"; 220 status = "disabled"; 221 }; 222 223 pcie_qmp1: phy@8e000 { 224 compatible = "qcom,ipq8074-qmp-pcie-phy"; 225 reg = <0x0008e000 0x1000>; 226 227 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 228 <&gcc GCC_PCIE1_AHB_CLK>, 229 <&gcc GCC_PCIE1_PIPE_CLK>; 230 clock-names = "aux", 231 "cfg_ahb", 232 "pipe"; 233 234 clock-output-names = "pcie20_phy1_pipe_clk"; 235 #clock-cells = <0>; 236 237 #phy-cells = <0>; 238 239 resets = <&gcc GCC_PCIE1_PHY_BCR>, 240 <&gcc GCC_PCIE1PHY_PHY_BCR>; 241 reset-names = "phy", 242 "common"; 243 status = "disabled"; 244 }; 245 246 mdio: mdio@90000 { 247 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; 248 reg = <0x00090000 0x64>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 252 clocks = <&gcc GCC_MDIO_AHB_CLK>; 253 clock-names = "gcc_mdio_ahb_clk"; 254 255 status = "disabled"; 256 }; 257 258 qfprom: efuse@a4000 { 259 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; 260 reg = <0x000a4000 0x2000>; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 }; 264 265 prng: rng@e3000 { 266 compatible = "qcom,prng-ee"; 267 reg = <0x000e3000 0x1000>; 268 clocks = <&gcc GCC_PRNG_AHB_CLK>; 269 clock-names = "core"; 270 status = "disabled"; 271 }; 272 273 tsens: thermal-sensor@4a9000 { 274 compatible = "qcom,ipq8074-tsens"; 275 reg = <0x4a9000 0x1000>, /* TM */ 276 <0x4a8000 0x1000>; /* SROT */ 277 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 278 interrupt-names = "combined"; 279 #qcom,sensors = <16>; 280 #thermal-sensor-cells = <1>; 281 }; 282 283 cryptobam: dma-controller@704000 { 284 compatible = "qcom,bam-v1.7.0"; 285 reg = <0x00704000 0x20000>; 286 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 288 clock-names = "bam_clk"; 289 #dma-cells = <1>; 290 qcom,ee = <1>; 291 qcom,controlled-remotely; 292 status = "disabled"; 293 }; 294 295 crypto: crypto@73a000 { 296 compatible = "qcom,crypto-v5.1"; 297 reg = <0x0073a000 0x6000>; 298 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 299 <&gcc GCC_CRYPTO_AXI_CLK>, 300 <&gcc GCC_CRYPTO_CLK>; 301 clock-names = "iface", "bus", "core"; 302 dmas = <&cryptobam 2>, <&cryptobam 3>; 303 dma-names = "rx", "tx"; 304 status = "disabled"; 305 }; 306 307 tlmm: pinctrl@1000000 { 308 compatible = "qcom,ipq8074-pinctrl"; 309 reg = <0x01000000 0x300000>; 310 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 311 gpio-controller; 312 gpio-ranges = <&tlmm 0 0 70>; 313 #gpio-cells = <2>; 314 interrupt-controller; 315 #interrupt-cells = <2>; 316 317 serial_4_pins: serial4-state { 318 pins = "gpio23", "gpio24"; 319 function = "blsp4_uart1"; 320 drive-strength = <8>; 321 bias-disable; 322 }; 323 324 i2c_0_pins: i2c-0-state { 325 pins = "gpio42", "gpio43"; 326 function = "blsp1_i2c"; 327 drive-strength = <8>; 328 bias-disable; 329 }; 330 331 spi_0_pins: spi-0-state { 332 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 333 function = "blsp0_spi"; 334 drive-strength = <8>; 335 bias-disable; 336 }; 337 338 hsuart_pins: hsuart-state { 339 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 340 function = "blsp2_uart"; 341 drive-strength = <8>; 342 bias-disable; 343 }; 344 345 qpic_pins: qpic-state { 346 pins = "gpio1", "gpio3", "gpio4", 347 "gpio5", "gpio6", "gpio7", 348 "gpio8", "gpio10", "gpio11", 349 "gpio12", "gpio13", "gpio14", 350 "gpio15", "gpio16", "gpio17"; 351 function = "qpic"; 352 drive-strength = <8>; 353 bias-disable; 354 }; 355 }; 356 357 gcc: gcc@1800000 { 358 compatible = "qcom,gcc-ipq8074"; 359 reg = <0x01800000 0x80000>; 360 clocks = <&xo>, 361 <&sleep_clk>, 362 <&pcie_qmp0>, 363 <&pcie_qmp1>; 364 clock-names = "xo", 365 "sleep_clk", 366 "pcie0_pipe", 367 "pcie1_pipe"; 368 #clock-cells = <1>; 369 #power-domain-cells = <1>; 370 #reset-cells = <1>; 371 }; 372 373 tcsr_mutex: hwlock@1905000 { 374 compatible = "qcom,tcsr-mutex"; 375 reg = <0x01905000 0x20000>; 376 #hwlock-cells = <1>; 377 }; 378 379 tcsr: syscon@1937000 { 380 compatible = "qcom,tcsr-ipq8074", "syscon"; 381 reg = <0x01937000 0x21000>; 382 }; 383 384 spmi_bus: spmi@200f000 { 385 compatible = "qcom,spmi-pmic-arb"; 386 reg = <0x0200f000 0x001000>, 387 <0x02400000 0x800000>, 388 <0x02c00000 0x800000>, 389 <0x03800000 0x200000>, 390 <0x0200a000 0x000700>; 391 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 392 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 393 interrupt-names = "periph_irq"; 394 qcom,ee = <0>; 395 qcom,channel = <0>; 396 #address-cells = <2>; 397 #size-cells = <0>; 398 interrupt-controller; 399 #interrupt-cells = <4>; 400 }; 401 402 sdhc_1: mmc@7824900 { 403 compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4"; 404 reg = <0x7824900 0x500>, <0x7824000 0x800>; 405 reg-names = "hc", "core"; 406 407 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 409 interrupt-names = "hc_irq", "pwr_irq"; 410 411 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 412 <&gcc GCC_SDCC1_APPS_CLK>, 413 <&xo>; 414 clock-names = "iface", "core", "xo"; 415 resets = <&gcc GCC_SDCC1_BCR>; 416 max-frequency = <384000000>; 417 mmc-ddr-1_8v; 418 mmc-hs200-1_8v; 419 mmc-hs400-1_8v; 420 bus-width = <8>; 421 422 status = "disabled"; 423 }; 424 425 blsp_dma: dma-controller@7884000 { 426 compatible = "qcom,bam-v1.7.0"; 427 reg = <0x07884000 0x2b000>; 428 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 430 clock-names = "bam_clk"; 431 #dma-cells = <1>; 432 qcom,ee = <0>; 433 }; 434 435 blsp1_uart1: serial@78af000 { 436 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 437 reg = <0x078af000 0x200>; 438 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 440 <&gcc GCC_BLSP1_AHB_CLK>; 441 clock-names = "core", "iface"; 442 status = "disabled"; 443 }; 444 445 blsp1_uart3: serial@78b1000 { 446 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 447 reg = <0x078b1000 0x200>; 448 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 450 <&gcc GCC_BLSP1_AHB_CLK>; 451 clock-names = "core", "iface"; 452 dmas = <&blsp_dma 4>, 453 <&blsp_dma 5>; 454 dma-names = "tx", "rx"; 455 pinctrl-0 = <&hsuart_pins>; 456 pinctrl-names = "default"; 457 status = "disabled"; 458 }; 459 460 blsp1_uart5: serial@78b3000 { 461 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 462 reg = <0x078b3000 0x200>; 463 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 465 <&gcc GCC_BLSP1_AHB_CLK>; 466 clock-names = "core", "iface"; 467 pinctrl-0 = <&serial_4_pins>; 468 pinctrl-names = "default"; 469 status = "disabled"; 470 }; 471 472 blsp1_spi1: spi@78b5000 { 473 compatible = "qcom,spi-qup-v2.2.1"; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 reg = <0x078b5000 0x600>; 477 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 479 <&gcc GCC_BLSP1_AHB_CLK>; 480 clock-names = "core", "iface"; 481 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 482 dma-names = "tx", "rx"; 483 pinctrl-0 = <&spi_0_pins>; 484 pinctrl-names = "default"; 485 status = "disabled"; 486 }; 487 488 blsp1_i2c2: i2c@78b6000 { 489 compatible = "qcom,i2c-qup-v2.2.1"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <0x078b6000 0x600>; 493 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 495 <&gcc GCC_BLSP1_AHB_CLK>; 496 clock-names = "core", "iface"; 497 clock-frequency = <400000>; 498 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 499 dma-names = "tx", "rx"; 500 pinctrl-0 = <&i2c_0_pins>; 501 pinctrl-names = "default"; 502 status = "disabled"; 503 }; 504 505 blsp1_i2c3: i2c@78b7000 { 506 compatible = "qcom,i2c-qup-v2.2.1"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 reg = <0x078b7000 0x600>; 510 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 512 <&gcc GCC_BLSP1_AHB_CLK>; 513 clock-names = "core", "iface"; 514 clock-frequency = <100000>; 515 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 516 dma-names = "tx", "rx"; 517 status = "disabled"; 518 }; 519 520 blsp1_spi4: spi@78b8000 { 521 compatible = "qcom,spi-qup-v2.2.1"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 reg = <0x78b8000 0x600>; 525 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 527 <&gcc GCC_BLSP1_AHB_CLK>; 528 clock-names = "core", "iface"; 529 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 530 dma-names = "tx", "rx"; 531 status = "disabled"; 532 }; 533 534 blsp1_i2c5: i2c@78b9000 { 535 compatible = "qcom,i2c-qup-v2.2.1"; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 reg = <0x78b9000 0x600>; 539 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 541 <&gcc GCC_BLSP1_AHB_CLK>; 542 clock-names = "core", "iface"; 543 clock-frequency = <400000>; 544 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 545 dma-names = "tx", "rx"; 546 status = "disabled"; 547 }; 548 549 blsp1_spi5: spi@78b9000 { 550 compatible = "qcom,spi-qup-v2.2.1"; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 reg = <0x78b9000 0x600>; 554 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 556 <&gcc GCC_BLSP1_AHB_CLK>; 557 clock-names = "core", "iface"; 558 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 559 dma-names = "tx", "rx"; 560 status = "disabled"; 561 }; 562 563 blsp1_i2c6: i2c@78ba000 { 564 compatible = "qcom,i2c-qup-v2.2.1"; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 reg = <0x078ba000 0x600>; 568 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 570 <&gcc GCC_BLSP1_AHB_CLK>; 571 clock-names = "core", "iface"; 572 clock-frequency = <100000>; 573 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 574 dma-names = "tx", "rx"; 575 status = "disabled"; 576 }; 577 578 qpic_bam: dma-controller@7984000 { 579 compatible = "qcom,bam-v1.7.0"; 580 reg = <0x07984000 0x1a000>; 581 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&gcc GCC_QPIC_AHB_CLK>; 583 clock-names = "bam_clk"; 584 #dma-cells = <1>; 585 qcom,ee = <0>; 586 status = "disabled"; 587 }; 588 589 qpic_nand: nand-controller@79b0000 { 590 compatible = "qcom,ipq8074-nand"; 591 reg = <0x079b0000 0x10000>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 clocks = <&gcc GCC_QPIC_CLK>, 595 <&gcc GCC_QPIC_AHB_CLK>; 596 clock-names = "core", "aon"; 597 598 dmas = <&qpic_bam 0>, 599 <&qpic_bam 1>, 600 <&qpic_bam 2>; 601 dma-names = "tx", "rx", "cmd"; 602 pinctrl-0 = <&qpic_pins>; 603 pinctrl-names = "default"; 604 status = "disabled"; 605 }; 606 607 usb_0: usb@8af8800 { 608 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 609 reg = <0x08af8800 0x400>; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges; 613 614 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 615 <&gcc GCC_USB0_MASTER_CLK>, 616 <&gcc GCC_USB0_SLEEP_CLK>, 617 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 618 clock-names = "cfg_noc", 619 "core", 620 "sleep", 621 "mock_utmi"; 622 623 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 624 <&gcc GCC_USB0_MASTER_CLK>, 625 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 626 assigned-clock-rates = <133330000>, 627 <133330000>, 628 <19200000>; 629 630 power-domains = <&gcc USB0_GDSC>; 631 632 resets = <&gcc GCC_USB0_BCR>; 633 status = "disabled"; 634 635 dwc_0: usb@8a00000 { 636 compatible = "snps,dwc3"; 637 reg = <0x8a00000 0xcd00>; 638 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 639 phys = <&qusb_phy_0>, <&ssphy_0>; 640 phy-names = "usb2-phy", "usb3-phy"; 641 snps,is-utmi-l1-suspend; 642 snps,hird-threshold = /bits/ 8 <0x0>; 643 snps,dis_u2_susphy_quirk; 644 snps,dis_u3_susphy_quirk; 645 dr_mode = "host"; 646 }; 647 }; 648 649 usb_1: usb@8cf8800 { 650 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 651 reg = <0x08cf8800 0x400>; 652 #address-cells = <1>; 653 #size-cells = <1>; 654 ranges; 655 656 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 657 <&gcc GCC_USB1_MASTER_CLK>, 658 <&gcc GCC_USB1_SLEEP_CLK>, 659 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 660 clock-names = "cfg_noc", 661 "core", 662 "sleep", 663 "mock_utmi"; 664 665 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 666 <&gcc GCC_USB1_MASTER_CLK>, 667 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 668 assigned-clock-rates = <133330000>, 669 <133330000>, 670 <19200000>; 671 672 power-domains = <&gcc USB1_GDSC>; 673 674 resets = <&gcc GCC_USB1_BCR>; 675 status = "disabled"; 676 677 dwc_1: usb@8c00000 { 678 compatible = "snps,dwc3"; 679 reg = <0x8c00000 0xcd00>; 680 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 681 phys = <&qusb_phy_1>, <&ssphy_1>; 682 phy-names = "usb2-phy", "usb3-phy"; 683 snps,is-utmi-l1-suspend; 684 snps,hird-threshold = /bits/ 8 <0x0>; 685 snps,dis_u2_susphy_quirk; 686 snps,dis_u3_susphy_quirk; 687 dr_mode = "host"; 688 }; 689 }; 690 691 intc: interrupt-controller@b000000 { 692 compatible = "qcom,msm-qgic2"; 693 #address-cells = <1>; 694 #size-cells = <1>; 695 interrupt-controller; 696 #interrupt-cells = <3>; 697 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 698 ranges = <0 0xb00a000 0xffd>; 699 700 v2m@0 { 701 compatible = "arm,gic-v2m-frame"; 702 msi-controller; 703 reg = <0x0 0xffd>; 704 }; 705 }; 706 707 watchdog: watchdog@b017000 { 708 compatible = "qcom,kpss-wdt"; 709 reg = <0xb017000 0x1000>; 710 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 711 clocks = <&sleep_clk>; 712 timeout-sec = <30>; 713 }; 714 715 apcs_glb: mailbox@b111000 { 716 compatible = "qcom,ipq8074-apcs-apps-global", 717 "qcom,ipq6018-apcs-apps-global"; 718 reg = <0x0b111000 0x1000>; 719 clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; 720 clock-names = "pll", "xo", "gpll0"; 721 722 #clock-cells = <1>; 723 #mbox-cells = <1>; 724 }; 725 726 a53pll: clock@b116000 { 727 compatible = "qcom,ipq8074-a53pll"; 728 reg = <0x0b116000 0x40>; 729 #clock-cells = <0>; 730 clocks = <&xo>; 731 clock-names = "xo"; 732 }; 733 734 timer@b120000 { 735 #address-cells = <1>; 736 #size-cells = <1>; 737 ranges; 738 compatible = "arm,armv7-timer-mem"; 739 reg = <0x0b120000 0x1000>; 740 741 frame@b120000 { 742 frame-number = <0>; 743 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 745 reg = <0x0b121000 0x1000>, 746 <0x0b122000 0x1000>; 747 }; 748 749 frame@b123000 { 750 frame-number = <1>; 751 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 752 reg = <0x0b123000 0x1000>; 753 status = "disabled"; 754 }; 755 756 frame@b124000 { 757 frame-number = <2>; 758 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 759 reg = <0x0b124000 0x1000>; 760 status = "disabled"; 761 }; 762 763 frame@b125000 { 764 frame-number = <3>; 765 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 766 reg = <0x0b125000 0x1000>; 767 status = "disabled"; 768 }; 769 770 frame@b126000 { 771 frame-number = <4>; 772 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 773 reg = <0x0b126000 0x1000>; 774 status = "disabled"; 775 }; 776 777 frame@b127000 { 778 frame-number = <5>; 779 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 780 reg = <0x0b127000 0x1000>; 781 status = "disabled"; 782 }; 783 784 frame@b128000 { 785 frame-number = <6>; 786 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 787 reg = <0x0b128000 0x1000>; 788 status = "disabled"; 789 }; 790 }; 791 792 pcie1: pcie@10000000 { 793 compatible = "qcom,pcie-ipq8074"; 794 reg = <0x10000000 0xf1d>, 795 <0x10000f20 0xa8>, 796 <0x00088000 0x2000>, 797 <0x10100000 0x1000>; 798 reg-names = "dbi", "elbi", "parf", "config"; 799 device_type = "pci"; 800 linux,pci-domain = <1>; 801 bus-range = <0x00 0xff>; 802 num-lanes = <1>; 803 max-link-speed = <2>; 804 #address-cells = <3>; 805 #size-cells = <2>; 806 807 phys = <&pcie_qmp1>; 808 phy-names = "pciephy"; 809 810 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ 811 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ 812 813 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 814 interrupt-names = "msi"; 815 #interrupt-cells = <1>; 816 interrupt-map-mask = <0 0 0 0x7>; 817 interrupt-map = <0 0 0 1 &intc 0 0 142 818 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 819 <0 0 0 2 &intc 0 0 143 820 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 821 <0 0 0 3 &intc 0 0 144 822 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 823 <0 0 0 4 &intc 0 0 145 824 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 825 826 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 827 <&gcc GCC_PCIE1_AXI_M_CLK>, 828 <&gcc GCC_PCIE1_AXI_S_CLK>, 829 <&gcc GCC_PCIE1_AHB_CLK>, 830 <&gcc GCC_PCIE1_AUX_CLK>; 831 clock-names = "iface", 832 "axi_m", 833 "axi_s", 834 "ahb", 835 "aux"; 836 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 837 <&gcc GCC_PCIE1_SLEEP_ARES>, 838 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 839 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 840 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 841 <&gcc GCC_PCIE1_AHB_ARES>, 842 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 843 reset-names = "pipe", 844 "sleep", 845 "sticky", 846 "axi_m", 847 "axi_s", 848 "ahb", 849 "axi_m_sticky"; 850 status = "disabled"; 851 }; 852 853 pcie0: pcie@20000000 { 854 compatible = "qcom,pcie-ipq8074-gen3"; 855 reg = <0x20000000 0xf1d>, 856 <0x20000f20 0xa8>, 857 <0x20001000 0x1000>, 858 <0x00080000 0x4000>, 859 <0x20100000 0x1000>; 860 reg-names = "dbi", "elbi", "atu", "parf", "config"; 861 device_type = "pci"; 862 linux,pci-domain = <0>; 863 bus-range = <0x00 0xff>; 864 num-lanes = <1>; 865 max-link-speed = <3>; 866 #address-cells = <3>; 867 #size-cells = <2>; 868 869 phys = <&pcie_qmp0>; 870 phy-names = "pciephy"; 871 872 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ 873 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ 874 875 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 876 interrupt-names = "msi"; 877 #interrupt-cells = <1>; 878 interrupt-map-mask = <0 0 0 0x7>; 879 interrupt-map = <0 0 0 1 &intc 0 0 75 880 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 881 <0 0 0 2 &intc 0 0 78 882 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 883 <0 0 0 3 &intc 0 0 79 884 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 885 <0 0 0 4 &intc 0 0 83 886 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 887 888 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 889 <&gcc GCC_PCIE0_AXI_M_CLK>, 890 <&gcc GCC_PCIE0_AXI_S_CLK>, 891 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 892 <&gcc GCC_PCIE0_RCHNG_CLK>; 893 clock-names = "iface", 894 "axi_m", 895 "axi_s", 896 "axi_bridge", 897 "rchng"; 898 899 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 900 <&gcc GCC_PCIE0_SLEEP_ARES>, 901 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 902 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 903 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 904 <&gcc GCC_PCIE0_AHB_ARES>, 905 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 906 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 907 reset-names = "pipe", 908 "sleep", 909 "sticky", 910 "axi_m", 911 "axi_s", 912 "ahb", 913 "axi_m_sticky", 914 "axi_s_sticky"; 915 status = "disabled"; 916 }; 917 }; 918 919 timer { 920 compatible = "arm,armv8-timer"; 921 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 922 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 923 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 924 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 925 }; 926 927 thermal-zones { 928 nss-top-thermal { 929 polling-delay-passive = <250>; 930 polling-delay = <1000>; 931 932 thermal-sensors = <&tsens 4>; 933 934 trips { 935 nss-top-crit { 936 temperature = <110000>; 937 hysteresis = <1000>; 938 type = "critical"; 939 }; 940 }; 941 }; 942 943 nss0-thermal { 944 polling-delay-passive = <250>; 945 polling-delay = <1000>; 946 947 thermal-sensors = <&tsens 5>; 948 949 trips { 950 nss-0-crit { 951 temperature = <110000>; 952 hysteresis = <1000>; 953 type = "critical"; 954 }; 955 }; 956 }; 957 958 nss1-thermal { 959 polling-delay-passive = <250>; 960 polling-delay = <1000>; 961 962 thermal-sensors = <&tsens 6>; 963 964 trips { 965 nss-1-crit { 966 temperature = <110000>; 967 hysteresis = <1000>; 968 type = "critical"; 969 }; 970 }; 971 }; 972 973 wcss-phya0-thermal { 974 polling-delay-passive = <250>; 975 polling-delay = <1000>; 976 977 thermal-sensors = <&tsens 7>; 978 979 trips { 980 wcss-phya0-crit { 981 temperature = <110000>; 982 hysteresis = <1000>; 983 type = "critical"; 984 }; 985 }; 986 }; 987 988 wcss-phya1-thermal { 989 polling-delay-passive = <250>; 990 polling-delay = <1000>; 991 992 thermal-sensors = <&tsens 8>; 993 994 trips { 995 wcss-phya1-crit { 996 temperature = <110000>; 997 hysteresis = <1000>; 998 type = "critical"; 999 }; 1000 }; 1001 }; 1002 1003 cpu0_thermal: cpu0-thermal { 1004 polling-delay-passive = <250>; 1005 polling-delay = <1000>; 1006 1007 thermal-sensors = <&tsens 9>; 1008 1009 trips { 1010 cpu0-crit { 1011 temperature = <110000>; 1012 hysteresis = <1000>; 1013 type = "critical"; 1014 }; 1015 }; 1016 }; 1017 1018 cpu1_thermal: cpu1-thermal { 1019 polling-delay-passive = <250>; 1020 polling-delay = <1000>; 1021 1022 thermal-sensors = <&tsens 10>; 1023 1024 trips { 1025 cpu1-crit { 1026 temperature = <110000>; 1027 hysteresis = <1000>; 1028 type = "critical"; 1029 }; 1030 }; 1031 }; 1032 1033 cpu2_thermal: cpu2-thermal { 1034 polling-delay-passive = <250>; 1035 polling-delay = <1000>; 1036 1037 thermal-sensors = <&tsens 11>; 1038 1039 trips { 1040 cpu2-crit { 1041 temperature = <110000>; 1042 hysteresis = <1000>; 1043 type = "critical"; 1044 }; 1045 }; 1046 }; 1047 1048 cpu3_thermal: cpu3-thermal { 1049 polling-delay-passive = <250>; 1050 polling-delay = <1000>; 1051 1052 thermal-sensors = <&tsens 12>; 1053 1054 trips { 1055 cpu3-crit { 1056 temperature = <110000>; 1057 hysteresis = <1000>; 1058 type = "critical"; 1059 }; 1060 }; 1061 }; 1062 1063 cluster_thermal: cluster-thermal { 1064 polling-delay-passive = <250>; 1065 polling-delay = <1000>; 1066 1067 thermal-sensors = <&tsens 13>; 1068 1069 trips { 1070 cluster-crit { 1071 temperature = <110000>; 1072 hysteresis = <1000>; 1073 type = "critical"; 1074 }; 1075 }; 1076 }; 1077 1078 wcss-phyb0-thermal { 1079 polling-delay-passive = <250>; 1080 polling-delay = <1000>; 1081 1082 thermal-sensors = <&tsens 14>; 1083 1084 trips { 1085 wcss-phyb0-crit { 1086 temperature = <110000>; 1087 hysteresis = <1000>; 1088 type = "critical"; 1089 }; 1090 }; 1091 }; 1092 1093 wcss-phyb1-thermal { 1094 polling-delay-passive = <250>; 1095 polling-delay = <1000>; 1096 1097 thermal-sensors = <&tsens 15>; 1098 1099 trips { 1100 wcss-phyb1-crit { 1101 temperature = <110000>; 1102 hysteresis = <1000>; 1103 type = "critical"; 1104 }; 1105 }; 1106 }; 1107 }; 1108}; 1109