xref: /freebsd/sys/contrib/device-tree/src/arm64/qcom/ipq5332-rdp442.dts (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * IPQ5332 RDP442 board device tree source
4 *
5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 */
7
8/dts-v1/;
9
10#include "ipq5332.dtsi"
11
12/ {
13	model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3";
14	compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332";
15
16	aliases {
17		serial0 = &blsp1_uart0;
18	};
19
20	chosen {
21		stdout-path = "serial0";
22	};
23};
24
25&blsp1_uart0 {
26	pinctrl-0 = <&serial_0_pins>;
27	pinctrl-names = "default";
28	status = "okay";
29};
30
31&blsp1_i2c1 {
32	clock-frequency  = <400000>;
33	pinctrl-0 = <&i2c_1_pins>;
34	pinctrl-names = "default";
35	status = "okay";
36};
37
38&blsp1_spi0 {
39	pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
40	pinctrl-names = "default";
41	status = "okay";
42
43	flash@0 {
44		compatible = "micron,n25q128a11", "jedec,spi-nor";
45		reg = <0>;
46		#address-cells = <1>;
47		#size-cells = <1>;
48		spi-max-frequency = <50000000>;
49	};
50};
51
52&sdhc {
53	bus-width = <4>;
54	max-frequency = <192000000>;
55	mmc-ddr-1_8v;
56	mmc-hs200-1_8v;
57	non-removable;
58	pinctrl-0 = <&sdc_default_state>;
59	pinctrl-names = "default";
60	status = "okay";
61};
62
63&sleep_clk {
64	clock-frequency = <32000>;
65};
66
67&xo_board {
68	clock-frequency = <24000000>;
69};
70
71/* PINCTRL */
72
73&tlmm {
74	i2c_1_pins: i2c-1-state {
75		pins = "gpio29", "gpio30";
76		function = "blsp1_i2c0";
77		drive-strength = <8>;
78		bias-pull-up;
79	};
80
81	sdc_default_state: sdc-default-state {
82		clk-pins {
83			pins = "gpio13";
84			function = "sdc_clk";
85			drive-strength = <8>;
86			bias-disable;
87		};
88
89		cmd-pins {
90			pins = "gpio12";
91			function = "sdc_cmd";
92			drive-strength = <8>;
93			bias-pull-up;
94		};
95
96		data-pins {
97			pins = "gpio8", "gpio9", "gpio10", "gpio11";
98			function = "sdc_data";
99			drive-strength = <8>;
100			bias-pull-up;
101		};
102	};
103
104	spi_0_data_clk_pins: spi-0-data-clk-state {
105		pins = "gpio14", "gpio15", "gpio16";
106		function = "blsp0_spi";
107		drive-strength = <2>;
108		bias-pull-down;
109	};
110
111	spi_0_cs_pins: spi-0-cs-state {
112		pins = "gpio17";
113		function = "blsp0_spi";
114		drive-strength = <2>;
115		bias-pull-up;
116	};
117};
118