1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * IPQ5018 SoC device tree source 4 * 5 * Copyright (c) 2023 The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/qcom,gcc-ipq5018.h> 11#include <dt-bindings/reset/qcom,gcc-ipq5018.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 }; 23 24 xo_board_clk: xo-board-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 CPU0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 enable-method = "psci"; 39 next-level-cache = <&L2_0>; 40 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 41 operating-points-v2 = <&cpu_opp_table>; 42 }; 43 44 CPU1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x1>; 48 enable-method = "psci"; 49 next-level-cache = <&L2_0>; 50 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 51 operating-points-v2 = <&cpu_opp_table>; 52 }; 53 54 L2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 cache-size = <0x80000>; 58 cache-unified; 59 }; 60 }; 61 62 cpu_opp_table: opp-table-cpu { 63 compatible = "operating-points-v2"; 64 opp-shared; 65 66 opp-800000000 { 67 opp-hz = /bits/ 64 <800000000>; 68 opp-microvolt = <1100000>; 69 clock-latency-ns = <200000>; 70 }; 71 72 opp-1008000000 { 73 opp-hz = /bits/ 64 <1008000000>; 74 opp-microvolt = <1100000>; 75 clock-latency-ns = <200000>; 76 }; 77 }; 78 79 firmware { 80 scm { 81 compatible = "qcom,scm-ipq5018", "qcom,scm"; 82 qcom,sdi-enabled; 83 }; 84 }; 85 86 memory@40000000 { 87 device_type = "memory"; 88 /* We expect the bootloader to fill in the size */ 89 reg = <0x0 0x40000000 0x0 0x0>; 90 }; 91 92 pmu { 93 compatible = "arm,cortex-a53-pmu"; 94 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 95 }; 96 97 psci { 98 compatible = "arm,psci-1.0"; 99 method = "smc"; 100 }; 101 102 reserved-memory { 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 107 bootloader@4a800000 { 108 reg = <0x0 0x4a800000 0x0 0x200000>; 109 no-map; 110 }; 111 112 sbl@4aa00000 { 113 reg = <0x0 0x4aa00000 0x0 0x100000>; 114 no-map; 115 }; 116 117 smem@4ab00000 { 118 compatible = "qcom,smem"; 119 reg = <0x0 0x4ab00000 0x0 0x100000>; 120 no-map; 121 122 hwlocks = <&tcsr_mutex 3>; 123 }; 124 125 tz_region: tz@4ac00000 { 126 reg = <0x0 0x4ac00000 0x0 0x200000>; 127 no-map; 128 }; 129 }; 130 131 soc: soc@0 { 132 compatible = "simple-bus"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 ranges = <0 0 0 0xffffffff>; 136 137 usbphy0: phy@5b000 { 138 compatible = "qcom,ipq5018-usb-hsphy"; 139 reg = <0x0005b000 0x120>; 140 141 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; 142 143 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 144 145 #phy-cells = <0>; 146 147 status = "disabled"; 148 }; 149 150 tlmm: pinctrl@1000000 { 151 compatible = "qcom,ipq5018-tlmm"; 152 reg = <0x01000000 0x300000>; 153 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 154 gpio-controller; 155 #gpio-cells = <2>; 156 gpio-ranges = <&tlmm 0 0 47>; 157 interrupt-controller; 158 #interrupt-cells = <2>; 159 160 uart1_pins: uart1-state { 161 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 162 function = "blsp1_uart1"; 163 drive-strength = <8>; 164 bias-pull-down; 165 }; 166 }; 167 168 gcc: clock-controller@1800000 { 169 compatible = "qcom,gcc-ipq5018"; 170 reg = <0x01800000 0x80000>; 171 clocks = <&xo_board_clk>, 172 <&sleep_clk>, 173 <0>, 174 <0>, 175 <0>, 176 <0>, 177 <0>, 178 <0>, 179 <0>; 180 #clock-cells = <1>; 181 #reset-cells = <1>; 182 #power-domain-cells = <1>; 183 }; 184 185 tcsr_mutex: hwlock@1905000 { 186 compatible = "qcom,tcsr-mutex"; 187 reg = <0x01905000 0x20000>; 188 #hwlock-cells = <1>; 189 }; 190 191 sdhc_1: mmc@7804000 { 192 compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; 193 reg = <0x7804000 0x1000>; 194 reg-names = "hc"; 195 196 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-names = "hc_irq", "pwr_irq"; 199 200 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 201 <&gcc GCC_SDCC1_APPS_CLK>, 202 <&xo_board_clk>; 203 clock-names = "iface", "core", "xo"; 204 non-removable; 205 status = "disabled"; 206 }; 207 208 blsp_dma: dma-controller@7884000 { 209 compatible = "qcom,bam-v1.7.0"; 210 reg = <0x07884000 0x1d000>; 211 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 213 clock-names = "bam_clk"; 214 #dma-cells = <1>; 215 qcom,ee = <0>; 216 }; 217 218 blsp1_uart1: serial@78af000 { 219 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 220 reg = <0x078af000 0x200>; 221 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 223 <&gcc GCC_BLSP1_AHB_CLK>; 224 clock-names = "core", "iface"; 225 status = "disabled"; 226 }; 227 228 blsp1_spi1: spi@78b5000 { 229 compatible = "qcom,spi-qup-v2.2.1"; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 reg = <0x078b5000 0x600>; 233 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 235 <&gcc GCC_BLSP1_AHB_CLK>; 236 clock-names = "core", "iface"; 237 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 238 dma-names = "tx", "rx"; 239 status = "disabled"; 240 }; 241 242 usb: usb@8af8800 { 243 compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; 244 reg = <0x08af8800 0x400>; 245 246 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 247 interrupt-names = "hs_phy_irq"; 248 249 clocks = <&gcc GCC_USB0_MASTER_CLK>, 250 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 251 <&gcc GCC_USB0_SLEEP_CLK>, 252 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 253 clock-names = "core", 254 "iface", 255 "sleep", 256 "mock_utmi"; 257 258 resets = <&gcc GCC_USB0_BCR>; 259 260 qcom,select-utmi-as-pipe-clk; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges; 264 265 status = "disabled"; 266 267 usb_dwc: usb@8a00000 { 268 compatible = "snps,dwc3"; 269 reg = <0x08a00000 0xe000>; 270 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 271 clock-names = "ref"; 272 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 273 phy-names = "usb2-phy"; 274 phys = <&usbphy0>; 275 tx-fifo-resize; 276 snps,is-utmi-l1-suspend; 277 snps,hird-threshold = /bits/ 8 <0x0>; 278 snps,dis_u2_susphy_quirk; 279 snps,dis_u3_susphy_quirk; 280 }; 281 }; 282 283 intc: interrupt-controller@b000000 { 284 compatible = "qcom,msm-qgic2"; 285 reg = <0x0b000000 0x1000>, /* GICD */ 286 <0x0b002000 0x2000>, /* GICC */ 287 <0x0b001000 0x1000>, /* GICH */ 288 <0x0b004000 0x2000>; /* GICV */ 289 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 290 interrupt-controller; 291 #interrupt-cells = <3>; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 ranges = <0 0x0b00a000 0x1ffa>; 295 296 v2m0: v2m@0 { 297 compatible = "arm,gic-v2m-frame"; 298 reg = <0x00000000 0xff8>; 299 msi-controller; 300 }; 301 302 v2m1: v2m@1000 { 303 compatible = "arm,gic-v2m-frame"; 304 reg = <0x00001000 0xff8>; 305 msi-controller; 306 }; 307 }; 308 309 watchdog: watchdog@b017000 { 310 compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; 311 reg = <0x0b017000 0x40>; 312 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 313 clocks = <&sleep_clk>; 314 }; 315 316 apcs_glb: mailbox@b111000 { 317 compatible = "qcom,ipq5018-apcs-apps-global", 318 "qcom,ipq6018-apcs-apps-global"; 319 reg = <0x0b111000 0x1000>; 320 #clock-cells = <1>; 321 clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; 322 clock-names = "pll", "xo", "gpll0"; 323 #mbox-cells = <1>; 324 }; 325 326 a53pll: clock@b116000 { 327 compatible = "qcom,ipq5018-a53pll"; 328 reg = <0x0b116000 0x40>; 329 #clock-cells = <0>; 330 clocks = <&xo_board_clk>; 331 clock-names = "xo"; 332 }; 333 334 timer@b120000 { 335 compatible = "arm,armv7-timer-mem"; 336 reg = <0x0b120000 0x1000>; 337 #address-cells = <1>; 338 #size-cells = <1>; 339 ranges; 340 341 frame@b120000 { 342 reg = <0x0b121000 0x1000>, 343 <0x0b122000 0x1000>; 344 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 346 frame-number = <0>; 347 }; 348 349 frame@b123000 { 350 reg = <0xb123000 0x1000>; 351 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 352 frame-number = <1>; 353 status = "disabled"; 354 }; 355 356 frame@b124000 { 357 frame-number = <2>; 358 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 359 reg = <0x0b124000 0x1000>; 360 status = "disabled"; 361 }; 362 363 frame@b125000 { 364 reg = <0x0b125000 0x1000>; 365 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 366 frame-number = <3>; 367 status = "disabled"; 368 }; 369 370 frame@b126000 { 371 reg = <0x0b126000 0x1000>; 372 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 373 frame-number = <4>; 374 status = "disabled"; 375 }; 376 377 frame@b127000 { 378 reg = <0x0b127000 0x1000>; 379 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 380 frame-number = <5>; 381 status = "disabled"; 382 }; 383 384 frame@b128000 { 385 reg = <0x0b128000 0x1000>; 386 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 387 frame-number = <6>; 388 status = "disabled"; 389 }; 390 }; 391 }; 392 393 timer { 394 compatible = "arm,armv8-timer"; 395 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 396 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 397 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 398 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 399 }; 400}; 401