1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/power/tegra234-powergate.h> 9#include <dt-bindings/reset/tegra234-reset.h> 10 11/ { 12 compatible = "nvidia,tegra234"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 bus@0 { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 ranges = <0x0 0x0 0x0 0x40000000>; 23 24 aconnect@2900000 { 25 compatible = "nvidia,tegra234-aconnect", 26 "nvidia,tegra210-aconnect"; 27 clocks = <&bpmp TEGRA234_CLK_APE>, 28 <&bpmp TEGRA234_CLK_APB2APE>; 29 clock-names = "ape", "apb2ape"; 30 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x02900000 0x02900000 0x200000>; 34 status = "disabled"; 35 36 tegra_ahub: ahub@2900800 { 37 compatible = "nvidia,tegra234-ahub"; 38 reg = <0x02900800 0x800>; 39 clocks = <&bpmp TEGRA234_CLK_AHUB>; 40 clock-names = "ahub"; 41 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 42 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x02900800 0x02900800 0x11800>; 46 status = "disabled"; 47 48 tegra_i2s1: i2s@2901000 { 49 compatible = "nvidia,tegra234-i2s", 50 "nvidia,tegra210-i2s"; 51 reg = <0x2901000 0x100>; 52 clocks = <&bpmp TEGRA234_CLK_I2S1>, 53 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 54 clock-names = "i2s", "sync_input"; 55 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 56 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 57 assigned-clock-rates = <1536000>; 58 sound-name-prefix = "I2S1"; 59 status = "disabled"; 60 }; 61 62 tegra_i2s2: i2s@2901100 { 63 compatible = "nvidia,tegra234-i2s", 64 "nvidia,tegra210-i2s"; 65 reg = <0x2901100 0x100>; 66 clocks = <&bpmp TEGRA234_CLK_I2S2>, 67 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 68 clock-names = "i2s", "sync_input"; 69 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 70 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 71 assigned-clock-rates = <1536000>; 72 sound-name-prefix = "I2S2"; 73 status = "disabled"; 74 }; 75 76 tegra_i2s3: i2s@2901200 { 77 compatible = "nvidia,tegra234-i2s", 78 "nvidia,tegra210-i2s"; 79 reg = <0x2901200 0x100>; 80 clocks = <&bpmp TEGRA234_CLK_I2S3>, 81 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 82 clock-names = "i2s", "sync_input"; 83 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 84 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 85 assigned-clock-rates = <1536000>; 86 sound-name-prefix = "I2S3"; 87 status = "disabled"; 88 }; 89 90 tegra_i2s4: i2s@2901300 { 91 compatible = "nvidia,tegra234-i2s", 92 "nvidia,tegra210-i2s"; 93 reg = <0x2901300 0x100>; 94 clocks = <&bpmp TEGRA234_CLK_I2S4>, 95 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 96 clock-names = "i2s", "sync_input"; 97 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 98 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 99 assigned-clock-rates = <1536000>; 100 sound-name-prefix = "I2S4"; 101 status = "disabled"; 102 }; 103 104 tegra_i2s5: i2s@2901400 { 105 compatible = "nvidia,tegra234-i2s", 106 "nvidia,tegra210-i2s"; 107 reg = <0x2901400 0x100>; 108 clocks = <&bpmp TEGRA234_CLK_I2S5>, 109 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 110 clock-names = "i2s", "sync_input"; 111 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 112 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 113 assigned-clock-rates = <1536000>; 114 sound-name-prefix = "I2S5"; 115 status = "disabled"; 116 }; 117 118 tegra_i2s6: i2s@2901500 { 119 compatible = "nvidia,tegra234-i2s", 120 "nvidia,tegra210-i2s"; 121 reg = <0x2901500 0x100>; 122 clocks = <&bpmp TEGRA234_CLK_I2S6>, 123 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 124 clock-names = "i2s", "sync_input"; 125 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 126 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 127 assigned-clock-rates = <1536000>; 128 sound-name-prefix = "I2S6"; 129 status = "disabled"; 130 }; 131 132 tegra_sfc1: sfc@2902000 { 133 compatible = "nvidia,tegra234-sfc", 134 "nvidia,tegra210-sfc"; 135 reg = <0x2902000 0x200>; 136 sound-name-prefix = "SFC1"; 137 status = "disabled"; 138 }; 139 140 tegra_sfc2: sfc@2902200 { 141 compatible = "nvidia,tegra234-sfc", 142 "nvidia,tegra210-sfc"; 143 reg = <0x2902200 0x200>; 144 sound-name-prefix = "SFC2"; 145 status = "disabled"; 146 }; 147 148 tegra_sfc3: sfc@2902400 { 149 compatible = "nvidia,tegra234-sfc", 150 "nvidia,tegra210-sfc"; 151 reg = <0x2902400 0x200>; 152 sound-name-prefix = "SFC3"; 153 status = "disabled"; 154 }; 155 156 tegra_sfc4: sfc@2902600 { 157 compatible = "nvidia,tegra234-sfc", 158 "nvidia,tegra210-sfc"; 159 reg = <0x2902600 0x200>; 160 sound-name-prefix = "SFC4"; 161 status = "disabled"; 162 }; 163 164 tegra_amx1: amx@2903000 { 165 compatible = "nvidia,tegra234-amx", 166 "nvidia,tegra194-amx"; 167 reg = <0x2903000 0x100>; 168 sound-name-prefix = "AMX1"; 169 status = "disabled"; 170 }; 171 172 tegra_amx2: amx@2903100 { 173 compatible = "nvidia,tegra234-amx", 174 "nvidia,tegra194-amx"; 175 reg = <0x2903100 0x100>; 176 sound-name-prefix = "AMX2"; 177 status = "disabled"; 178 }; 179 180 tegra_amx3: amx@2903200 { 181 compatible = "nvidia,tegra234-amx", 182 "nvidia,tegra194-amx"; 183 reg = <0x2903200 0x100>; 184 sound-name-prefix = "AMX3"; 185 status = "disabled"; 186 }; 187 188 tegra_amx4: amx@2903300 { 189 compatible = "nvidia,tegra234-amx", 190 "nvidia,tegra194-amx"; 191 reg = <0x2903300 0x100>; 192 sound-name-prefix = "AMX4"; 193 status = "disabled"; 194 }; 195 196 tegra_adx1: adx@2903800 { 197 compatible = "nvidia,tegra234-adx", 198 "nvidia,tegra210-adx"; 199 reg = <0x2903800 0x100>; 200 sound-name-prefix = "ADX1"; 201 status = "disabled"; 202 }; 203 204 tegra_adx2: adx@2903900 { 205 compatible = "nvidia,tegra234-adx", 206 "nvidia,tegra210-adx"; 207 reg = <0x2903900 0x100>; 208 sound-name-prefix = "ADX2"; 209 status = "disabled"; 210 }; 211 212 tegra_adx3: adx@2903a00 { 213 compatible = "nvidia,tegra234-adx", 214 "nvidia,tegra210-adx"; 215 reg = <0x2903a00 0x100>; 216 sound-name-prefix = "ADX3"; 217 status = "disabled"; 218 }; 219 220 tegra_adx4: adx@2903b00 { 221 compatible = "nvidia,tegra234-adx", 222 "nvidia,tegra210-adx"; 223 reg = <0x2903b00 0x100>; 224 sound-name-prefix = "ADX4"; 225 status = "disabled"; 226 }; 227 228 229 tegra_dmic1: dmic@2904000 { 230 compatible = "nvidia,tegra234-dmic", 231 "nvidia,tegra210-dmic"; 232 reg = <0x2904000 0x100>; 233 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 234 clock-names = "dmic"; 235 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 236 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 237 assigned-clock-rates = <3072000>; 238 sound-name-prefix = "DMIC1"; 239 status = "disabled"; 240 }; 241 242 tegra_dmic2: dmic@2904100 { 243 compatible = "nvidia,tegra234-dmic", 244 "nvidia,tegra210-dmic"; 245 reg = <0x2904100 0x100>; 246 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 247 clock-names = "dmic"; 248 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 249 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 250 assigned-clock-rates = <3072000>; 251 sound-name-prefix = "DMIC2"; 252 status = "disabled"; 253 }; 254 255 tegra_dmic3: dmic@2904200 { 256 compatible = "nvidia,tegra234-dmic", 257 "nvidia,tegra210-dmic"; 258 reg = <0x2904200 0x100>; 259 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 260 clock-names = "dmic"; 261 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 262 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 263 assigned-clock-rates = <3072000>; 264 sound-name-prefix = "DMIC3"; 265 status = "disabled"; 266 }; 267 268 tegra_dmic4: dmic@2904300 { 269 compatible = "nvidia,tegra234-dmic", 270 "nvidia,tegra210-dmic"; 271 reg = <0x2904300 0x100>; 272 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 273 clock-names = "dmic"; 274 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 275 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 276 assigned-clock-rates = <3072000>; 277 sound-name-prefix = "DMIC4"; 278 status = "disabled"; 279 }; 280 281 tegra_dspk1: dspk@2905000 { 282 compatible = "nvidia,tegra234-dspk", 283 "nvidia,tegra186-dspk"; 284 reg = <0x2905000 0x100>; 285 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 286 clock-names = "dspk"; 287 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 288 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 289 assigned-clock-rates = <12288000>; 290 sound-name-prefix = "DSPK1"; 291 status = "disabled"; 292 }; 293 294 tegra_dspk2: dspk@2905100 { 295 compatible = "nvidia,tegra234-dspk", 296 "nvidia,tegra186-dspk"; 297 reg = <0x2905100 0x100>; 298 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 299 clock-names = "dspk"; 300 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 301 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 302 assigned-clock-rates = <12288000>; 303 sound-name-prefix = "DSPK2"; 304 status = "disabled"; 305 }; 306 307 tegra_mvc1: mvc@290a000 { 308 compatible = "nvidia,tegra234-mvc", 309 "nvidia,tegra210-mvc"; 310 reg = <0x290a000 0x200>; 311 sound-name-prefix = "MVC1"; 312 status = "disabled"; 313 }; 314 315 tegra_mvc2: mvc@290a200 { 316 compatible = "nvidia,tegra234-mvc", 317 "nvidia,tegra210-mvc"; 318 reg = <0x290a200 0x200>; 319 sound-name-prefix = "MVC2"; 320 status = "disabled"; 321 }; 322 323 tegra_amixer: amixer@290bb00 { 324 compatible = "nvidia,tegra234-amixer", 325 "nvidia,tegra210-amixer"; 326 reg = <0x290bb00 0x800>; 327 sound-name-prefix = "MIXER1"; 328 status = "disabled"; 329 }; 330 331 tegra_admaif: admaif@290f000 { 332 compatible = "nvidia,tegra234-admaif", 333 "nvidia,tegra186-admaif"; 334 reg = <0x0290f000 0x1000>; 335 dmas = <&adma 1>, <&adma 1>, 336 <&adma 2>, <&adma 2>, 337 <&adma 3>, <&adma 3>, 338 <&adma 4>, <&adma 4>, 339 <&adma 5>, <&adma 5>, 340 <&adma 6>, <&adma 6>, 341 <&adma 7>, <&adma 7>, 342 <&adma 8>, <&adma 8>, 343 <&adma 9>, <&adma 9>, 344 <&adma 10>, <&adma 10>, 345 <&adma 11>, <&adma 11>, 346 <&adma 12>, <&adma 12>, 347 <&adma 13>, <&adma 13>, 348 <&adma 14>, <&adma 14>, 349 <&adma 15>, <&adma 15>, 350 <&adma 16>, <&adma 16>, 351 <&adma 17>, <&adma 17>, 352 <&adma 18>, <&adma 18>, 353 <&adma 19>, <&adma 19>, 354 <&adma 20>, <&adma 20>; 355 dma-names = "rx1", "tx1", 356 "rx2", "tx2", 357 "rx3", "tx3", 358 "rx4", "tx4", 359 "rx5", "tx5", 360 "rx6", "tx6", 361 "rx7", "tx7", 362 "rx8", "tx8", 363 "rx9", "tx9", 364 "rx10", "tx10", 365 "rx11", "tx11", 366 "rx12", "tx12", 367 "rx13", "tx13", 368 "rx14", "tx14", 369 "rx15", "tx15", 370 "rx16", "tx16", 371 "rx17", "tx17", 372 "rx18", "tx18", 373 "rx19", "tx19", 374 "rx20", "tx20"; 375 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 376 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 377 interconnect-names = "dma-mem", "write"; 378 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 379 status = "disabled"; 380 }; 381 }; 382 383 adma: dma-controller@2930000 { 384 compatible = "nvidia,tegra234-adma", 385 "nvidia,tegra186-adma"; 386 reg = <0x02930000 0x20000>; 387 interrupt-parent = <&agic>; 388 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 420 #dma-cells = <1>; 421 clocks = <&bpmp TEGRA234_CLK_AHUB>; 422 clock-names = "d_audio"; 423 status = "disabled"; 424 }; 425 426 agic: interrupt-controller@2a40000 { 427 compatible = "nvidia,tegra234-agic", 428 "nvidia,tegra210-agic"; 429 #interrupt-cells = <3>; 430 interrupt-controller; 431 reg = <0x02a41000 0x1000>, 432 <0x02a42000 0x2000>; 433 interrupts = <GIC_SPI 145 434 (GIC_CPU_MASK_SIMPLE(4) | 435 IRQ_TYPE_LEVEL_HIGH)>; 436 clocks = <&bpmp TEGRA234_CLK_APE>; 437 clock-names = "clk"; 438 status = "disabled"; 439 }; 440 }; 441 442 misc@100000 { 443 compatible = "nvidia,tegra234-misc"; 444 reg = <0x00100000 0xf000>, 445 <0x0010f000 0x1000>; 446 status = "okay"; 447 }; 448 449 gpio: gpio@2200000 { 450 compatible = "nvidia,tegra234-gpio"; 451 reg-names = "security", "gpio"; 452 reg = <0x02200000 0x10000>, 453 <0x02210000 0x10000>; 454 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 502 #interrupt-cells = <2>; 503 interrupt-controller; 504 #gpio-cells = <2>; 505 gpio-controller; 506 }; 507 508 mc: memory-controller@2c00000 { 509 compatible = "nvidia,tegra234-mc"; 510 reg = <0x02c00000 0x100000>, 511 <0x02b80000 0x040000>, 512 <0x01700000 0x100000>; 513 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 514 #interconnect-cells = <1>; 515 status = "okay"; 516 517 #address-cells = <2>; 518 #size-cells = <2>; 519 520 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 521 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 522 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 523 524 /* 525 * Bit 39 of addresses passing through the memory 526 * controller selects the XBAR format used when memory 527 * is accessed. This is used to transparently access 528 * memory in the XBAR format used by the discrete GPU 529 * (bit 39 set) or Tegra (bit 39 clear). 530 * 531 * As a consequence, the operating system must ensure 532 * that bit 39 is never used implicitly, for example 533 * via an I/O virtual address mapping of an IOMMU. If 534 * devices require access to the XBAR switch, their 535 * drivers must set this bit explicitly. 536 * 537 * Limit the DMA range for memory clients to [38:0]. 538 */ 539 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 540 541 emc: external-memory-controller@2c60000 { 542 compatible = "nvidia,tegra234-emc"; 543 reg = <0x0 0x02c60000 0x0 0x90000>, 544 <0x0 0x01780000 0x0 0x80000>; 545 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&bpmp TEGRA234_CLK_EMC>; 547 clock-names = "emc"; 548 status = "okay"; 549 550 #interconnect-cells = <0>; 551 552 nvidia,bpmp = <&bpmp>; 553 }; 554 }; 555 556 uarta: serial@3100000 { 557 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 558 reg = <0x03100000 0x10000>; 559 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&bpmp TEGRA234_CLK_UARTA>; 561 clock-names = "serial"; 562 resets = <&bpmp TEGRA234_RESET_UARTA>; 563 reset-names = "serial"; 564 status = "disabled"; 565 }; 566 567 gen1_i2c: i2c@3160000 { 568 compatible = "nvidia,tegra194-i2c"; 569 reg = <0x3160000 0x100>; 570 status = "disabled"; 571 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 572 clock-frequency = <400000>; 573 clocks = <&bpmp TEGRA234_CLK_I2C1 574 &bpmp TEGRA234_CLK_PLLP_OUT0>; 575 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 576 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 577 clock-names = "div-clk", "parent"; 578 resets = <&bpmp TEGRA234_RESET_I2C1>; 579 reset-names = "i2c"; 580 }; 581 582 cam_i2c: i2c@3180000 { 583 compatible = "nvidia,tegra194-i2c"; 584 reg = <0x3180000 0x100>; 585 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 586 status = "disabled"; 587 clock-frequency = <400000>; 588 clocks = <&bpmp TEGRA234_CLK_I2C3 589 &bpmp TEGRA234_CLK_PLLP_OUT0>; 590 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 591 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 592 clock-names = "div-clk", "parent"; 593 resets = <&bpmp TEGRA234_RESET_I2C3>; 594 reset-names = "i2c"; 595 }; 596 597 dp_aux_ch1_i2c: i2c@3190000 { 598 compatible = "nvidia,tegra194-i2c"; 599 reg = <0x3190000 0x100>; 600 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 601 status = "disabled"; 602 clock-frequency = <100000>; 603 clocks = <&bpmp TEGRA234_CLK_I2C4 604 &bpmp TEGRA234_CLK_PLLP_OUT0>; 605 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 606 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 607 clock-names = "div-clk", "parent"; 608 resets = <&bpmp TEGRA234_RESET_I2C4>; 609 reset-names = "i2c"; 610 }; 611 612 dp_aux_ch0_i2c: i2c@31b0000 { 613 compatible = "nvidia,tegra194-i2c"; 614 reg = <0x31b0000 0x100>; 615 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 616 status = "disabled"; 617 clock-frequency = <100000>; 618 clocks = <&bpmp TEGRA234_CLK_I2C6 619 &bpmp TEGRA234_CLK_PLLP_OUT0>; 620 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 621 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 622 clock-names = "div-clk", "parent"; 623 resets = <&bpmp TEGRA234_RESET_I2C6>; 624 reset-names = "i2c"; 625 }; 626 627 dp_aux_ch2_i2c: i2c@31c0000 { 628 compatible = "nvidia,tegra194-i2c"; 629 reg = <0x31c0000 0x100>; 630 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 631 status = "disabled"; 632 clock-frequency = <100000>; 633 clocks = <&bpmp TEGRA234_CLK_I2C7 634 &bpmp TEGRA234_CLK_PLLP_OUT0>; 635 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 636 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 637 clock-names = "div-clk", "parent"; 638 resets = <&bpmp TEGRA234_RESET_I2C7>; 639 reset-names = "i2c"; 640 }; 641 642 dp_aux_ch3_i2c: i2c@31e0000 { 643 compatible = "nvidia,tegra194-i2c"; 644 reg = <0x31e0000 0x100>; 645 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 646 status = "disabled"; 647 clock-frequency = <100000>; 648 clocks = <&bpmp TEGRA234_CLK_I2C9 649 &bpmp TEGRA234_CLK_PLLP_OUT0>; 650 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 651 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 652 clock-names = "div-clk", "parent"; 653 resets = <&bpmp TEGRA234_RESET_I2C9>; 654 reset-names = "i2c"; 655 }; 656 657 pwm1: pwm@3280000 { 658 compatible = "nvidia,tegra194-pwm", 659 "nvidia,tegra186-pwm"; 660 reg = <0x3280000 0x10000>; 661 clocks = <&bpmp TEGRA234_CLK_PWM1>; 662 clock-names = "pwm"; 663 resets = <&bpmp TEGRA234_RESET_PWM1>; 664 reset-names = "pwm"; 665 status = "disabled"; 666 #pwm-cells = <2>; 667 }; 668 669 mmc@3460000 { 670 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 671 reg = <0x03460000 0x20000>; 672 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 674 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 675 clock-names = "sdhci", "tmclk"; 676 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 677 <&bpmp TEGRA234_CLK_PLLC4>; 678 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 679 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 680 reset-names = "sdhci"; 681 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 682 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 683 interconnect-names = "dma-mem", "write"; 684 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 685 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 686 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 687 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 688 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 689 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 690 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 691 nvidia,default-tap = <0x8>; 692 nvidia,default-trim = <0x14>; 693 nvidia,dqs-trim = <40>; 694 supports-cqe; 695 status = "disabled"; 696 }; 697 698 hda@3510000 { 699 compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 700 reg = <0x3510000 0x10000>; 701 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 703 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 704 clock-names = "hda", "hda2codec_2x"; 705 resets = <&bpmp TEGRA234_RESET_HDA>, 706 <&bpmp TEGRA234_RESET_HDACODEC>; 707 reset-names = "hda", "hda2codec_2x"; 708 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 709 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 710 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 711 interconnect-names = "dma-mem", "write"; 712 status = "disabled"; 713 }; 714 715 fuse@3810000 { 716 compatible = "nvidia,tegra234-efuse"; 717 reg = <0x03810000 0x10000>; 718 clocks = <&bpmp TEGRA234_CLK_FUSE>; 719 clock-names = "fuse"; 720 }; 721 722 hsp_top0: hsp@3c00000 { 723 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 724 reg = <0x03c00000 0xa0000>; 725 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 734 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 735 "shared3", "shared4", "shared5", "shared6", 736 "shared7"; 737 #mbox-cells = <2>; 738 }; 739 740 smmu_niso1: iommu@8000000 { 741 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 742 reg = <0x8000000 0x1000000>, 743 <0x7000000 0x1000000>; 744 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 874 stream-match-mask = <0x7f80>; 875 #global-interrupts = <2>; 876 #iommu-cells = <1>; 877 878 nvidia,memory-controller = <&mc>; 879 status = "okay"; 880 }; 881 882 hsp_aon: hsp@c150000 { 883 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 884 reg = <0x0c150000 0x90000>; 885 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 889 /* 890 * Shared interrupt 0 is routed only to AON/SPE, so 891 * we only have 4 shared interrupts for the CCPLEX. 892 */ 893 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 894 #mbox-cells = <2>; 895 }; 896 897 gen2_i2c: i2c@c240000 { 898 compatible = "nvidia,tegra194-i2c"; 899 reg = <0xc240000 0x100>; 900 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 901 status = "disabled"; 902 clock-frequency = <100000>; 903 clocks = <&bpmp TEGRA234_CLK_I2C2 904 &bpmp TEGRA234_CLK_PLLP_OUT0>; 905 clock-names = "div-clk", "parent"; 906 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 907 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 908 resets = <&bpmp TEGRA234_RESET_I2C2>; 909 reset-names = "i2c"; 910 }; 911 912 gen8_i2c: i2c@c250000 { 913 compatible = "nvidia,tegra194-i2c"; 914 reg = <0xc250000 0x100>; 915 nvidia,hw-instance-id = <0x7>; 916 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 917 status = "disabled"; 918 clock-frequency = <400000>; 919 clocks = <&bpmp TEGRA234_CLK_I2C8 920 &bpmp TEGRA234_CLK_PLLP_OUT0>; 921 clock-names = "div-clk", "parent"; 922 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 923 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 924 resets = <&bpmp TEGRA234_RESET_I2C8>; 925 reset-names = "i2c"; 926 }; 927 928 rtc@c2a0000 { 929 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 930 reg = <0x0c2a0000 0x10000>; 931 interrupt-parent = <&pmc>; 932 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 934 clock-names = "rtc"; 935 status = "disabled"; 936 }; 937 938 gpio_aon: gpio@c2f0000 { 939 compatible = "nvidia,tegra234-gpio-aon"; 940 reg-names = "security", "gpio"; 941 reg = <0x0c2f0000 0x1000>, 942 <0x0c2f1000 0x1000>; 943 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 947 #interrupt-cells = <2>; 948 interrupt-controller; 949 #gpio-cells = <2>; 950 gpio-controller; 951 }; 952 953 pmc: pmc@c360000 { 954 compatible = "nvidia,tegra234-pmc"; 955 reg = <0x0c360000 0x10000>, 956 <0x0c370000 0x10000>, 957 <0x0c380000 0x10000>, 958 <0x0c390000 0x10000>, 959 <0x0c3a0000 0x10000>; 960 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 961 962 #interrupt-cells = <2>; 963 interrupt-controller; 964 }; 965 966 gic: interrupt-controller@f400000 { 967 compatible = "arm,gic-v3"; 968 reg = <0x0f400000 0x010000>, /* GICD */ 969 <0x0f440000 0x200000>; /* GICR */ 970 interrupt-parent = <&gic>; 971 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 972 973 #redistributor-regions = <1>; 974 #interrupt-cells = <3>; 975 interrupt-controller; 976 }; 977 978 smmu_iso: iommu@10000000{ 979 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 980 reg = <0x10000000 0x1000000>; 981 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1110 stream-match-mask = <0x7f80>; 1111 #global-interrupts = <1>; 1112 #iommu-cells = <1>; 1113 1114 nvidia,memory-controller = <&mc>; 1115 status = "okay"; 1116 }; 1117 1118 smmu_niso0: iommu@12000000 { 1119 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1120 reg = <0x12000000 0x1000000>, 1121 <0x11000000 0x1000000>; 1122 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1252 stream-match-mask = <0x7f80>; 1253 #global-interrupts = <2>; 1254 #iommu-cells = <1>; 1255 1256 nvidia,memory-controller = <&mc>; 1257 status = "okay"; 1258 }; 1259 }; 1260 1261 sram@40000000 { 1262 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 1263 reg = <0x0 0x40000000 0x0 0x80000>; 1264 #address-cells = <1>; 1265 #size-cells = <1>; 1266 ranges = <0x0 0x0 0x40000000 0x80000>; 1267 1268 cpu_bpmp_tx: sram@70000 { 1269 reg = <0x70000 0x1000>; 1270 label = "cpu-bpmp-tx"; 1271 pool; 1272 }; 1273 1274 cpu_bpmp_rx: sram@71000 { 1275 reg = <0x71000 0x1000>; 1276 label = "cpu-bpmp-rx"; 1277 pool; 1278 }; 1279 }; 1280 1281 bpmp: bpmp { 1282 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 1283 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1284 TEGRA_HSP_DB_MASTER_BPMP>; 1285 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1286 #clock-cells = <1>; 1287 #reset-cells = <1>; 1288 #power-domain-cells = <1>; 1289 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 1290 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 1291 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 1292 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 1293 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1294 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 1295 1296 bpmp_i2c: i2c { 1297 compatible = "nvidia,tegra186-bpmp-i2c"; 1298 nvidia,bpmp-bus-id = <5>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 }; 1302 }; 1303 1304 cpus { 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 1308 cpu0_0: cpu@0 { 1309 compatible = "arm,cortex-a78"; 1310 device_type = "cpu"; 1311 reg = <0x00000>; 1312 1313 enable-method = "psci"; 1314 1315 i-cache-size = <65536>; 1316 i-cache-line-size = <64>; 1317 i-cache-sets = <256>; 1318 d-cache-size = <65536>; 1319 d-cache-line-size = <64>; 1320 d-cache-sets = <256>; 1321 next-level-cache = <&l2c0_0>; 1322 }; 1323 1324 cpu0_1: cpu@100 { 1325 compatible = "arm,cortex-a78"; 1326 device_type = "cpu"; 1327 reg = <0x00100>; 1328 1329 enable-method = "psci"; 1330 1331 i-cache-size = <65536>; 1332 i-cache-line-size = <64>; 1333 i-cache-sets = <256>; 1334 d-cache-size = <65536>; 1335 d-cache-line-size = <64>; 1336 d-cache-sets = <256>; 1337 next-level-cache = <&l2c0_1>; 1338 }; 1339 1340 cpu0_2: cpu@200 { 1341 compatible = "arm,cortex-a78"; 1342 device_type = "cpu"; 1343 reg = <0x00200>; 1344 1345 enable-method = "psci"; 1346 1347 i-cache-size = <65536>; 1348 i-cache-line-size = <64>; 1349 i-cache-sets = <256>; 1350 d-cache-size = <65536>; 1351 d-cache-line-size = <64>; 1352 d-cache-sets = <256>; 1353 next-level-cache = <&l2c0_2>; 1354 }; 1355 1356 cpu0_3: cpu@300 { 1357 compatible = "arm,cortex-a78"; 1358 device_type = "cpu"; 1359 reg = <0x00300>; 1360 1361 enable-method = "psci"; 1362 1363 i-cache-size = <65536>; 1364 i-cache-line-size = <64>; 1365 i-cache-sets = <256>; 1366 d-cache-size = <65536>; 1367 d-cache-line-size = <64>; 1368 d-cache-sets = <256>; 1369 next-level-cache = <&l2c0_3>; 1370 }; 1371 1372 cpu1_0: cpu@10000 { 1373 compatible = "arm,cortex-a78"; 1374 device_type = "cpu"; 1375 reg = <0x10000>; 1376 1377 enable-method = "psci"; 1378 1379 i-cache-size = <65536>; 1380 i-cache-line-size = <64>; 1381 i-cache-sets = <256>; 1382 d-cache-size = <65536>; 1383 d-cache-line-size = <64>; 1384 d-cache-sets = <256>; 1385 next-level-cache = <&l2c1_0>; 1386 }; 1387 1388 cpu1_1: cpu@10100 { 1389 compatible = "arm,cortex-a78"; 1390 device_type = "cpu"; 1391 reg = <0x10100>; 1392 1393 enable-method = "psci"; 1394 1395 i-cache-size = <65536>; 1396 i-cache-line-size = <64>; 1397 i-cache-sets = <256>; 1398 d-cache-size = <65536>; 1399 d-cache-line-size = <64>; 1400 d-cache-sets = <256>; 1401 next-level-cache = <&l2c1_1>; 1402 }; 1403 1404 cpu1_2: cpu@10200 { 1405 compatible = "arm,cortex-a78"; 1406 device_type = "cpu"; 1407 reg = <0x10200>; 1408 1409 enable-method = "psci"; 1410 1411 i-cache-size = <65536>; 1412 i-cache-line-size = <64>; 1413 i-cache-sets = <256>; 1414 d-cache-size = <65536>; 1415 d-cache-line-size = <64>; 1416 d-cache-sets = <256>; 1417 next-level-cache = <&l2c1_2>; 1418 }; 1419 1420 cpu1_3: cpu@10300 { 1421 compatible = "arm,cortex-a78"; 1422 device_type = "cpu"; 1423 reg = <0x10300>; 1424 1425 enable-method = "psci"; 1426 1427 i-cache-size = <65536>; 1428 i-cache-line-size = <64>; 1429 i-cache-sets = <256>; 1430 d-cache-size = <65536>; 1431 d-cache-line-size = <64>; 1432 d-cache-sets = <256>; 1433 next-level-cache = <&l2c1_3>; 1434 }; 1435 1436 cpu2_0: cpu@20000 { 1437 compatible = "arm,cortex-a78"; 1438 device_type = "cpu"; 1439 reg = <0x20000>; 1440 1441 enable-method = "psci"; 1442 1443 i-cache-size = <65536>; 1444 i-cache-line-size = <64>; 1445 i-cache-sets = <256>; 1446 d-cache-size = <65536>; 1447 d-cache-line-size = <64>; 1448 d-cache-sets = <256>; 1449 next-level-cache = <&l2c2_0>; 1450 }; 1451 1452 cpu2_1: cpu@20100 { 1453 compatible = "arm,cortex-a78"; 1454 device_type = "cpu"; 1455 reg = <0x20100>; 1456 1457 enable-method = "psci"; 1458 1459 i-cache-size = <65536>; 1460 i-cache-line-size = <64>; 1461 i-cache-sets = <256>; 1462 d-cache-size = <65536>; 1463 d-cache-line-size = <64>; 1464 d-cache-sets = <256>; 1465 next-level-cache = <&l2c2_1>; 1466 }; 1467 1468 cpu2_2: cpu@20200 { 1469 compatible = "arm,cortex-a78"; 1470 device_type = "cpu"; 1471 reg = <0x20200>; 1472 1473 enable-method = "psci"; 1474 1475 i-cache-size = <65536>; 1476 i-cache-line-size = <64>; 1477 i-cache-sets = <256>; 1478 d-cache-size = <65536>; 1479 d-cache-line-size = <64>; 1480 d-cache-sets = <256>; 1481 next-level-cache = <&l2c2_2>; 1482 }; 1483 1484 cpu2_3: cpu@20300 { 1485 compatible = "arm,cortex-a78"; 1486 device_type = "cpu"; 1487 reg = <0x20300>; 1488 1489 enable-method = "psci"; 1490 1491 i-cache-size = <65536>; 1492 i-cache-line-size = <64>; 1493 i-cache-sets = <256>; 1494 d-cache-size = <65536>; 1495 d-cache-line-size = <64>; 1496 d-cache-sets = <256>; 1497 next-level-cache = <&l2c2_3>; 1498 }; 1499 1500 cpu-map { 1501 cluster0 { 1502 core0 { 1503 cpu = <&cpu0_0>; 1504 }; 1505 1506 core1 { 1507 cpu = <&cpu0_1>; 1508 }; 1509 1510 core2 { 1511 cpu = <&cpu0_2>; 1512 }; 1513 1514 core3 { 1515 cpu = <&cpu0_3>; 1516 }; 1517 }; 1518 1519 cluster1 { 1520 core0 { 1521 cpu = <&cpu1_0>; 1522 }; 1523 1524 core1 { 1525 cpu = <&cpu1_1>; 1526 }; 1527 1528 core2 { 1529 cpu = <&cpu1_2>; 1530 }; 1531 1532 core3 { 1533 cpu = <&cpu1_3>; 1534 }; 1535 }; 1536 1537 cluster2 { 1538 core0 { 1539 cpu = <&cpu2_0>; 1540 }; 1541 1542 core1 { 1543 cpu = <&cpu2_1>; 1544 }; 1545 1546 core2 { 1547 cpu = <&cpu2_2>; 1548 }; 1549 1550 core3 { 1551 cpu = <&cpu2_3>; 1552 }; 1553 }; 1554 }; 1555 1556 l2c0_0: l2-cache00 { 1557 cache-size = <262144>; 1558 cache-line-size = <64>; 1559 cache-sets = <512>; 1560 cache-unified; 1561 next-level-cache = <&l3c0>; 1562 }; 1563 1564 l2c0_1: l2-cache01 { 1565 cache-size = <262144>; 1566 cache-line-size = <64>; 1567 cache-sets = <512>; 1568 cache-unified; 1569 next-level-cache = <&l3c0>; 1570 }; 1571 1572 l2c0_2: l2-cache02 { 1573 cache-size = <262144>; 1574 cache-line-size = <64>; 1575 cache-sets = <512>; 1576 cache-unified; 1577 next-level-cache = <&l3c0>; 1578 }; 1579 1580 l2c0_3: l2-cache03 { 1581 cache-size = <262144>; 1582 cache-line-size = <64>; 1583 cache-sets = <512>; 1584 cache-unified; 1585 next-level-cache = <&l3c0>; 1586 }; 1587 1588 l2c1_0: l2-cache10 { 1589 cache-size = <262144>; 1590 cache-line-size = <64>; 1591 cache-sets = <512>; 1592 cache-unified; 1593 next-level-cache = <&l3c1>; 1594 }; 1595 1596 l2c1_1: l2-cache11 { 1597 cache-size = <262144>; 1598 cache-line-size = <64>; 1599 cache-sets = <512>; 1600 cache-unified; 1601 next-level-cache = <&l3c1>; 1602 }; 1603 1604 l2c1_2: l2-cache12 { 1605 cache-size = <262144>; 1606 cache-line-size = <64>; 1607 cache-sets = <512>; 1608 cache-unified; 1609 next-level-cache = <&l3c1>; 1610 }; 1611 1612 l2c1_3: l2-cache13 { 1613 cache-size = <262144>; 1614 cache-line-size = <64>; 1615 cache-sets = <512>; 1616 cache-unified; 1617 next-level-cache = <&l3c1>; 1618 }; 1619 1620 l2c2_0: l2-cache20 { 1621 cache-size = <262144>; 1622 cache-line-size = <64>; 1623 cache-sets = <512>; 1624 cache-unified; 1625 next-level-cache = <&l3c2>; 1626 }; 1627 1628 l2c2_1: l2-cache21 { 1629 cache-size = <262144>; 1630 cache-line-size = <64>; 1631 cache-sets = <512>; 1632 cache-unified; 1633 next-level-cache = <&l3c2>; 1634 }; 1635 1636 l2c2_2: l2-cache22 { 1637 cache-size = <262144>; 1638 cache-line-size = <64>; 1639 cache-sets = <512>; 1640 cache-unified; 1641 next-level-cache = <&l3c2>; 1642 }; 1643 1644 l2c2_3: l2-cache23 { 1645 cache-size = <262144>; 1646 cache-line-size = <64>; 1647 cache-sets = <512>; 1648 cache-unified; 1649 next-level-cache = <&l3c2>; 1650 }; 1651 1652 l3c0: l3-cache0 { 1653 cache-size = <2097152>; 1654 cache-line-size = <64>; 1655 cache-sets = <2048>; 1656 }; 1657 1658 l3c1: l3-cache1 { 1659 cache-size = <2097152>; 1660 cache-line-size = <64>; 1661 cache-sets = <2048>; 1662 }; 1663 1664 l3c2: l3-cache2 { 1665 cache-size = <2097152>; 1666 cache-line-size = <64>; 1667 cache-sets = <2048>; 1668 }; 1669 }; 1670 1671 pmu { 1672 compatible = "arm,cortex-a78-pmu"; 1673 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1674 status = "okay"; 1675 }; 1676 1677 psci { 1678 compatible = "arm,psci-1.0"; 1679 status = "okay"; 1680 method = "smc"; 1681 }; 1682 1683 tcu: serial { 1684 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 1685 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1686 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1687 mbox-names = "rx", "tx"; 1688 status = "disabled"; 1689 }; 1690 1691 sound { 1692 status = "disabled"; 1693 1694 clocks = <&bpmp TEGRA234_CLK_PLLA>, 1695 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1696 clock-names = "pll_a", "plla_out0"; 1697 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 1698 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 1699 <&bpmp TEGRA234_CLK_AUD_MCLK>; 1700 assigned-clock-parents = <0>, 1701 <&bpmp TEGRA234_CLK_PLLA>, 1702 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1703 }; 1704 1705 timer { 1706 compatible = "arm,armv8-timer"; 1707 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1708 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1709 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1710 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1711 interrupt-parent = <&gic>; 1712 always-on; 1713 }; 1714}; 1715