1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 97 reset-names = "host1x", "mc"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 186 clock-names = "tsec"; 187 resets = <&tegra_car 83>; 188 reset-names = "tsec"; 189 status = "disabled"; 190 }; 191 192 dc@54200000 { 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 200 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 205 }; 206 207 dc@54240000 { 208 compatible = "nvidia,tegra210-dc"; 209 reg = <0x0 0x54240000 0x0 0x00040000>; 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212 clock-names = "dc"; 213 resets = <&tegra_car 26>; 214 reset-names = "dc"; 215 216 iommus = <&mc TEGRA_SWGROUP_DCB>; 217 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219 nvidia,head = <1>; 220 }; 221 222 dsia: dsi@54300000 { 223 compatible = "nvidia,tegra210-dsi"; 224 reg = <0x0 0x54300000 0x0 0x00040000>; 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226 <&tegra_car TEGRA210_CLK_DSIALP>, 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "lp", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_sor>; 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233 234 status = "disabled"; 235 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 240 vic@54340000 { 241 compatible = "nvidia,tegra210-vic"; 242 reg = <0x0 0x54340000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 245 clock-names = "vic"; 246 resets = <&tegra_car 178>; 247 reset-names = "vic"; 248 249 iommus = <&mc TEGRA_SWGROUP_VIC>; 250 power-domains = <&pd_vic>; 251 }; 252 253 nvjpg@54380000 { 254 compatible = "nvidia,tegra210-nvjpg"; 255 reg = <0x0 0x54380000 0x0 0x00040000>; 256 status = "disabled"; 257 }; 258 259 dsib: dsi@54400000 { 260 compatible = "nvidia,tegra210-dsi"; 261 reg = <0x0 0x54400000 0x0 0x00040000>; 262 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 263 <&tegra_car TEGRA210_CLK_DSIBLP>, 264 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 265 clock-names = "dsi", "lp", "parent"; 266 resets = <&tegra_car 82>; 267 reset-names = "dsi"; 268 power-domains = <&pd_sor>; 269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 270 271 status = "disabled"; 272 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 277 nvdec@54480000 { 278 compatible = "nvidia,tegra210-nvdec"; 279 reg = <0x0 0x54480000 0x0 0x00040000>; 280 status = "disabled"; 281 }; 282 283 nvenc@544c0000 { 284 compatible = "nvidia,tegra210-nvenc"; 285 reg = <0x0 0x544c0000 0x0 0x00040000>; 286 status = "disabled"; 287 }; 288 289 tsec@54500000 { 290 compatible = "nvidia,tegra210-tsec"; 291 reg = <0x0 0x54500000 0x0 0x00040000>; 292 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 294 clock-names = "tsec"; 295 resets = <&tegra_car 206>; 296 reset-names = "tsec"; 297 status = "disabled"; 298 }; 299 300 sor0: sor@54540000 { 301 compatible = "nvidia,tegra210-sor"; 302 reg = <0x0 0x54540000 0x0 0x00040000>; 303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 305 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 306 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 307 <&tegra_car TEGRA210_CLK_PLL_DP>, 308 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 309 clock-names = "sor", "out", "parent", "dp", "safe"; 310 resets = <&tegra_car 182>; 311 reset-names = "sor"; 312 pinctrl-0 = <&state_dpaux_aux>; 313 pinctrl-1 = <&state_dpaux_i2c>; 314 pinctrl-2 = <&state_dpaux_off>; 315 pinctrl-names = "aux", "i2c", "off"; 316 power-domains = <&pd_sor>; 317 status = "disabled"; 318 }; 319 320 sor1: sor@54580000 { 321 compatible = "nvidia,tegra210-sor1"; 322 reg = <0x0 0x54580000 0x0 0x00040000>; 323 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 325 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 326 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 327 <&tegra_car TEGRA210_CLK_PLL_DP>, 328 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 329 clock-names = "sor", "out", "parent", "dp", "safe"; 330 resets = <&tegra_car 183>; 331 reset-names = "sor"; 332 pinctrl-0 = <&state_dpaux1_aux>; 333 pinctrl-1 = <&state_dpaux1_i2c>; 334 pinctrl-2 = <&state_dpaux1_off>; 335 pinctrl-names = "aux", "i2c", "off"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 }; 339 340 dpaux: dpaux@545c0000 { 341 compatible = "nvidia,tegra210-dpaux"; 342 reg = <0x0 0x545c0000 0x0 0x00040000>; 343 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 345 <&tegra_car TEGRA210_CLK_PLL_DP>; 346 clock-names = "dpaux", "parent"; 347 resets = <&tegra_car 181>; 348 reset-names = "dpaux"; 349 power-domains = <&pd_sor>; 350 status = "disabled"; 351 352 state_dpaux_aux: pinmux-aux { 353 groups = "dpaux-io"; 354 function = "aux"; 355 }; 356 357 state_dpaux_i2c: pinmux-i2c { 358 groups = "dpaux-io"; 359 function = "i2c"; 360 }; 361 362 state_dpaux_off: pinmux-off { 363 groups = "dpaux-io"; 364 function = "off"; 365 }; 366 367 i2c-bus { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 }; 371 }; 372 373 isp@54600000 { 374 compatible = "nvidia,tegra210-isp"; 375 reg = <0x0 0x54600000 0x0 0x00040000>; 376 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 378 resets = <&tegra_car 23>; 379 reset-names = "isp"; 380 status = "disabled"; 381 }; 382 383 isp@54680000 { 384 compatible = "nvidia,tegra210-isp"; 385 reg = <0x0 0x54680000 0x0 0x00040000>; 386 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 388 resets = <&tegra_car 3>; 389 reset-names = "isp"; 390 status = "disabled"; 391 }; 392 393 i2c@546c0000 { 394 compatible = "nvidia,tegra210-i2c-vi"; 395 reg = <0x0 0x546c0000 0x0 0x00040000>; 396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 398 <&tegra_car TEGRA210_CLK_I2CSLOW>; 399 clock-names = "div-clk", "slow"; 400 resets = <&tegra_car 208>; 401 reset-names = "i2c"; 402 power-domains = <&pd_venc>; 403 status = "disabled"; 404 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 }; 409 410 gic: interrupt-controller@50041000 { 411 compatible = "arm,gic-400"; 412 #interrupt-cells = <3>; 413 interrupt-controller; 414 reg = <0x0 0x50041000 0x0 0x1000>, 415 <0x0 0x50042000 0x0 0x2000>, 416 <0x0 0x50044000 0x0 0x2000>, 417 <0x0 0x50046000 0x0 0x2000>; 418 interrupts = <GIC_PPI 9 419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 420 interrupt-parent = <&gic>; 421 }; 422 423 gpu@57000000 { 424 compatible = "nvidia,gm20b"; 425 reg = <0x0 0x57000000 0x0 0x01000000>, 426 <0x0 0x58000000 0x0 0x01000000>; 427 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "stall", "nonstall"; 430 clocks = <&tegra_car TEGRA210_CLK_GPU>, 431 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 432 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 433 clock-names = "gpu", "pwr", "ref"; 434 resets = <&tegra_car 184>; 435 reset-names = "gpu"; 436 437 iommus = <&mc TEGRA_SWGROUP_GPU>; 438 439 status = "disabled"; 440 }; 441 442 lic: interrupt-controller@60004000 { 443 compatible = "nvidia,tegra210-ictlr"; 444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 449 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 450 interrupt-controller; 451 #interrupt-cells = <3>; 452 interrupt-parent = <&gic>; 453 }; 454 455 timer@60005000 { 456 compatible = "nvidia,tegra210-timer"; 457 reg = <0x0 0x60005000 0x0 0x400>; 458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 473 clock-names = "timer"; 474 }; 475 476 tegra_car: clock@60006000 { 477 compatible = "nvidia,tegra210-car"; 478 reg = <0x0 0x60006000 0x0 0x1000>; 479 #clock-cells = <1>; 480 #reset-cells = <1>; 481 }; 482 483 flow-controller@60007000 { 484 compatible = "nvidia,tegra210-flowctrl"; 485 reg = <0x0 0x60007000 0x0 0x1000>; 486 }; 487 488 gpio: gpio@6000d000 { 489 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 490 reg = <0x0 0x6000d000 0x0 0x1000>; 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 499 #gpio-cells = <2>; 500 gpio-controller; 501 #interrupt-cells = <2>; 502 interrupt-controller; 503 }; 504 505 apbdma: dma@60020000 { 506 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 507 reg = <0x0 0x60020000 0x0 0x1400>; 508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 541 clock-names = "dma"; 542 resets = <&tegra_car 34>; 543 reset-names = "dma"; 544 #dma-cells = <1>; 545 }; 546 547 apbmisc@70000800 { 548 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 551 }; 552 553 pinmux: pinmux@700008d4 { 554 compatible = "nvidia,tegra210-pinmux"; 555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 557 558 sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { 559 sdmmc1 { 560 nvidia,pins = "drive_sdmmc1"; 561 nvidia,pull-down-strength = <0x4>; 562 nvidia,pull-up-strength = <0x3>; 563 }; 564 }; 565 566 sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { 567 sdmmc1 { 568 nvidia,pins = "drive_sdmmc1"; 569 nvidia,pull-down-strength = <0x8>; 570 nvidia,pull-up-strength = <0x8>; 571 }; 572 }; 573 574 sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { 575 sdmmc2 { 576 nvidia,pins = "drive_sdmmc2"; 577 nvidia,pull-down-strength = <0x10>; 578 nvidia,pull-up-strength = <0x10>; 579 }; 580 }; 581 582 sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { 583 sdmmc3 { 584 nvidia,pins = "drive_sdmmc3"; 585 nvidia,pull-down-strength = <0x4>; 586 nvidia,pull-up-strength = <0x3>; 587 }; 588 }; 589 590 sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { 591 sdmmc3 { 592 nvidia,pins = "drive_sdmmc3"; 593 nvidia,pull-down-strength = <0x8>; 594 nvidia,pull-up-strength = <0x8>; 595 }; 596 }; 597 598 sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { 599 sdmmc4 { 600 nvidia,pins = "drive_sdmmc4"; 601 nvidia,pull-down-strength = <0x10>; 602 nvidia,pull-up-strength = <0x10>; 603 }; 604 }; 605 }; 606 607 /* 608 * There are two serial driver i.e. 8250 based simple serial 609 * driver and APB DMA based serial driver for higher baudrate 610 * and performance. To enable the 8250 based driver, the compatible 611 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 612 * the APB DMA based serial driver, the compatible is 613 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 614 */ 615 uarta: serial@70006000 { 616 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 617 reg = <0x0 0x70006000 0x0 0x40>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 621 resets = <&tegra_car 6>; 622 dmas = <&apbdma 8>, <&apbdma 8>; 623 dma-names = "rx", "tx"; 624 status = "disabled"; 625 }; 626 627 uartb: serial@70006040 { 628 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 629 reg = <0x0 0x70006040 0x0 0x40>; 630 reg-shift = <2>; 631 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 633 resets = <&tegra_car 7>; 634 dmas = <&apbdma 9>, <&apbdma 9>; 635 dma-names = "rx", "tx"; 636 status = "disabled"; 637 }; 638 639 uartc: serial@70006200 { 640 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 641 reg = <0x0 0x70006200 0x0 0x40>; 642 reg-shift = <2>; 643 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 645 resets = <&tegra_car 55>; 646 dmas = <&apbdma 10>, <&apbdma 10>; 647 dma-names = "rx", "tx"; 648 status = "disabled"; 649 }; 650 651 uartd: serial@70006300 { 652 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 653 reg = <0x0 0x70006300 0x0 0x40>; 654 reg-shift = <2>; 655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 657 resets = <&tegra_car 65>; 658 dmas = <&apbdma 19>, <&apbdma 19>; 659 dma-names = "rx", "tx"; 660 status = "disabled"; 661 }; 662 663 pwm: pwm@7000a000 { 664 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 665 reg = <0x0 0x7000a000 0x0 0x100>; 666 #pwm-cells = <2>; 667 clocks = <&tegra_car TEGRA210_CLK_PWM>; 668 resets = <&tegra_car 17>; 669 reset-names = "pwm"; 670 status = "disabled"; 671 }; 672 673 i2c@7000c000 { 674 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 675 reg = <0x0 0x7000c000 0x0 0x100>; 676 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 680 clock-names = "div-clk"; 681 resets = <&tegra_car 12>; 682 reset-names = "i2c"; 683 dmas = <&apbdma 21>, <&apbdma 21>; 684 dma-names = "rx", "tx"; 685 status = "disabled"; 686 }; 687 688 i2c@7000c400 { 689 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 690 reg = <0x0 0x7000c400 0x0 0x100>; 691 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 695 clock-names = "div-clk"; 696 resets = <&tegra_car 54>; 697 reset-names = "i2c"; 698 dmas = <&apbdma 22>, <&apbdma 22>; 699 dma-names = "rx", "tx"; 700 status = "disabled"; 701 }; 702 703 i2c@7000c500 { 704 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 705 reg = <0x0 0x7000c500 0x0 0x100>; 706 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 710 clock-names = "div-clk"; 711 resets = <&tegra_car 67>; 712 reset-names = "i2c"; 713 dmas = <&apbdma 23>, <&apbdma 23>; 714 dma-names = "rx", "tx"; 715 status = "disabled"; 716 }; 717 718 i2c@7000c700 { 719 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 720 reg = <0x0 0x7000c700 0x0 0x100>; 721 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 725 clock-names = "div-clk"; 726 resets = <&tegra_car 103>; 727 reset-names = "i2c"; 728 dmas = <&apbdma 26>, <&apbdma 26>; 729 dma-names = "rx", "tx"; 730 pinctrl-0 = <&state_dpaux1_i2c>; 731 pinctrl-1 = <&state_dpaux1_off>; 732 pinctrl-names = "default", "idle"; 733 status = "disabled"; 734 }; 735 736 i2c@7000d000 { 737 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 738 reg = <0x0 0x7000d000 0x0 0x100>; 739 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 743 clock-names = "div-clk"; 744 resets = <&tegra_car 47>; 745 reset-names = "i2c"; 746 dmas = <&apbdma 24>, <&apbdma 24>; 747 dma-names = "rx", "tx"; 748 status = "disabled"; 749 }; 750 751 i2c@7000d100 { 752 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 753 reg = <0x0 0x7000d100 0x0 0x100>; 754 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 758 clock-names = "div-clk"; 759 resets = <&tegra_car 166>; 760 reset-names = "i2c"; 761 dmas = <&apbdma 30>, <&apbdma 30>; 762 dma-names = "rx", "tx"; 763 pinctrl-0 = <&state_dpaux_i2c>; 764 pinctrl-1 = <&state_dpaux_off>; 765 pinctrl-names = "default", "idle"; 766 status = "disabled"; 767 }; 768 769 spi@7000d400 { 770 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 771 reg = <0x0 0x7000d400 0x0 0x200>; 772 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 776 clock-names = "spi"; 777 resets = <&tegra_car 41>; 778 reset-names = "spi"; 779 dmas = <&apbdma 15>, <&apbdma 15>; 780 dma-names = "rx", "tx"; 781 status = "disabled"; 782 }; 783 784 spi@7000d600 { 785 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 786 reg = <0x0 0x7000d600 0x0 0x200>; 787 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 791 clock-names = "spi"; 792 resets = <&tegra_car 44>; 793 reset-names = "spi"; 794 dmas = <&apbdma 16>, <&apbdma 16>; 795 dma-names = "rx", "tx"; 796 status = "disabled"; 797 }; 798 799 spi@7000d800 { 800 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 801 reg = <0x0 0x7000d800 0x0 0x200>; 802 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 806 clock-names = "spi"; 807 resets = <&tegra_car 46>; 808 reset-names = "spi"; 809 dmas = <&apbdma 17>, <&apbdma 17>; 810 dma-names = "rx", "tx"; 811 status = "disabled"; 812 }; 813 814 spi@7000da00 { 815 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 816 reg = <0x0 0x7000da00 0x0 0x200>; 817 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 821 clock-names = "spi"; 822 resets = <&tegra_car 68>; 823 reset-names = "spi"; 824 dmas = <&apbdma 18>, <&apbdma 18>; 825 dma-names = "rx", "tx"; 826 status = "disabled"; 827 }; 828 829 rtc@7000e000 { 830 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 831 reg = <0x0 0x7000e000 0x0 0x100>; 832 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-parent = <&tegra_pmc>; 834 clocks = <&tegra_car TEGRA210_CLK_RTC>; 835 clock-names = "rtc"; 836 }; 837 838 tegra_pmc: pmc@7000e400 { 839 compatible = "nvidia,tegra210-pmc"; 840 reg = <0x0 0x7000e400 0x0 0x400>; 841 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 842 clock-names = "pclk", "clk32k_in"; 843 #clock-cells = <1>; 844 #interrupt-cells = <2>; 845 interrupt-controller; 846 847 pinmux { 848 pex_dpd_disable: pex-dpd-disable { 849 pins = "pex-bias", "pex-clk1", "pex-clk2"; 850 low-power-disable; 851 }; 852 853 pex_dpd_enable: pex-dpd-enable { 854 pins = "pex-bias", "pex-clk1", "pex-clk2"; 855 low-power-enable; 856 }; 857 858 sdmmc1_1v8: sdmmc1-1v8 { 859 pins = "sdmmc1"; 860 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 861 }; 862 863 sdmmc1_3v3: sdmmc1-3v3 { 864 pins = "sdmmc1"; 865 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 866 }; 867 868 sdmmc3_1v8: sdmmc3-1v8 { 869 pins = "sdmmc3"; 870 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 871 }; 872 873 sdmmc3_3v3: sdmmc3-3v3 { 874 pins = "sdmmc3"; 875 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 876 }; 877 }; 878 879 powergates { 880 pd_audio: aud { 881 clocks = <&tegra_car TEGRA210_CLK_APE>, 882 <&tegra_car TEGRA210_CLK_APB2APE>; 883 resets = <&tegra_car 198>; 884 #power-domain-cells = <0>; 885 }; 886 887 pd_sor: sor { 888 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 889 <&tegra_car TEGRA210_CLK_SOR1>, 890 <&tegra_car TEGRA210_CLK_CILAB>, 891 <&tegra_car TEGRA210_CLK_CILCD>, 892 <&tegra_car TEGRA210_CLK_CILE>, 893 <&tegra_car TEGRA210_CLK_DSIA>, 894 <&tegra_car TEGRA210_CLK_DSIB>, 895 <&tegra_car TEGRA210_CLK_DPAUX>, 896 <&tegra_car TEGRA210_CLK_DPAUX1>, 897 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 898 resets = <&tegra_car TEGRA210_CLK_SOR0>, 899 <&tegra_car TEGRA210_CLK_SOR1>, 900 <&tegra_car TEGRA210_CLK_DSIA>, 901 <&tegra_car TEGRA210_CLK_DSIB>, 902 <&tegra_car TEGRA210_CLK_DPAUX>, 903 <&tegra_car TEGRA210_CLK_DPAUX1>, 904 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 905 #power-domain-cells = <0>; 906 }; 907 908 pd_venc: venc { 909 clocks = <&tegra_car TEGRA210_CLK_VI>, 910 <&tegra_car TEGRA210_CLK_CSI>; 911 resets = <&mc TEGRA210_MC_RESET_VI>, 912 <&tegra_car 20>, 913 <&tegra_car 52>; 914 #power-domain-cells = <0>; 915 }; 916 917 pd_vic: vic { 918 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 919 clock-names = "vic"; 920 resets = <&tegra_car 178>; 921 reset-names = "vic"; 922 #power-domain-cells = <0>; 923 }; 924 925 pd_xusbss: xusba { 926 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 927 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 928 #power-domain-cells = <0>; 929 }; 930 931 pd_xusbdev: xusbb { 932 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 933 resets = <&tegra_car 95>; 934 #power-domain-cells = <0>; 935 }; 936 937 pd_xusbhost: xusbc { 938 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 939 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 940 #power-domain-cells = <0>; 941 }; 942 }; 943 }; 944 945 fuse@7000f800 { 946 compatible = "nvidia,tegra210-efuse"; 947 reg = <0x0 0x7000f800 0x0 0x400>; 948 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 949 clock-names = "fuse"; 950 resets = <&tegra_car 39>; 951 reset-names = "fuse"; 952 }; 953 954 mc: memory-controller@70019000 { 955 compatible = "nvidia,tegra210-mc"; 956 reg = <0x0 0x70019000 0x0 0x1000>; 957 clocks = <&tegra_car TEGRA210_CLK_MC>; 958 clock-names = "mc"; 959 960 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 961 962 #iommu-cells = <1>; 963 #reset-cells = <1>; 964 }; 965 966 emc: external-memory-controller@7001b000 { 967 compatible = "nvidia,tegra210-emc"; 968 reg = <0x0 0x7001b000 0x0 0x1000>, 969 <0x0 0x7001e000 0x0 0x1000>, 970 <0x0 0x7001f000 0x0 0x1000>; 971 clocks = <&tegra_car TEGRA210_CLK_EMC>; 972 clock-names = "emc"; 973 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 974 nvidia,memory-controller = <&mc>; 975 #cooling-cells = <2>; 976 }; 977 978 sata@70020000 { 979 compatible = "nvidia,tegra210-ahci"; 980 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 981 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 982 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 983 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&tegra_car TEGRA210_CLK_SATA>, 985 <&tegra_car TEGRA210_CLK_SATA_OOB>; 986 clock-names = "sata", "sata-oob"; 987 resets = <&tegra_car 124>, 988 <&tegra_car 129>, 989 <&tegra_car 123>; 990 reset-names = "sata", "sata-cold", "sata-oob"; 991 status = "disabled"; 992 }; 993 994 hda@70030000 { 995 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 996 reg = <0x0 0x70030000 0x0 0x10000>; 997 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&tegra_car TEGRA210_CLK_HDA>, 999 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1000 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1001 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1002 resets = <&tegra_car 125>, /* hda */ 1003 <&tegra_car 128>, /* hda2hdmi */ 1004 <&tegra_car 111>; /* hda2codec_2x */ 1005 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1006 power-domains = <&pd_sor>; 1007 status = "disabled"; 1008 }; 1009 1010 usb@70090000 { 1011 compatible = "nvidia,tegra210-xusb"; 1012 reg = <0x0 0x70090000 0x0 0x8000>, 1013 <0x0 0x70098000 0x0 0x1000>, 1014 <0x0 0x70099000 0x0 0x1000>; 1015 reg-names = "hcd", "fpci", "ipfs"; 1016 1017 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1019 1020 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1021 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1022 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1023 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1024 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1025 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1026 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1027 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1028 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1029 <&tegra_car TEGRA210_CLK_CLK_M>, 1030 <&tegra_car TEGRA210_CLK_PLL_E>; 1031 clock-names = "xusb_host", "xusb_host_src", 1032 "xusb_falcon_src", "xusb_ss", 1033 "xusb_ss_div2", "xusb_ss_src", 1034 "xusb_hs_src", "xusb_fs_src", 1035 "pll_u_480m", "clk_m", "pll_e"; 1036 resets = <&tegra_car 89>, <&tegra_car 156>, 1037 <&tegra_car 143>; 1038 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1039 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1040 power-domain-names = "xusb_host", "xusb_ss"; 1041 1042 nvidia,xusb-padctl = <&padctl>; 1043 1044 status = "disabled"; 1045 }; 1046 1047 padctl: padctl@7009f000 { 1048 compatible = "nvidia,tegra210-xusb-padctl"; 1049 reg = <0x0 0x7009f000 0x0 0x1000>; 1050 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1051 resets = <&tegra_car 142>; 1052 reset-names = "padctl"; 1053 nvidia,pmc = <&tegra_pmc>; 1054 1055 status = "disabled"; 1056 1057 pads { 1058 usb2 { 1059 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1060 clock-names = "trk"; 1061 status = "disabled"; 1062 1063 lanes { 1064 usb2-0 { 1065 status = "disabled"; 1066 #phy-cells = <0>; 1067 }; 1068 1069 usb2-1 { 1070 status = "disabled"; 1071 #phy-cells = <0>; 1072 }; 1073 1074 usb2-2 { 1075 status = "disabled"; 1076 #phy-cells = <0>; 1077 }; 1078 1079 usb2-3 { 1080 status = "disabled"; 1081 #phy-cells = <0>; 1082 }; 1083 }; 1084 }; 1085 1086 hsic { 1087 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1088 clock-names = "trk"; 1089 status = "disabled"; 1090 1091 lanes { 1092 hsic-0 { 1093 status = "disabled"; 1094 #phy-cells = <0>; 1095 }; 1096 1097 hsic-1 { 1098 status = "disabled"; 1099 #phy-cells = <0>; 1100 }; 1101 }; 1102 }; 1103 1104 pcie { 1105 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1106 clock-names = "pll"; 1107 resets = <&tegra_car 205>; 1108 reset-names = "phy"; 1109 status = "disabled"; 1110 1111 lanes { 1112 pcie-0 { 1113 status = "disabled"; 1114 #phy-cells = <0>; 1115 }; 1116 1117 pcie-1 { 1118 status = "disabled"; 1119 #phy-cells = <0>; 1120 }; 1121 1122 pcie-2 { 1123 status = "disabled"; 1124 #phy-cells = <0>; 1125 }; 1126 1127 pcie-3 { 1128 status = "disabled"; 1129 #phy-cells = <0>; 1130 }; 1131 1132 pcie-4 { 1133 status = "disabled"; 1134 #phy-cells = <0>; 1135 }; 1136 1137 pcie-5 { 1138 status = "disabled"; 1139 #phy-cells = <0>; 1140 }; 1141 1142 pcie-6 { 1143 status = "disabled"; 1144 #phy-cells = <0>; 1145 }; 1146 }; 1147 }; 1148 1149 sata { 1150 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1151 clock-names = "pll"; 1152 resets = <&tegra_car 204>; 1153 reset-names = "phy"; 1154 status = "disabled"; 1155 1156 lanes { 1157 sata-0 { 1158 status = "disabled"; 1159 #phy-cells = <0>; 1160 }; 1161 }; 1162 }; 1163 }; 1164 1165 ports { 1166 usb2-0 { 1167 status = "disabled"; 1168 }; 1169 1170 usb2-1 { 1171 status = "disabled"; 1172 }; 1173 1174 usb2-2 { 1175 status = "disabled"; 1176 }; 1177 1178 usb2-3 { 1179 status = "disabled"; 1180 }; 1181 1182 hsic-0 { 1183 status = "disabled"; 1184 }; 1185 1186 usb3-0 { 1187 status = "disabled"; 1188 }; 1189 1190 usb3-1 { 1191 status = "disabled"; 1192 }; 1193 1194 usb3-2 { 1195 status = "disabled"; 1196 }; 1197 1198 usb3-3 { 1199 status = "disabled"; 1200 }; 1201 }; 1202 }; 1203 1204 mmc@700b0000 { 1205 compatible = "nvidia,tegra210-sdhci"; 1206 reg = <0x0 0x700b0000 0x0 0x200>; 1207 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1208 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1209 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1210 clock-names = "sdhci", "tmclk"; 1211 resets = <&tegra_car 14>; 1212 reset-names = "sdhci"; 1213 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1214 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1215 pinctrl-0 = <&sdmmc1_3v3>; 1216 pinctrl-1 = <&sdmmc1_1v8>; 1217 pinctrl-2 = <&sdmmc1_3v3_drv>; 1218 pinctrl-3 = <&sdmmc1_1v8_drv>; 1219 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1220 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1221 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1222 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1223 nvidia,default-tap = <0x2>; 1224 nvidia,default-trim = <0x4>; 1225 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1226 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1227 <&tegra_car TEGRA210_CLK_PLL_C4>; 1228 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1229 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1230 status = "disabled"; 1231 }; 1232 1233 mmc@700b0200 { 1234 compatible = "nvidia,tegra210-sdhci"; 1235 reg = <0x0 0x700b0200 0x0 0x200>; 1236 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1237 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1238 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1239 clock-names = "sdhci", "tmclk"; 1240 resets = <&tegra_car 9>; 1241 reset-names = "sdhci"; 1242 pinctrl-names = "sdmmc-1v8-drv"; 1243 pinctrl-0 = <&sdmmc2_1v8_drv>; 1244 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1245 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1246 nvidia,default-tap = <0x8>; 1247 nvidia,default-trim = <0x0>; 1248 status = "disabled"; 1249 }; 1250 1251 mmc@700b0400 { 1252 compatible = "nvidia,tegra210-sdhci"; 1253 reg = <0x0 0x700b0400 0x0 0x200>; 1254 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1256 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1257 clock-names = "sdhci", "tmclk"; 1258 resets = <&tegra_car 69>; 1259 reset-names = "sdhci"; 1260 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1261 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1262 pinctrl-0 = <&sdmmc3_3v3>; 1263 pinctrl-1 = <&sdmmc3_1v8>; 1264 pinctrl-2 = <&sdmmc3_3v3_drv>; 1265 pinctrl-3 = <&sdmmc3_1v8_drv>; 1266 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1267 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1268 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1269 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1270 nvidia,default-tap = <0x3>; 1271 nvidia,default-trim = <0x3>; 1272 status = "disabled"; 1273 }; 1274 1275 mmc@700b0600 { 1276 compatible = "nvidia,tegra210-sdhci"; 1277 reg = <0x0 0x700b0600 0x0 0x200>; 1278 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1280 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1281 clock-names = "sdhci", "tmclk"; 1282 resets = <&tegra_car 15>; 1283 reset-names = "sdhci"; 1284 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1285 pinctrl-0 = <&sdmmc4_1v8_drv>; 1286 pinctrl-1 = <&sdmmc4_1v8_drv>; 1287 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1288 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1289 nvidia,default-tap = <0x8>; 1290 nvidia,default-trim = <0x0>; 1291 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1292 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1293 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1294 nvidia,dqs-trim = <40>; 1295 mmc-hs400-1_8v; 1296 status = "disabled"; 1297 }; 1298 1299 usb@700d0000 { 1300 compatible = "nvidia,tegra210-xudc"; 1301 reg = <0x0 0x700d0000 0x0 0x8000>, 1302 <0x0 0x700d8000 0x0 0x1000>, 1303 <0x0 0x700d9000 0x0 0x1000>; 1304 reg-names = "base", "fpci", "ipfs"; 1305 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1307 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1308 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1309 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1310 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1311 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1312 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1313 power-domain-names = "dev", "ss"; 1314 nvidia,xusb-padctl = <&padctl>; 1315 status = "disabled"; 1316 }; 1317 1318 soctherm: thermal-sensor@700e2000 { 1319 compatible = "nvidia,tegra210-soctherm"; 1320 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1321 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1322 reg-names = "soctherm-reg", "car-reg"; 1323 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1325 interrupt-names = "thermal", "edp"; 1326 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1327 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1328 clock-names = "tsensor", "soctherm"; 1329 resets = <&tegra_car 78>; 1330 reset-names = "soctherm"; 1331 #thermal-sensor-cells = <1>; 1332 1333 throttle-cfgs { 1334 throttle_heavy: heavy { 1335 nvidia,priority = <100>; 1336 nvidia,cpu-throt-percent = <85>; 1337 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1338 1339 #cooling-cells = <2>; 1340 }; 1341 }; 1342 }; 1343 1344 mipi: mipi@700e3000 { 1345 compatible = "nvidia,tegra210-mipi"; 1346 reg = <0x0 0x700e3000 0x0 0x100>; 1347 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1348 clock-names = "mipi-cal"; 1349 power-domains = <&pd_sor>; 1350 #nvidia,mipi-calibrate-cells = <1>; 1351 }; 1352 1353 dfll: clock@70110000 { 1354 compatible = "nvidia,tegra210-dfll"; 1355 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1356 <0 0x70110000 0 0x100>, /* I2C output control */ 1357 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1358 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1359 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1361 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1362 <&tegra_car TEGRA210_CLK_I2C5>; 1363 clock-names = "soc", "ref", "i2c"; 1364 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1365 <&tegra_car 155>; 1366 reset-names = "dvco", "dfll"; 1367 #clock-cells = <0>; 1368 clock-output-names = "dfllCPU_out"; 1369 status = "disabled"; 1370 }; 1371 1372 aconnect@702c0000 { 1373 compatible = "nvidia,tegra210-aconnect"; 1374 clocks = <&tegra_car TEGRA210_CLK_APE>, 1375 <&tegra_car TEGRA210_CLK_APB2APE>; 1376 clock-names = "ape", "apb2ape"; 1377 power-domains = <&pd_audio>; 1378 #address-cells = <1>; 1379 #size-cells = <1>; 1380 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1381 status = "disabled"; 1382 1383 tegra_ahub: ahub@702d0800 { 1384 compatible = "nvidia,tegra210-ahub"; 1385 reg = <0x702d0800 0x800>; 1386 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1387 clock-names = "ahub"; 1388 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1389 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1390 #address-cells = <1>; 1391 #size-cells = <1>; 1392 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1393 status = "disabled"; 1394 1395 tegra_admaif: admaif@702d0000 { 1396 compatible = "nvidia,tegra210-admaif"; 1397 reg = <0x702d0000 0x800>; 1398 dmas = <&adma 1>, <&adma 1>, 1399 <&adma 2>, <&adma 2>, 1400 <&adma 3>, <&adma 3>, 1401 <&adma 4>, <&adma 4>, 1402 <&adma 5>, <&adma 5>, 1403 <&adma 6>, <&adma 6>, 1404 <&adma 7>, <&adma 7>, 1405 <&adma 8>, <&adma 8>, 1406 <&adma 9>, <&adma 9>, 1407 <&adma 10>, <&adma 10>; 1408 dma-names = "rx1", "tx1", 1409 "rx2", "tx2", 1410 "rx3", "tx3", 1411 "rx4", "tx4", 1412 "rx5", "tx5", 1413 "rx6", "tx6", 1414 "rx7", "tx7", 1415 "rx8", "tx8", 1416 "rx9", "tx9", 1417 "rx10", "tx10"; 1418 status = "disabled"; 1419 1420 ports { 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 1424 admaif1_port: port@0 { 1425 reg = <0>; 1426 1427 admaif1_ep: endpoint { 1428 remote-endpoint = <&xbar_admaif1_ep>; 1429 }; 1430 }; 1431 1432 admaif2_port: port@1 { 1433 reg = <1>; 1434 1435 admaif2_ep: endpoint { 1436 remote-endpoint = <&xbar_admaif2_ep>; 1437 }; 1438 }; 1439 1440 admaif3_port: port@2 { 1441 reg = <2>; 1442 1443 admaif3_ep: endpoint { 1444 remote-endpoint = <&xbar_admaif3_ep>; 1445 }; 1446 }; 1447 1448 admaif4_port: port@3 { 1449 reg = <3>; 1450 1451 admaif4_ep: endpoint { 1452 remote-endpoint = <&xbar_admaif4_ep>; 1453 }; 1454 }; 1455 1456 admaif5_port: port@4 { 1457 reg = <4>; 1458 1459 admaif5_ep: endpoint { 1460 remote-endpoint = <&xbar_admaif5_ep>; 1461 }; 1462 }; 1463 1464 admaif6_port: port@5 { 1465 reg = <5>; 1466 1467 admaif6_ep: endpoint { 1468 remote-endpoint = <&xbar_admaif6_ep>; 1469 }; 1470 }; 1471 1472 admaif7_port: port@6 { 1473 reg = <6>; 1474 1475 admaif7_ep: endpoint { 1476 remote-endpoint = <&xbar_admaif7_ep>; 1477 }; 1478 }; 1479 1480 admaif8_port: port@7 { 1481 reg = <7>; 1482 1483 admaif8_ep: endpoint { 1484 remote-endpoint = <&xbar_admaif8_ep>; 1485 }; 1486 }; 1487 1488 admaif9_port: port@8 { 1489 reg = <8>; 1490 1491 admaif9_ep: endpoint { 1492 remote-endpoint = <&xbar_admaif9_ep>; 1493 }; 1494 }; 1495 1496 admaif10_port: port@9 { 1497 reg = <9>; 1498 1499 admaif10_ep: endpoint { 1500 remote-endpoint = <&xbar_admaif10_ep>; 1501 }; 1502 }; 1503 }; 1504 }; 1505 1506 tegra_i2s1: i2s@702d1000 { 1507 compatible = "nvidia,tegra210-i2s"; 1508 reg = <0x702d1000 0x100>; 1509 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1510 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1511 clock-names = "i2s", "sync_input"; 1512 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1513 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1514 assigned-clock-rates = <1536000>; 1515 sound-name-prefix = "I2S1"; 1516 status = "disabled"; 1517 }; 1518 1519 tegra_i2s2: i2s@702d1100 { 1520 compatible = "nvidia,tegra210-i2s"; 1521 reg = <0x702d1100 0x100>; 1522 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1523 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1524 clock-names = "i2s", "sync_input"; 1525 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1526 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1527 assigned-clock-rates = <1536000>; 1528 sound-name-prefix = "I2S2"; 1529 status = "disabled"; 1530 }; 1531 1532 tegra_i2s3: i2s@702d1200 { 1533 compatible = "nvidia,tegra210-i2s"; 1534 reg = <0x702d1200 0x100>; 1535 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1536 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1537 clock-names = "i2s", "sync_input"; 1538 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1539 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1540 assigned-clock-rates = <1536000>; 1541 sound-name-prefix = "I2S3"; 1542 status = "disabled"; 1543 }; 1544 1545 tegra_i2s4: i2s@702d1300 { 1546 compatible = "nvidia,tegra210-i2s"; 1547 reg = <0x702d1300 0x100>; 1548 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1549 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1550 clock-names = "i2s", "sync_input"; 1551 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1552 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1553 assigned-clock-rates = <1536000>; 1554 sound-name-prefix = "I2S4"; 1555 status = "disabled"; 1556 }; 1557 1558 tegra_i2s5: i2s@702d1400 { 1559 compatible = "nvidia,tegra210-i2s"; 1560 reg = <0x702d1400 0x100>; 1561 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1562 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1563 clock-names = "i2s", "sync_input"; 1564 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1565 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1566 assigned-clock-rates = <1536000>; 1567 sound-name-prefix = "I2S5"; 1568 status = "disabled"; 1569 }; 1570 1571 tegra_sfc1: sfc@702d2000 { 1572 compatible = "nvidia,tegra210-sfc"; 1573 reg = <0x702d2000 0x200>; 1574 sound-name-prefix = "SFC1"; 1575 status = "disabled"; 1576 }; 1577 1578 tegra_sfc2: sfc@702d2200 { 1579 compatible = "nvidia,tegra210-sfc"; 1580 reg = <0x702d2200 0x200>; 1581 sound-name-prefix = "SFC2"; 1582 status = "disabled"; 1583 }; 1584 1585 tegra_sfc3: sfc@702d2400 { 1586 compatible = "nvidia,tegra210-sfc"; 1587 reg = <0x702d2400 0x200>; 1588 sound-name-prefix = "SFC3"; 1589 status = "disabled"; 1590 }; 1591 1592 tegra_sfc4: sfc@702d2600 { 1593 compatible = "nvidia,tegra210-sfc"; 1594 reg = <0x702d2600 0x200>; 1595 sound-name-prefix = "SFC4"; 1596 status = "disabled"; 1597 }; 1598 1599 tegra_amx1: amx@702d3000 { 1600 compatible = "nvidia,tegra210-amx"; 1601 reg = <0x702d3000 0x100>; 1602 sound-name-prefix = "AMX1"; 1603 status = "disabled"; 1604 }; 1605 1606 tegra_amx2: amx@702d3100 { 1607 compatible = "nvidia,tegra210-amx"; 1608 reg = <0x702d3100 0x100>; 1609 sound-name-prefix = "AMX2"; 1610 status = "disabled"; 1611 }; 1612 1613 tegra_adx1: adx@702d3800 { 1614 compatible = "nvidia,tegra210-adx"; 1615 reg = <0x702d3800 0x100>; 1616 sound-name-prefix = "ADX1"; 1617 status = "disabled"; 1618 }; 1619 1620 tegra_adx2: adx@702d3900 { 1621 compatible = "nvidia,tegra210-adx"; 1622 reg = <0x702d3900 0x100>; 1623 sound-name-prefix = "ADX2"; 1624 status = "disabled"; 1625 }; 1626 1627 tegra_dmic1: dmic@702d4000 { 1628 compatible = "nvidia,tegra210-dmic"; 1629 reg = <0x702d4000 0x100>; 1630 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1631 clock-names = "dmic"; 1632 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1633 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1634 assigned-clock-rates = <3072000>; 1635 sound-name-prefix = "DMIC1"; 1636 status = "disabled"; 1637 }; 1638 1639 tegra_dmic2: dmic@702d4100 { 1640 compatible = "nvidia,tegra210-dmic"; 1641 reg = <0x702d4100 0x100>; 1642 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1643 clock-names = "dmic"; 1644 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1645 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1646 assigned-clock-rates = <3072000>; 1647 sound-name-prefix = "DMIC2"; 1648 status = "disabled"; 1649 }; 1650 1651 tegra_dmic3: dmic@702d4200 { 1652 compatible = "nvidia,tegra210-dmic"; 1653 reg = <0x702d4200 0x100>; 1654 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1655 clock-names = "dmic"; 1656 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1657 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1658 assigned-clock-rates = <3072000>; 1659 sound-name-prefix = "DMIC3"; 1660 status = "disabled"; 1661 }; 1662 1663 tegra_ope1: processing-engine@702d8000 { 1664 compatible = "nvidia,tegra210-ope"; 1665 reg = <0x702d8000 0x100>; 1666 #address-cells = <1>; 1667 #size-cells = <1>; 1668 ranges; 1669 sound-name-prefix = "OPE1"; 1670 status = "disabled"; 1671 1672 equalizer@702d8100 { 1673 compatible = "nvidia,tegra210-peq"; 1674 reg = <0x702d8100 0x100>; 1675 }; 1676 1677 dynamic-range-compressor@702d8200 { 1678 compatible = "nvidia,tegra210-mbdrc"; 1679 reg = <0x702d8200 0x200>; 1680 }; 1681 }; 1682 1683 tegra_ope2: processing-engine@702d8400 { 1684 compatible = "nvidia,tegra210-ope"; 1685 reg = <0x702d8400 0x100>; 1686 #address-cells = <1>; 1687 #size-cells = <1>; 1688 ranges; 1689 sound-name-prefix = "OPE2"; 1690 status = "disabled"; 1691 1692 equalizer@702d8500 { 1693 compatible = "nvidia,tegra210-peq"; 1694 reg = <0x702d8500 0x100>; 1695 }; 1696 1697 dynamic-range-compressor@702d8600 { 1698 compatible = "nvidia,tegra210-mbdrc"; 1699 reg = <0x702d8600 0x200>; 1700 }; 1701 }; 1702 1703 tegra_mvc1: mvc@702da000 { 1704 compatible = "nvidia,tegra210-mvc"; 1705 reg = <0x702da000 0x200>; 1706 sound-name-prefix = "MVC1"; 1707 status = "disabled"; 1708 }; 1709 1710 tegra_mvc2: mvc@702da200 { 1711 compatible = "nvidia,tegra210-mvc"; 1712 reg = <0x702da200 0x200>; 1713 sound-name-prefix = "MVC2"; 1714 status = "disabled"; 1715 }; 1716 1717 tegra_amixer: amixer@702dbb00 { 1718 compatible = "nvidia,tegra210-amixer"; 1719 reg = <0x702dbb00 0x800>; 1720 sound-name-prefix = "MIXER1"; 1721 status = "disabled"; 1722 }; 1723 1724 ports { 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 1728 port@0 { 1729 reg = <0x0>; 1730 1731 xbar_admaif1_ep: endpoint { 1732 remote-endpoint = <&admaif1_ep>; 1733 }; 1734 }; 1735 1736 port@1 { 1737 reg = <0x1>; 1738 1739 xbar_admaif2_ep: endpoint { 1740 remote-endpoint = <&admaif2_ep>; 1741 }; 1742 }; 1743 1744 port@2 { 1745 reg = <0x2>; 1746 1747 xbar_admaif3_ep: endpoint { 1748 remote-endpoint = <&admaif3_ep>; 1749 }; 1750 }; 1751 1752 port@3 { 1753 reg = <0x3>; 1754 1755 xbar_admaif4_ep: endpoint { 1756 remote-endpoint = <&admaif4_ep>; 1757 }; 1758 }; 1759 1760 port@4 { 1761 reg = <0x4>; 1762 xbar_admaif5_ep: endpoint { 1763 remote-endpoint = <&admaif5_ep>; 1764 }; 1765 }; 1766 port@5 { 1767 reg = <0x5>; 1768 1769 xbar_admaif6_ep: endpoint { 1770 remote-endpoint = <&admaif6_ep>; 1771 }; 1772 }; 1773 1774 port@6 { 1775 reg = <0x6>; 1776 1777 xbar_admaif7_ep: endpoint { 1778 remote-endpoint = <&admaif7_ep>; 1779 }; 1780 }; 1781 1782 port@7 { 1783 reg = <0x7>; 1784 1785 xbar_admaif8_ep: endpoint { 1786 remote-endpoint = <&admaif8_ep>; 1787 }; 1788 }; 1789 1790 port@8 { 1791 reg = <0x8>; 1792 1793 xbar_admaif9_ep: endpoint { 1794 remote-endpoint = <&admaif9_ep>; 1795 }; 1796 }; 1797 1798 port@9 { 1799 reg = <0x9>; 1800 1801 xbar_admaif10_ep: endpoint { 1802 remote-endpoint = <&admaif10_ep>; 1803 }; 1804 }; 1805 }; 1806 }; 1807 1808 adma: dma-controller@702e2000 { 1809 compatible = "nvidia,tegra210-adma"; 1810 reg = <0x702e2000 0x2000>; 1811 interrupt-parent = <&agic>; 1812 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1834 #dma-cells = <1>; 1835 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1836 clock-names = "d_audio"; 1837 status = "disabled"; 1838 }; 1839 1840 agic: interrupt-controller@702f9000 { 1841 compatible = "nvidia,tegra210-agic"; 1842 #interrupt-cells = <3>; 1843 interrupt-controller; 1844 reg = <0x702f9000 0x1000>, 1845 <0x702fa000 0x2000>; 1846 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1847 clocks = <&tegra_car TEGRA210_CLK_APE>; 1848 clock-names = "clk"; 1849 status = "disabled"; 1850 }; 1851 }; 1852 1853 spi@70410000 { 1854 compatible = "nvidia,tegra210-qspi"; 1855 reg = <0x0 0x70410000 0x0 0x1000>; 1856 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1860 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1861 clock-names = "qspi", "qspi_out"; 1862 resets = <&tegra_car 211>; 1863 dmas = <&apbdma 5>, <&apbdma 5>; 1864 dma-names = "rx", "tx"; 1865 status = "disabled"; 1866 }; 1867 1868 usb@7d000000 { 1869 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1870 reg = <0x0 0x7d000000 0x0 0x4000>; 1871 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1872 phy_type = "utmi"; 1873 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1874 clock-names = "usb"; 1875 resets = <&tegra_car 22>; 1876 reset-names = "usb"; 1877 nvidia,phy = <&phy1>; 1878 status = "disabled"; 1879 }; 1880 1881 phy1: usb-phy@7d000000 { 1882 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1883 reg = <0x0 0x7d000000 0x0 0x4000>, 1884 <0x0 0x7d000000 0x0 0x4000>; 1885 phy_type = "utmi"; 1886 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1887 <&tegra_car TEGRA210_CLK_PLL_U>, 1888 <&tegra_car TEGRA210_CLK_USBD>; 1889 clock-names = "reg", "pll_u", "utmi-pads"; 1890 resets = <&tegra_car 22>, <&tegra_car 22>; 1891 reset-names = "usb", "utmi-pads"; 1892 nvidia,hssync-start-delay = <0>; 1893 nvidia,idle-wait-delay = <17>; 1894 nvidia,elastic-limit = <16>; 1895 nvidia,term-range-adj = <6>; 1896 nvidia,xcvr-setup = <9>; 1897 nvidia,xcvr-lsfslew = <0>; 1898 nvidia,xcvr-lsrslew = <3>; 1899 nvidia,hssquelch-level = <2>; 1900 nvidia,hsdiscon-level = <5>; 1901 nvidia,xcvr-hsslew = <12>; 1902 nvidia,has-utmi-pad-registers; 1903 status = "disabled"; 1904 }; 1905 1906 usb@7d004000 { 1907 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1908 reg = <0x0 0x7d004000 0x0 0x4000>; 1909 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1910 phy_type = "utmi"; 1911 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1912 clock-names = "usb"; 1913 resets = <&tegra_car 58>; 1914 reset-names = "usb"; 1915 nvidia,phy = <&phy2>; 1916 status = "disabled"; 1917 }; 1918 1919 phy2: usb-phy@7d004000 { 1920 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1921 reg = <0x0 0x7d004000 0x0 0x4000>, 1922 <0x0 0x7d000000 0x0 0x4000>; 1923 phy_type = "utmi"; 1924 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1925 <&tegra_car TEGRA210_CLK_PLL_U>, 1926 <&tegra_car TEGRA210_CLK_USBD>; 1927 clock-names = "reg", "pll_u", "utmi-pads"; 1928 resets = <&tegra_car 58>, <&tegra_car 22>; 1929 reset-names = "usb", "utmi-pads"; 1930 nvidia,hssync-start-delay = <0>; 1931 nvidia,idle-wait-delay = <17>; 1932 nvidia,elastic-limit = <16>; 1933 nvidia,term-range-adj = <6>; 1934 nvidia,xcvr-setup = <9>; 1935 nvidia,xcvr-lsfslew = <0>; 1936 nvidia,xcvr-lsrslew = <3>; 1937 nvidia,hssquelch-level = <2>; 1938 nvidia,hsdiscon-level = <5>; 1939 nvidia,xcvr-hsslew = <12>; 1940 status = "disabled"; 1941 }; 1942 1943 cpus { 1944 #address-cells = <1>; 1945 #size-cells = <0>; 1946 1947 cpu@0 { 1948 device_type = "cpu"; 1949 compatible = "arm,cortex-a57"; 1950 reg = <0>; 1951 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1952 <&tegra_car TEGRA210_CLK_PLL_X>, 1953 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1954 <&dfll>; 1955 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1956 clock-latency = <300000>; 1957 cpu-idle-states = <&CPU_SLEEP>; 1958 next-level-cache = <&L2>; 1959 }; 1960 1961 cpu@1 { 1962 device_type = "cpu"; 1963 compatible = "arm,cortex-a57"; 1964 reg = <1>; 1965 cpu-idle-states = <&CPU_SLEEP>; 1966 next-level-cache = <&L2>; 1967 }; 1968 1969 cpu@2 { 1970 device_type = "cpu"; 1971 compatible = "arm,cortex-a57"; 1972 reg = <2>; 1973 cpu-idle-states = <&CPU_SLEEP>; 1974 next-level-cache = <&L2>; 1975 }; 1976 1977 cpu@3 { 1978 device_type = "cpu"; 1979 compatible = "arm,cortex-a57"; 1980 reg = <3>; 1981 cpu-idle-states = <&CPU_SLEEP>; 1982 next-level-cache = <&L2>; 1983 }; 1984 1985 idle-states { 1986 entry-method = "psci"; 1987 1988 CPU_SLEEP: cpu-sleep { 1989 compatible = "arm,idle-state"; 1990 arm,psci-suspend-param = <0x40000007>; 1991 entry-latency-us = <100>; 1992 exit-latency-us = <30>; 1993 min-residency-us = <1000>; 1994 wakeup-latency-us = <130>; 1995 idle-state-name = "cpu-sleep"; 1996 status = "disabled"; 1997 }; 1998 }; 1999 2000 L2: l2-cache { 2001 compatible = "cache"; 2002 cache-level = <2>; 2003 }; 2004 }; 2005 2006 pmu { 2007 compatible = "arm,armv8-pmuv3"; 2008 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2012 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2013 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2014 }; 2015 2016 sound { 2017 status = "disabled"; 2018 2019 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2020 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2021 clock-names = "pll_a", "plla_out0"; 2022 2023 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2024 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2025 <&tegra_car TEGRA210_CLK_EXTERN1>; 2026 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2027 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2028 }; 2029 2030 thermal-zones { 2031 cpu-thermal { 2032 polling-delay-passive = <1000>; 2033 polling-delay = <0>; 2034 2035 thermal-sensors = 2036 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2037 2038 trips { 2039 cpu-shutdown-trip { 2040 temperature = <102500>; 2041 hysteresis = <0>; 2042 type = "critical"; 2043 }; 2044 2045 cpu_throttle_trip: throttle-trip { 2046 temperature = <98500>; 2047 hysteresis = <1000>; 2048 type = "hot"; 2049 }; 2050 }; 2051 2052 cooling-maps { 2053 map0 { 2054 trip = <&cpu_throttle_trip>; 2055 cooling-device = <&throttle_heavy 1 1>; 2056 }; 2057 }; 2058 }; 2059 2060 mem-thermal { 2061 polling-delay-passive = <0>; 2062 polling-delay = <0>; 2063 2064 thermal-sensors = 2065 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2066 2067 trips { 2068 dram_nominal: mem-nominal-trip { 2069 temperature = <50000>; 2070 hysteresis = <1000>; 2071 type = "passive"; 2072 }; 2073 2074 dram_throttle: mem-throttle-trip { 2075 temperature = <70000>; 2076 hysteresis = <1000>; 2077 type = "active"; 2078 }; 2079 2080 mem-hot-trip { 2081 temperature = <100000>; 2082 hysteresis = <1000>; 2083 type = "hot"; 2084 }; 2085 2086 mem-shutdown-trip { 2087 temperature = <103000>; 2088 hysteresis = <0>; 2089 type = "critical"; 2090 }; 2091 }; 2092 2093 cooling-maps { 2094 dram-passive { 2095 cooling-device = <&emc 0 0>; 2096 trip = <&dram_nominal>; 2097 }; 2098 2099 dram-active { 2100 cooling-device = <&emc 1 1>; 2101 trip = <&dram_throttle>; 2102 }; 2103 }; 2104 }; 2105 2106 gpu-thermal { 2107 polling-delay-passive = <1000>; 2108 polling-delay = <0>; 2109 2110 thermal-sensors = 2111 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2112 2113 trips { 2114 gpu-shutdown-trip { 2115 temperature = <103000>; 2116 hysteresis = <0>; 2117 type = "critical"; 2118 }; 2119 2120 gpu_throttle_trip: throttle-trip { 2121 temperature = <100000>; 2122 hysteresis = <1000>; 2123 type = "hot"; 2124 }; 2125 }; 2126 2127 cooling-maps { 2128 map0 { 2129 trip = <&gpu_throttle_trip>; 2130 cooling-device = <&throttle_heavy 1 1>; 2131 }; 2132 }; 2133 }; 2134 2135 pllx-thermal { 2136 polling-delay-passive = <0>; 2137 polling-delay = <0>; 2138 2139 thermal-sensors = 2140 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2141 2142 trips { 2143 pllx-shutdown-trip { 2144 temperature = <103000>; 2145 hysteresis = <0>; 2146 type = "critical"; 2147 }; 2148 2149 pllx-throttle-trip { 2150 temperature = <100000>; 2151 hysteresis = <1000>; 2152 type = "hot"; 2153 }; 2154 }; 2155 2156 cooling-maps { 2157 /* 2158 * There are currently no cooling maps, 2159 * because there are no cooling devices. 2160 */ 2161 }; 2162 }; 2163 }; 2164 2165 timer { 2166 compatible = "arm,armv8-timer"; 2167 interrupts = <GIC_PPI 13 2168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2169 <GIC_PPI 14 2170 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2171 <GIC_PPI 11 2172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2173 <GIC_PPI 10 2174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2175 interrupt-parent = <&gic>; 2176 arm,no-tick-in-suspend; 2177 }; 2178}; 2179