1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/gpio-keys.h> 5#include <dt-bindings/input/linux-event-codes.h> 6#include <dt-bindings/mfd/max77620.h> 7 8#include "tegra210.dtsi" 9 10/ { 11 model = "NVIDIA Jetson Nano Developer Kit"; 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210"; 13 14 aliases { 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; 16 rtc0 = "/i2c@7000d000/pmic@3c"; 17 rtc1 = "/rtc@7000e000"; 18 serial0 = &uarta; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 reg = <0x0 0x80000000 0x1 0x0>; 28 }; 29 30 pcie@1003000 { 31 status = "okay"; 32 33 hvddio-pex-supply = <&vdd_1v8>; 34 dvddio-pex-supply = <&vdd_pex_1v05>; 35 vddio-pex-ctl-supply = <&vdd_1v8>; 36 37 pci@1,0 { 38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 39 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 40 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, 41 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 42 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 43 nvidia,num-lanes = <4>; 44 status = "okay"; 45 }; 46 47 pci@2,0 { 48 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 49 phy-names = "pcie-0"; 50 status = "okay"; 51 52 ethernet@0,0 { 53 reg = <0x000000 0 0 0 0>; 54 local-mac-address = [ 00 00 00 00 00 00 ]; 55 }; 56 }; 57 }; 58 59 host1x@50000000 { 60 dpaux@54040000 { 61 status = "okay"; 62 }; 63 64 vi@54080000 { 65 status = "okay"; 66 67 avdd-dsi-csi-supply = <&vdd_sys_1v2>; 68 69 csi@838 { 70 status = "okay"; 71 }; 72 }; 73 74 sor@54540000 { 75 status = "okay"; 76 77 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; 78 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 79 80 nvidia,xbar-cfg = <2 1 0 3 4>; 81 nvidia,dpaux = <&dpaux>; 82 }; 83 84 sor@54580000 { 85 status = "okay"; 86 87 avdd-io-hdmi-dp-supply = <&avdd_1v05>; 88 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 89 hdmi-supply = <&vdd_hdmi>; 90 91 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 92 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 93 GPIO_ACTIVE_LOW>; 94 nvidia,xbar-cfg = <0 1 2 3 4>; 95 }; 96 97 dpaux@545c0000 { 98 status = "okay"; 99 }; 100 101 i2c@546c0000 { 102 status = "okay"; 103 }; 104 }; 105 106 gpu@57000000 { 107 vdd-supply = <&vdd_gpu>; 108 status = "okay"; 109 }; 110 111 pinmux@700008d4 { 112 dvfs_pwm_active_state: dvfs_pwm_active { 113 dvfs_pwm_pbb1 { 114 nvidia,pins = "dvfs_pwm_pbb1"; 115 nvidia,tristate = <TEGRA_PIN_DISABLE>; 116 }; 117 }; 118 119 dvfs_pwm_inactive_state: dvfs_pwm_inactive { 120 dvfs_pwm_pbb1 { 121 nvidia,pins = "dvfs_pwm_pbb1"; 122 nvidia,tristate = <TEGRA_PIN_ENABLE>; 123 }; 124 }; 125 }; 126 127 /* debug port */ 128 serial@70006000 { 129 status = "okay"; 130 }; 131 132 pwm@7000a000 { 133 status = "okay"; 134 }; 135 136 i2c@7000c500 { 137 status = "okay"; 138 clock-frequency = <100000>; 139 140 eeprom@50 { 141 compatible = "atmel,24c02"; 142 reg = <0x50>; 143 144 label = "module"; 145 vcc-supply = <&vdd_1v8>; 146 address-width = <8>; 147 pagesize = <8>; 148 size = <256>; 149 read-only; 150 }; 151 152 eeprom@57 { 153 compatible = "atmel,24c02"; 154 reg = <0x57>; 155 156 label = "system"; 157 vcc-supply = <&vdd_1v8>; 158 address-width = <8>; 159 pagesize = <8>; 160 size = <256>; 161 read-only; 162 }; 163 }; 164 165 hdmi_ddc: i2c@7000c700 { 166 status = "okay"; 167 clock-frequency = <100000>; 168 }; 169 170 i2c@7000d000 { 171 status = "okay"; 172 clock-frequency = <400000>; 173 174 pmic: pmic@3c { 175 compatible = "maxim,max77620"; 176 reg = <0x3c>; 177 interrupt-parent = <&tegra_pmc>; 178 interrupts = <51 IRQ_TYPE_LEVEL_LOW>; 179 180 #interrupt-cells = <2>; 181 interrupt-controller; 182 183 #gpio-cells = <2>; 184 gpio-controller; 185 186 pinctrl-names = "default"; 187 pinctrl-0 = <&max77620_default>; 188 189 max77620_default: pinmux { 190 gpio0 { 191 pins = "gpio0"; 192 function = "gpio"; 193 }; 194 195 gpio1 { 196 pins = "gpio1"; 197 function = "fps-out"; 198 drive-push-pull = <1>; 199 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 200 maxim,active-fps-power-up-slot = <0>; 201 maxim,active-fps-power-down-slot = <7>; 202 }; 203 204 gpio2 { 205 pins = "gpio2"; 206 function = "fps-out"; 207 drive-open-drain = <1>; 208 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 209 maxim,active-fps-power-up-slot = <0>; 210 maxim,active-fps-power-down-slot = <7>; 211 }; 212 213 gpio3 { 214 pins = "gpio3"; 215 function = "fps-out"; 216 drive-open-drain = <1>; 217 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 218 maxim,active-fps-power-up-slot = <4>; 219 maxim,active-fps-power-down-slot = <3>; 220 }; 221 222 gpio4 { 223 pins = "gpio4"; 224 function = "32k-out1"; 225 }; 226 227 gpio5_6_7 { 228 pins = "gpio5", "gpio6", "gpio7"; 229 function = "gpio"; 230 drive-push-pull = <1>; 231 }; 232 }; 233 234 fps { 235 fps0 { 236 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 237 maxim,suspend-fps-time-period-us = <5120>; 238 }; 239 240 fps1 { 241 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 242 maxim,suspend-fps-time-period-us = <5120>; 243 }; 244 245 fps2 { 246 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 247 }; 248 }; 249 250 regulators { 251 in-ldo0-1-supply = <&vdd_pre>; 252 in-ldo2-supply = <&vdd_3v3_sys>; 253 in-ldo3-5-supply = <&vdd_1v8>; 254 in-ldo4-6-supply = <&vdd_5v0_sys>; 255 in-ldo7-8-supply = <&vdd_pre>; 256 in-sd0-supply = <&vdd_5v0_sys>; 257 in-sd1-supply = <&vdd_5v0_sys>; 258 in-sd2-supply = <&vdd_5v0_sys>; 259 in-sd3-supply = <&vdd_5v0_sys>; 260 261 vdd_soc: sd0 { 262 regulator-name = "VDD_SOC"; 263 regulator-min-microvolt = <1000000>; 264 regulator-max-microvolt = <1170000>; 265 regulator-enable-ramp-delay = <146>; 266 regulator-ramp-delay = <27500>; 267 regulator-ramp-delay-scale = <300>; 268 regulator-always-on; 269 regulator-boot-on; 270 271 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 272 maxim,active-fps-power-up-slot = <1>; 273 maxim,active-fps-power-down-slot = <6>; 274 }; 275 276 vdd_ddr: sd1 { 277 regulator-name = "VDD_DDR_1V1_PMIC"; 278 regulator-min-microvolt = <1150000>; 279 regulator-max-microvolt = <1150000>; 280 regulator-enable-ramp-delay = <176>; 281 regulator-ramp-delay = <27500>; 282 regulator-ramp-delay-scale = <300>; 283 regulator-always-on; 284 regulator-boot-on; 285 286 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 287 maxim,active-fps-power-up-slot = <5>; 288 maxim,active-fps-power-down-slot = <2>; 289 }; 290 291 vdd_pre: sd2 { 292 regulator-name = "VDD_PRE_REG_1V35"; 293 regulator-min-microvolt = <1350000>; 294 regulator-max-microvolt = <1350000>; 295 regulator-enable-ramp-delay = <176>; 296 regulator-ramp-delay = <27500>; 297 regulator-ramp-delay-scale = <350>; 298 regulator-always-on; 299 regulator-boot-on; 300 301 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 302 maxim,active-fps-power-up-slot = <2>; 303 maxim,active-fps-power-down-slot = <5>; 304 }; 305 306 vdd_1v8: sd3 { 307 regulator-name = "VDD_1V8"; 308 regulator-min-microvolt = <1800000>; 309 regulator-max-microvolt = <1800000>; 310 regulator-enable-ramp-delay = <242>; 311 regulator-ramp-delay = <27500>; 312 regulator-ramp-delay-scale = <360>; 313 regulator-always-on; 314 regulator-boot-on; 315 316 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 317 maxim,active-fps-power-up-slot = <3>; 318 maxim,active-fps-power-down-slot = <4>; 319 }; 320 321 vdd_sys_1v2: ldo0 { 322 regulator-name = "AVDD_SYS_1V2"; 323 regulator-min-microvolt = <1200000>; 324 regulator-max-microvolt = <1200000>; 325 regulator-enable-ramp-delay = <26>; 326 regulator-ramp-delay = <100000>; 327 regulator-ramp-delay-scale = <200>; 328 regulator-always-on; 329 regulator-boot-on; 330 331 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 332 maxim,active-fps-power-up-slot = <0>; 333 maxim,active-fps-power-down-slot = <7>; 334 }; 335 336 vdd_pex_1v05: ldo1 { 337 regulator-name = "VDD_PEX_1V05"; 338 regulator-min-microvolt = <1050000>; 339 regulator-max-microvolt = <1050000>; 340 regulator-enable-ramp-delay = <22>; 341 regulator-ramp-delay = <100000>; 342 regulator-ramp-delay-scale = <200>; 343 344 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 345 maxim,active-fps-power-up-slot = <0>; 346 maxim,active-fps-power-down-slot = <7>; 347 }; 348 349 vddio_sdmmc: ldo2 { 350 regulator-name = "VDDIO_SDMMC"; 351 regulator-min-microvolt = <1800000>; 352 regulator-max-microvolt = <3300000>; 353 regulator-enable-ramp-delay = <62>; 354 regulator-ramp-delay = <100000>; 355 regulator-ramp-delay-scale = <200>; 356 357 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 358 maxim,active-fps-power-up-slot = <0>; 359 maxim,active-fps-power-down-slot = <7>; 360 }; 361 362 ldo3 { 363 status = "disabled"; 364 }; 365 366 vdd_rtc: ldo4 { 367 regulator-name = "VDD_RTC"; 368 regulator-min-microvolt = <850000>; 369 regulator-max-microvolt = <1100000>; 370 regulator-enable-ramp-delay = <22>; 371 regulator-ramp-delay = <100000>; 372 regulator-ramp-delay-scale = <200>; 373 regulator-disable-active-discharge; 374 regulator-always-on; 375 regulator-boot-on; 376 377 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 378 maxim,active-fps-power-up-slot = <1>; 379 maxim,active-fps-power-down-slot = <6>; 380 }; 381 382 ldo5 { 383 status = "disabled"; 384 }; 385 386 ldo6 { 387 status = "disabled"; 388 }; 389 390 avdd_1v05_pll: ldo7 { 391 regulator-name = "AVDD_1V05_PLL"; 392 regulator-min-microvolt = <1050000>; 393 regulator-max-microvolt = <1050000>; 394 regulator-enable-ramp-delay = <24>; 395 regulator-ramp-delay = <100000>; 396 regulator-ramp-delay-scale = <200>; 397 398 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 399 maxim,active-fps-power-up-slot = <3>; 400 maxim,active-fps-power-down-slot = <4>; 401 }; 402 403 avdd_1v05: ldo8 { 404 regulator-name = "AVDD_SATA_HDMI_DP_1V05"; 405 regulator-min-microvolt = <1050000>; 406 regulator-max-microvolt = <1050000>; 407 regulator-enable-ramp-delay = <22>; 408 regulator-ramp-delay = <100000>; 409 regulator-ramp-delay-scale = <200>; 410 411 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 412 maxim,active-fps-power-up-slot = <6>; 413 maxim,active-fps-power-down-slot = <1>; 414 }; 415 }; 416 }; 417 }; 418 419 pmc@7000e400 { 420 nvidia,invert-interrupt; 421 nvidia,suspend-mode = <0>; 422 nvidia,cpu-pwr-good-time = <0>; 423 nvidia,cpu-pwr-off-time = <0>; 424 nvidia,core-pwr-good-time = <4587 3876>; 425 nvidia,core-pwr-off-time = <39065>; 426 nvidia,core-power-req-active-high; 427 nvidia,sys-clock-req-active-high; 428 }; 429 430 hda@70030000 { 431 nvidia,model = "NVIDIA Jetson Nano HDA"; 432 433 status = "okay"; 434 }; 435 436 usb@70090000 { 437 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 438 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 439 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 440 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; 441 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; 442 443 avdd-usb-supply = <&vdd_3v3_sys>; 444 dvddio-pex-supply = <&vdd_pex_1v05>; 445 hvddio-pex-supply = <&vdd_1v8>; 446 447 status = "okay"; 448 }; 449 450 padctl@7009f000 { 451 status = "okay"; 452 453 avdd-pll-utmip-supply = <&vdd_1v8>; 454 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 455 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 456 hvdd-pex-pll-e-supply = <&vdd_1v8>; 457 458 pads { 459 usb2 { 460 status = "okay"; 461 462 lanes { 463 micro_b: usb2-0 { 464 nvidia,function = "xusb"; 465 status = "okay"; 466 }; 467 468 usb2-1 { 469 nvidia,function = "xusb"; 470 status = "okay"; 471 }; 472 473 usb2-2 { 474 nvidia,function = "xusb"; 475 status = "okay"; 476 }; 477 }; 478 }; 479 480 pcie { 481 status = "okay"; 482 483 lanes { 484 pcie-0 { 485 nvidia,function = "pcie-x1"; 486 status = "okay"; 487 }; 488 489 pcie-1 { 490 nvidia,function = "pcie-x4"; 491 status = "okay"; 492 }; 493 494 pcie-2 { 495 nvidia,function = "pcie-x4"; 496 status = "okay"; 497 }; 498 499 pcie-3 { 500 nvidia,function = "pcie-x4"; 501 status = "okay"; 502 }; 503 504 pcie-4 { 505 nvidia,function = "pcie-x4"; 506 status = "okay"; 507 }; 508 509 pcie-5 { 510 nvidia,function = "usb3-ss"; 511 status = "okay"; 512 }; 513 514 pcie-6 { 515 nvidia,function = "usb3-ss"; 516 status = "okay"; 517 }; 518 }; 519 }; 520 }; 521 522 ports { 523 usb2-0 { 524 status = "okay"; 525 mode = "peripheral"; 526 usb-role-switch; 527 528 vbus-supply = <&vdd_5v0_usb>; 529 530 connector { 531 compatible = "gpio-usb-b-connector", 532 "usb-b-connector"; 533 label = "micro-USB"; 534 type = "micro"; 535 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) 536 GPIO_ACTIVE_LOW>; 537 }; 538 }; 539 540 usb2-1 { 541 status = "okay"; 542 mode = "host"; 543 }; 544 545 usb2-2 { 546 status = "okay"; 547 mode = "host"; 548 }; 549 550 usb3-0 { 551 status = "okay"; 552 nvidia,usb2-companion = <1>; 553 vbus-supply = <&vdd_hub_3v3>; 554 }; 555 }; 556 }; 557 558 mmc@700b0000 { 559 status = "okay"; 560 bus-width = <4>; 561 562 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 563 disable-wp; 564 565 vqmmc-supply = <&vddio_sdmmc>; 566 vmmc-supply = <&vdd_3v3_sd>; 567 }; 568 569 mmc@700b0400 { 570 status = "okay"; 571 bus-width = <4>; 572 573 vqmmc-supply = <&vdd_1v8>; 574 vmmc-supply = <&vdd_3v3_sys>; 575 576 non-removable; 577 cap-sdio-irq; 578 keep-power-in-suspend; 579 wakeup-source; 580 }; 581 582 usb@700d0000 { 583 status = "okay"; 584 phys = <µ_b>; 585 phy-names = "usb2-0"; 586 avddio-usb-supply = <&vdd_3v3_sys>; 587 hvdd-usb-supply = <&vdd_1v8>; 588 }; 589 590 clock@70110000 { 591 status = "okay"; 592 593 nvidia,cf = <6>; 594 nvidia,ci = <0>; 595 nvidia,cg = <2>; 596 nvidia,droop-ctrl = <0x00000f00>; 597 nvidia,force-mode = <1>; 598 nvidia,sample-rate = <25000>; 599 600 nvidia,pwm-min-microvolts = <708000>; 601 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 602 nvidia,pwm-to-pmic; 603 nvidia,pwm-tristate-microvolts = <1000000>; 604 nvidia,pwm-voltage-step-microvolts = <19200>; 605 606 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; 607 pinctrl-0 = <&dvfs_pwm_active_state>; 608 pinctrl-1 = <&dvfs_pwm_inactive_state>; 609 }; 610 611 aconnect@702c0000 { 612 status = "okay"; 613 614 dma-controller@702e2000 { 615 status = "okay"; 616 }; 617 618 interrupt-controller@702f9000 { 619 status = "okay"; 620 }; 621 622 ahub@702d0800 { 623 status = "okay"; 624 625 admaif@702d0000 { 626 status = "okay"; 627 }; 628 629 i2s@702d1200 { 630 status = "okay"; 631 632 ports { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 636 port@0 { 637 reg = <0>; 638 639 i2s3_cif_ep: endpoint { 640 remote-endpoint = <&xbar_i2s3_ep>; 641 }; 642 }; 643 644 i2s3_port: port@1 { 645 reg = <1>; 646 647 i2s3_dap_ep: endpoint { 648 dai-format = "i2s"; 649 /* Placeholder for external Codec */ 650 }; 651 }; 652 }; 653 }; 654 655 i2s@702d1300 { 656 status = "okay"; 657 658 ports { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 662 port@0 { 663 reg = <0>; 664 665 i2s4_cif_ep: endpoint { 666 remote-endpoint = <&xbar_i2s4_ep>; 667 }; 668 }; 669 670 i2s4_port: port@1 { 671 reg = <1>; 672 673 i2s4_dap_ep: endpoint { 674 dai-format = "i2s"; 675 /* Placeholder for external Codec */ 676 }; 677 }; 678 }; 679 }; 680 681 dmic@702d4000 { 682 status = "okay"; 683 684 ports { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 688 port@0 { 689 reg = <0>; 690 691 dmic1_cif_ep: endpoint { 692 remote-endpoint = <&xbar_dmic1_ep>; 693 }; 694 }; 695 696 dmic1_port: port@1 { 697 reg = <1>; 698 699 dmic1_dap_ep: endpoint { 700 /* Placeholder for external Codec */ 701 }; 702 }; 703 }; 704 }; 705 706 dmic@702d4100 { 707 status = "okay"; 708 709 ports { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 713 port@0 { 714 reg = <0>; 715 716 dmic2_cif_ep: endpoint { 717 remote-endpoint = <&xbar_dmic2_ep>; 718 }; 719 }; 720 721 dmic2_port: port@1 { 722 reg = <1>; 723 724 dmic2_dap_ep: endpoint { 725 /* Placeholder for external Codec */ 726 }; 727 }; 728 }; 729 }; 730 731 sfc@702d2000 { 732 status = "okay"; 733 734 ports { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 738 port@0 { 739 reg = <0>; 740 741 sfc1_cif_in_ep: endpoint { 742 remote-endpoint = <&xbar_sfc1_in_ep>; 743 }; 744 }; 745 746 sfc1_out_port: port@1 { 747 reg = <1>; 748 749 sfc1_cif_out_ep: endpoint { 750 remote-endpoint = <&xbar_sfc1_out_ep>; 751 }; 752 }; 753 }; 754 }; 755 756 sfc@702d2200 { 757 status = "okay"; 758 759 ports { 760 #address-cells = <1>; 761 #size-cells = <0>; 762 763 port@0 { 764 reg = <0>; 765 766 sfc2_cif_in_ep: endpoint { 767 remote-endpoint = <&xbar_sfc2_in_ep>; 768 }; 769 }; 770 771 sfc2_out_port: port@1 { 772 reg = <1>; 773 774 sfc2_cif_out_ep: endpoint { 775 remote-endpoint = <&xbar_sfc2_out_ep>; 776 }; 777 }; 778 }; 779 }; 780 781 sfc@702d2400 { 782 status = "okay"; 783 784 ports { 785 #address-cells = <1>; 786 #size-cells = <0>; 787 788 port@0 { 789 reg = <0>; 790 791 sfc3_cif_in_ep: endpoint { 792 remote-endpoint = <&xbar_sfc3_in_ep>; 793 }; 794 }; 795 796 sfc3_out_port: port@1 { 797 reg = <1>; 798 799 sfc3_cif_out_ep: endpoint { 800 remote-endpoint = <&xbar_sfc3_out_ep>; 801 }; 802 }; 803 }; 804 }; 805 806 sfc@702d2600 { 807 status = "okay"; 808 809 ports { 810 #address-cells = <1>; 811 #size-cells = <0>; 812 813 port@0 { 814 reg = <0>; 815 816 sfc4_cif_in_ep: endpoint { 817 remote-endpoint = <&xbar_sfc4_in_ep>; 818 }; 819 }; 820 821 sfc4_out_port: port@1 { 822 reg = <1>; 823 824 sfc4_cif_out_ep: endpoint { 825 remote-endpoint = <&xbar_sfc4_out_ep>; 826 }; 827 }; 828 }; 829 }; 830 831 mvc@702da000 { 832 status = "okay"; 833 834 ports { 835 #address-cells = <1>; 836 #size-cells = <0>; 837 838 port@0 { 839 reg = <0>; 840 841 mvc1_cif_in_ep: endpoint { 842 remote-endpoint = <&xbar_mvc1_in_ep>; 843 }; 844 }; 845 846 mvc1_out_port: port@1 { 847 reg = <1>; 848 849 mvc1_cif_out_ep: endpoint { 850 remote-endpoint = <&xbar_mvc1_out_ep>; 851 }; 852 }; 853 }; 854 }; 855 856 mvc@702da200 { 857 status = "okay"; 858 859 ports { 860 #address-cells = <1>; 861 #size-cells = <0>; 862 863 port@0 { 864 reg = <0>; 865 866 mvc2_cif_in_ep: endpoint { 867 remote-endpoint = <&xbar_mvc2_in_ep>; 868 }; 869 }; 870 871 mvc2_out_port: port@1 { 872 reg = <1>; 873 874 mvc2_cif_out_ep: endpoint { 875 remote-endpoint = <&xbar_mvc2_out_ep>; 876 }; 877 }; 878 }; 879 }; 880 881 amx@702d3000 { 882 status = "okay"; 883 884 ports { 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 port@0 { 889 reg = <0>; 890 891 amx1_in1_ep: endpoint { 892 remote-endpoint = <&xbar_amx1_in1_ep>; 893 }; 894 }; 895 896 port@1 { 897 reg = <1>; 898 899 amx1_in2_ep: endpoint { 900 remote-endpoint = <&xbar_amx1_in2_ep>; 901 }; 902 }; 903 904 port@2 { 905 reg = <2>; 906 907 amx1_in3_ep: endpoint { 908 remote-endpoint = <&xbar_amx1_in3_ep>; 909 }; 910 }; 911 912 port@3 { 913 reg = <3>; 914 915 amx1_in4_ep: endpoint { 916 remote-endpoint = <&xbar_amx1_in4_ep>; 917 }; 918 }; 919 920 amx1_out_port: port@4 { 921 reg = <4>; 922 923 amx1_out_ep: endpoint { 924 remote-endpoint = <&xbar_amx1_out_ep>; 925 }; 926 }; 927 }; 928 }; 929 930 amx@702d3100 { 931 status = "okay"; 932 933 ports { 934 #address-cells = <1>; 935 #size-cells = <0>; 936 937 port@0 { 938 reg = <0>; 939 940 amx2_in1_ep: endpoint { 941 remote-endpoint = <&xbar_amx2_in1_ep>; 942 }; 943 }; 944 945 port@1 { 946 reg = <1>; 947 948 amx2_in2_ep: endpoint { 949 remote-endpoint = <&xbar_amx2_in2_ep>; 950 }; 951 }; 952 953 amx2_in3_port: port@2 { 954 reg = <2>; 955 956 amx2_in3_ep: endpoint { 957 remote-endpoint = <&xbar_amx2_in3_ep>; 958 }; 959 }; 960 961 amx2_in4_port: port@3 { 962 reg = <3>; 963 964 amx2_in4_ep: endpoint { 965 remote-endpoint = <&xbar_amx2_in4_ep>; 966 }; 967 }; 968 969 amx2_out_port: port@4 { 970 reg = <4>; 971 972 amx2_out_ep: endpoint { 973 remote-endpoint = <&xbar_amx2_out_ep>; 974 }; 975 }; 976 }; 977 }; 978 979 adx@702d3800 { 980 status = "okay"; 981 982 ports { 983 #address-cells = <1>; 984 #size-cells = <0>; 985 986 port@0 { 987 reg = <0>; 988 989 adx1_in_ep: endpoint { 990 remote-endpoint = <&xbar_adx1_in_ep>; 991 }; 992 }; 993 994 adx1_out1_port: port@1 { 995 reg = <1>; 996 997 adx1_out1_ep: endpoint { 998 remote-endpoint = <&xbar_adx1_out1_ep>; 999 }; 1000 }; 1001 1002 adx1_out2_port: port@2 { 1003 reg = <2>; 1004 1005 adx1_out2_ep: endpoint { 1006 remote-endpoint = <&xbar_adx1_out2_ep>; 1007 }; 1008 }; 1009 1010 adx1_out3_port: port@3 { 1011 reg = <3>; 1012 1013 adx1_out3_ep: endpoint { 1014 remote-endpoint = <&xbar_adx1_out3_ep>; 1015 }; 1016 }; 1017 1018 adx1_out4_port: port@4 { 1019 reg = <4>; 1020 1021 adx1_out4_ep: endpoint { 1022 remote-endpoint = <&xbar_adx1_out4_ep>; 1023 }; 1024 }; 1025 }; 1026 }; 1027 1028 adx@702d3900 { 1029 status = "okay"; 1030 1031 ports { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 port@0 { 1036 reg = <0>; 1037 1038 adx2_in_ep: endpoint { 1039 remote-endpoint = <&xbar_adx2_in_ep>; 1040 }; 1041 }; 1042 1043 adx2_out1_port: port@1 { 1044 reg = <1>; 1045 1046 adx2_out1_ep: endpoint { 1047 remote-endpoint = <&xbar_adx2_out1_ep>; 1048 }; 1049 }; 1050 1051 adx2_out2_port: port@2 { 1052 reg = <2>; 1053 1054 adx2_out2_ep: endpoint { 1055 remote-endpoint = <&xbar_adx2_out2_ep>; 1056 }; 1057 }; 1058 1059 adx2_out3_port: port@3 { 1060 reg = <3>; 1061 1062 adx2_out3_ep: endpoint { 1063 remote-endpoint = <&xbar_adx2_out3_ep>; 1064 }; 1065 }; 1066 1067 adx2_out4_port: port@4 { 1068 reg = <4>; 1069 1070 adx2_out4_ep: endpoint { 1071 remote-endpoint = <&xbar_adx2_out4_ep>; 1072 }; 1073 }; 1074 }; 1075 }; 1076 1077 amixer@702dbb00 { 1078 status = "okay"; 1079 1080 ports { 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 port@0 { 1085 reg = <0x0>; 1086 1087 mixer_in1_ep: endpoint { 1088 remote-endpoint = <&xbar_mixer_in1_ep>; 1089 }; 1090 }; 1091 1092 port@1 { 1093 reg = <0x1>; 1094 1095 mixer_in2_ep: endpoint { 1096 remote-endpoint = <&xbar_mixer_in2_ep>; 1097 }; 1098 }; 1099 1100 port@2 { 1101 reg = <0x2>; 1102 1103 mixer_in3_ep: endpoint { 1104 remote-endpoint = <&xbar_mixer_in3_ep>; 1105 }; 1106 }; 1107 1108 port@3 { 1109 reg = <0x3>; 1110 1111 mixer_in4_ep: endpoint { 1112 remote-endpoint = <&xbar_mixer_in4_ep>; 1113 }; 1114 }; 1115 1116 port@4 { 1117 reg = <0x4>; 1118 1119 mixer_in5_ep: endpoint { 1120 remote-endpoint = <&xbar_mixer_in5_ep>; 1121 }; 1122 }; 1123 1124 port@5 { 1125 reg = <0x5>; 1126 1127 mixer_in6_ep: endpoint { 1128 remote-endpoint = <&xbar_mixer_in6_ep>; 1129 }; 1130 }; 1131 1132 port@6 { 1133 reg = <0x6>; 1134 1135 mixer_in7_ep: endpoint { 1136 remote-endpoint = <&xbar_mixer_in7_ep>; 1137 }; 1138 }; 1139 1140 port@7 { 1141 reg = <0x7>; 1142 1143 mixer_in8_ep: endpoint { 1144 remote-endpoint = <&xbar_mixer_in8_ep>; 1145 }; 1146 }; 1147 1148 port@8 { 1149 reg = <0x8>; 1150 1151 mixer_in9_ep: endpoint { 1152 remote-endpoint = <&xbar_mixer_in9_ep>; 1153 }; 1154 }; 1155 1156 port@9 { 1157 reg = <0x9>; 1158 1159 mixer_in10_ep: endpoint { 1160 remote-endpoint = <&xbar_mixer_in10_ep>; 1161 }; 1162 }; 1163 1164 mixer_out1_port: port@a { 1165 reg = <0xa>; 1166 1167 mixer_out1_ep: endpoint { 1168 remote-endpoint = <&xbar_mixer_out1_ep>; 1169 }; 1170 }; 1171 1172 mixer_out2_port: port@b { 1173 reg = <0xb>; 1174 1175 mixer_out2_ep: endpoint { 1176 remote-endpoint = <&xbar_mixer_out2_ep>; 1177 }; 1178 }; 1179 1180 mixer_out3_port: port@c { 1181 reg = <0xc>; 1182 1183 mixer_out3_ep: endpoint { 1184 remote-endpoint = <&xbar_mixer_out3_ep>; 1185 }; 1186 }; 1187 1188 mixer_out4_port: port@d { 1189 reg = <0xd>; 1190 1191 mixer_out4_ep: endpoint { 1192 remote-endpoint = <&xbar_mixer_out4_ep>; 1193 }; 1194 }; 1195 1196 mixer_out5_port: port@e { 1197 reg = <0xe>; 1198 1199 mixer_out5_ep: endpoint { 1200 remote-endpoint = <&xbar_mixer_out5_ep>; 1201 }; 1202 }; 1203 }; 1204 }; 1205 1206 ports { 1207 xbar_i2s3_port: port@c { 1208 reg = <0xc>; 1209 1210 xbar_i2s3_ep: endpoint { 1211 remote-endpoint = <&i2s3_cif_ep>; 1212 }; 1213 }; 1214 1215 xbar_i2s4_port: port@d { 1216 reg = <0xd>; 1217 1218 xbar_i2s4_ep: endpoint { 1219 remote-endpoint = <&i2s4_cif_ep>; 1220 }; 1221 }; 1222 1223 xbar_dmic1_port: port@f { 1224 reg = <0xf>; 1225 1226 xbar_dmic1_ep: endpoint { 1227 remote-endpoint = <&dmic1_cif_ep>; 1228 }; 1229 }; 1230 1231 xbar_dmic2_port: port@10 { 1232 reg = <0x10>; 1233 1234 xbar_dmic2_ep: endpoint { 1235 remote-endpoint = <&dmic2_cif_ep>; 1236 }; 1237 }; 1238 1239 xbar_sfc1_in_port: port@12 { 1240 reg = <0x12>; 1241 1242 xbar_sfc1_in_ep: endpoint { 1243 remote-endpoint = <&sfc1_cif_in_ep>; 1244 }; 1245 }; 1246 1247 port@13 { 1248 reg = <0x13>; 1249 1250 xbar_sfc1_out_ep: endpoint { 1251 remote-endpoint = <&sfc1_cif_out_ep>; 1252 }; 1253 }; 1254 1255 xbar_sfc2_in_port: port@14 { 1256 reg = <0x14>; 1257 1258 xbar_sfc2_in_ep: endpoint { 1259 remote-endpoint = <&sfc2_cif_in_ep>; 1260 }; 1261 }; 1262 1263 port@15 { 1264 reg = <0x15>; 1265 1266 xbar_sfc2_out_ep: endpoint { 1267 remote-endpoint = <&sfc2_cif_out_ep>; 1268 }; 1269 }; 1270 1271 xbar_sfc3_in_port: port@16 { 1272 reg = <0x16>; 1273 1274 xbar_sfc3_in_ep: endpoint { 1275 remote-endpoint = <&sfc3_cif_in_ep>; 1276 }; 1277 }; 1278 1279 port@17 { 1280 reg = <0x17>; 1281 1282 xbar_sfc3_out_ep: endpoint { 1283 remote-endpoint = <&sfc3_cif_out_ep>; 1284 }; 1285 }; 1286 1287 xbar_sfc4_in_port: port@18 { 1288 reg = <0x18>; 1289 1290 xbar_sfc4_in_ep: endpoint { 1291 remote-endpoint = <&sfc4_cif_in_ep>; 1292 }; 1293 }; 1294 1295 port@19 { 1296 reg = <0x19>; 1297 1298 xbar_sfc4_out_ep: endpoint { 1299 remote-endpoint = <&sfc4_cif_out_ep>; 1300 }; 1301 }; 1302 1303 xbar_mvc1_in_port: port@1a { 1304 reg = <0x1a>; 1305 1306 xbar_mvc1_in_ep: endpoint { 1307 remote-endpoint = <&mvc1_cif_in_ep>; 1308 }; 1309 }; 1310 1311 port@1b { 1312 reg = <0x1b>; 1313 1314 xbar_mvc1_out_ep: endpoint { 1315 remote-endpoint = <&mvc1_cif_out_ep>; 1316 }; 1317 }; 1318 1319 xbar_mvc2_in_port: port@1c { 1320 reg = <0x1c>; 1321 1322 xbar_mvc2_in_ep: endpoint { 1323 remote-endpoint = <&mvc2_cif_in_ep>; 1324 }; 1325 }; 1326 1327 port@1d { 1328 reg = <0x1d>; 1329 1330 xbar_mvc2_out_ep: endpoint { 1331 remote-endpoint = <&mvc2_cif_out_ep>; 1332 }; 1333 }; 1334 1335 xbar_amx1_in1_port: port@1e { 1336 reg = <0x1e>; 1337 1338 xbar_amx1_in1_ep: endpoint { 1339 remote-endpoint = <&amx1_in1_ep>; 1340 }; 1341 }; 1342 1343 xbar_amx1_in2_port: port@1f { 1344 reg = <0x1f>; 1345 1346 xbar_amx1_in2_ep: endpoint { 1347 remote-endpoint = <&amx1_in2_ep>; 1348 }; 1349 }; 1350 1351 xbar_amx1_in3_port: port@20 { 1352 reg = <0x20>; 1353 1354 xbar_amx1_in3_ep: endpoint { 1355 remote-endpoint = <&amx1_in3_ep>; 1356 }; 1357 }; 1358 1359 xbar_amx1_in4_port: port@21 { 1360 reg = <0x21>; 1361 1362 xbar_amx1_in4_ep: endpoint { 1363 remote-endpoint = <&amx1_in4_ep>; 1364 }; 1365 }; 1366 1367 port@22 { 1368 reg = <0x22>; 1369 1370 xbar_amx1_out_ep: endpoint { 1371 remote-endpoint = <&amx1_out_ep>; 1372 }; 1373 }; 1374 1375 xbar_amx2_in1_port: port@23 { 1376 reg = <0x23>; 1377 1378 xbar_amx2_in1_ep: endpoint { 1379 remote-endpoint = <&amx2_in1_ep>; 1380 }; 1381 }; 1382 1383 xbar_amx2_in2_port: port@24 { 1384 reg = <0x24>; 1385 1386 xbar_amx2_in2_ep: endpoint { 1387 remote-endpoint = <&amx2_in2_ep>; 1388 }; 1389 }; 1390 1391 xbar_amx2_in3_port: port@25 { 1392 reg = <0x25>; 1393 1394 xbar_amx2_in3_ep: endpoint { 1395 remote-endpoint = <&amx2_in3_ep>; 1396 }; 1397 }; 1398 1399 xbar_amx2_in4_port: port@26 { 1400 reg = <0x26>; 1401 1402 xbar_amx2_in4_ep: endpoint { 1403 remote-endpoint = <&amx2_in4_ep>; 1404 }; 1405 }; 1406 1407 port@27 { 1408 reg = <0x27>; 1409 1410 xbar_amx2_out_ep: endpoint { 1411 remote-endpoint = <&amx2_out_ep>; 1412 }; 1413 }; 1414 1415 xbar_adx1_in_port: port@28 { 1416 reg = <0x28>; 1417 1418 xbar_adx1_in_ep: endpoint { 1419 remote-endpoint = <&adx1_in_ep>; 1420 }; 1421 }; 1422 1423 port@29 { 1424 reg = <0x29>; 1425 1426 xbar_adx1_out1_ep: endpoint { 1427 remote-endpoint = <&adx1_out1_ep>; 1428 }; 1429 }; 1430 1431 port@2a { 1432 reg = <0x2a>; 1433 1434 xbar_adx1_out2_ep: endpoint { 1435 remote-endpoint = <&adx1_out2_ep>; 1436 }; 1437 }; 1438 1439 port@2b { 1440 reg = <0x2b>; 1441 1442 xbar_adx1_out3_ep: endpoint { 1443 remote-endpoint = <&adx1_out3_ep>; 1444 }; 1445 }; 1446 1447 port@2c { 1448 reg = <0x2c>; 1449 1450 xbar_adx1_out4_ep: endpoint { 1451 remote-endpoint = <&adx1_out4_ep>; 1452 }; 1453 }; 1454 1455 xbar_adx2_in_port: port@2d { 1456 reg = <0x2d>; 1457 1458 xbar_adx2_in_ep: endpoint { 1459 remote-endpoint = <&adx2_in_ep>; 1460 }; 1461 }; 1462 1463 port@2e { 1464 reg = <0x2e>; 1465 1466 xbar_adx2_out1_ep: endpoint { 1467 remote-endpoint = <&adx2_out1_ep>; 1468 }; 1469 }; 1470 1471 port@2f { 1472 reg = <0x2f>; 1473 1474 xbar_adx2_out2_ep: endpoint { 1475 remote-endpoint = <&adx2_out2_ep>; 1476 }; 1477 }; 1478 1479 port@30 { 1480 reg = <0x30>; 1481 1482 xbar_adx2_out3_ep: endpoint { 1483 remote-endpoint = <&adx2_out3_ep>; 1484 }; 1485 }; 1486 1487 port@31 { 1488 reg = <0x31>; 1489 1490 xbar_adx2_out4_ep: endpoint { 1491 remote-endpoint = <&adx2_out4_ep>; 1492 }; 1493 }; 1494 1495 xbar_mixer_in1_port: port@32 { 1496 reg = <0x32>; 1497 1498 xbar_mixer_in1_ep: endpoint { 1499 remote-endpoint = <&mixer_in1_ep>; 1500 }; 1501 }; 1502 1503 xbar_mixer_in2_port: port@33 { 1504 reg = <0x33>; 1505 1506 xbar_mixer_in2_ep: endpoint { 1507 remote-endpoint = <&mixer_in2_ep>; 1508 }; 1509 }; 1510 1511 xbar_mixer_in3_port: port@34 { 1512 reg = <0x34>; 1513 1514 xbar_mixer_in3_ep: endpoint { 1515 remote-endpoint = <&mixer_in3_ep>; 1516 }; 1517 }; 1518 1519 xbar_mixer_in4_port: port@35 { 1520 reg = <0x35>; 1521 1522 xbar_mixer_in4_ep: endpoint { 1523 remote-endpoint = <&mixer_in4_ep>; 1524 }; 1525 }; 1526 1527 xbar_mixer_in5_port: port@36 { 1528 reg = <0x36>; 1529 1530 xbar_mixer_in5_ep: endpoint { 1531 remote-endpoint = <&mixer_in5_ep>; 1532 }; 1533 }; 1534 1535 xbar_mixer_in6_port: port@37 { 1536 reg = <0x37>; 1537 1538 xbar_mixer_in6_ep: endpoint { 1539 remote-endpoint = <&mixer_in6_ep>; 1540 }; 1541 }; 1542 1543 xbar_mixer_in7_port: port@38 { 1544 reg = <0x38>; 1545 1546 xbar_mixer_in7_ep: endpoint { 1547 remote-endpoint = <&mixer_in7_ep>; 1548 }; 1549 }; 1550 1551 xbar_mixer_in8_port: port@39 { 1552 reg = <0x39>; 1553 1554 xbar_mixer_in8_ep: endpoint { 1555 remote-endpoint = <&mixer_in8_ep>; 1556 }; 1557 }; 1558 1559 xbar_mixer_in9_port: port@3a { 1560 reg = <0x3a>; 1561 1562 xbar_mixer_in9_ep: endpoint { 1563 remote-endpoint = <&mixer_in9_ep>; 1564 }; 1565 }; 1566 1567 xbar_mixer_in10_port: port@3b { 1568 reg = <0x3b>; 1569 1570 xbar_mixer_in10_ep: endpoint { 1571 remote-endpoint = <&mixer_in10_ep>; 1572 }; 1573 }; 1574 1575 port@3c { 1576 reg = <0x3c>; 1577 1578 xbar_mixer_out1_ep: endpoint { 1579 remote-endpoint = <&mixer_out1_ep>; 1580 }; 1581 }; 1582 1583 port@3d { 1584 reg = <0x3d>; 1585 1586 xbar_mixer_out2_ep: endpoint { 1587 remote-endpoint = <&mixer_out2_ep>; 1588 }; 1589 }; 1590 1591 port@3e { 1592 reg = <0x3e>; 1593 1594 xbar_mixer_out3_ep: endpoint { 1595 remote-endpoint = <&mixer_out3_ep>; 1596 }; 1597 }; 1598 1599 port@3f { 1600 reg = <0x3f>; 1601 1602 xbar_mixer_out4_ep: endpoint { 1603 remote-endpoint = <&mixer_out4_ep>; 1604 }; 1605 }; 1606 1607 port@40 { 1608 reg = <0x40>; 1609 1610 xbar_mixer_out5_ep: endpoint { 1611 remote-endpoint = <&mixer_out5_ep>; 1612 }; 1613 }; 1614 }; 1615 }; 1616 }; 1617 1618 spi@70410000 { 1619 status = "okay"; 1620 1621 flash@0 { 1622 compatible = "jedec,spi-nor"; 1623 reg = <0>; 1624 spi-max-frequency = <104000000>; 1625 spi-tx-bus-width = <2>; 1626 spi-rx-bus-width = <2>; 1627 }; 1628 }; 1629 1630 clk32k_in: clock-32k { 1631 compatible = "fixed-clock"; 1632 clock-frequency = <32768>; 1633 #clock-cells = <0>; 1634 }; 1635 1636 cpus { 1637 cpu@0 { 1638 enable-method = "psci"; 1639 }; 1640 1641 cpu@1 { 1642 enable-method = "psci"; 1643 }; 1644 1645 cpu@2 { 1646 enable-method = "psci"; 1647 }; 1648 1649 cpu@3 { 1650 enable-method = "psci"; 1651 }; 1652 1653 idle-states { 1654 cpu-sleep { 1655 status = "okay"; 1656 }; 1657 }; 1658 }; 1659 1660 fan: pwm-fan { 1661 compatible = "pwm-fan"; 1662 pwms = <&pwm 3 45334>; 1663 1664 cooling-levels = <0 64 128 255>; 1665 #cooling-cells = <2>; 1666 }; 1667 1668 thermal-zones { 1669 cpu-thermal { 1670 trips { 1671 cpu_trip_critical: critical { 1672 temperature = <96500>; 1673 hysteresis = <0>; 1674 type = "critical"; 1675 }; 1676 1677 cpu_trip_hot: hot { 1678 temperature = <70000>; 1679 hysteresis = <2000>; 1680 type = "hot"; 1681 }; 1682 1683 cpu_trip_active: active { 1684 temperature = <50000>; 1685 hysteresis = <2000>; 1686 type = "active"; 1687 }; 1688 1689 cpu_trip_passive: passive { 1690 temperature = <30000>; 1691 hysteresis = <2000>; 1692 type = "passive"; 1693 }; 1694 }; 1695 1696 cooling-maps { 1697 cpu-critical { 1698 cooling-device = <&fan 3 3>; 1699 trip = <&cpu_trip_critical>; 1700 }; 1701 1702 cpu-hot { 1703 cooling-device = <&fan 2 2>; 1704 trip = <&cpu_trip_hot>; 1705 }; 1706 1707 cpu-active { 1708 cooling-device = <&fan 1 1>; 1709 trip = <&cpu_trip_active>; 1710 }; 1711 1712 cpu-passive { 1713 cooling-device = <&fan 0 0>; 1714 trip = <&cpu_trip_passive>; 1715 }; 1716 }; 1717 }; 1718 }; 1719 1720 gpio-keys { 1721 compatible = "gpio-keys"; 1722 1723 power { 1724 label = "Power"; 1725 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; 1726 linux,input-type = <EV_KEY>; 1727 linux,code = <KEY_POWER>; 1728 debounce-interval = <30>; 1729 wakeup-event-action = <EV_ACT_ASSERTED>; 1730 wakeup-source; 1731 }; 1732 1733 force-recovery { 1734 label = "Force Recovery"; 1735 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 1736 linux,input-type = <EV_KEY>; 1737 linux,code = <BTN_1>; 1738 debounce-interval = <30>; 1739 }; 1740 }; 1741 1742 psci { 1743 compatible = "arm,psci-1.0"; 1744 method = "smc"; 1745 }; 1746 1747 vdd_5v0_sys: regulator-vdd-5v0-sys { 1748 compatible = "regulator-fixed"; 1749 1750 regulator-name = "VDD_5V0_SYS"; 1751 regulator-min-microvolt = <5000000>; 1752 regulator-max-microvolt = <5000000>; 1753 regulator-always-on; 1754 regulator-boot-on; 1755 }; 1756 1757 vdd_3v3_sys: regulator-vdd-3v3-sys { 1758 compatible = "regulator-fixed"; 1759 1760 regulator-name = "VDD_3V3_SYS"; 1761 regulator-min-microvolt = <3300000>; 1762 regulator-max-microvolt = <3300000>; 1763 regulator-enable-ramp-delay = <240>; 1764 regulator-always-on; 1765 regulator-boot-on; 1766 1767 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; 1768 enable-active-high; 1769 1770 vin-supply = <&vdd_5v0_sys>; 1771 }; 1772 1773 vdd_3v3_sd: regulator-vdd-3v3-sd { 1774 compatible = "regulator-fixed"; 1775 1776 regulator-name = "VDD_3V3_SD"; 1777 regulator-min-microvolt = <3300000>; 1778 regulator-max-microvolt = <3300000>; 1779 1780 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; 1781 enable-active-high; 1782 1783 vin-supply = <&vdd_3v3_sys>; 1784 }; 1785 1786 vdd_hdmi: regulator-vdd-hdmi-5v0 { 1787 compatible = "regulator-fixed"; 1788 1789 regulator-name = "VDD_HDMI_5V0"; 1790 regulator-min-microvolt = <5000000>; 1791 regulator-max-microvolt = <5000000>; 1792 1793 vin-supply = <&vdd_5v0_sys>; 1794 }; 1795 1796 vdd_hub_3v3: regulator-vdd-hub-3v3 { 1797 compatible = "regulator-fixed"; 1798 1799 regulator-name = "VDD_HUB_3V3"; 1800 regulator-min-microvolt = <3300000>; 1801 regulator-max-microvolt = <3300000>; 1802 1803 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; 1804 enable-active-high; 1805 1806 vin-supply = <&vdd_5v0_sys>; 1807 }; 1808 1809 vdd_cpu: regulator-vdd-cpu { 1810 compatible = "regulator-fixed"; 1811 1812 regulator-name = "VDD_CPU"; 1813 regulator-min-microvolt = <5000000>; 1814 regulator-max-microvolt = <5000000>; 1815 regulator-always-on; 1816 regulator-boot-on; 1817 1818 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; 1819 enable-active-high; 1820 1821 vin-supply = <&vdd_5v0_sys>; 1822 }; 1823 1824 vdd_gpu: regulator-vdd-gpu { 1825 compatible = "pwm-regulator"; 1826 pwms = <&pwm 1 8000>; 1827 1828 regulator-name = "VDD_GPU"; 1829 regulator-min-microvolt = <710000>; 1830 regulator-max-microvolt = <1320000>; 1831 regulator-ramp-delay = <80>; 1832 regulator-enable-ramp-delay = <2000>; 1833 regulator-settling-time-us = <160>; 1834 1835 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; 1836 vin-supply = <&vdd_5v0_sys>; 1837 }; 1838 1839 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { 1840 compatible = "regulator-fixed"; 1841 1842 regulator-name = "AVDD_IO_EDP_1V05"; 1843 regulator-min-microvolt = <1050000>; 1844 regulator-max-microvolt = <1050000>; 1845 1846 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 1847 enable-active-high; 1848 1849 vin-supply = <&avdd_1v05_pll>; 1850 }; 1851 1852 vdd_5v0_usb: regulator-vdd-5v-usb { 1853 compatible = "regulator-fixed"; 1854 1855 regulator-name = "VDD_5V_USB"; 1856 regulator-min-microvolt = <50000000>; 1857 regulator-max-microvolt = <50000000>; 1858 1859 vin-supply = <&vdd_5v0_sys>; 1860 }; 1861 1862 sound { 1863 compatible = "nvidia,tegra210-audio-graph-card"; 1864 status = "okay"; 1865 1866 dais = /* FE */ 1867 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 1868 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, 1869 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, 1870 <&admaif10_port>, 1871 /* Router */ 1872 <&xbar_i2s3_port>, <&xbar_i2s4_port>, 1873 <&xbar_dmic1_port>, <&xbar_dmic2_port>, 1874 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 1875 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 1876 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 1877 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 1878 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 1879 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 1880 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 1881 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 1882 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 1883 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 1884 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 1885 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 1886 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 1887 /* HW accelerators */ 1888 <&sfc1_out_port>, <&sfc2_out_port>, 1889 <&sfc3_out_port>, <&sfc4_out_port>, 1890 <&mvc1_out_port>, <&mvc2_out_port>, 1891 <&amx1_out_port>, <&amx2_out_port>, 1892 <&adx1_out1_port>, <&adx1_out2_port>, 1893 <&adx1_out3_port>, <&adx1_out4_port>, 1894 <&adx2_out1_port>, <&adx2_out2_port>, 1895 <&adx2_out3_port>, <&adx2_out4_port>, 1896 <&mixer_out1_port>, <&mixer_out2_port>, 1897 <&mixer_out3_port>, <&mixer_out4_port>, 1898 <&mixer_out5_port>, 1899 /* I/O DAP Ports */ 1900 <&i2s3_port>, <&i2s4_port>, 1901 <&dmic1_port>, <&dmic2_port>; 1902 1903 label = "NVIDIA Jetson Nano APE"; 1904 }; 1905}; 1906