1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/gpio-keys.h> 5#include <dt-bindings/input/linux-event-codes.h> 6#include <dt-bindings/mfd/max77620.h> 7 8#include "tegra210.dtsi" 9 10/ { 11 model = "NVIDIA Jetson Nano Developer Kit"; 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210"; 13 14 aliases { 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; 16 rtc0 = "/i2c@7000d000/pmic@3c"; 17 rtc1 = "/rtc@7000e000"; 18 serial0 = &uarta; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 reg = <0x0 0x80000000 0x1 0x0>; 28 }; 29 30 pcie@1003000 { 31 status = "okay"; 32 33 hvddio-pex-supply = <&vdd_1v8>; 34 dvddio-pex-supply = <&vdd_pex_1v05>; 35 vddio-pex-ctl-supply = <&vdd_1v8>; 36 37 pci@1,0 { 38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 39 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 40 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, 41 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 42 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 43 nvidia,num-lanes = <4>; 44 status = "okay"; 45 }; 46 47 pci@2,0 { 48 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 49 phy-names = "pcie-0"; 50 status = "okay"; 51 52 ethernet@0,0 { 53 reg = <0x000000 0 0 0 0>; 54 local-mac-address = [ 00 00 00 00 00 00 ]; 55 }; 56 }; 57 }; 58 59 host1x@50000000 { 60 dpaux@54040000 { 61 status = "okay"; 62 }; 63 64 vi@54080000 { 65 status = "okay"; 66 67 avdd-dsi-csi-supply = <&vdd_sys_1v2>; 68 69 csi@838 { 70 status = "okay"; 71 }; 72 }; 73 74 sor@54540000 { 75 status = "okay"; 76 77 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; 78 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 79 80 nvidia,xbar-cfg = <2 1 0 3 4>; 81 nvidia,dpaux = <&dpaux>; 82 }; 83 84 sor@54580000 { 85 status = "okay"; 86 87 avdd-io-hdmi-dp-supply = <&avdd_1v05>; 88 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 89 hdmi-supply = <&vdd_hdmi>; 90 91 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 92 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 93 GPIO_ACTIVE_LOW>; 94 nvidia,xbar-cfg = <0 1 2 3 4>; 95 }; 96 97 dpaux@545c0000 { 98 status = "okay"; 99 }; 100 101 i2c@546c0000 { 102 status = "okay"; 103 }; 104 }; 105 106 gpu@57000000 { 107 vdd-supply = <&vdd_gpu>; 108 status = "okay"; 109 }; 110 111 pinmux@700008d4 { 112 dvfs_pwm_active_state: pinmux-dvfs-pwm-active { 113 dvfs_pwm_pbb1 { 114 nvidia,pins = "dvfs_pwm_pbb1"; 115 nvidia,tristate = <TEGRA_PIN_DISABLE>; 116 }; 117 }; 118 119 dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { 120 dvfs_pwm_pbb1 { 121 nvidia,pins = "dvfs_pwm_pbb1"; 122 nvidia,tristate = <TEGRA_PIN_ENABLE>; 123 }; 124 }; 125 }; 126 127 /* debug port */ 128 serial@70006000 { 129 /delete-property/ dmas; 130 /delete-property/ dma-names; 131 status = "okay"; 132 }; 133 134 pwm@7000a000 { 135 status = "okay"; 136 }; 137 138 i2c@7000c500 { 139 status = "okay"; 140 clock-frequency = <100000>; 141 142 eeprom@50 { 143 compatible = "atmel,24c02"; 144 reg = <0x50>; 145 146 label = "module"; 147 vcc-supply = <&vdd_1v8>; 148 address-width = <8>; 149 pagesize = <8>; 150 size = <256>; 151 read-only; 152 }; 153 154 eeprom@57 { 155 compatible = "atmel,24c02"; 156 reg = <0x57>; 157 158 label = "system"; 159 vcc-supply = <&vdd_1v8>; 160 address-width = <8>; 161 pagesize = <8>; 162 size = <256>; 163 read-only; 164 }; 165 }; 166 167 hdmi_ddc: i2c@7000c700 { 168 status = "okay"; 169 clock-frequency = <100000>; 170 }; 171 172 i2c@7000d000 { 173 status = "okay"; 174 clock-frequency = <400000>; 175 176 pmic: pmic@3c { 177 compatible = "maxim,max77620"; 178 reg = <0x3c>; 179 interrupt-parent = <&tegra_pmc>; 180 interrupts = <51 IRQ_TYPE_LEVEL_LOW>; 181 182 #interrupt-cells = <2>; 183 interrupt-controller; 184 185 #gpio-cells = <2>; 186 gpio-controller; 187 188 pinctrl-names = "default"; 189 pinctrl-0 = <&max77620_default>; 190 191 fps { 192 fps0 { 193 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 194 maxim,suspend-fps-time-period-us = <5120>; 195 }; 196 197 fps1 { 198 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 199 maxim,suspend-fps-time-period-us = <5120>; 200 }; 201 202 fps2 { 203 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 204 }; 205 }; 206 207 max77620_default: pinmux { 208 gpio0 { 209 pins = "gpio0"; 210 function = "gpio"; 211 }; 212 213 gpio1 { 214 pins = "gpio1"; 215 function = "fps-out"; 216 drive-push-pull = <1>; 217 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 218 maxim,active-fps-power-up-slot = <0>; 219 maxim,active-fps-power-down-slot = <7>; 220 }; 221 222 gpio2 { 223 pins = "gpio2"; 224 function = "fps-out"; 225 drive-open-drain = <1>; 226 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 227 maxim,active-fps-power-up-slot = <0>; 228 maxim,active-fps-power-down-slot = <7>; 229 }; 230 231 gpio3 { 232 pins = "gpio3"; 233 function = "fps-out"; 234 drive-open-drain = <1>; 235 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 236 maxim,active-fps-power-up-slot = <4>; 237 maxim,active-fps-power-down-slot = <3>; 238 }; 239 240 gpio4 { 241 pins = "gpio4"; 242 function = "32k-out1"; 243 }; 244 245 gpio5_6_7 { 246 pins = "gpio5", "gpio6", "gpio7"; 247 function = "gpio"; 248 drive-push-pull = <1>; 249 }; 250 }; 251 252 regulators { 253 in-ldo0-1-supply = <&vdd_pre>; 254 in-ldo2-supply = <&vdd_3v3_sys>; 255 in-ldo3-5-supply = <&vdd_1v8>; 256 in-ldo4-6-supply = <&vdd_5v0_sys>; 257 in-ldo7-8-supply = <&vdd_pre>; 258 in-sd0-supply = <&vdd_5v0_sys>; 259 in-sd1-supply = <&vdd_5v0_sys>; 260 in-sd2-supply = <&vdd_5v0_sys>; 261 in-sd3-supply = <&vdd_5v0_sys>; 262 263 vdd_soc: sd0 { 264 regulator-name = "VDD_SOC"; 265 regulator-min-microvolt = <1000000>; 266 regulator-max-microvolt = <1170000>; 267 regulator-enable-ramp-delay = <146>; 268 regulator-ramp-delay = <27500>; 269 regulator-ramp-delay-scale = <300>; 270 regulator-always-on; 271 regulator-boot-on; 272 273 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 274 maxim,active-fps-power-up-slot = <1>; 275 maxim,active-fps-power-down-slot = <6>; 276 }; 277 278 vdd_ddr: sd1 { 279 regulator-name = "VDD_DDR_1V1_PMIC"; 280 regulator-min-microvolt = <1150000>; 281 regulator-max-microvolt = <1150000>; 282 regulator-enable-ramp-delay = <176>; 283 regulator-ramp-delay = <27500>; 284 regulator-ramp-delay-scale = <300>; 285 regulator-always-on; 286 regulator-boot-on; 287 288 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 289 maxim,active-fps-power-up-slot = <5>; 290 maxim,active-fps-power-down-slot = <2>; 291 }; 292 293 vdd_pre: sd2 { 294 regulator-name = "VDD_PRE_REG_1V35"; 295 regulator-min-microvolt = <1350000>; 296 regulator-max-microvolt = <1350000>; 297 regulator-enable-ramp-delay = <176>; 298 regulator-ramp-delay = <27500>; 299 regulator-ramp-delay-scale = <350>; 300 regulator-always-on; 301 regulator-boot-on; 302 303 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 304 maxim,active-fps-power-up-slot = <2>; 305 maxim,active-fps-power-down-slot = <5>; 306 }; 307 308 vdd_1v8: sd3 { 309 regulator-name = "VDD_1V8"; 310 regulator-min-microvolt = <1800000>; 311 regulator-max-microvolt = <1800000>; 312 regulator-enable-ramp-delay = <242>; 313 regulator-ramp-delay = <27500>; 314 regulator-ramp-delay-scale = <360>; 315 regulator-always-on; 316 regulator-boot-on; 317 318 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 319 maxim,active-fps-power-up-slot = <3>; 320 maxim,active-fps-power-down-slot = <4>; 321 }; 322 323 vdd_sys_1v2: ldo0 { 324 regulator-name = "AVDD_SYS_1V2"; 325 regulator-min-microvolt = <1200000>; 326 regulator-max-microvolt = <1200000>; 327 regulator-enable-ramp-delay = <26>; 328 regulator-ramp-delay = <100000>; 329 regulator-ramp-delay-scale = <200>; 330 regulator-always-on; 331 regulator-boot-on; 332 333 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 334 maxim,active-fps-power-up-slot = <0>; 335 maxim,active-fps-power-down-slot = <7>; 336 }; 337 338 vdd_pex_1v05: ldo1 { 339 regulator-name = "VDD_PEX_1V05"; 340 regulator-min-microvolt = <1050000>; 341 regulator-max-microvolt = <1050000>; 342 regulator-enable-ramp-delay = <22>; 343 regulator-ramp-delay = <100000>; 344 regulator-ramp-delay-scale = <200>; 345 346 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 347 maxim,active-fps-power-up-slot = <0>; 348 maxim,active-fps-power-down-slot = <7>; 349 }; 350 351 vddio_sdmmc: ldo2 { 352 regulator-name = "VDDIO_SDMMC"; 353 regulator-min-microvolt = <1800000>; 354 regulator-max-microvolt = <3300000>; 355 regulator-enable-ramp-delay = <62>; 356 regulator-ramp-delay = <100000>; 357 regulator-ramp-delay-scale = <200>; 358 359 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 360 maxim,active-fps-power-up-slot = <0>; 361 maxim,active-fps-power-down-slot = <7>; 362 }; 363 364 ldo3 { 365 status = "disabled"; 366 }; 367 368 vdd_rtc: ldo4 { 369 regulator-name = "VDD_RTC"; 370 regulator-min-microvolt = <850000>; 371 regulator-max-microvolt = <1100000>; 372 regulator-enable-ramp-delay = <22>; 373 regulator-ramp-delay = <100000>; 374 regulator-ramp-delay-scale = <200>; 375 regulator-disable-active-discharge; 376 regulator-always-on; 377 regulator-boot-on; 378 379 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 380 maxim,active-fps-power-up-slot = <1>; 381 maxim,active-fps-power-down-slot = <6>; 382 }; 383 384 ldo5 { 385 status = "disabled"; 386 }; 387 388 ldo6 { 389 status = "disabled"; 390 }; 391 392 avdd_1v05_pll: ldo7 { 393 regulator-name = "AVDD_1V05_PLL"; 394 regulator-min-microvolt = <1050000>; 395 regulator-max-microvolt = <1050000>; 396 regulator-enable-ramp-delay = <24>; 397 regulator-ramp-delay = <100000>; 398 regulator-ramp-delay-scale = <200>; 399 400 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 401 maxim,active-fps-power-up-slot = <3>; 402 maxim,active-fps-power-down-slot = <4>; 403 }; 404 405 avdd_1v05: ldo8 { 406 regulator-name = "AVDD_SATA_HDMI_DP_1V05"; 407 regulator-min-microvolt = <1050000>; 408 regulator-max-microvolt = <1050000>; 409 regulator-enable-ramp-delay = <22>; 410 regulator-ramp-delay = <100000>; 411 regulator-ramp-delay-scale = <200>; 412 413 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 414 maxim,active-fps-power-up-slot = <6>; 415 maxim,active-fps-power-down-slot = <1>; 416 }; 417 }; 418 }; 419 }; 420 421 pmc@7000e400 { 422 nvidia,invert-interrupt; 423 nvidia,suspend-mode = <0>; 424 nvidia,cpu-pwr-good-time = <0>; 425 nvidia,cpu-pwr-off-time = <0>; 426 nvidia,core-pwr-good-time = <4587 3876>; 427 nvidia,core-pwr-off-time = <39065>; 428 nvidia,core-power-req-active-high; 429 nvidia,sys-clock-req-active-high; 430 }; 431 432 hda@70030000 { 433 nvidia,model = "NVIDIA Jetson Nano HDA"; 434 435 status = "okay"; 436 }; 437 438 usb@70090000 { 439 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 440 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 441 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 442 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; 443 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; 444 445 avdd-usb-supply = <&vdd_3v3_sys>; 446 dvddio-pex-supply = <&vdd_pex_1v05>; 447 hvddio-pex-supply = <&vdd_1v8>; 448 449 status = "okay"; 450 }; 451 452 padctl@7009f000 { 453 status = "okay"; 454 455 avdd-pll-utmip-supply = <&vdd_1v8>; 456 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 457 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 458 hvdd-pex-pll-e-supply = <&vdd_1v8>; 459 460 pads { 461 usb2 { 462 status = "okay"; 463 464 lanes { 465 micro_b: usb2-0 { 466 nvidia,function = "xusb"; 467 status = "okay"; 468 }; 469 470 usb2-1 { 471 nvidia,function = "xusb"; 472 status = "okay"; 473 }; 474 475 usb2-2 { 476 nvidia,function = "xusb"; 477 status = "okay"; 478 }; 479 }; 480 }; 481 482 pcie { 483 status = "okay"; 484 485 lanes { 486 pcie-0 { 487 nvidia,function = "pcie-x1"; 488 status = "okay"; 489 }; 490 491 pcie-1 { 492 nvidia,function = "pcie-x4"; 493 status = "okay"; 494 }; 495 496 pcie-2 { 497 nvidia,function = "pcie-x4"; 498 status = "okay"; 499 }; 500 501 pcie-3 { 502 nvidia,function = "pcie-x4"; 503 status = "okay"; 504 }; 505 506 pcie-4 { 507 nvidia,function = "pcie-x4"; 508 status = "okay"; 509 }; 510 511 pcie-5 { 512 nvidia,function = "usb3-ss"; 513 status = "okay"; 514 }; 515 516 pcie-6 { 517 nvidia,function = "usb3-ss"; 518 status = "okay"; 519 }; 520 }; 521 }; 522 }; 523 524 ports { 525 usb2-0 { 526 status = "okay"; 527 mode = "peripheral"; 528 usb-role-switch; 529 530 vbus-supply = <&vdd_5v0_usb>; 531 532 connector { 533 compatible = "gpio-usb-b-connector", 534 "usb-b-connector"; 535 label = "micro-USB"; 536 type = "micro"; 537 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) 538 GPIO_ACTIVE_LOW>; 539 }; 540 }; 541 542 usb2-1 { 543 status = "okay"; 544 mode = "host"; 545 }; 546 547 usb2-2 { 548 status = "okay"; 549 mode = "host"; 550 }; 551 552 usb3-0 { 553 status = "okay"; 554 nvidia,usb2-companion = <1>; 555 vbus-supply = <&vdd_hub_3v3>; 556 }; 557 }; 558 }; 559 560 mmc@700b0000 { 561 status = "okay"; 562 bus-width = <4>; 563 564 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 565 disable-wp; 566 567 vqmmc-supply = <&vddio_sdmmc>; 568 vmmc-supply = <&vdd_3v3_sd>; 569 }; 570 571 mmc@700b0400 { 572 status = "okay"; 573 bus-width = <4>; 574 575 vqmmc-supply = <&vdd_1v8>; 576 vmmc-supply = <&vdd_3v3_sys>; 577 578 non-removable; 579 cap-sdio-irq; 580 keep-power-in-suspend; 581 wakeup-source; 582 }; 583 584 usb@700d0000 { 585 status = "okay"; 586 phys = <µ_b>; 587 phy-names = "usb2-0"; 588 avddio-usb-supply = <&vdd_3v3_sys>; 589 hvdd-usb-supply = <&vdd_1v8>; 590 }; 591 592 clock@70110000 { 593 status = "okay"; 594 595 nvidia,cf = <6>; 596 nvidia,ci = <0>; 597 nvidia,cg = <2>; 598 nvidia,droop-ctrl = <0x00000f00>; 599 nvidia,force-mode = <1>; 600 nvidia,sample-rate = <25000>; 601 602 nvidia,pwm-min-microvolts = <708000>; 603 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 604 nvidia,pwm-to-pmic; 605 nvidia,pwm-tristate-microvolts = <1000000>; 606 nvidia,pwm-voltage-step-microvolts = <19200>; 607 608 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; 609 pinctrl-0 = <&dvfs_pwm_active_state>; 610 pinctrl-1 = <&dvfs_pwm_inactive_state>; 611 }; 612 613 aconnect@702c0000 { 614 status = "okay"; 615 616 ahub@702d0800 { 617 status = "okay"; 618 619 admaif@702d0000 { 620 status = "okay"; 621 }; 622 623 i2s@702d1200 { 624 status = "okay"; 625 626 ports { 627 #address-cells = <1>; 628 #size-cells = <0>; 629 630 port@0 { 631 reg = <0>; 632 633 i2s3_cif_ep: endpoint { 634 remote-endpoint = <&xbar_i2s3_ep>; 635 }; 636 }; 637 638 i2s3_port: port@1 { 639 reg = <1>; 640 641 i2s3_dap_ep: endpoint { 642 dai-format = "i2s"; 643 /* Placeholder for external Codec */ 644 }; 645 }; 646 }; 647 }; 648 649 i2s@702d1300 { 650 status = "okay"; 651 652 ports { 653 #address-cells = <1>; 654 #size-cells = <0>; 655 656 port@0 { 657 reg = <0>; 658 659 i2s4_cif_ep: endpoint { 660 remote-endpoint = <&xbar_i2s4_ep>; 661 }; 662 }; 663 664 i2s4_port: port@1 { 665 reg = <1>; 666 667 i2s4_dap_ep: endpoint { 668 dai-format = "i2s"; 669 /* Placeholder for external Codec */ 670 }; 671 }; 672 }; 673 }; 674 675 sfc@702d2000 { 676 status = "okay"; 677 678 ports { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 682 port@0 { 683 reg = <0>; 684 685 sfc1_cif_in_ep: endpoint { 686 remote-endpoint = <&xbar_sfc1_in_ep>; 687 }; 688 }; 689 690 sfc1_out_port: port@1 { 691 reg = <1>; 692 693 sfc1_cif_out_ep: endpoint { 694 remote-endpoint = <&xbar_sfc1_out_ep>; 695 }; 696 }; 697 }; 698 }; 699 700 sfc@702d2200 { 701 status = "okay"; 702 703 ports { 704 #address-cells = <1>; 705 #size-cells = <0>; 706 707 port@0 { 708 reg = <0>; 709 710 sfc2_cif_in_ep: endpoint { 711 remote-endpoint = <&xbar_sfc2_in_ep>; 712 }; 713 }; 714 715 sfc2_out_port: port@1 { 716 reg = <1>; 717 718 sfc2_cif_out_ep: endpoint { 719 remote-endpoint = <&xbar_sfc2_out_ep>; 720 }; 721 }; 722 }; 723 }; 724 725 sfc@702d2400 { 726 status = "okay"; 727 728 ports { 729 #address-cells = <1>; 730 #size-cells = <0>; 731 732 port@0 { 733 reg = <0>; 734 735 sfc3_cif_in_ep: endpoint { 736 remote-endpoint = <&xbar_sfc3_in_ep>; 737 }; 738 }; 739 740 sfc3_out_port: port@1 { 741 reg = <1>; 742 743 sfc3_cif_out_ep: endpoint { 744 remote-endpoint = <&xbar_sfc3_out_ep>; 745 }; 746 }; 747 }; 748 }; 749 750 sfc@702d2600 { 751 status = "okay"; 752 753 ports { 754 #address-cells = <1>; 755 #size-cells = <0>; 756 757 port@0 { 758 reg = <0>; 759 760 sfc4_cif_in_ep: endpoint { 761 remote-endpoint = <&xbar_sfc4_in_ep>; 762 }; 763 }; 764 765 sfc4_out_port: port@1 { 766 reg = <1>; 767 768 sfc4_cif_out_ep: endpoint { 769 remote-endpoint = <&xbar_sfc4_out_ep>; 770 }; 771 }; 772 }; 773 }; 774 775 amx@702d3000 { 776 status = "okay"; 777 778 ports { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 782 port@0 { 783 reg = <0>; 784 785 amx1_in1_ep: endpoint { 786 remote-endpoint = <&xbar_amx1_in1_ep>; 787 }; 788 }; 789 790 port@1 { 791 reg = <1>; 792 793 amx1_in2_ep: endpoint { 794 remote-endpoint = <&xbar_amx1_in2_ep>; 795 }; 796 }; 797 798 port@2 { 799 reg = <2>; 800 801 amx1_in3_ep: endpoint { 802 remote-endpoint = <&xbar_amx1_in3_ep>; 803 }; 804 }; 805 806 port@3 { 807 reg = <3>; 808 809 amx1_in4_ep: endpoint { 810 remote-endpoint = <&xbar_amx1_in4_ep>; 811 }; 812 }; 813 814 amx1_out_port: port@4 { 815 reg = <4>; 816 817 amx1_out_ep: endpoint { 818 remote-endpoint = <&xbar_amx1_out_ep>; 819 }; 820 }; 821 }; 822 }; 823 824 amx@702d3100 { 825 status = "okay"; 826 827 ports { 828 #address-cells = <1>; 829 #size-cells = <0>; 830 831 port@0 { 832 reg = <0>; 833 834 amx2_in1_ep: endpoint { 835 remote-endpoint = <&xbar_amx2_in1_ep>; 836 }; 837 }; 838 839 port@1 { 840 reg = <1>; 841 842 amx2_in2_ep: endpoint { 843 remote-endpoint = <&xbar_amx2_in2_ep>; 844 }; 845 }; 846 847 amx2_in3_port: port@2 { 848 reg = <2>; 849 850 amx2_in3_ep: endpoint { 851 remote-endpoint = <&xbar_amx2_in3_ep>; 852 }; 853 }; 854 855 amx2_in4_port: port@3 { 856 reg = <3>; 857 858 amx2_in4_ep: endpoint { 859 remote-endpoint = <&xbar_amx2_in4_ep>; 860 }; 861 }; 862 863 amx2_out_port: port@4 { 864 reg = <4>; 865 866 amx2_out_ep: endpoint { 867 remote-endpoint = <&xbar_amx2_out_ep>; 868 }; 869 }; 870 }; 871 }; 872 873 adx@702d3800 { 874 status = "okay"; 875 876 ports { 877 #address-cells = <1>; 878 #size-cells = <0>; 879 880 port@0 { 881 reg = <0>; 882 883 adx1_in_ep: endpoint { 884 remote-endpoint = <&xbar_adx1_in_ep>; 885 }; 886 }; 887 888 adx1_out1_port: port@1 { 889 reg = <1>; 890 891 adx1_out1_ep: endpoint { 892 remote-endpoint = <&xbar_adx1_out1_ep>; 893 }; 894 }; 895 896 adx1_out2_port: port@2 { 897 reg = <2>; 898 899 adx1_out2_ep: endpoint { 900 remote-endpoint = <&xbar_adx1_out2_ep>; 901 }; 902 }; 903 904 adx1_out3_port: port@3 { 905 reg = <3>; 906 907 adx1_out3_ep: endpoint { 908 remote-endpoint = <&xbar_adx1_out3_ep>; 909 }; 910 }; 911 912 adx1_out4_port: port@4 { 913 reg = <4>; 914 915 adx1_out4_ep: endpoint { 916 remote-endpoint = <&xbar_adx1_out4_ep>; 917 }; 918 }; 919 }; 920 }; 921 922 adx@702d3900 { 923 status = "okay"; 924 925 ports { 926 #address-cells = <1>; 927 #size-cells = <0>; 928 929 port@0 { 930 reg = <0>; 931 932 adx2_in_ep: endpoint { 933 remote-endpoint = <&xbar_adx2_in_ep>; 934 }; 935 }; 936 937 adx2_out1_port: port@1 { 938 reg = <1>; 939 940 adx2_out1_ep: endpoint { 941 remote-endpoint = <&xbar_adx2_out1_ep>; 942 }; 943 }; 944 945 adx2_out2_port: port@2 { 946 reg = <2>; 947 948 adx2_out2_ep: endpoint { 949 remote-endpoint = <&xbar_adx2_out2_ep>; 950 }; 951 }; 952 953 adx2_out3_port: port@3 { 954 reg = <3>; 955 956 adx2_out3_ep: endpoint { 957 remote-endpoint = <&xbar_adx2_out3_ep>; 958 }; 959 }; 960 961 adx2_out4_port: port@4 { 962 reg = <4>; 963 964 adx2_out4_ep: endpoint { 965 remote-endpoint = <&xbar_adx2_out4_ep>; 966 }; 967 }; 968 }; 969 }; 970 971 dmic@702d4000 { 972 status = "okay"; 973 974 ports { 975 #address-cells = <1>; 976 #size-cells = <0>; 977 978 port@0 { 979 reg = <0>; 980 981 dmic1_cif_ep: endpoint { 982 remote-endpoint = <&xbar_dmic1_ep>; 983 }; 984 }; 985 986 dmic1_port: port@1 { 987 reg = <1>; 988 989 dmic1_dap_ep: endpoint { 990 /* Placeholder for external Codec */ 991 }; 992 }; 993 }; 994 }; 995 996 dmic@702d4100 { 997 status = "okay"; 998 999 ports { 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 1003 port@0 { 1004 reg = <0>; 1005 1006 dmic2_cif_ep: endpoint { 1007 remote-endpoint = <&xbar_dmic2_ep>; 1008 }; 1009 }; 1010 1011 dmic2_port: port@1 { 1012 reg = <1>; 1013 1014 dmic2_dap_ep: endpoint { 1015 /* Placeholder for external Codec */ 1016 }; 1017 }; 1018 }; 1019 }; 1020 1021 processing-engine@702d8000 { 1022 status = "okay"; 1023 1024 ports { 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 1028 port@0 { 1029 reg = <0x0>; 1030 1031 ope1_cif_in_ep: endpoint { 1032 remote-endpoint = <&xbar_ope1_in_ep>; 1033 }; 1034 }; 1035 1036 ope1_out_port: port@1 { 1037 reg = <0x1>; 1038 1039 ope1_cif_out_ep: endpoint { 1040 remote-endpoint = <&xbar_ope1_out_ep>; 1041 }; 1042 }; 1043 }; 1044 }; 1045 1046 processing-engine@702d8400 { 1047 status = "okay"; 1048 1049 ports { 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 1053 port@0 { 1054 reg = <0x0>; 1055 1056 ope2_cif_in_ep: endpoint { 1057 remote-endpoint = <&xbar_ope2_in_ep>; 1058 }; 1059 }; 1060 1061 ope2_out_port: port@1 { 1062 reg = <0x1>; 1063 1064 ope2_cif_out_ep: endpoint { 1065 remote-endpoint = <&xbar_ope2_out_ep>; 1066 }; 1067 }; 1068 }; 1069 }; 1070 1071 mvc@702da000 { 1072 status = "okay"; 1073 1074 ports { 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 1078 port@0 { 1079 reg = <0>; 1080 1081 mvc1_cif_in_ep: endpoint { 1082 remote-endpoint = <&xbar_mvc1_in_ep>; 1083 }; 1084 }; 1085 1086 mvc1_out_port: port@1 { 1087 reg = <1>; 1088 1089 mvc1_cif_out_ep: endpoint { 1090 remote-endpoint = <&xbar_mvc1_out_ep>; 1091 }; 1092 }; 1093 }; 1094 }; 1095 1096 mvc@702da200 { 1097 status = "okay"; 1098 1099 ports { 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 1103 port@0 { 1104 reg = <0>; 1105 1106 mvc2_cif_in_ep: endpoint { 1107 remote-endpoint = <&xbar_mvc2_in_ep>; 1108 }; 1109 }; 1110 1111 mvc2_out_port: port@1 { 1112 reg = <1>; 1113 1114 mvc2_cif_out_ep: endpoint { 1115 remote-endpoint = <&xbar_mvc2_out_ep>; 1116 }; 1117 }; 1118 }; 1119 }; 1120 1121 amixer@702dbb00 { 1122 status = "okay"; 1123 1124 ports { 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 1128 port@0 { 1129 reg = <0x0>; 1130 1131 mixer_in1_ep: endpoint { 1132 remote-endpoint = <&xbar_mixer_in1_ep>; 1133 }; 1134 }; 1135 1136 port@1 { 1137 reg = <0x1>; 1138 1139 mixer_in2_ep: endpoint { 1140 remote-endpoint = <&xbar_mixer_in2_ep>; 1141 }; 1142 }; 1143 1144 port@2 { 1145 reg = <0x2>; 1146 1147 mixer_in3_ep: endpoint { 1148 remote-endpoint = <&xbar_mixer_in3_ep>; 1149 }; 1150 }; 1151 1152 port@3 { 1153 reg = <0x3>; 1154 1155 mixer_in4_ep: endpoint { 1156 remote-endpoint = <&xbar_mixer_in4_ep>; 1157 }; 1158 }; 1159 1160 port@4 { 1161 reg = <0x4>; 1162 1163 mixer_in5_ep: endpoint { 1164 remote-endpoint = <&xbar_mixer_in5_ep>; 1165 }; 1166 }; 1167 1168 port@5 { 1169 reg = <0x5>; 1170 1171 mixer_in6_ep: endpoint { 1172 remote-endpoint = <&xbar_mixer_in6_ep>; 1173 }; 1174 }; 1175 1176 port@6 { 1177 reg = <0x6>; 1178 1179 mixer_in7_ep: endpoint { 1180 remote-endpoint = <&xbar_mixer_in7_ep>; 1181 }; 1182 }; 1183 1184 port@7 { 1185 reg = <0x7>; 1186 1187 mixer_in8_ep: endpoint { 1188 remote-endpoint = <&xbar_mixer_in8_ep>; 1189 }; 1190 }; 1191 1192 port@8 { 1193 reg = <0x8>; 1194 1195 mixer_in9_ep: endpoint { 1196 remote-endpoint = <&xbar_mixer_in9_ep>; 1197 }; 1198 }; 1199 1200 port@9 { 1201 reg = <0x9>; 1202 1203 mixer_in10_ep: endpoint { 1204 remote-endpoint = <&xbar_mixer_in10_ep>; 1205 }; 1206 }; 1207 1208 mixer_out1_port: port@a { 1209 reg = <0xa>; 1210 1211 mixer_out1_ep: endpoint { 1212 remote-endpoint = <&xbar_mixer_out1_ep>; 1213 }; 1214 }; 1215 1216 mixer_out2_port: port@b { 1217 reg = <0xb>; 1218 1219 mixer_out2_ep: endpoint { 1220 remote-endpoint = <&xbar_mixer_out2_ep>; 1221 }; 1222 }; 1223 1224 mixer_out3_port: port@c { 1225 reg = <0xc>; 1226 1227 mixer_out3_ep: endpoint { 1228 remote-endpoint = <&xbar_mixer_out3_ep>; 1229 }; 1230 }; 1231 1232 mixer_out4_port: port@d { 1233 reg = <0xd>; 1234 1235 mixer_out4_ep: endpoint { 1236 remote-endpoint = <&xbar_mixer_out4_ep>; 1237 }; 1238 }; 1239 1240 mixer_out5_port: port@e { 1241 reg = <0xe>; 1242 1243 mixer_out5_ep: endpoint { 1244 remote-endpoint = <&xbar_mixer_out5_ep>; 1245 }; 1246 }; 1247 }; 1248 }; 1249 1250 ports { 1251 xbar_i2s3_port: port@c { 1252 reg = <0xc>; 1253 1254 xbar_i2s3_ep: endpoint { 1255 remote-endpoint = <&i2s3_cif_ep>; 1256 }; 1257 }; 1258 1259 xbar_i2s4_port: port@d { 1260 reg = <0xd>; 1261 1262 xbar_i2s4_ep: endpoint { 1263 remote-endpoint = <&i2s4_cif_ep>; 1264 }; 1265 }; 1266 1267 xbar_dmic1_port: port@f { 1268 reg = <0xf>; 1269 1270 xbar_dmic1_ep: endpoint { 1271 remote-endpoint = <&dmic1_cif_ep>; 1272 }; 1273 }; 1274 1275 xbar_dmic2_port: port@10 { 1276 reg = <0x10>; 1277 1278 xbar_dmic2_ep: endpoint { 1279 remote-endpoint = <&dmic2_cif_ep>; 1280 }; 1281 }; 1282 1283 xbar_sfc1_in_port: port@12 { 1284 reg = <0x12>; 1285 1286 xbar_sfc1_in_ep: endpoint { 1287 remote-endpoint = <&sfc1_cif_in_ep>; 1288 }; 1289 }; 1290 1291 port@13 { 1292 reg = <0x13>; 1293 1294 xbar_sfc1_out_ep: endpoint { 1295 remote-endpoint = <&sfc1_cif_out_ep>; 1296 }; 1297 }; 1298 1299 xbar_sfc2_in_port: port@14 { 1300 reg = <0x14>; 1301 1302 xbar_sfc2_in_ep: endpoint { 1303 remote-endpoint = <&sfc2_cif_in_ep>; 1304 }; 1305 }; 1306 1307 port@15 { 1308 reg = <0x15>; 1309 1310 xbar_sfc2_out_ep: endpoint { 1311 remote-endpoint = <&sfc2_cif_out_ep>; 1312 }; 1313 }; 1314 1315 xbar_sfc3_in_port: port@16 { 1316 reg = <0x16>; 1317 1318 xbar_sfc3_in_ep: endpoint { 1319 remote-endpoint = <&sfc3_cif_in_ep>; 1320 }; 1321 }; 1322 1323 port@17 { 1324 reg = <0x17>; 1325 1326 xbar_sfc3_out_ep: endpoint { 1327 remote-endpoint = <&sfc3_cif_out_ep>; 1328 }; 1329 }; 1330 1331 xbar_sfc4_in_port: port@18 { 1332 reg = <0x18>; 1333 1334 xbar_sfc4_in_ep: endpoint { 1335 remote-endpoint = <&sfc4_cif_in_ep>; 1336 }; 1337 }; 1338 1339 port@19 { 1340 reg = <0x19>; 1341 1342 xbar_sfc4_out_ep: endpoint { 1343 remote-endpoint = <&sfc4_cif_out_ep>; 1344 }; 1345 }; 1346 1347 xbar_mvc1_in_port: port@1a { 1348 reg = <0x1a>; 1349 1350 xbar_mvc1_in_ep: endpoint { 1351 remote-endpoint = <&mvc1_cif_in_ep>; 1352 }; 1353 }; 1354 1355 port@1b { 1356 reg = <0x1b>; 1357 1358 xbar_mvc1_out_ep: endpoint { 1359 remote-endpoint = <&mvc1_cif_out_ep>; 1360 }; 1361 }; 1362 1363 xbar_mvc2_in_port: port@1c { 1364 reg = <0x1c>; 1365 1366 xbar_mvc2_in_ep: endpoint { 1367 remote-endpoint = <&mvc2_cif_in_ep>; 1368 }; 1369 }; 1370 1371 port@1d { 1372 reg = <0x1d>; 1373 1374 xbar_mvc2_out_ep: endpoint { 1375 remote-endpoint = <&mvc2_cif_out_ep>; 1376 }; 1377 }; 1378 1379 xbar_amx1_in1_port: port@1e { 1380 reg = <0x1e>; 1381 1382 xbar_amx1_in1_ep: endpoint { 1383 remote-endpoint = <&amx1_in1_ep>; 1384 }; 1385 }; 1386 1387 xbar_amx1_in2_port: port@1f { 1388 reg = <0x1f>; 1389 1390 xbar_amx1_in2_ep: endpoint { 1391 remote-endpoint = <&amx1_in2_ep>; 1392 }; 1393 }; 1394 1395 xbar_amx1_in3_port: port@20 { 1396 reg = <0x20>; 1397 1398 xbar_amx1_in3_ep: endpoint { 1399 remote-endpoint = <&amx1_in3_ep>; 1400 }; 1401 }; 1402 1403 xbar_amx1_in4_port: port@21 { 1404 reg = <0x21>; 1405 1406 xbar_amx1_in4_ep: endpoint { 1407 remote-endpoint = <&amx1_in4_ep>; 1408 }; 1409 }; 1410 1411 port@22 { 1412 reg = <0x22>; 1413 1414 xbar_amx1_out_ep: endpoint { 1415 remote-endpoint = <&amx1_out_ep>; 1416 }; 1417 }; 1418 1419 xbar_amx2_in1_port: port@23 { 1420 reg = <0x23>; 1421 1422 xbar_amx2_in1_ep: endpoint { 1423 remote-endpoint = <&amx2_in1_ep>; 1424 }; 1425 }; 1426 1427 xbar_amx2_in2_port: port@24 { 1428 reg = <0x24>; 1429 1430 xbar_amx2_in2_ep: endpoint { 1431 remote-endpoint = <&amx2_in2_ep>; 1432 }; 1433 }; 1434 1435 xbar_amx2_in3_port: port@25 { 1436 reg = <0x25>; 1437 1438 xbar_amx2_in3_ep: endpoint { 1439 remote-endpoint = <&amx2_in3_ep>; 1440 }; 1441 }; 1442 1443 xbar_amx2_in4_port: port@26 { 1444 reg = <0x26>; 1445 1446 xbar_amx2_in4_ep: endpoint { 1447 remote-endpoint = <&amx2_in4_ep>; 1448 }; 1449 }; 1450 1451 port@27 { 1452 reg = <0x27>; 1453 1454 xbar_amx2_out_ep: endpoint { 1455 remote-endpoint = <&amx2_out_ep>; 1456 }; 1457 }; 1458 1459 xbar_adx1_in_port: port@28 { 1460 reg = <0x28>; 1461 1462 xbar_adx1_in_ep: endpoint { 1463 remote-endpoint = <&adx1_in_ep>; 1464 }; 1465 }; 1466 1467 port@29 { 1468 reg = <0x29>; 1469 1470 xbar_adx1_out1_ep: endpoint { 1471 remote-endpoint = <&adx1_out1_ep>; 1472 }; 1473 }; 1474 1475 port@2a { 1476 reg = <0x2a>; 1477 1478 xbar_adx1_out2_ep: endpoint { 1479 remote-endpoint = <&adx1_out2_ep>; 1480 }; 1481 }; 1482 1483 port@2b { 1484 reg = <0x2b>; 1485 1486 xbar_adx1_out3_ep: endpoint { 1487 remote-endpoint = <&adx1_out3_ep>; 1488 }; 1489 }; 1490 1491 port@2c { 1492 reg = <0x2c>; 1493 1494 xbar_adx1_out4_ep: endpoint { 1495 remote-endpoint = <&adx1_out4_ep>; 1496 }; 1497 }; 1498 1499 xbar_adx2_in_port: port@2d { 1500 reg = <0x2d>; 1501 1502 xbar_adx2_in_ep: endpoint { 1503 remote-endpoint = <&adx2_in_ep>; 1504 }; 1505 }; 1506 1507 port@2e { 1508 reg = <0x2e>; 1509 1510 xbar_adx2_out1_ep: endpoint { 1511 remote-endpoint = <&adx2_out1_ep>; 1512 }; 1513 }; 1514 1515 port@2f { 1516 reg = <0x2f>; 1517 1518 xbar_adx2_out2_ep: endpoint { 1519 remote-endpoint = <&adx2_out2_ep>; 1520 }; 1521 }; 1522 1523 port@30 { 1524 reg = <0x30>; 1525 1526 xbar_adx2_out3_ep: endpoint { 1527 remote-endpoint = <&adx2_out3_ep>; 1528 }; 1529 }; 1530 1531 port@31 { 1532 reg = <0x31>; 1533 1534 xbar_adx2_out4_ep: endpoint { 1535 remote-endpoint = <&adx2_out4_ep>; 1536 }; 1537 }; 1538 1539 xbar_mixer_in1_port: port@32 { 1540 reg = <0x32>; 1541 1542 xbar_mixer_in1_ep: endpoint { 1543 remote-endpoint = <&mixer_in1_ep>; 1544 }; 1545 }; 1546 1547 xbar_mixer_in2_port: port@33 { 1548 reg = <0x33>; 1549 1550 xbar_mixer_in2_ep: endpoint { 1551 remote-endpoint = <&mixer_in2_ep>; 1552 }; 1553 }; 1554 1555 xbar_mixer_in3_port: port@34 { 1556 reg = <0x34>; 1557 1558 xbar_mixer_in3_ep: endpoint { 1559 remote-endpoint = <&mixer_in3_ep>; 1560 }; 1561 }; 1562 1563 xbar_mixer_in4_port: port@35 { 1564 reg = <0x35>; 1565 1566 xbar_mixer_in4_ep: endpoint { 1567 remote-endpoint = <&mixer_in4_ep>; 1568 }; 1569 }; 1570 1571 xbar_mixer_in5_port: port@36 { 1572 reg = <0x36>; 1573 1574 xbar_mixer_in5_ep: endpoint { 1575 remote-endpoint = <&mixer_in5_ep>; 1576 }; 1577 }; 1578 1579 xbar_mixer_in6_port: port@37 { 1580 reg = <0x37>; 1581 1582 xbar_mixer_in6_ep: endpoint { 1583 remote-endpoint = <&mixer_in6_ep>; 1584 }; 1585 }; 1586 1587 xbar_mixer_in7_port: port@38 { 1588 reg = <0x38>; 1589 1590 xbar_mixer_in7_ep: endpoint { 1591 remote-endpoint = <&mixer_in7_ep>; 1592 }; 1593 }; 1594 1595 xbar_mixer_in8_port: port@39 { 1596 reg = <0x39>; 1597 1598 xbar_mixer_in8_ep: endpoint { 1599 remote-endpoint = <&mixer_in8_ep>; 1600 }; 1601 }; 1602 1603 xbar_mixer_in9_port: port@3a { 1604 reg = <0x3a>; 1605 1606 xbar_mixer_in9_ep: endpoint { 1607 remote-endpoint = <&mixer_in9_ep>; 1608 }; 1609 }; 1610 1611 xbar_mixer_in10_port: port@3b { 1612 reg = <0x3b>; 1613 1614 xbar_mixer_in10_ep: endpoint { 1615 remote-endpoint = <&mixer_in10_ep>; 1616 }; 1617 }; 1618 1619 port@3c { 1620 reg = <0x3c>; 1621 1622 xbar_mixer_out1_ep: endpoint { 1623 remote-endpoint = <&mixer_out1_ep>; 1624 }; 1625 }; 1626 1627 port@3d { 1628 reg = <0x3d>; 1629 1630 xbar_mixer_out2_ep: endpoint { 1631 remote-endpoint = <&mixer_out2_ep>; 1632 }; 1633 }; 1634 1635 port@3e { 1636 reg = <0x3e>; 1637 1638 xbar_mixer_out3_ep: endpoint { 1639 remote-endpoint = <&mixer_out3_ep>; 1640 }; 1641 }; 1642 1643 port@3f { 1644 reg = <0x3f>; 1645 1646 xbar_mixer_out4_ep: endpoint { 1647 remote-endpoint = <&mixer_out4_ep>; 1648 }; 1649 }; 1650 1651 port@40 { 1652 reg = <0x40>; 1653 1654 xbar_mixer_out5_ep: endpoint { 1655 remote-endpoint = <&mixer_out5_ep>; 1656 }; 1657 }; 1658 1659 xbar_ope1_in_port: port@41 { 1660 reg = <0x41>; 1661 1662 xbar_ope1_in_ep: endpoint { 1663 remote-endpoint = <&ope1_cif_in_ep>; 1664 }; 1665 }; 1666 1667 port@42 { 1668 reg = <0x42>; 1669 1670 xbar_ope1_out_ep: endpoint { 1671 remote-endpoint = <&ope1_cif_out_ep>; 1672 }; 1673 }; 1674 1675 xbar_ope2_in_port: port@43 { 1676 reg = <0x43>; 1677 1678 xbar_ope2_in_ep: endpoint { 1679 remote-endpoint = <&ope2_cif_in_ep>; 1680 }; 1681 }; 1682 1683 port@44 { 1684 reg = <0x44>; 1685 1686 xbar_ope2_out_ep: endpoint { 1687 remote-endpoint = <&ope2_cif_out_ep>; 1688 }; 1689 }; 1690 }; 1691 }; 1692 1693 dma-controller@702e2000 { 1694 status = "okay"; 1695 }; 1696 1697 interrupt-controller@702f9000 { 1698 status = "okay"; 1699 }; 1700 }; 1701 1702 spi@70410000 { 1703 status = "okay"; 1704 1705 flash@0 { 1706 compatible = "jedec,spi-nor"; 1707 reg = <0>; 1708 spi-max-frequency = <104000000>; 1709 spi-tx-bus-width = <2>; 1710 spi-rx-bus-width = <2>; 1711 }; 1712 }; 1713 1714 clk32k_in: clock-32k { 1715 compatible = "fixed-clock"; 1716 clock-frequency = <32768>; 1717 #clock-cells = <0>; 1718 }; 1719 1720 cpus { 1721 cpu@0 { 1722 enable-method = "psci"; 1723 }; 1724 1725 cpu@1 { 1726 enable-method = "psci"; 1727 }; 1728 1729 cpu@2 { 1730 enable-method = "psci"; 1731 }; 1732 1733 cpu@3 { 1734 enable-method = "psci"; 1735 }; 1736 1737 idle-states { 1738 cpu-sleep { 1739 status = "okay"; 1740 }; 1741 }; 1742 }; 1743 1744 gpio-keys { 1745 compatible = "gpio-keys"; 1746 1747 key-force-recovery { 1748 label = "Force Recovery"; 1749 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 1750 linux,input-type = <EV_KEY>; 1751 linux,code = <BTN_1>; 1752 debounce-interval = <30>; 1753 }; 1754 1755 key-power { 1756 label = "Power"; 1757 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; 1758 linux,input-type = <EV_KEY>; 1759 linux,code = <KEY_POWER>; 1760 debounce-interval = <30>; 1761 wakeup-event-action = <EV_ACT_ASSERTED>; 1762 wakeup-source; 1763 }; 1764 }; 1765 1766 psci { 1767 compatible = "arm,psci-1.0"; 1768 method = "smc"; 1769 }; 1770 1771 fan: pwm-fan { 1772 compatible = "pwm-fan"; 1773 pwms = <&pwm 3 45334>; 1774 1775 cooling-levels = <0 64 128 255>; 1776 #cooling-cells = <2>; 1777 }; 1778 1779 vdd_5v0_sys: regulator-vdd-5v0-sys { 1780 compatible = "regulator-fixed"; 1781 1782 regulator-name = "VDD_5V0_SYS"; 1783 regulator-min-microvolt = <5000000>; 1784 regulator-max-microvolt = <5000000>; 1785 regulator-always-on; 1786 regulator-boot-on; 1787 }; 1788 1789 vdd_3v3_sys: regulator-vdd-3v3-sys { 1790 compatible = "regulator-fixed"; 1791 1792 regulator-name = "VDD_3V3_SYS"; 1793 regulator-min-microvolt = <3300000>; 1794 regulator-max-microvolt = <3300000>; 1795 regulator-enable-ramp-delay = <240>; 1796 regulator-always-on; 1797 regulator-boot-on; 1798 1799 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; 1800 enable-active-high; 1801 1802 vin-supply = <&vdd_5v0_sys>; 1803 }; 1804 1805 vdd_3v3_sd: regulator-vdd-3v3-sd { 1806 compatible = "regulator-fixed"; 1807 1808 regulator-name = "VDD_3V3_SD"; 1809 regulator-min-microvolt = <3300000>; 1810 regulator-max-microvolt = <3300000>; 1811 1812 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; 1813 enable-active-high; 1814 1815 vin-supply = <&vdd_3v3_sys>; 1816 }; 1817 1818 vdd_hdmi: regulator-vdd-hdmi-5v0 { 1819 compatible = "regulator-fixed"; 1820 1821 regulator-name = "VDD_HDMI_5V0"; 1822 regulator-min-microvolt = <5000000>; 1823 regulator-max-microvolt = <5000000>; 1824 1825 vin-supply = <&vdd_5v0_sys>; 1826 }; 1827 1828 vdd_hub_3v3: regulator-vdd-hub-3v3 { 1829 compatible = "regulator-fixed"; 1830 1831 regulator-name = "VDD_HUB_3V3"; 1832 regulator-min-microvolt = <3300000>; 1833 regulator-max-microvolt = <3300000>; 1834 1835 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; 1836 enable-active-high; 1837 1838 vin-supply = <&vdd_5v0_sys>; 1839 }; 1840 1841 vdd_cpu: regulator-vdd-cpu { 1842 compatible = "regulator-fixed"; 1843 1844 regulator-name = "VDD_CPU"; 1845 regulator-min-microvolt = <5000000>; 1846 regulator-max-microvolt = <5000000>; 1847 regulator-always-on; 1848 regulator-boot-on; 1849 1850 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; 1851 enable-active-high; 1852 1853 vin-supply = <&vdd_5v0_sys>; 1854 }; 1855 1856 vdd_gpu: regulator-vdd-gpu { 1857 compatible = "pwm-regulator"; 1858 pwms = <&pwm 1 8000>; 1859 1860 regulator-name = "VDD_GPU"; 1861 regulator-min-microvolt = <710000>; 1862 regulator-max-microvolt = <1320000>; 1863 regulator-ramp-delay = <80>; 1864 regulator-enable-ramp-delay = <2000>; 1865 regulator-settling-time-us = <160>; 1866 1867 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; 1868 vin-supply = <&vdd_5v0_sys>; 1869 }; 1870 1871 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { 1872 compatible = "regulator-fixed"; 1873 1874 regulator-name = "AVDD_IO_EDP_1V05"; 1875 regulator-min-microvolt = <1050000>; 1876 regulator-max-microvolt = <1050000>; 1877 1878 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 1879 enable-active-high; 1880 1881 vin-supply = <&avdd_1v05_pll>; 1882 }; 1883 1884 vdd_5v0_usb: regulator-vdd-5v-usb { 1885 compatible = "regulator-fixed"; 1886 1887 regulator-name = "VDD_5V_USB"; 1888 regulator-min-microvolt = <50000000>; 1889 regulator-max-microvolt = <50000000>; 1890 1891 vin-supply = <&vdd_5v0_sys>; 1892 }; 1893 1894 sound { 1895 compatible = "nvidia,tegra210-audio-graph-card"; 1896 status = "okay"; 1897 1898 dais = /* FE */ 1899 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 1900 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, 1901 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, 1902 <&admaif10_port>, 1903 /* Router */ 1904 <&xbar_i2s3_port>, <&xbar_i2s4_port>, 1905 <&xbar_dmic1_port>, <&xbar_dmic2_port>, 1906 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 1907 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 1908 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 1909 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 1910 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 1911 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 1912 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 1913 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 1914 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 1915 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 1916 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 1917 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 1918 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 1919 <&xbar_ope1_in_port>, <&xbar_ope2_in_port>, 1920 /* HW accelerators */ 1921 <&sfc1_out_port>, <&sfc2_out_port>, 1922 <&sfc3_out_port>, <&sfc4_out_port>, 1923 <&mvc1_out_port>, <&mvc2_out_port>, 1924 <&amx1_out_port>, <&amx2_out_port>, 1925 <&adx1_out1_port>, <&adx1_out2_port>, 1926 <&adx1_out3_port>, <&adx1_out4_port>, 1927 <&adx2_out1_port>, <&adx2_out2_port>, 1928 <&adx2_out3_port>, <&adx2_out4_port>, 1929 <&mixer_out1_port>, <&mixer_out2_port>, 1930 <&mixer_out3_port>, <&mixer_out4_port>, 1931 <&mixer_out5_port>, 1932 <&ope1_out_port>, <&ope2_out_port>, 1933 /* I/O DAP Ports */ 1934 <&i2s3_port>, <&i2s4_port>, 1935 <&dmic1_port>, <&dmic2_port>; 1936 1937 label = "NVIDIA Jetson Nano APE"; 1938 }; 1939 1940 thermal-zones { 1941 cpu-thermal { 1942 trips { 1943 cpu_trip_critical: critical { 1944 temperature = <96500>; 1945 hysteresis = <0>; 1946 type = "critical"; 1947 }; 1948 1949 cpu_trip_hot: hot { 1950 temperature = <70000>; 1951 hysteresis = <2000>; 1952 type = "hot"; 1953 }; 1954 1955 cpu_trip_active: active { 1956 temperature = <50000>; 1957 hysteresis = <2000>; 1958 type = "active"; 1959 }; 1960 1961 cpu_trip_passive: passive { 1962 temperature = <30000>; 1963 hysteresis = <2000>; 1964 type = "passive"; 1965 }; 1966 }; 1967 1968 cooling-maps { 1969 cpu-critical { 1970 cooling-device = <&fan 3 3>; 1971 trip = <&cpu_trip_critical>; 1972 }; 1973 1974 cpu-hot { 1975 cooling-device = <&fan 2 2>; 1976 trip = <&cpu_trip_hot>; 1977 }; 1978 1979 cpu-active { 1980 cooling-device = <&fan 1 1>; 1981 trip = <&cpu_trip_active>; 1982 }; 1983 1984 cpu-passive { 1985 cooling-device = <&fan 0 0>; 1986 trip = <&cpu_trip_passive>; 1987 }; 1988 }; 1989 }; 1990 }; 1991}; 1992