1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/input/gpio-keys.h> 5#include <dt-bindings/input/linux-event-codes.h> 6#include <dt-bindings/mfd/max77620.h> 7 8#include "tegra210.dtsi" 9 10/ { 11 model = "NVIDIA Jetson Nano Developer Kit"; 12 compatible = "nvidia,p3450-0000", "nvidia,tegra210"; 13 14 aliases { 15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; 16 rtc0 = "/i2c@7000d000/pmic@3c"; 17 rtc1 = "/rtc@7000e000"; 18 serial0 = &uarta; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 reg = <0x0 0x80000000 0x1 0x0>; 28 }; 29 30 pcie@1003000 { 31 status = "okay"; 32 33 hvddio-pex-supply = <&vdd_1v8>; 34 dvddio-pex-supply = <&vdd_pex_1v05>; 35 vddio-pex-ctl-supply = <&vdd_1v8>; 36 37 pci@1,0 { 38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 39 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 40 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, 41 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 42 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 43 nvidia,num-lanes = <4>; 44 status = "okay"; 45 }; 46 47 pci@2,0 { 48 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 49 phy-names = "pcie-0"; 50 status = "okay"; 51 52 ethernet@0,0 { 53 reg = <0x000000 0 0 0 0>; 54 local-mac-address = [ 00 00 00 00 00 00 ]; 55 }; 56 }; 57 }; 58 59 host1x@50000000 { 60 dpaux@54040000 { 61 status = "okay"; 62 }; 63 64 vi@54080000 { 65 status = "okay"; 66 67 avdd-dsi-csi-supply = <&vdd_sys_1v2>; 68 69 csi@838 { 70 status = "okay"; 71 }; 72 }; 73 74 sor@54540000 { 75 status = "okay"; 76 77 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; 78 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 79 80 nvidia,xbar-cfg = <2 1 0 3 4>; 81 nvidia,dpaux = <&dpaux>; 82 }; 83 84 sor@54580000 { 85 status = "okay"; 86 87 avdd-io-hdmi-dp-supply = <&avdd_1v05>; 88 vdd-hdmi-dp-pll-supply = <&vdd_1v8>; 89 hdmi-supply = <&vdd_hdmi>; 90 91 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 92 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 93 GPIO_ACTIVE_LOW>; 94 nvidia,xbar-cfg = <0 1 2 3 4>; 95 }; 96 97 dpaux@545c0000 { 98 status = "okay"; 99 }; 100 101 i2c@546c0000 { 102 status = "okay"; 103 }; 104 }; 105 106 gpu@57000000 { 107 vdd-supply = <&vdd_gpu>; 108 status = "okay"; 109 }; 110 111 pinmux@700008d4 { 112 dvfs_pwm_active_state: dvfs_pwm_active { 113 dvfs_pwm_pbb1 { 114 nvidia,pins = "dvfs_pwm_pbb1"; 115 nvidia,tristate = <TEGRA_PIN_DISABLE>; 116 }; 117 }; 118 119 dvfs_pwm_inactive_state: dvfs_pwm_inactive { 120 dvfs_pwm_pbb1 { 121 nvidia,pins = "dvfs_pwm_pbb1"; 122 nvidia,tristate = <TEGRA_PIN_ENABLE>; 123 }; 124 }; 125 }; 126 127 /* debug port */ 128 serial@70006000 { 129 status = "okay"; 130 }; 131 132 pwm@7000a000 { 133 status = "okay"; 134 }; 135 136 i2c@7000c500 { 137 status = "okay"; 138 clock-frequency = <100000>; 139 140 eeprom@50 { 141 compatible = "atmel,24c02"; 142 reg = <0x50>; 143 144 label = "module"; 145 vcc-supply = <&vdd_1v8>; 146 address-width = <8>; 147 pagesize = <8>; 148 size = <256>; 149 read-only; 150 }; 151 152 eeprom@57 { 153 compatible = "atmel,24c02"; 154 reg = <0x57>; 155 156 label = "system"; 157 vcc-supply = <&vdd_1v8>; 158 address-width = <8>; 159 pagesize = <8>; 160 size = <256>; 161 read-only; 162 }; 163 }; 164 165 hdmi_ddc: i2c@7000c700 { 166 status = "okay"; 167 clock-frequency = <100000>; 168 }; 169 170 i2c@7000d000 { 171 status = "okay"; 172 clock-frequency = <400000>; 173 174 pmic: pmic@3c { 175 compatible = "maxim,max77620"; 176 reg = <0x3c>; 177 interrupt-parent = <&tegra_pmc>; 178 interrupts = <51 IRQ_TYPE_LEVEL_LOW>; 179 180 #interrupt-cells = <2>; 181 interrupt-controller; 182 183 #gpio-cells = <2>; 184 gpio-controller; 185 186 pinctrl-names = "default"; 187 pinctrl-0 = <&max77620_default>; 188 189 max77620_default: pinmux { 190 gpio0 { 191 pins = "gpio0"; 192 function = "gpio"; 193 }; 194 195 gpio1 { 196 pins = "gpio1"; 197 function = "fps-out"; 198 drive-push-pull = <1>; 199 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 200 maxim,active-fps-power-up-slot = <0>; 201 maxim,active-fps-power-down-slot = <7>; 202 }; 203 204 gpio2 { 205 pins = "gpio2"; 206 function = "fps-out"; 207 drive-open-drain = <1>; 208 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 209 maxim,active-fps-power-up-slot = <0>; 210 maxim,active-fps-power-down-slot = <7>; 211 }; 212 213 gpio3 { 214 pins = "gpio3"; 215 function = "fps-out"; 216 drive-open-drain = <1>; 217 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 218 maxim,active-fps-power-up-slot = <4>; 219 maxim,active-fps-power-down-slot = <3>; 220 }; 221 222 gpio4 { 223 pins = "gpio4"; 224 function = "32k-out1"; 225 }; 226 227 gpio5_6_7 { 228 pins = "gpio5", "gpio6", "gpio7"; 229 function = "gpio"; 230 drive-push-pull = <1>; 231 }; 232 }; 233 234 fps { 235 fps0 { 236 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 237 maxim,suspend-fps-time-period-us = <5120>; 238 }; 239 240 fps1 { 241 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 242 maxim,suspend-fps-time-period-us = <5120>; 243 }; 244 245 fps2 { 246 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 247 }; 248 }; 249 250 regulators { 251 in-ldo0-1-supply = <&vdd_pre>; 252 in-ldo2-supply = <&vdd_3v3_sys>; 253 in-ldo3-5-supply = <&vdd_1v8>; 254 in-ldo4-6-supply = <&vdd_5v0_sys>; 255 in-ldo7-8-supply = <&vdd_pre>; 256 in-sd0-supply = <&vdd_5v0_sys>; 257 in-sd1-supply = <&vdd_5v0_sys>; 258 in-sd2-supply = <&vdd_5v0_sys>; 259 in-sd3-supply = <&vdd_5v0_sys>; 260 261 vdd_soc: sd0 { 262 regulator-name = "VDD_SOC"; 263 regulator-min-microvolt = <1000000>; 264 regulator-max-microvolt = <1170000>; 265 regulator-enable-ramp-delay = <146>; 266 regulator-ramp-delay = <27500>; 267 regulator-ramp-delay-scale = <300>; 268 regulator-always-on; 269 regulator-boot-on; 270 271 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 272 maxim,active-fps-power-up-slot = <1>; 273 maxim,active-fps-power-down-slot = <6>; 274 }; 275 276 vdd_ddr: sd1 { 277 regulator-name = "VDD_DDR_1V1_PMIC"; 278 regulator-min-microvolt = <1150000>; 279 regulator-max-microvolt = <1150000>; 280 regulator-enable-ramp-delay = <176>; 281 regulator-ramp-delay = <27500>; 282 regulator-ramp-delay-scale = <300>; 283 regulator-always-on; 284 regulator-boot-on; 285 286 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 287 maxim,active-fps-power-up-slot = <5>; 288 maxim,active-fps-power-down-slot = <2>; 289 }; 290 291 vdd_pre: sd2 { 292 regulator-name = "VDD_PRE_REG_1V35"; 293 regulator-min-microvolt = <1350000>; 294 regulator-max-microvolt = <1350000>; 295 regulator-enable-ramp-delay = <176>; 296 regulator-ramp-delay = <27500>; 297 regulator-ramp-delay-scale = <350>; 298 regulator-always-on; 299 regulator-boot-on; 300 301 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 302 maxim,active-fps-power-up-slot = <2>; 303 maxim,active-fps-power-down-slot = <5>; 304 }; 305 306 vdd_1v8: sd3 { 307 regulator-name = "VDD_1V8"; 308 regulator-min-microvolt = <1800000>; 309 regulator-max-microvolt = <1800000>; 310 regulator-enable-ramp-delay = <242>; 311 regulator-ramp-delay = <27500>; 312 regulator-ramp-delay-scale = <360>; 313 regulator-always-on; 314 regulator-boot-on; 315 316 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 317 maxim,active-fps-power-up-slot = <3>; 318 maxim,active-fps-power-down-slot = <4>; 319 }; 320 321 vdd_sys_1v2: ldo0 { 322 regulator-name = "AVDD_SYS_1V2"; 323 regulator-min-microvolt = <1200000>; 324 regulator-max-microvolt = <1200000>; 325 regulator-enable-ramp-delay = <26>; 326 regulator-ramp-delay = <100000>; 327 regulator-ramp-delay-scale = <200>; 328 regulator-always-on; 329 regulator-boot-on; 330 331 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 332 maxim,active-fps-power-up-slot = <0>; 333 maxim,active-fps-power-down-slot = <7>; 334 }; 335 336 vdd_pex_1v05: ldo1 { 337 regulator-name = "VDD_PEX_1V05"; 338 regulator-min-microvolt = <1050000>; 339 regulator-max-microvolt = <1050000>; 340 regulator-enable-ramp-delay = <22>; 341 regulator-ramp-delay = <100000>; 342 regulator-ramp-delay-scale = <200>; 343 344 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 345 maxim,active-fps-power-up-slot = <0>; 346 maxim,active-fps-power-down-slot = <7>; 347 }; 348 349 vddio_sdmmc: ldo2 { 350 regulator-name = "VDDIO_SDMMC"; 351 regulator-min-microvolt = <1800000>; 352 regulator-max-microvolt = <3300000>; 353 regulator-enable-ramp-delay = <62>; 354 regulator-ramp-delay = <100000>; 355 regulator-ramp-delay-scale = <200>; 356 357 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 358 maxim,active-fps-power-up-slot = <0>; 359 maxim,active-fps-power-down-slot = <7>; 360 }; 361 362 ldo3 { 363 status = "disabled"; 364 }; 365 366 vdd_rtc: ldo4 { 367 regulator-name = "VDD_RTC"; 368 regulator-min-microvolt = <850000>; 369 regulator-max-microvolt = <1100000>; 370 regulator-enable-ramp-delay = <22>; 371 regulator-ramp-delay = <100000>; 372 regulator-ramp-delay-scale = <200>; 373 regulator-disable-active-discharge; 374 regulator-always-on; 375 regulator-boot-on; 376 377 maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 378 maxim,active-fps-power-up-slot = <1>; 379 maxim,active-fps-power-down-slot = <6>; 380 }; 381 382 ldo5 { 383 status = "disabled"; 384 }; 385 386 ldo6 { 387 status = "disabled"; 388 }; 389 390 avdd_1v05_pll: ldo7 { 391 regulator-name = "AVDD_1V05_PLL"; 392 regulator-min-microvolt = <1050000>; 393 regulator-max-microvolt = <1050000>; 394 regulator-enable-ramp-delay = <24>; 395 regulator-ramp-delay = <100000>; 396 regulator-ramp-delay-scale = <200>; 397 398 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 399 maxim,active-fps-power-up-slot = <3>; 400 maxim,active-fps-power-down-slot = <4>; 401 }; 402 403 avdd_1v05: ldo8 { 404 regulator-name = "AVDD_SATA_HDMI_DP_1V05"; 405 regulator-min-microvolt = <1050000>; 406 regulator-max-microvolt = <1050000>; 407 regulator-enable-ramp-delay = <22>; 408 regulator-ramp-delay = <100000>; 409 regulator-ramp-delay-scale = <200>; 410 411 maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 412 maxim,active-fps-power-up-slot = <6>; 413 maxim,active-fps-power-down-slot = <1>; 414 }; 415 }; 416 }; 417 }; 418 419 pmc@7000e400 { 420 nvidia,invert-interrupt; 421 nvidia,suspend-mode = <0>; 422 nvidia,cpu-pwr-good-time = <0>; 423 nvidia,cpu-pwr-off-time = <0>; 424 nvidia,core-pwr-good-time = <4587 3876>; 425 nvidia,core-pwr-off-time = <39065>; 426 nvidia,core-power-req-active-high; 427 nvidia,sys-clock-req-active-high; 428 }; 429 430 hda@70030000 { 431 nvidia,model = "NVIDIA Jetson Nano HDA"; 432 433 status = "okay"; 434 }; 435 436 usb@70090000 { 437 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 438 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 439 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 440 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; 441 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; 442 443 avdd-usb-supply = <&vdd_3v3_sys>; 444 dvddio-pex-supply = <&vdd_pex_1v05>; 445 hvddio-pex-supply = <&vdd_1v8>; 446 447 status = "okay"; 448 }; 449 450 padctl@7009f000 { 451 status = "okay"; 452 453 avdd-pll-utmip-supply = <&vdd_1v8>; 454 avdd-pll-uerefe-supply = <&vdd_pex_1v05>; 455 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 456 hvdd-pex-pll-e-supply = <&vdd_1v8>; 457 458 pads { 459 usb2 { 460 status = "okay"; 461 462 lanes { 463 micro_b: usb2-0 { 464 nvidia,function = "xusb"; 465 status = "okay"; 466 }; 467 468 usb2-1 { 469 nvidia,function = "xusb"; 470 status = "okay"; 471 }; 472 473 usb2-2 { 474 nvidia,function = "xusb"; 475 status = "okay"; 476 }; 477 }; 478 }; 479 480 pcie { 481 status = "okay"; 482 483 lanes { 484 pcie-0 { 485 nvidia,function = "pcie-x1"; 486 status = "okay"; 487 }; 488 489 pcie-1 { 490 nvidia,function = "pcie-x4"; 491 status = "okay"; 492 }; 493 494 pcie-2 { 495 nvidia,function = "pcie-x4"; 496 status = "okay"; 497 }; 498 499 pcie-3 { 500 nvidia,function = "pcie-x4"; 501 status = "okay"; 502 }; 503 504 pcie-4 { 505 nvidia,function = "pcie-x4"; 506 status = "okay"; 507 }; 508 509 pcie-5 { 510 nvidia,function = "usb3-ss"; 511 status = "okay"; 512 }; 513 514 pcie-6 { 515 nvidia,function = "usb3-ss"; 516 status = "okay"; 517 }; 518 }; 519 }; 520 }; 521 522 ports { 523 usb2-0 { 524 status = "okay"; 525 mode = "peripheral"; 526 usb-role-switch; 527 528 vbus-supply = <&vdd_5v0_usb>; 529 530 connector { 531 compatible = "gpio-usb-b-connector", 532 "usb-b-connector"; 533 label = "micro-USB"; 534 type = "micro"; 535 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) 536 GPIO_ACTIVE_LOW>; 537 }; 538 }; 539 540 usb2-1 { 541 status = "okay"; 542 mode = "host"; 543 }; 544 545 usb2-2 { 546 status = "okay"; 547 mode = "host"; 548 }; 549 550 usb3-0 { 551 status = "okay"; 552 nvidia,usb2-companion = <1>; 553 vbus-supply = <&vdd_hub_3v3>; 554 }; 555 }; 556 }; 557 558 mmc@700b0000 { 559 status = "okay"; 560 bus-width = <4>; 561 562 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; 563 disable-wp; 564 565 vqmmc-supply = <&vddio_sdmmc>; 566 vmmc-supply = <&vdd_3v3_sd>; 567 }; 568 569 mmc@700b0400 { 570 status = "okay"; 571 bus-width = <4>; 572 573 vqmmc-supply = <&vdd_1v8>; 574 vmmc-supply = <&vdd_3v3_sys>; 575 576 non-removable; 577 cap-sdio-irq; 578 keep-power-in-suspend; 579 wakeup-source; 580 }; 581 582 usb@700d0000 { 583 status = "okay"; 584 phys = <µ_b>; 585 phy-names = "usb2-0"; 586 avddio-usb-supply = <&vdd_3v3_sys>; 587 hvdd-usb-supply = <&vdd_1v8>; 588 }; 589 590 clock@70110000 { 591 status = "okay"; 592 593 nvidia,cf = <6>; 594 nvidia,ci = <0>; 595 nvidia,cg = <2>; 596 nvidia,droop-ctrl = <0x00000f00>; 597 nvidia,force-mode = <1>; 598 nvidia,sample-rate = <25000>; 599 600 nvidia,pwm-min-microvolts = <708000>; 601 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 602 nvidia,pwm-to-pmic; 603 nvidia,pwm-tristate-microvolts = <1000000>; 604 nvidia,pwm-voltage-step-microvolts = <19200>; 605 606 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; 607 pinctrl-0 = <&dvfs_pwm_active_state>; 608 pinctrl-1 = <&dvfs_pwm_inactive_state>; 609 }; 610 611 aconnect@702c0000 { 612 status = "okay"; 613 614 dma-controller@702e2000 { 615 status = "okay"; 616 }; 617 618 interrupt-controller@702f9000 { 619 status = "okay"; 620 }; 621 622 ahub@702d0800 { 623 status = "okay"; 624 625 admaif@702d0000 { 626 status = "okay"; 627 }; 628 629 i2s@702d1200 { 630 status = "okay"; 631 632 ports { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 636 port@0 { 637 reg = <0>; 638 639 i2s3_cif_ep: endpoint { 640 remote-endpoint = <&xbar_i2s3_ep>; 641 }; 642 }; 643 644 i2s3_port: port@1 { 645 reg = <1>; 646 647 i2s3_dap_ep: endpoint { 648 dai-format = "i2s"; 649 /* Placeholder for external Codec */ 650 }; 651 }; 652 }; 653 }; 654 655 i2s@702d1300 { 656 status = "okay"; 657 658 ports { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 662 port@0 { 663 reg = <0>; 664 665 i2s4_cif_ep: endpoint { 666 remote-endpoint = <&xbar_i2s4_ep>; 667 }; 668 }; 669 670 i2s4_port: port@1 { 671 reg = <1>; 672 673 i2s4_dap_ep: endpoint { 674 dai-format = "i2s"; 675 /* Placeholder for external Codec */ 676 }; 677 }; 678 }; 679 }; 680 681 dmic@702d4000 { 682 status = "okay"; 683 684 ports { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 688 port@0 { 689 reg = <0>; 690 691 dmic1_cif_ep: endpoint { 692 remote-endpoint = <&xbar_dmic1_ep>; 693 }; 694 }; 695 696 dmic1_port: port@1 { 697 reg = <1>; 698 699 dmic1_dap_ep: endpoint { 700 /* Placeholder for external Codec */ 701 }; 702 }; 703 }; 704 }; 705 706 dmic@702d4100 { 707 status = "okay"; 708 709 ports { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 713 port@0 { 714 reg = <0>; 715 716 dmic2_cif_ep: endpoint { 717 remote-endpoint = <&xbar_dmic2_ep>; 718 }; 719 }; 720 721 dmic2_port: port@1 { 722 reg = <1>; 723 724 dmic2_dap_ep: endpoint { 725 /* Placeholder for external Codec */ 726 }; 727 }; 728 }; 729 }; 730 731 sfc@702d2000 { 732 status = "okay"; 733 734 ports { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 738 port@0 { 739 reg = <0>; 740 741 sfc1_cif_in_ep: endpoint { 742 remote-endpoint = <&xbar_sfc1_in_ep>; 743 }; 744 }; 745 746 sfc1_out_port: port@1 { 747 reg = <1>; 748 749 sfc1_cif_out_ep: endpoint { 750 remote-endpoint = <&xbar_sfc1_out_ep>; 751 }; 752 }; 753 }; 754 }; 755 756 sfc@702d2200 { 757 status = "okay"; 758 759 ports { 760 #address-cells = <1>; 761 #size-cells = <0>; 762 763 port@0 { 764 reg = <0>; 765 766 sfc2_cif_in_ep: endpoint { 767 remote-endpoint = <&xbar_sfc2_in_ep>; 768 }; 769 }; 770 771 sfc2_out_port: port@1 { 772 reg = <1>; 773 774 sfc2_cif_out_ep: endpoint { 775 remote-endpoint = <&xbar_sfc2_out_ep>; 776 }; 777 }; 778 }; 779 }; 780 781 sfc@702d2400 { 782 status = "okay"; 783 784 ports { 785 #address-cells = <1>; 786 #size-cells = <0>; 787 788 port@0 { 789 reg = <0>; 790 791 sfc3_cif_in_ep: endpoint { 792 remote-endpoint = <&xbar_sfc3_in_ep>; 793 }; 794 }; 795 796 sfc3_out_port: port@1 { 797 reg = <1>; 798 799 sfc3_cif_out_ep: endpoint { 800 remote-endpoint = <&xbar_sfc3_out_ep>; 801 }; 802 }; 803 }; 804 }; 805 806 sfc@702d2600 { 807 status = "okay"; 808 809 ports { 810 #address-cells = <1>; 811 #size-cells = <0>; 812 813 port@0 { 814 reg = <0>; 815 816 sfc4_cif_in_ep: endpoint { 817 remote-endpoint = <&xbar_sfc4_in_ep>; 818 }; 819 }; 820 821 sfc4_out_port: port@1 { 822 reg = <1>; 823 824 sfc4_cif_out_ep: endpoint { 825 remote-endpoint = <&xbar_sfc4_out_ep>; 826 }; 827 }; 828 }; 829 }; 830 831 mvc@702da000 { 832 status = "okay"; 833 834 ports { 835 #address-cells = <1>; 836 #size-cells = <0>; 837 838 port@0 { 839 reg = <0>; 840 841 mvc1_cif_in_ep: endpoint { 842 remote-endpoint = <&xbar_mvc1_in_ep>; 843 }; 844 }; 845 846 mvc1_out_port: port@1 { 847 reg = <1>; 848 849 mvc1_cif_out_ep: endpoint { 850 remote-endpoint = <&xbar_mvc1_out_ep>; 851 }; 852 }; 853 }; 854 }; 855 856 mvc@702da200 { 857 status = "okay"; 858 859 ports { 860 #address-cells = <1>; 861 #size-cells = <0>; 862 863 port@0 { 864 reg = <0>; 865 866 mvc2_cif_in_ep: endpoint { 867 remote-endpoint = <&xbar_mvc2_in_ep>; 868 }; 869 }; 870 871 mvc2_out_port: port@1 { 872 reg = <1>; 873 874 mvc2_cif_out_ep: endpoint { 875 remote-endpoint = <&xbar_mvc2_out_ep>; 876 }; 877 }; 878 }; 879 }; 880 881 amx@702d3000 { 882 status = "okay"; 883 884 ports { 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 port@0 { 889 reg = <0>; 890 891 amx1_in1_ep: endpoint { 892 remote-endpoint = <&xbar_amx1_in1_ep>; 893 }; 894 }; 895 896 port@1 { 897 reg = <1>; 898 899 amx1_in2_ep: endpoint { 900 remote-endpoint = <&xbar_amx1_in2_ep>; 901 }; 902 }; 903 904 port@2 { 905 reg = <2>; 906 907 amx1_in3_ep: endpoint { 908 remote-endpoint = <&xbar_amx1_in3_ep>; 909 }; 910 }; 911 912 port@3 { 913 reg = <3>; 914 915 amx1_in4_ep: endpoint { 916 remote-endpoint = <&xbar_amx1_in4_ep>; 917 }; 918 }; 919 920 amx1_out_port: port@4 { 921 reg = <4>; 922 923 amx1_out_ep: endpoint { 924 remote-endpoint = <&xbar_amx1_out_ep>; 925 }; 926 }; 927 }; 928 }; 929 930 amx@702d3100 { 931 status = "okay"; 932 933 ports { 934 #address-cells = <1>; 935 #size-cells = <0>; 936 937 port@0 { 938 reg = <0>; 939 940 amx2_in1_ep: endpoint { 941 remote-endpoint = <&xbar_amx2_in1_ep>; 942 }; 943 }; 944 945 port@1 { 946 reg = <1>; 947 948 amx2_in2_ep: endpoint { 949 remote-endpoint = <&xbar_amx2_in2_ep>; 950 }; 951 }; 952 953 amx2_in3_port: port@2 { 954 reg = <2>; 955 956 amx2_in3_ep: endpoint { 957 remote-endpoint = <&xbar_amx2_in3_ep>; 958 }; 959 }; 960 961 amx2_in4_port: port@3 { 962 reg = <3>; 963 964 amx2_in4_ep: endpoint { 965 remote-endpoint = <&xbar_amx2_in4_ep>; 966 }; 967 }; 968 969 amx2_out_port: port@4 { 970 reg = <4>; 971 972 amx2_out_ep: endpoint { 973 remote-endpoint = <&xbar_amx2_out_ep>; 974 }; 975 }; 976 }; 977 }; 978 979 adx@702d3800 { 980 status = "okay"; 981 982 ports { 983 #address-cells = <1>; 984 #size-cells = <0>; 985 986 port@0 { 987 reg = <0>; 988 989 adx1_in_ep: endpoint { 990 remote-endpoint = <&xbar_adx1_in_ep>; 991 }; 992 }; 993 994 adx1_out1_port: port@1 { 995 reg = <1>; 996 997 adx1_out1_ep: endpoint { 998 remote-endpoint = <&xbar_adx1_out1_ep>; 999 }; 1000 }; 1001 1002 adx1_out2_port: port@2 { 1003 reg = <2>; 1004 1005 adx1_out2_ep: endpoint { 1006 remote-endpoint = <&xbar_adx1_out2_ep>; 1007 }; 1008 }; 1009 1010 adx1_out3_port: port@3 { 1011 reg = <3>; 1012 1013 adx1_out3_ep: endpoint { 1014 remote-endpoint = <&xbar_adx1_out3_ep>; 1015 }; 1016 }; 1017 1018 adx1_out4_port: port@4 { 1019 reg = <4>; 1020 1021 adx1_out4_ep: endpoint { 1022 remote-endpoint = <&xbar_adx1_out4_ep>; 1023 }; 1024 }; 1025 }; 1026 }; 1027 1028 adx@702d3900 { 1029 status = "okay"; 1030 1031 ports { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 port@0 { 1036 reg = <0>; 1037 1038 adx2_in_ep: endpoint { 1039 remote-endpoint = <&xbar_adx2_in_ep>; 1040 }; 1041 }; 1042 1043 adx2_out1_port: port@1 { 1044 reg = <1>; 1045 1046 adx2_out1_ep: endpoint { 1047 remote-endpoint = <&xbar_adx2_out1_ep>; 1048 }; 1049 }; 1050 1051 adx2_out2_port: port@2 { 1052 reg = <2>; 1053 1054 adx2_out2_ep: endpoint { 1055 remote-endpoint = <&xbar_adx2_out2_ep>; 1056 }; 1057 }; 1058 1059 adx2_out3_port: port@3 { 1060 reg = <3>; 1061 1062 adx2_out3_ep: endpoint { 1063 remote-endpoint = <&xbar_adx2_out3_ep>; 1064 }; 1065 }; 1066 1067 adx2_out4_port: port@4 { 1068 reg = <4>; 1069 1070 adx2_out4_ep: endpoint { 1071 remote-endpoint = <&xbar_adx2_out4_ep>; 1072 }; 1073 }; 1074 }; 1075 }; 1076 1077 processing-engine@702d8000 { 1078 status = "okay"; 1079 1080 ports { 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 port@0 { 1085 reg = <0x0>; 1086 1087 ope1_cif_in_ep: endpoint { 1088 remote-endpoint = <&xbar_ope1_in_ep>; 1089 }; 1090 }; 1091 1092 ope1_out_port: port@1 { 1093 reg = <0x1>; 1094 1095 ope1_cif_out_ep: endpoint { 1096 remote-endpoint = <&xbar_ope1_out_ep>; 1097 }; 1098 }; 1099 }; 1100 }; 1101 1102 processing-engine@702d8400 { 1103 status = "okay"; 1104 1105 ports { 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 1109 port@0 { 1110 reg = <0x0>; 1111 1112 ope2_cif_in_ep: endpoint { 1113 remote-endpoint = <&xbar_ope2_in_ep>; 1114 }; 1115 }; 1116 1117 ope2_out_port: port@1 { 1118 reg = <0x1>; 1119 1120 ope2_cif_out_ep: endpoint { 1121 remote-endpoint = <&xbar_ope2_out_ep>; 1122 }; 1123 }; 1124 }; 1125 }; 1126 1127 amixer@702dbb00 { 1128 status = "okay"; 1129 1130 ports { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 1134 port@0 { 1135 reg = <0x0>; 1136 1137 mixer_in1_ep: endpoint { 1138 remote-endpoint = <&xbar_mixer_in1_ep>; 1139 }; 1140 }; 1141 1142 port@1 { 1143 reg = <0x1>; 1144 1145 mixer_in2_ep: endpoint { 1146 remote-endpoint = <&xbar_mixer_in2_ep>; 1147 }; 1148 }; 1149 1150 port@2 { 1151 reg = <0x2>; 1152 1153 mixer_in3_ep: endpoint { 1154 remote-endpoint = <&xbar_mixer_in3_ep>; 1155 }; 1156 }; 1157 1158 port@3 { 1159 reg = <0x3>; 1160 1161 mixer_in4_ep: endpoint { 1162 remote-endpoint = <&xbar_mixer_in4_ep>; 1163 }; 1164 }; 1165 1166 port@4 { 1167 reg = <0x4>; 1168 1169 mixer_in5_ep: endpoint { 1170 remote-endpoint = <&xbar_mixer_in5_ep>; 1171 }; 1172 }; 1173 1174 port@5 { 1175 reg = <0x5>; 1176 1177 mixer_in6_ep: endpoint { 1178 remote-endpoint = <&xbar_mixer_in6_ep>; 1179 }; 1180 }; 1181 1182 port@6 { 1183 reg = <0x6>; 1184 1185 mixer_in7_ep: endpoint { 1186 remote-endpoint = <&xbar_mixer_in7_ep>; 1187 }; 1188 }; 1189 1190 port@7 { 1191 reg = <0x7>; 1192 1193 mixer_in8_ep: endpoint { 1194 remote-endpoint = <&xbar_mixer_in8_ep>; 1195 }; 1196 }; 1197 1198 port@8 { 1199 reg = <0x8>; 1200 1201 mixer_in9_ep: endpoint { 1202 remote-endpoint = <&xbar_mixer_in9_ep>; 1203 }; 1204 }; 1205 1206 port@9 { 1207 reg = <0x9>; 1208 1209 mixer_in10_ep: endpoint { 1210 remote-endpoint = <&xbar_mixer_in10_ep>; 1211 }; 1212 }; 1213 1214 mixer_out1_port: port@a { 1215 reg = <0xa>; 1216 1217 mixer_out1_ep: endpoint { 1218 remote-endpoint = <&xbar_mixer_out1_ep>; 1219 }; 1220 }; 1221 1222 mixer_out2_port: port@b { 1223 reg = <0xb>; 1224 1225 mixer_out2_ep: endpoint { 1226 remote-endpoint = <&xbar_mixer_out2_ep>; 1227 }; 1228 }; 1229 1230 mixer_out3_port: port@c { 1231 reg = <0xc>; 1232 1233 mixer_out3_ep: endpoint { 1234 remote-endpoint = <&xbar_mixer_out3_ep>; 1235 }; 1236 }; 1237 1238 mixer_out4_port: port@d { 1239 reg = <0xd>; 1240 1241 mixer_out4_ep: endpoint { 1242 remote-endpoint = <&xbar_mixer_out4_ep>; 1243 }; 1244 }; 1245 1246 mixer_out5_port: port@e { 1247 reg = <0xe>; 1248 1249 mixer_out5_ep: endpoint { 1250 remote-endpoint = <&xbar_mixer_out5_ep>; 1251 }; 1252 }; 1253 }; 1254 }; 1255 1256 ports { 1257 xbar_i2s3_port: port@c { 1258 reg = <0xc>; 1259 1260 xbar_i2s3_ep: endpoint { 1261 remote-endpoint = <&i2s3_cif_ep>; 1262 }; 1263 }; 1264 1265 xbar_i2s4_port: port@d { 1266 reg = <0xd>; 1267 1268 xbar_i2s4_ep: endpoint { 1269 remote-endpoint = <&i2s4_cif_ep>; 1270 }; 1271 }; 1272 1273 xbar_dmic1_port: port@f { 1274 reg = <0xf>; 1275 1276 xbar_dmic1_ep: endpoint { 1277 remote-endpoint = <&dmic1_cif_ep>; 1278 }; 1279 }; 1280 1281 xbar_dmic2_port: port@10 { 1282 reg = <0x10>; 1283 1284 xbar_dmic2_ep: endpoint { 1285 remote-endpoint = <&dmic2_cif_ep>; 1286 }; 1287 }; 1288 1289 xbar_sfc1_in_port: port@12 { 1290 reg = <0x12>; 1291 1292 xbar_sfc1_in_ep: endpoint { 1293 remote-endpoint = <&sfc1_cif_in_ep>; 1294 }; 1295 }; 1296 1297 port@13 { 1298 reg = <0x13>; 1299 1300 xbar_sfc1_out_ep: endpoint { 1301 remote-endpoint = <&sfc1_cif_out_ep>; 1302 }; 1303 }; 1304 1305 xbar_sfc2_in_port: port@14 { 1306 reg = <0x14>; 1307 1308 xbar_sfc2_in_ep: endpoint { 1309 remote-endpoint = <&sfc2_cif_in_ep>; 1310 }; 1311 }; 1312 1313 port@15 { 1314 reg = <0x15>; 1315 1316 xbar_sfc2_out_ep: endpoint { 1317 remote-endpoint = <&sfc2_cif_out_ep>; 1318 }; 1319 }; 1320 1321 xbar_sfc3_in_port: port@16 { 1322 reg = <0x16>; 1323 1324 xbar_sfc3_in_ep: endpoint { 1325 remote-endpoint = <&sfc3_cif_in_ep>; 1326 }; 1327 }; 1328 1329 port@17 { 1330 reg = <0x17>; 1331 1332 xbar_sfc3_out_ep: endpoint { 1333 remote-endpoint = <&sfc3_cif_out_ep>; 1334 }; 1335 }; 1336 1337 xbar_sfc4_in_port: port@18 { 1338 reg = <0x18>; 1339 1340 xbar_sfc4_in_ep: endpoint { 1341 remote-endpoint = <&sfc4_cif_in_ep>; 1342 }; 1343 }; 1344 1345 port@19 { 1346 reg = <0x19>; 1347 1348 xbar_sfc4_out_ep: endpoint { 1349 remote-endpoint = <&sfc4_cif_out_ep>; 1350 }; 1351 }; 1352 1353 xbar_mvc1_in_port: port@1a { 1354 reg = <0x1a>; 1355 1356 xbar_mvc1_in_ep: endpoint { 1357 remote-endpoint = <&mvc1_cif_in_ep>; 1358 }; 1359 }; 1360 1361 port@1b { 1362 reg = <0x1b>; 1363 1364 xbar_mvc1_out_ep: endpoint { 1365 remote-endpoint = <&mvc1_cif_out_ep>; 1366 }; 1367 }; 1368 1369 xbar_mvc2_in_port: port@1c { 1370 reg = <0x1c>; 1371 1372 xbar_mvc2_in_ep: endpoint { 1373 remote-endpoint = <&mvc2_cif_in_ep>; 1374 }; 1375 }; 1376 1377 port@1d { 1378 reg = <0x1d>; 1379 1380 xbar_mvc2_out_ep: endpoint { 1381 remote-endpoint = <&mvc2_cif_out_ep>; 1382 }; 1383 }; 1384 1385 xbar_amx1_in1_port: port@1e { 1386 reg = <0x1e>; 1387 1388 xbar_amx1_in1_ep: endpoint { 1389 remote-endpoint = <&amx1_in1_ep>; 1390 }; 1391 }; 1392 1393 xbar_amx1_in2_port: port@1f { 1394 reg = <0x1f>; 1395 1396 xbar_amx1_in2_ep: endpoint { 1397 remote-endpoint = <&amx1_in2_ep>; 1398 }; 1399 }; 1400 1401 xbar_amx1_in3_port: port@20 { 1402 reg = <0x20>; 1403 1404 xbar_amx1_in3_ep: endpoint { 1405 remote-endpoint = <&amx1_in3_ep>; 1406 }; 1407 }; 1408 1409 xbar_amx1_in4_port: port@21 { 1410 reg = <0x21>; 1411 1412 xbar_amx1_in4_ep: endpoint { 1413 remote-endpoint = <&amx1_in4_ep>; 1414 }; 1415 }; 1416 1417 port@22 { 1418 reg = <0x22>; 1419 1420 xbar_amx1_out_ep: endpoint { 1421 remote-endpoint = <&amx1_out_ep>; 1422 }; 1423 }; 1424 1425 xbar_amx2_in1_port: port@23 { 1426 reg = <0x23>; 1427 1428 xbar_amx2_in1_ep: endpoint { 1429 remote-endpoint = <&amx2_in1_ep>; 1430 }; 1431 }; 1432 1433 xbar_amx2_in2_port: port@24 { 1434 reg = <0x24>; 1435 1436 xbar_amx2_in2_ep: endpoint { 1437 remote-endpoint = <&amx2_in2_ep>; 1438 }; 1439 }; 1440 1441 xbar_amx2_in3_port: port@25 { 1442 reg = <0x25>; 1443 1444 xbar_amx2_in3_ep: endpoint { 1445 remote-endpoint = <&amx2_in3_ep>; 1446 }; 1447 }; 1448 1449 xbar_amx2_in4_port: port@26 { 1450 reg = <0x26>; 1451 1452 xbar_amx2_in4_ep: endpoint { 1453 remote-endpoint = <&amx2_in4_ep>; 1454 }; 1455 }; 1456 1457 port@27 { 1458 reg = <0x27>; 1459 1460 xbar_amx2_out_ep: endpoint { 1461 remote-endpoint = <&amx2_out_ep>; 1462 }; 1463 }; 1464 1465 xbar_adx1_in_port: port@28 { 1466 reg = <0x28>; 1467 1468 xbar_adx1_in_ep: endpoint { 1469 remote-endpoint = <&adx1_in_ep>; 1470 }; 1471 }; 1472 1473 port@29 { 1474 reg = <0x29>; 1475 1476 xbar_adx1_out1_ep: endpoint { 1477 remote-endpoint = <&adx1_out1_ep>; 1478 }; 1479 }; 1480 1481 port@2a { 1482 reg = <0x2a>; 1483 1484 xbar_adx1_out2_ep: endpoint { 1485 remote-endpoint = <&adx1_out2_ep>; 1486 }; 1487 }; 1488 1489 port@2b { 1490 reg = <0x2b>; 1491 1492 xbar_adx1_out3_ep: endpoint { 1493 remote-endpoint = <&adx1_out3_ep>; 1494 }; 1495 }; 1496 1497 port@2c { 1498 reg = <0x2c>; 1499 1500 xbar_adx1_out4_ep: endpoint { 1501 remote-endpoint = <&adx1_out4_ep>; 1502 }; 1503 }; 1504 1505 xbar_adx2_in_port: port@2d { 1506 reg = <0x2d>; 1507 1508 xbar_adx2_in_ep: endpoint { 1509 remote-endpoint = <&adx2_in_ep>; 1510 }; 1511 }; 1512 1513 port@2e { 1514 reg = <0x2e>; 1515 1516 xbar_adx2_out1_ep: endpoint { 1517 remote-endpoint = <&adx2_out1_ep>; 1518 }; 1519 }; 1520 1521 port@2f { 1522 reg = <0x2f>; 1523 1524 xbar_adx2_out2_ep: endpoint { 1525 remote-endpoint = <&adx2_out2_ep>; 1526 }; 1527 }; 1528 1529 port@30 { 1530 reg = <0x30>; 1531 1532 xbar_adx2_out3_ep: endpoint { 1533 remote-endpoint = <&adx2_out3_ep>; 1534 }; 1535 }; 1536 1537 port@31 { 1538 reg = <0x31>; 1539 1540 xbar_adx2_out4_ep: endpoint { 1541 remote-endpoint = <&adx2_out4_ep>; 1542 }; 1543 }; 1544 1545 xbar_mixer_in1_port: port@32 { 1546 reg = <0x32>; 1547 1548 xbar_mixer_in1_ep: endpoint { 1549 remote-endpoint = <&mixer_in1_ep>; 1550 }; 1551 }; 1552 1553 xbar_mixer_in2_port: port@33 { 1554 reg = <0x33>; 1555 1556 xbar_mixer_in2_ep: endpoint { 1557 remote-endpoint = <&mixer_in2_ep>; 1558 }; 1559 }; 1560 1561 xbar_mixer_in3_port: port@34 { 1562 reg = <0x34>; 1563 1564 xbar_mixer_in3_ep: endpoint { 1565 remote-endpoint = <&mixer_in3_ep>; 1566 }; 1567 }; 1568 1569 xbar_mixer_in4_port: port@35 { 1570 reg = <0x35>; 1571 1572 xbar_mixer_in4_ep: endpoint { 1573 remote-endpoint = <&mixer_in4_ep>; 1574 }; 1575 }; 1576 1577 xbar_mixer_in5_port: port@36 { 1578 reg = <0x36>; 1579 1580 xbar_mixer_in5_ep: endpoint { 1581 remote-endpoint = <&mixer_in5_ep>; 1582 }; 1583 }; 1584 1585 xbar_mixer_in6_port: port@37 { 1586 reg = <0x37>; 1587 1588 xbar_mixer_in6_ep: endpoint { 1589 remote-endpoint = <&mixer_in6_ep>; 1590 }; 1591 }; 1592 1593 xbar_mixer_in7_port: port@38 { 1594 reg = <0x38>; 1595 1596 xbar_mixer_in7_ep: endpoint { 1597 remote-endpoint = <&mixer_in7_ep>; 1598 }; 1599 }; 1600 1601 xbar_mixer_in8_port: port@39 { 1602 reg = <0x39>; 1603 1604 xbar_mixer_in8_ep: endpoint { 1605 remote-endpoint = <&mixer_in8_ep>; 1606 }; 1607 }; 1608 1609 xbar_mixer_in9_port: port@3a { 1610 reg = <0x3a>; 1611 1612 xbar_mixer_in9_ep: endpoint { 1613 remote-endpoint = <&mixer_in9_ep>; 1614 }; 1615 }; 1616 1617 xbar_mixer_in10_port: port@3b { 1618 reg = <0x3b>; 1619 1620 xbar_mixer_in10_ep: endpoint { 1621 remote-endpoint = <&mixer_in10_ep>; 1622 }; 1623 }; 1624 1625 port@3c { 1626 reg = <0x3c>; 1627 1628 xbar_mixer_out1_ep: endpoint { 1629 remote-endpoint = <&mixer_out1_ep>; 1630 }; 1631 }; 1632 1633 port@3d { 1634 reg = <0x3d>; 1635 1636 xbar_mixer_out2_ep: endpoint { 1637 remote-endpoint = <&mixer_out2_ep>; 1638 }; 1639 }; 1640 1641 port@3e { 1642 reg = <0x3e>; 1643 1644 xbar_mixer_out3_ep: endpoint { 1645 remote-endpoint = <&mixer_out3_ep>; 1646 }; 1647 }; 1648 1649 port@3f { 1650 reg = <0x3f>; 1651 1652 xbar_mixer_out4_ep: endpoint { 1653 remote-endpoint = <&mixer_out4_ep>; 1654 }; 1655 }; 1656 1657 port@40 { 1658 reg = <0x40>; 1659 1660 xbar_mixer_out5_ep: endpoint { 1661 remote-endpoint = <&mixer_out5_ep>; 1662 }; 1663 }; 1664 1665 xbar_ope1_in_port: port@41 { 1666 reg = <0x41>; 1667 1668 xbar_ope1_in_ep: endpoint { 1669 remote-endpoint = <&ope1_cif_in_ep>; 1670 }; 1671 }; 1672 1673 port@42 { 1674 reg = <0x42>; 1675 1676 xbar_ope1_out_ep: endpoint { 1677 remote-endpoint = <&ope1_cif_out_ep>; 1678 }; 1679 }; 1680 1681 xbar_ope2_in_port: port@43 { 1682 reg = <0x43>; 1683 1684 xbar_ope2_in_ep: endpoint { 1685 remote-endpoint = <&ope2_cif_in_ep>; 1686 }; 1687 }; 1688 1689 port@44 { 1690 reg = <0x44>; 1691 1692 xbar_ope2_out_ep: endpoint { 1693 remote-endpoint = <&ope2_cif_out_ep>; 1694 }; 1695 }; 1696 }; 1697 }; 1698 }; 1699 1700 spi@70410000 { 1701 status = "okay"; 1702 1703 flash@0 { 1704 compatible = "jedec,spi-nor"; 1705 reg = <0>; 1706 spi-max-frequency = <104000000>; 1707 spi-tx-bus-width = <2>; 1708 spi-rx-bus-width = <2>; 1709 }; 1710 }; 1711 1712 clk32k_in: clock-32k { 1713 compatible = "fixed-clock"; 1714 clock-frequency = <32768>; 1715 #clock-cells = <0>; 1716 }; 1717 1718 cpus { 1719 cpu@0 { 1720 enable-method = "psci"; 1721 }; 1722 1723 cpu@1 { 1724 enable-method = "psci"; 1725 }; 1726 1727 cpu@2 { 1728 enable-method = "psci"; 1729 }; 1730 1731 cpu@3 { 1732 enable-method = "psci"; 1733 }; 1734 1735 idle-states { 1736 cpu-sleep { 1737 status = "okay"; 1738 }; 1739 }; 1740 }; 1741 1742 fan: pwm-fan { 1743 compatible = "pwm-fan"; 1744 pwms = <&pwm 3 45334>; 1745 1746 cooling-levels = <0 64 128 255>; 1747 #cooling-cells = <2>; 1748 }; 1749 1750 thermal-zones { 1751 cpu-thermal { 1752 trips { 1753 cpu_trip_critical: critical { 1754 temperature = <96500>; 1755 hysteresis = <0>; 1756 type = "critical"; 1757 }; 1758 1759 cpu_trip_hot: hot { 1760 temperature = <70000>; 1761 hysteresis = <2000>; 1762 type = "hot"; 1763 }; 1764 1765 cpu_trip_active: active { 1766 temperature = <50000>; 1767 hysteresis = <2000>; 1768 type = "active"; 1769 }; 1770 1771 cpu_trip_passive: passive { 1772 temperature = <30000>; 1773 hysteresis = <2000>; 1774 type = "passive"; 1775 }; 1776 }; 1777 1778 cooling-maps { 1779 cpu-critical { 1780 cooling-device = <&fan 3 3>; 1781 trip = <&cpu_trip_critical>; 1782 }; 1783 1784 cpu-hot { 1785 cooling-device = <&fan 2 2>; 1786 trip = <&cpu_trip_hot>; 1787 }; 1788 1789 cpu-active { 1790 cooling-device = <&fan 1 1>; 1791 trip = <&cpu_trip_active>; 1792 }; 1793 1794 cpu-passive { 1795 cooling-device = <&fan 0 0>; 1796 trip = <&cpu_trip_passive>; 1797 }; 1798 }; 1799 }; 1800 }; 1801 1802 gpio-keys { 1803 compatible = "gpio-keys"; 1804 1805 key-power { 1806 label = "Power"; 1807 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; 1808 linux,input-type = <EV_KEY>; 1809 linux,code = <KEY_POWER>; 1810 debounce-interval = <30>; 1811 wakeup-event-action = <EV_ACT_ASSERTED>; 1812 wakeup-source; 1813 }; 1814 1815 key-force-recovery { 1816 label = "Force Recovery"; 1817 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 1818 linux,input-type = <EV_KEY>; 1819 linux,code = <BTN_1>; 1820 debounce-interval = <30>; 1821 }; 1822 }; 1823 1824 psci { 1825 compatible = "arm,psci-1.0"; 1826 method = "smc"; 1827 }; 1828 1829 vdd_5v0_sys: regulator-vdd-5v0-sys { 1830 compatible = "regulator-fixed"; 1831 1832 regulator-name = "VDD_5V0_SYS"; 1833 regulator-min-microvolt = <5000000>; 1834 regulator-max-microvolt = <5000000>; 1835 regulator-always-on; 1836 regulator-boot-on; 1837 }; 1838 1839 vdd_3v3_sys: regulator-vdd-3v3-sys { 1840 compatible = "regulator-fixed"; 1841 1842 regulator-name = "VDD_3V3_SYS"; 1843 regulator-min-microvolt = <3300000>; 1844 regulator-max-microvolt = <3300000>; 1845 regulator-enable-ramp-delay = <240>; 1846 regulator-always-on; 1847 regulator-boot-on; 1848 1849 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; 1850 enable-active-high; 1851 1852 vin-supply = <&vdd_5v0_sys>; 1853 }; 1854 1855 vdd_3v3_sd: regulator-vdd-3v3-sd { 1856 compatible = "regulator-fixed"; 1857 1858 regulator-name = "VDD_3V3_SD"; 1859 regulator-min-microvolt = <3300000>; 1860 regulator-max-microvolt = <3300000>; 1861 1862 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; 1863 enable-active-high; 1864 1865 vin-supply = <&vdd_3v3_sys>; 1866 }; 1867 1868 vdd_hdmi: regulator-vdd-hdmi-5v0 { 1869 compatible = "regulator-fixed"; 1870 1871 regulator-name = "VDD_HDMI_5V0"; 1872 regulator-min-microvolt = <5000000>; 1873 regulator-max-microvolt = <5000000>; 1874 1875 vin-supply = <&vdd_5v0_sys>; 1876 }; 1877 1878 vdd_hub_3v3: regulator-vdd-hub-3v3 { 1879 compatible = "regulator-fixed"; 1880 1881 regulator-name = "VDD_HUB_3V3"; 1882 regulator-min-microvolt = <3300000>; 1883 regulator-max-microvolt = <3300000>; 1884 1885 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; 1886 enable-active-high; 1887 1888 vin-supply = <&vdd_5v0_sys>; 1889 }; 1890 1891 vdd_cpu: regulator-vdd-cpu { 1892 compatible = "regulator-fixed"; 1893 1894 regulator-name = "VDD_CPU"; 1895 regulator-min-microvolt = <5000000>; 1896 regulator-max-microvolt = <5000000>; 1897 regulator-always-on; 1898 regulator-boot-on; 1899 1900 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; 1901 enable-active-high; 1902 1903 vin-supply = <&vdd_5v0_sys>; 1904 }; 1905 1906 vdd_gpu: regulator-vdd-gpu { 1907 compatible = "pwm-regulator"; 1908 pwms = <&pwm 1 8000>; 1909 1910 regulator-name = "VDD_GPU"; 1911 regulator-min-microvolt = <710000>; 1912 regulator-max-microvolt = <1320000>; 1913 regulator-ramp-delay = <80>; 1914 regulator-enable-ramp-delay = <2000>; 1915 regulator-settling-time-us = <160>; 1916 1917 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; 1918 vin-supply = <&vdd_5v0_sys>; 1919 }; 1920 1921 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { 1922 compatible = "regulator-fixed"; 1923 1924 regulator-name = "AVDD_IO_EDP_1V05"; 1925 regulator-min-microvolt = <1050000>; 1926 regulator-max-microvolt = <1050000>; 1927 1928 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 1929 enable-active-high; 1930 1931 vin-supply = <&avdd_1v05_pll>; 1932 }; 1933 1934 vdd_5v0_usb: regulator-vdd-5v-usb { 1935 compatible = "regulator-fixed"; 1936 1937 regulator-name = "VDD_5V_USB"; 1938 regulator-min-microvolt = <50000000>; 1939 regulator-max-microvolt = <50000000>; 1940 1941 vin-supply = <&vdd_5v0_sys>; 1942 }; 1943 1944 sound { 1945 compatible = "nvidia,tegra210-audio-graph-card"; 1946 status = "okay"; 1947 1948 dais = /* FE */ 1949 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 1950 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, 1951 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, 1952 <&admaif10_port>, 1953 /* Router */ 1954 <&xbar_i2s3_port>, <&xbar_i2s4_port>, 1955 <&xbar_dmic1_port>, <&xbar_dmic2_port>, 1956 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 1957 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 1958 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 1959 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 1960 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 1961 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 1962 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 1963 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 1964 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 1965 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 1966 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 1967 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 1968 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 1969 <&xbar_ope1_in_port>, <&xbar_ope2_in_port>, 1970 /* HW accelerators */ 1971 <&sfc1_out_port>, <&sfc2_out_port>, 1972 <&sfc3_out_port>, <&sfc4_out_port>, 1973 <&mvc1_out_port>, <&mvc2_out_port>, 1974 <&amx1_out_port>, <&amx2_out_port>, 1975 <&adx1_out1_port>, <&adx1_out2_port>, 1976 <&adx1_out3_port>, <&adx1_out4_port>, 1977 <&adx2_out1_port>, <&adx2_out2_port>, 1978 <&adx2_out3_port>, <&adx2_out4_port>, 1979 <&mixer_out1_port>, <&mixer_out2_port>, 1980 <&mixer_out3_port>, <&mixer_out4_port>, 1981 <&mixer_out5_port>, 1982 <&ope1_out_port>, <&ope2_out_port>, 1983 /* I/O DAP Ports */ 1984 <&i2s3_port>, <&i2s4_port>, 1985 <&dmic1_port>, <&dmic2_port>; 1986 1987 label = "NVIDIA Jetson Nano APE"; 1988 }; 1989}; 1990