1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include "tegra210-p2180.dtsi" 5#include "tegra210-p2597.dtsi" 6 7/ { 8 model = "NVIDIA Jetson TX1 Developer Kit"; 9 compatible = "nvidia,p2371-2180", "nvidia,tegra210"; 10 11 pcie@1003000 { 12 status = "okay"; 13 14 hvddio-pex-supply = <&vdd_1v8>; 15 dvddio-pex-supply = <&vdd_pex_1v05>; 16 vddio-pex-ctl-supply = <&vdd_1v8>; 17 18 pci@1,0 { 19 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, 20 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 21 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 22 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; 23 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 24 status = "okay"; 25 }; 26 27 pci@2,0 { 28 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 29 phy-names = "pcie-0"; 30 status = "okay"; 31 }; 32 }; 33 34 host1x@50000000 { 35 dsi@54300000 { 36 status = "okay"; 37 38 avdd-dsi-csi-supply = <&vdd_dsi_csi>; 39 40 panel@0 { 41 compatible = "auo,b080uan01"; 42 reg = <0>; 43 44 enable-gpios = <&gpio TEGRA_GPIO(V, 2) 45 GPIO_ACTIVE_HIGH>; 46 power-supply = <&vdd_5v0_io>; 47 backlight = <&backlight>; 48 }; 49 }; 50 }; 51 52 i2c@7000c400 { 53 backlight: backlight@2c { 54 compatible = "ti,lp8557"; 55 reg = <0x2c>; 56 power-supply = <&vdd_3v3_sys>; 57 58 dev-ctrl = /bits/ 8 <0x80>; 59 init-brt = /bits/ 8 <0xff>; 60 61 pwm-period = <29334>; 62 63 pwms = <&pwm 0 29334>; 64 pwm-names = "lp8557"; 65 66 /* boost frequency 1 MHz */ 67 rom_13h { 68 rom-addr = /bits/ 8 <0x13>; 69 rom-val = /bits/ 8 <0x01>; 70 }; 71 72 /* 3 LED string */ 73 rom_14h { 74 rom-addr = /bits/ 8 <0x14>; 75 rom-val = /bits/ 8 <0x87>; 76 }; 77 }; 78 }; 79 80 i2c@7000c500 { 81 /* carrier board ID EEPROM */ 82 eeprom@57 { 83 compatible = "atmel,24c02"; 84 reg = <0x57>; 85 86 label = "system"; 87 vcc-supply = <&vdd_1v8>; 88 address-width = <8>; 89 pagesize = <8>; 90 size = <256>; 91 read-only; 92 }; 93 }; 94 95 clock@70110000 { 96 status = "okay"; 97 98 nvidia,cf = <6>; 99 nvidia,ci = <0>; 100 nvidia,cg = <2>; 101 nvidia,droop-ctrl = <0x00000f00>; 102 nvidia,force-mode = <1>; 103 nvidia,sample-rate = <25000>; 104 105 nvidia,pwm-min-microvolts = <708000>; 106 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 107 nvidia,pwm-to-pmic; 108 nvidia,pwm-tristate-microvolts = <1000000>; 109 nvidia,pwm-voltage-step-microvolts = <19200>; 110 111 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; 112 pinctrl-0 = <&dvfs_pwm_active_state>; 113 pinctrl-1 = <&dvfs_pwm_inactive_state>; 114 }; 115 116 aconnect@702c0000 { 117 status = "okay"; 118 119 ahub@702d0800 { 120 status = "okay"; 121 122 admaif@702d0000 { 123 status = "okay"; 124 }; 125 126 i2s@702d1000 { 127 status = "okay"; 128 129 ports { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 port@0 { 134 reg = <0>; 135 136 i2s1_cif_ep: endpoint { 137 remote-endpoint = <&xbar_i2s1_ep>; 138 }; 139 }; 140 141 i2s1_port: port@1 { 142 reg = <1>; 143 144 i2s1_dap_ep: endpoint { 145 dai-format = "i2s"; 146 /* Placeholder for external Codec */ 147 }; 148 }; 149 }; 150 }; 151 152 i2s@702d1100 { 153 status = "okay"; 154 155 ports { 156 #address-cells = <1>; 157 #size-cells = <0>; 158 159 port@0 { 160 reg = <0>; 161 162 i2s2_cif_ep: endpoint { 163 remote-endpoint = <&xbar_i2s2_ep>; 164 }; 165 }; 166 167 i2s2_port: port@1 { 168 reg = <1>; 169 170 i2s2_dap_ep: endpoint { 171 dai-format = "i2s"; 172 /* Placeholder for external Codec */ 173 }; 174 }; 175 }; 176 }; 177 178 i2s@702d1200 { 179 status = "okay"; 180 181 ports { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 185 port@0 { 186 reg = <0>; 187 188 i2s3_cif_ep: endpoint { 189 remote-endpoint = <&xbar_i2s3_ep>; 190 }; 191 }; 192 193 i2s3_port: port@1 { 194 reg = <1>; 195 196 i2s3_dap_ep: endpoint { 197 dai-format = "i2s"; 198 /* Placeholder for external Codec */ 199 }; 200 }; 201 }; 202 }; 203 204 i2s@702d1300 { 205 status = "okay"; 206 207 ports { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 211 port@0 { 212 reg = <0>; 213 214 i2s4_cif_ep: endpoint { 215 remote-endpoint = <&xbar_i2s4_ep>; 216 }; 217 }; 218 219 i2s4_port: port@1 { 220 reg = <1>; 221 222 i2s4_dap_ep: endpoint { 223 dai-format = "i2s"; 224 /* Placeholder for external Codec */ 225 }; 226 }; 227 }; 228 }; 229 230 i2s@702d1400 { 231 status = "okay"; 232 233 ports { 234 #address-cells = <1>; 235 #size-cells = <0>; 236 237 port@0 { 238 reg = <0>; 239 240 i2s5_cif_ep: endpoint { 241 remote-endpoint = <&xbar_i2s5_ep>; 242 }; 243 }; 244 245 i2s5_port: port@1 { 246 reg = <1>; 247 248 i2s5_dap_ep: endpoint { 249 dai-format = "i2s"; 250 /* Placeholder for external Codec */ 251 }; 252 }; 253 }; 254 }; 255 256 sfc@702d2000 { 257 status = "okay"; 258 259 ports { 260 #address-cells = <1>; 261 #size-cells = <0>; 262 263 port@0 { 264 reg = <0>; 265 266 sfc1_cif_in_ep: endpoint { 267 remote-endpoint = <&xbar_sfc1_in_ep>; 268 }; 269 }; 270 271 sfc1_out_port: port@1 { 272 reg = <1>; 273 274 sfc1_cif_out_ep: endpoint { 275 remote-endpoint = <&xbar_sfc1_out_ep>; 276 }; 277 }; 278 }; 279 }; 280 281 sfc@702d2200 { 282 status = "okay"; 283 284 ports { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 port@0 { 289 reg = <0>; 290 291 sfc2_cif_in_ep: endpoint { 292 remote-endpoint = <&xbar_sfc2_in_ep>; 293 }; 294 }; 295 296 sfc2_out_port: port@1 { 297 reg = <1>; 298 299 sfc2_cif_out_ep: endpoint { 300 remote-endpoint = <&xbar_sfc2_out_ep>; 301 }; 302 }; 303 }; 304 }; 305 306 sfc@702d2400 { 307 status = "okay"; 308 309 ports { 310 #address-cells = <1>; 311 #size-cells = <0>; 312 313 port@0 { 314 reg = <0>; 315 316 sfc3_cif_in_ep: endpoint { 317 remote-endpoint = <&xbar_sfc3_in_ep>; 318 }; 319 }; 320 321 sfc3_out_port: port@1 { 322 reg = <1>; 323 324 sfc3_cif_out_ep: endpoint { 325 remote-endpoint = <&xbar_sfc3_out_ep>; 326 }; 327 }; 328 }; 329 }; 330 331 sfc@702d2600 { 332 status = "okay"; 333 334 ports { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 338 port@0 { 339 reg = <0>; 340 341 sfc4_cif_in_ep: endpoint { 342 remote-endpoint = <&xbar_sfc4_in_ep>; 343 }; 344 }; 345 346 sfc4_out_port: port@1 { 347 reg = <1>; 348 349 sfc4_cif_out_ep: endpoint { 350 remote-endpoint = <&xbar_sfc4_out_ep>; 351 }; 352 }; 353 }; 354 }; 355 356 amx@702d3000 { 357 status = "okay"; 358 359 ports { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 363 port@0 { 364 reg = <0>; 365 366 amx1_in1_ep: endpoint { 367 remote-endpoint = <&xbar_amx1_in1_ep>; 368 }; 369 }; 370 371 port@1 { 372 reg = <1>; 373 374 amx1_in2_ep: endpoint { 375 remote-endpoint = <&xbar_amx1_in2_ep>; 376 }; 377 }; 378 379 port@2 { 380 reg = <2>; 381 382 amx1_in3_ep: endpoint { 383 remote-endpoint = <&xbar_amx1_in3_ep>; 384 }; 385 }; 386 387 port@3 { 388 reg = <3>; 389 390 amx1_in4_ep: endpoint { 391 remote-endpoint = <&xbar_amx1_in4_ep>; 392 }; 393 }; 394 395 amx1_out_port: port@4 { 396 reg = <4>; 397 398 amx1_out_ep: endpoint { 399 remote-endpoint = <&xbar_amx1_out_ep>; 400 }; 401 }; 402 }; 403 }; 404 405 amx@702d3100 { 406 status = "okay"; 407 408 ports { 409 #address-cells = <1>; 410 #size-cells = <0>; 411 412 port@0 { 413 reg = <0>; 414 415 amx2_in1_ep: endpoint { 416 remote-endpoint = <&xbar_amx2_in1_ep>; 417 }; 418 }; 419 420 port@1 { 421 reg = <1>; 422 423 amx2_in2_ep: endpoint { 424 remote-endpoint = <&xbar_amx2_in2_ep>; 425 }; 426 }; 427 428 amx2_in3_port: port@2 { 429 reg = <2>; 430 431 amx2_in3_ep: endpoint { 432 remote-endpoint = <&xbar_amx2_in3_ep>; 433 }; 434 }; 435 436 amx2_in4_port: port@3 { 437 reg = <3>; 438 439 amx2_in4_ep: endpoint { 440 remote-endpoint = <&xbar_amx2_in4_ep>; 441 }; 442 }; 443 444 amx2_out_port: port@4 { 445 reg = <4>; 446 447 amx2_out_ep: endpoint { 448 remote-endpoint = <&xbar_amx2_out_ep>; 449 }; 450 }; 451 }; 452 }; 453 454 adx@702d3800 { 455 status = "okay"; 456 457 ports { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 461 port@0 { 462 reg = <0>; 463 464 adx1_in_ep: endpoint { 465 remote-endpoint = <&xbar_adx1_in_ep>; 466 }; 467 }; 468 469 adx1_out1_port: port@1 { 470 reg = <1>; 471 472 adx1_out1_ep: endpoint { 473 remote-endpoint = <&xbar_adx1_out1_ep>; 474 }; 475 }; 476 477 adx1_out2_port: port@2 { 478 reg = <2>; 479 480 adx1_out2_ep: endpoint { 481 remote-endpoint = <&xbar_adx1_out2_ep>; 482 }; 483 }; 484 485 adx1_out3_port: port@3 { 486 reg = <3>; 487 488 adx1_out3_ep: endpoint { 489 remote-endpoint = <&xbar_adx1_out3_ep>; 490 }; 491 }; 492 493 adx1_out4_port: port@4 { 494 reg = <4>; 495 496 adx1_out4_ep: endpoint { 497 remote-endpoint = <&xbar_adx1_out4_ep>; 498 }; 499 }; 500 }; 501 }; 502 503 adx@702d3900 { 504 status = "okay"; 505 506 ports { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 510 port@0 { 511 reg = <0>; 512 513 adx2_in_ep: endpoint { 514 remote-endpoint = <&xbar_adx2_in_ep>; 515 }; 516 }; 517 518 adx2_out1_port: port@1 { 519 reg = <1>; 520 521 adx2_out1_ep: endpoint { 522 remote-endpoint = <&xbar_adx2_out1_ep>; 523 }; 524 }; 525 526 adx2_out2_port: port@2 { 527 reg = <2>; 528 529 adx2_out2_ep: endpoint { 530 remote-endpoint = <&xbar_adx2_out2_ep>; 531 }; 532 }; 533 534 adx2_out3_port: port@3 { 535 reg = <3>; 536 537 adx2_out3_ep: endpoint { 538 remote-endpoint = <&xbar_adx2_out3_ep>; 539 }; 540 }; 541 542 adx2_out4_port: port@4 { 543 reg = <4>; 544 545 adx2_out4_ep: endpoint { 546 remote-endpoint = <&xbar_adx2_out4_ep>; 547 }; 548 }; 549 }; 550 }; 551 552 dmic@702d4000 { 553 status = "okay"; 554 555 ports { 556 #address-cells = <1>; 557 #size-cells = <0>; 558 559 port@0 { 560 reg = <0>; 561 562 dmic1_cif_ep: endpoint { 563 remote-endpoint = <&xbar_dmic1_ep>; 564 }; 565 }; 566 567 dmic1_port: port@1 { 568 reg = <1>; 569 570 dmic1_dap_ep: endpoint { 571 /* Placeholder for external Codec */ 572 }; 573 }; 574 }; 575 }; 576 577 dmic@702d4100 { 578 status = "okay"; 579 580 ports { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 584 port@0 { 585 reg = <0>; 586 587 dmic2_cif_ep: endpoint { 588 remote-endpoint = <&xbar_dmic2_ep>; 589 }; 590 }; 591 592 dmic2_port: port@1 { 593 reg = <1>; 594 595 dmic2_dap_ep: endpoint { 596 /* Placeholder for external Codec */ 597 }; 598 }; 599 }; 600 }; 601 602 dmic@702d4200 { 603 status = "okay"; 604 605 ports { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 609 port@0 { 610 reg = <0>; 611 612 dmic3_cif_ep: endpoint { 613 remote-endpoint = <&xbar_dmic3_ep>; 614 }; 615 }; 616 617 dmic3_port: port@1 { 618 reg = <1>; 619 620 dmic3_dap_ep: endpoint { 621 /* Placeholder for external Codec */ 622 }; 623 }; 624 }; 625 }; 626 627 processing-engine@702d8000 { 628 status = "okay"; 629 630 ports { 631 #address-cells = <1>; 632 #size-cells = <0>; 633 634 port@0 { 635 reg = <0x0>; 636 637 ope1_cif_in_ep: endpoint { 638 remote-endpoint = <&xbar_ope1_in_ep>; 639 }; 640 }; 641 642 ope1_out_port: port@1 { 643 reg = <0x1>; 644 645 ope1_cif_out_ep: endpoint { 646 remote-endpoint = <&xbar_ope1_out_ep>; 647 }; 648 }; 649 }; 650 }; 651 652 processing-engine@702d8400 { 653 status = "okay"; 654 655 ports { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 659 port@0 { 660 reg = <0x0>; 661 662 ope2_cif_in_ep: endpoint { 663 remote-endpoint = <&xbar_ope2_in_ep>; 664 }; 665 }; 666 667 ope2_out_port: port@1 { 668 reg = <0x1>; 669 670 ope2_cif_out_ep: endpoint { 671 remote-endpoint = <&xbar_ope2_out_ep>; 672 }; 673 }; 674 }; 675 }; 676 677 mvc@702da000 { 678 status = "okay"; 679 680 ports { 681 #address-cells = <1>; 682 #size-cells = <0>; 683 684 port@0 { 685 reg = <0>; 686 687 mvc1_cif_in_ep: endpoint { 688 remote-endpoint = <&xbar_mvc1_in_ep>; 689 }; 690 }; 691 692 mvc1_out_port: port@1 { 693 reg = <1>; 694 695 mvc1_cif_out_ep: endpoint { 696 remote-endpoint = <&xbar_mvc1_out_ep>; 697 }; 698 }; 699 }; 700 }; 701 702 mvc@702da200 { 703 status = "okay"; 704 705 ports { 706 #address-cells = <1>; 707 #size-cells = <0>; 708 709 port@0 { 710 reg = <0>; 711 712 mvc2_cif_in_ep: endpoint { 713 remote-endpoint = <&xbar_mvc2_in_ep>; 714 }; 715 }; 716 717 mvc2_out_port: port@1 { 718 reg = <1>; 719 720 mvc2_cif_out_ep: endpoint { 721 remote-endpoint = <&xbar_mvc2_out_ep>; 722 }; 723 }; 724 }; 725 }; 726 727 amixer@702dbb00 { 728 status = "okay"; 729 730 ports { 731 #address-cells = <1>; 732 #size-cells = <0>; 733 734 port@0 { 735 reg = <0x0>; 736 737 mixer_in1_ep: endpoint { 738 remote-endpoint = <&xbar_mixer_in1_ep>; 739 }; 740 }; 741 742 port@1 { 743 reg = <0x1>; 744 745 mixer_in2_ep: endpoint { 746 remote-endpoint = <&xbar_mixer_in2_ep>; 747 }; 748 }; 749 750 port@2 { 751 reg = <0x2>; 752 753 mixer_in3_ep: endpoint { 754 remote-endpoint = <&xbar_mixer_in3_ep>; 755 }; 756 }; 757 758 port@3 { 759 reg = <0x3>; 760 761 mixer_in4_ep: endpoint { 762 remote-endpoint = <&xbar_mixer_in4_ep>; 763 }; 764 }; 765 766 port@4 { 767 reg = <0x4>; 768 769 mixer_in5_ep: endpoint { 770 remote-endpoint = <&xbar_mixer_in5_ep>; 771 }; 772 }; 773 774 port@5 { 775 reg = <0x5>; 776 777 mixer_in6_ep: endpoint { 778 remote-endpoint = <&xbar_mixer_in6_ep>; 779 }; 780 }; 781 782 port@6 { 783 reg = <0x6>; 784 785 mixer_in7_ep: endpoint { 786 remote-endpoint = <&xbar_mixer_in7_ep>; 787 }; 788 }; 789 790 port@7 { 791 reg = <0x7>; 792 793 mixer_in8_ep: endpoint { 794 remote-endpoint = <&xbar_mixer_in8_ep>; 795 }; 796 }; 797 798 port@8 { 799 reg = <0x8>; 800 801 mixer_in9_ep: endpoint { 802 remote-endpoint = <&xbar_mixer_in9_ep>; 803 }; 804 }; 805 806 port@9 { 807 reg = <0x9>; 808 809 mixer_in10_ep: endpoint { 810 remote-endpoint = <&xbar_mixer_in10_ep>; 811 }; 812 }; 813 814 mixer_out1_port: port@a { 815 reg = <0xa>; 816 817 mixer_out1_ep: endpoint { 818 remote-endpoint = <&xbar_mixer_out1_ep>; 819 }; 820 }; 821 822 mixer_out2_port: port@b { 823 reg = <0xb>; 824 825 mixer_out2_ep: endpoint { 826 remote-endpoint = <&xbar_mixer_out2_ep>; 827 }; 828 }; 829 830 mixer_out3_port: port@c { 831 reg = <0xc>; 832 833 mixer_out3_ep: endpoint { 834 remote-endpoint = <&xbar_mixer_out3_ep>; 835 }; 836 }; 837 838 mixer_out4_port: port@d { 839 reg = <0xd>; 840 841 mixer_out4_ep: endpoint { 842 remote-endpoint = <&xbar_mixer_out4_ep>; 843 }; 844 }; 845 846 mixer_out5_port: port@e { 847 reg = <0xe>; 848 849 mixer_out5_ep: endpoint { 850 remote-endpoint = <&xbar_mixer_out5_ep>; 851 }; 852 }; 853 }; 854 }; 855 856 ports { 857 xbar_i2s1_port: port@a { 858 reg = <0xa>; 859 860 xbar_i2s1_ep: endpoint { 861 remote-endpoint = <&i2s1_cif_ep>; 862 }; 863 }; 864 865 xbar_i2s2_port: port@b { 866 reg = <0xb>; 867 868 xbar_i2s2_ep: endpoint { 869 remote-endpoint = <&i2s2_cif_ep>; 870 }; 871 }; 872 873 xbar_i2s3_port: port@c { 874 reg = <0xc>; 875 876 xbar_i2s3_ep: endpoint { 877 remote-endpoint = <&i2s3_cif_ep>; 878 }; 879 }; 880 881 xbar_i2s4_port: port@d { 882 reg = <0xd>; 883 884 xbar_i2s4_ep: endpoint { 885 remote-endpoint = <&i2s4_cif_ep>; 886 }; 887 }; 888 889 xbar_i2s5_port: port@e { 890 reg = <0xe>; 891 892 xbar_i2s5_ep: endpoint { 893 remote-endpoint = <&i2s5_cif_ep>; 894 }; 895 }; 896 897 xbar_dmic1_port: port@f { 898 reg = <0xf>; 899 900 xbar_dmic1_ep: endpoint { 901 remote-endpoint = <&dmic1_cif_ep>; 902 }; 903 }; 904 905 xbar_dmic2_port: port@10 { 906 reg = <0x10>; 907 908 xbar_dmic2_ep: endpoint { 909 remote-endpoint = <&dmic2_cif_ep>; 910 }; 911 }; 912 913 xbar_dmic3_port: port@11 { 914 reg = <0x11>; 915 916 xbar_dmic3_ep: endpoint { 917 remote-endpoint = <&dmic3_cif_ep>; 918 }; 919 }; 920 921 xbar_sfc1_in_port: port@12 { 922 reg = <0x12>; 923 924 xbar_sfc1_in_ep: endpoint { 925 remote-endpoint = <&sfc1_cif_in_ep>; 926 }; 927 }; 928 929 port@13 { 930 reg = <0x13>; 931 932 xbar_sfc1_out_ep: endpoint { 933 remote-endpoint = <&sfc1_cif_out_ep>; 934 }; 935 }; 936 937 xbar_sfc2_in_port: port@14 { 938 reg = <0x14>; 939 940 xbar_sfc2_in_ep: endpoint { 941 remote-endpoint = <&sfc2_cif_in_ep>; 942 }; 943 }; 944 945 port@15 { 946 reg = <0x15>; 947 948 xbar_sfc2_out_ep: endpoint { 949 remote-endpoint = <&sfc2_cif_out_ep>; 950 }; 951 }; 952 953 xbar_sfc3_in_port: port@16 { 954 reg = <0x16>; 955 956 xbar_sfc3_in_ep: endpoint { 957 remote-endpoint = <&sfc3_cif_in_ep>; 958 }; 959 }; 960 961 port@17 { 962 reg = <0x17>; 963 964 xbar_sfc3_out_ep: endpoint { 965 remote-endpoint = <&sfc3_cif_out_ep>; 966 }; 967 }; 968 969 xbar_sfc4_in_port: port@18 { 970 reg = <0x18>; 971 972 xbar_sfc4_in_ep: endpoint { 973 remote-endpoint = <&sfc4_cif_in_ep>; 974 }; 975 }; 976 977 port@19 { 978 reg = <0x19>; 979 980 xbar_sfc4_out_ep: endpoint { 981 remote-endpoint = <&sfc4_cif_out_ep>; 982 }; 983 }; 984 985 xbar_mvc1_in_port: port@1a { 986 reg = <0x1a>; 987 988 xbar_mvc1_in_ep: endpoint { 989 remote-endpoint = <&mvc1_cif_in_ep>; 990 }; 991 }; 992 993 port@1b { 994 reg = <0x1b>; 995 996 xbar_mvc1_out_ep: endpoint { 997 remote-endpoint = <&mvc1_cif_out_ep>; 998 }; 999 }; 1000 1001 xbar_mvc2_in_port: port@1c { 1002 reg = <0x1c>; 1003 1004 xbar_mvc2_in_ep: endpoint { 1005 remote-endpoint = <&mvc2_cif_in_ep>; 1006 }; 1007 }; 1008 1009 port@1d { 1010 reg = <0x1d>; 1011 1012 xbar_mvc2_out_ep: endpoint { 1013 remote-endpoint = <&mvc2_cif_out_ep>; 1014 }; 1015 }; 1016 1017 xbar_amx1_in1_port: port@1e { 1018 reg = <0x1e>; 1019 1020 xbar_amx1_in1_ep: endpoint { 1021 remote-endpoint = <&amx1_in1_ep>; 1022 }; 1023 }; 1024 1025 xbar_amx1_in2_port: port@1f { 1026 reg = <0x1f>; 1027 1028 xbar_amx1_in2_ep: endpoint { 1029 remote-endpoint = <&amx1_in2_ep>; 1030 }; 1031 }; 1032 1033 xbar_amx1_in3_port: port@20 { 1034 reg = <0x20>; 1035 1036 xbar_amx1_in3_ep: endpoint { 1037 remote-endpoint = <&amx1_in3_ep>; 1038 }; 1039 }; 1040 1041 xbar_amx1_in4_port: port@21 { 1042 reg = <0x21>; 1043 1044 xbar_amx1_in4_ep: endpoint { 1045 remote-endpoint = <&amx1_in4_ep>; 1046 }; 1047 }; 1048 1049 port@22 { 1050 reg = <0x22>; 1051 1052 xbar_amx1_out_ep: endpoint { 1053 remote-endpoint = <&amx1_out_ep>; 1054 }; 1055 }; 1056 1057 xbar_amx2_in1_port: port@23 { 1058 reg = <0x23>; 1059 1060 xbar_amx2_in1_ep: endpoint { 1061 remote-endpoint = <&amx2_in1_ep>; 1062 }; 1063 }; 1064 1065 xbar_amx2_in2_port: port@24 { 1066 reg = <0x24>; 1067 1068 xbar_amx2_in2_ep: endpoint { 1069 remote-endpoint = <&amx2_in2_ep>; 1070 }; 1071 }; 1072 1073 xbar_amx2_in3_port: port@25 { 1074 reg = <0x25>; 1075 1076 xbar_amx2_in3_ep: endpoint { 1077 remote-endpoint = <&amx2_in3_ep>; 1078 }; 1079 }; 1080 1081 xbar_amx2_in4_port: port@26 { 1082 reg = <0x26>; 1083 1084 xbar_amx2_in4_ep: endpoint { 1085 remote-endpoint = <&amx2_in4_ep>; 1086 }; 1087 }; 1088 1089 port@27 { 1090 reg = <0x27>; 1091 1092 xbar_amx2_out_ep: endpoint { 1093 remote-endpoint = <&amx2_out_ep>; 1094 }; 1095 }; 1096 1097 xbar_adx1_in_port: port@28 { 1098 reg = <0x28>; 1099 1100 xbar_adx1_in_ep: endpoint { 1101 remote-endpoint = <&adx1_in_ep>; 1102 }; 1103 }; 1104 1105 port@29 { 1106 reg = <0x29>; 1107 1108 xbar_adx1_out1_ep: endpoint { 1109 remote-endpoint = <&adx1_out1_ep>; 1110 }; 1111 }; 1112 1113 port@2a { 1114 reg = <0x2a>; 1115 1116 xbar_adx1_out2_ep: endpoint { 1117 remote-endpoint = <&adx1_out2_ep>; 1118 }; 1119 }; 1120 1121 port@2b { 1122 reg = <0x2b>; 1123 1124 xbar_adx1_out3_ep: endpoint { 1125 remote-endpoint = <&adx1_out3_ep>; 1126 }; 1127 }; 1128 1129 port@2c { 1130 reg = <0x2c>; 1131 1132 xbar_adx1_out4_ep: endpoint { 1133 remote-endpoint = <&adx1_out4_ep>; 1134 }; 1135 }; 1136 1137 xbar_adx2_in_port: port@2d { 1138 reg = <0x2d>; 1139 1140 xbar_adx2_in_ep: endpoint { 1141 remote-endpoint = <&adx2_in_ep>; 1142 }; 1143 }; 1144 1145 port@2e { 1146 reg = <0x2e>; 1147 1148 xbar_adx2_out1_ep: endpoint { 1149 remote-endpoint = <&adx2_out1_ep>; 1150 }; 1151 }; 1152 1153 port@2f { 1154 reg = <0x2f>; 1155 1156 xbar_adx2_out2_ep: endpoint { 1157 remote-endpoint = <&adx2_out2_ep>; 1158 }; 1159 }; 1160 1161 port@30 { 1162 reg = <0x30>; 1163 1164 xbar_adx2_out3_ep: endpoint { 1165 remote-endpoint = <&adx2_out3_ep>; 1166 }; 1167 }; 1168 1169 port@31 { 1170 reg = <0x31>; 1171 1172 xbar_adx2_out4_ep: endpoint { 1173 remote-endpoint = <&adx2_out4_ep>; 1174 }; 1175 }; 1176 1177 xbar_mixer_in1_port: port@32 { 1178 reg = <0x32>; 1179 1180 xbar_mixer_in1_ep: endpoint { 1181 remote-endpoint = <&mixer_in1_ep>; 1182 }; 1183 }; 1184 1185 xbar_mixer_in2_port: port@33 { 1186 reg = <0x33>; 1187 1188 xbar_mixer_in2_ep: endpoint { 1189 remote-endpoint = <&mixer_in2_ep>; 1190 }; 1191 }; 1192 1193 xbar_mixer_in3_port: port@34 { 1194 reg = <0x34>; 1195 1196 xbar_mixer_in3_ep: endpoint { 1197 remote-endpoint = <&mixer_in3_ep>; 1198 }; 1199 }; 1200 1201 xbar_mixer_in4_port: port@35 { 1202 reg = <0x35>; 1203 1204 xbar_mixer_in4_ep: endpoint { 1205 remote-endpoint = <&mixer_in4_ep>; 1206 }; 1207 }; 1208 1209 xbar_mixer_in5_port: port@36 { 1210 reg = <0x36>; 1211 1212 xbar_mixer_in5_ep: endpoint { 1213 remote-endpoint = <&mixer_in5_ep>; 1214 }; 1215 }; 1216 1217 xbar_mixer_in6_port: port@37 { 1218 reg = <0x37>; 1219 1220 xbar_mixer_in6_ep: endpoint { 1221 remote-endpoint = <&mixer_in6_ep>; 1222 }; 1223 }; 1224 1225 xbar_mixer_in7_port: port@38 { 1226 reg = <0x38>; 1227 1228 xbar_mixer_in7_ep: endpoint { 1229 remote-endpoint = <&mixer_in7_ep>; 1230 }; 1231 }; 1232 1233 xbar_mixer_in8_port: port@39 { 1234 reg = <0x39>; 1235 1236 xbar_mixer_in8_ep: endpoint { 1237 remote-endpoint = <&mixer_in8_ep>; 1238 }; 1239 }; 1240 1241 xbar_mixer_in9_port: port@3a { 1242 reg = <0x3a>; 1243 1244 xbar_mixer_in9_ep: endpoint { 1245 remote-endpoint = <&mixer_in9_ep>; 1246 }; 1247 }; 1248 1249 xbar_mixer_in10_port: port@3b { 1250 reg = <0x3b>; 1251 1252 xbar_mixer_in10_ep: endpoint { 1253 remote-endpoint = <&mixer_in10_ep>; 1254 }; 1255 }; 1256 1257 port@3c { 1258 reg = <0x3c>; 1259 1260 xbar_mixer_out1_ep: endpoint { 1261 remote-endpoint = <&mixer_out1_ep>; 1262 }; 1263 }; 1264 1265 port@3d { 1266 reg = <0x3d>; 1267 1268 xbar_mixer_out2_ep: endpoint { 1269 remote-endpoint = <&mixer_out2_ep>; 1270 }; 1271 }; 1272 1273 port@3e { 1274 reg = <0x3e>; 1275 1276 xbar_mixer_out3_ep: endpoint { 1277 remote-endpoint = <&mixer_out3_ep>; 1278 }; 1279 }; 1280 1281 port@3f { 1282 reg = <0x3f>; 1283 1284 xbar_mixer_out4_ep: endpoint { 1285 remote-endpoint = <&mixer_out4_ep>; 1286 }; 1287 }; 1288 1289 port@40 { 1290 reg = <0x40>; 1291 1292 xbar_mixer_out5_ep: endpoint { 1293 remote-endpoint = <&mixer_out5_ep>; 1294 }; 1295 }; 1296 1297 xbar_ope1_in_port: port@41 { 1298 reg = <0x41>; 1299 1300 xbar_ope1_in_ep: endpoint { 1301 remote-endpoint = <&ope1_cif_in_ep>; 1302 }; 1303 }; 1304 1305 port@42 { 1306 reg = <0x42>; 1307 1308 xbar_ope1_out_ep: endpoint { 1309 remote-endpoint = <&ope1_cif_out_ep>; 1310 }; 1311 }; 1312 1313 xbar_ope2_in_port: port@43 { 1314 reg = <0x43>; 1315 1316 xbar_ope2_in_ep: endpoint { 1317 remote-endpoint = <&ope2_cif_in_ep>; 1318 }; 1319 }; 1320 1321 port@44 { 1322 reg = <0x44>; 1323 1324 xbar_ope2_out_ep: endpoint { 1325 remote-endpoint = <&ope2_cif_out_ep>; 1326 }; 1327 }; 1328 }; 1329 }; 1330 1331 dma-controller@702e2000 { 1332 status = "okay"; 1333 }; 1334 1335 interrupt-controller@702f9000 { 1336 status = "okay"; 1337 }; 1338 }; 1339 1340 sound { 1341 compatible = "nvidia,tegra210-audio-graph-card"; 1342 status = "okay"; 1343 1344 dais = /* FE */ 1345 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 1346 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, 1347 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, 1348 <&admaif10_port>, 1349 /* Router */ 1350 <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, 1351 <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>, 1352 <&xbar_dmic2_port>, <&xbar_dmic3_port>, 1353 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 1354 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 1355 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 1356 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 1357 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 1358 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 1359 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 1360 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 1361 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 1362 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 1363 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 1364 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 1365 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 1366 <&xbar_ope1_in_port>, <&xbar_ope2_in_port>, 1367 /* HW accelerators */ 1368 <&sfc1_out_port>, <&sfc2_out_port>, 1369 <&sfc3_out_port>, <&sfc4_out_port>, 1370 <&mvc1_out_port>, <&mvc2_out_port>, 1371 <&amx1_out_port>, <&amx2_out_port>, 1372 <&adx1_out1_port>, <&adx1_out2_port>, 1373 <&adx1_out3_port>, <&adx1_out4_port>, 1374 <&adx2_out1_port>, <&adx2_out2_port>, 1375 <&adx2_out3_port>, <&adx2_out4_port>, 1376 <&mixer_out1_port>, <&mixer_out2_port>, 1377 <&mixer_out3_port>, <&mixer_out4_port>, 1378 <&mixer_out5_port>, 1379 <&ope1_out_port>, <&ope2_out_port>, 1380 /* I/O DAP Ports */ 1381 <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, 1382 <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>; 1383 1384 label = "NVIDIA Jetson TX1 APE"; 1385 }; 1386}; 1387