1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 aconnect { 77 compatible = "nvidia,tegra186-aconnect", 78 "nvidia,tegra210-aconnect"; 79 clocks = <&bpmp TEGRA186_CLK_APE>, 80 <&bpmp TEGRA186_CLK_APB2APE>; 81 clock-names = "ape", "apb2ape"; 82 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0x02900000 0x0 0x02900000 0x200000>; 86 status = "disabled"; 87 88 dma-controller@2930000 { 89 compatible = "nvidia,tegra186-adma"; 90 reg = <0x02930000 0x20000>; 91 interrupt-parent = <&agic>; 92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 124 #dma-cells = <1>; 125 clocks = <&bpmp TEGRA186_CLK_AHUB>; 126 clock-names = "d_audio"; 127 status = "disabled"; 128 }; 129 130 agic: interrupt-controller@2a40000 { 131 compatible = "nvidia,tegra186-agic", 132 "nvidia,tegra210-agic"; 133 #interrupt-cells = <3>; 134 interrupt-controller; 135 reg = <0x02a41000 0x1000>, 136 <0x02a42000 0x2000>; 137 interrupts = <GIC_SPI 145 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA186_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 }; 144 145 mc: memory-controller@2c00000 { 146 compatible = "nvidia,tegra186-mc"; 147 reg = <0x0 0x02c00000 0x0 0xb0000>; 148 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 149 status = "disabled"; 150 151 #interconnect-cells = <1>; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 155 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 156 157 /* 158 * Memory clients have access to all 40 bits that the memory 159 * controller can address. 160 */ 161 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 162 163 emc: external-memory-controller@2c60000 { 164 compatible = "nvidia,tegra186-emc"; 165 reg = <0x0 0x02c60000 0x0 0x50000>; 166 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&bpmp TEGRA186_CLK_EMC>; 168 clock-names = "emc"; 169 170 #interconnect-cells = <0>; 171 172 nvidia,bpmp = <&bpmp>; 173 }; 174 }; 175 176 uarta: serial@3100000 { 177 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 178 reg = <0x0 0x03100000 0x0 0x40>; 179 reg-shift = <2>; 180 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&bpmp TEGRA186_CLK_UARTA>; 182 clock-names = "serial"; 183 resets = <&bpmp TEGRA186_RESET_UARTA>; 184 reset-names = "serial"; 185 status = "disabled"; 186 }; 187 188 uartb: serial@3110000 { 189 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 190 reg = <0x0 0x03110000 0x0 0x40>; 191 reg-shift = <2>; 192 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&bpmp TEGRA186_CLK_UARTB>; 194 clock-names = "serial"; 195 resets = <&bpmp TEGRA186_RESET_UARTB>; 196 reset-names = "serial"; 197 status = "disabled"; 198 }; 199 200 uartd: serial@3130000 { 201 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 202 reg = <0x0 0x03130000 0x0 0x40>; 203 reg-shift = <2>; 204 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&bpmp TEGRA186_CLK_UARTD>; 206 clock-names = "serial"; 207 resets = <&bpmp TEGRA186_RESET_UARTD>; 208 reset-names = "serial"; 209 status = "disabled"; 210 }; 211 212 uarte: serial@3140000 { 213 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 214 reg = <0x0 0x03140000 0x0 0x40>; 215 reg-shift = <2>; 216 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&bpmp TEGRA186_CLK_UARTE>; 218 clock-names = "serial"; 219 resets = <&bpmp TEGRA186_RESET_UARTE>; 220 reset-names = "serial"; 221 status = "disabled"; 222 }; 223 224 uartf: serial@3150000 { 225 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 226 reg = <0x0 0x03150000 0x0 0x40>; 227 reg-shift = <2>; 228 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&bpmp TEGRA186_CLK_UARTF>; 230 clock-names = "serial"; 231 resets = <&bpmp TEGRA186_RESET_UARTF>; 232 reset-names = "serial"; 233 status = "disabled"; 234 }; 235 236 gen1_i2c: i2c@3160000 { 237 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 238 reg = <0x0 0x03160000 0x0 0x10000>; 239 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 clocks = <&bpmp TEGRA186_CLK_I2C1>; 243 clock-names = "div-clk"; 244 resets = <&bpmp TEGRA186_RESET_I2C1>; 245 reset-names = "i2c"; 246 status = "disabled"; 247 }; 248 249 cam_i2c: i2c@3180000 { 250 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 251 reg = <0x0 0x03180000 0x0 0x10000>; 252 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 clocks = <&bpmp TEGRA186_CLK_I2C3>; 256 clock-names = "div-clk"; 257 resets = <&bpmp TEGRA186_RESET_I2C3>; 258 reset-names = "i2c"; 259 status = "disabled"; 260 }; 261 262 /* shares pads with dpaux1 */ 263 dp_aux_ch1_i2c: i2c@3190000 { 264 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 265 reg = <0x0 0x03190000 0x0 0x10000>; 266 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 clocks = <&bpmp TEGRA186_CLK_I2C4>; 270 clock-names = "div-clk"; 271 resets = <&bpmp TEGRA186_RESET_I2C4>; 272 reset-names = "i2c"; 273 pinctrl-names = "default", "idle"; 274 pinctrl-0 = <&state_dpaux1_i2c>; 275 pinctrl-1 = <&state_dpaux1_off>; 276 status = "disabled"; 277 }; 278 279 /* controlled by BPMP, should not be enabled */ 280 pwr_i2c: i2c@31a0000 { 281 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 282 reg = <0x0 0x031a0000 0x0 0x10000>; 283 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clocks = <&bpmp TEGRA186_CLK_I2C5>; 287 clock-names = "div-clk"; 288 resets = <&bpmp TEGRA186_RESET_I2C5>; 289 reset-names = "i2c"; 290 status = "disabled"; 291 }; 292 293 /* shares pads with dpaux0 */ 294 dp_aux_ch0_i2c: i2c@31b0000 { 295 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 296 reg = <0x0 0x031b0000 0x0 0x10000>; 297 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 clocks = <&bpmp TEGRA186_CLK_I2C6>; 301 clock-names = "div-clk"; 302 resets = <&bpmp TEGRA186_RESET_I2C6>; 303 reset-names = "i2c"; 304 pinctrl-names = "default", "idle"; 305 pinctrl-0 = <&state_dpaux_i2c>; 306 pinctrl-1 = <&state_dpaux_off>; 307 status = "disabled"; 308 }; 309 310 gen7_i2c: i2c@31c0000 { 311 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 312 reg = <0x0 0x031c0000 0x0 0x10000>; 313 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 clocks = <&bpmp TEGRA186_CLK_I2C7>; 317 clock-names = "div-clk"; 318 resets = <&bpmp TEGRA186_RESET_I2C7>; 319 reset-names = "i2c"; 320 status = "disabled"; 321 }; 322 323 gen9_i2c: i2c@31e0000 { 324 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 325 reg = <0x0 0x031e0000 0x0 0x10000>; 326 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 clocks = <&bpmp TEGRA186_CLK_I2C9>; 330 clock-names = "div-clk"; 331 resets = <&bpmp TEGRA186_RESET_I2C9>; 332 reset-names = "i2c"; 333 status = "disabled"; 334 }; 335 336 sdmmc1: mmc@3400000 { 337 compatible = "nvidia,tegra186-sdhci"; 338 reg = <0x0 0x03400000 0x0 0x10000>; 339 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 341 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 342 clock-names = "sdhci", "tmclk"; 343 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 344 reset-names = "sdhci"; 345 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 346 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 347 interconnect-names = "dma-mem", "write"; 348 iommus = <&smmu TEGRA186_SID_SDMMC1>; 349 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 350 pinctrl-0 = <&sdmmc1_3v3>; 351 pinctrl-1 = <&sdmmc1_1v8>; 352 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 353 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 354 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 355 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 356 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 357 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 358 nvidia,default-tap = <0x5>; 359 nvidia,default-trim = <0xb>; 360 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 361 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 362 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 363 status = "disabled"; 364 }; 365 366 sdmmc2: mmc@3420000 { 367 compatible = "nvidia,tegra186-sdhci"; 368 reg = <0x0 0x03420000 0x0 0x10000>; 369 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 371 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 372 clock-names = "sdhci", "tmclk"; 373 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 374 reset-names = "sdhci"; 375 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 376 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 377 interconnect-names = "dma-mem", "write"; 378 iommus = <&smmu TEGRA186_SID_SDMMC2>; 379 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 380 pinctrl-0 = <&sdmmc2_3v3>; 381 pinctrl-1 = <&sdmmc2_1v8>; 382 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 383 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 384 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 385 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 386 nvidia,default-tap = <0x5>; 387 nvidia,default-trim = <0xb>; 388 status = "disabled"; 389 }; 390 391 sdmmc3: mmc@3440000 { 392 compatible = "nvidia,tegra186-sdhci"; 393 reg = <0x0 0x03440000 0x0 0x10000>; 394 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 396 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 397 clock-names = "sdhci", "tmclk"; 398 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 399 reset-names = "sdhci"; 400 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 401 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 402 interconnect-names = "dma-mem", "write"; 403 iommus = <&smmu TEGRA186_SID_SDMMC3>; 404 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 405 pinctrl-0 = <&sdmmc3_3v3>; 406 pinctrl-1 = <&sdmmc3_1v8>; 407 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 408 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 409 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 410 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 411 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 412 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 413 nvidia,default-tap = <0x5>; 414 nvidia,default-trim = <0xb>; 415 status = "disabled"; 416 }; 417 418 sdmmc4: mmc@3460000 { 419 compatible = "nvidia,tegra186-sdhci"; 420 reg = <0x0 0x03460000 0x0 0x10000>; 421 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 423 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 424 clock-names = "sdhci", "tmclk"; 425 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 426 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 427 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 428 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 429 reset-names = "sdhci"; 430 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 431 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 432 interconnect-names = "dma-mem", "write"; 433 iommus = <&smmu TEGRA186_SID_SDMMC4>; 434 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 435 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 436 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 437 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 438 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 439 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 440 nvidia,default-tap = <0x9>; 441 nvidia,default-trim = <0x5>; 442 nvidia,dqs-trim = <63>; 443 mmc-hs400-1_8v; 444 supports-cqe; 445 status = "disabled"; 446 }; 447 448 hda@3510000 { 449 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 450 reg = <0x0 0x03510000 0x0 0x10000>; 451 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&bpmp TEGRA186_CLK_HDA>, 453 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 454 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 455 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 456 resets = <&bpmp TEGRA186_RESET_HDA>, 457 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 458 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 459 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 460 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 461 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 462 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 463 interconnect-names = "dma-mem", "write"; 464 iommus = <&smmu TEGRA186_SID_HDA>; 465 status = "disabled"; 466 }; 467 468 padctl: padctl@3520000 { 469 compatible = "nvidia,tegra186-xusb-padctl"; 470 reg = <0x0 0x03520000 0x0 0x1000>, 471 <0x0 0x03540000 0x0 0x1000>; 472 reg-names = "padctl", "ao"; 473 474 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 475 reset-names = "padctl"; 476 477 status = "disabled"; 478 479 pads { 480 usb2 { 481 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 482 clock-names = "trk"; 483 status = "disabled"; 484 485 lanes { 486 usb2-0 { 487 status = "disabled"; 488 #phy-cells = <0>; 489 }; 490 491 usb2-1 { 492 status = "disabled"; 493 #phy-cells = <0>; 494 }; 495 496 usb2-2 { 497 status = "disabled"; 498 #phy-cells = <0>; 499 }; 500 }; 501 }; 502 503 hsic { 504 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 505 clock-names = "trk"; 506 status = "disabled"; 507 508 lanes { 509 hsic-0 { 510 status = "disabled"; 511 #phy-cells = <0>; 512 }; 513 }; 514 }; 515 516 usb3 { 517 status = "disabled"; 518 519 lanes { 520 usb3-0 { 521 status = "disabled"; 522 #phy-cells = <0>; 523 }; 524 525 usb3-1 { 526 status = "disabled"; 527 #phy-cells = <0>; 528 }; 529 530 usb3-2 { 531 status = "disabled"; 532 #phy-cells = <0>; 533 }; 534 }; 535 }; 536 }; 537 538 ports { 539 usb2-0 { 540 status = "disabled"; 541 }; 542 543 usb2-1 { 544 status = "disabled"; 545 }; 546 547 usb2-2 { 548 status = "disabled"; 549 }; 550 551 hsic-0 { 552 status = "disabled"; 553 }; 554 555 usb3-0 { 556 status = "disabled"; 557 }; 558 559 usb3-1 { 560 status = "disabled"; 561 }; 562 563 usb3-2 { 564 status = "disabled"; 565 }; 566 }; 567 }; 568 569 usb@3530000 { 570 compatible = "nvidia,tegra186-xusb"; 571 reg = <0x0 0x03530000 0x0 0x8000>, 572 <0x0 0x03538000 0x0 0x1000>; 573 reg-names = "hcd", "fpci"; 574 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 577 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 578 <&bpmp TEGRA186_CLK_XUSB_SS>, 579 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 580 <&bpmp TEGRA186_CLK_CLK_M>, 581 <&bpmp TEGRA186_CLK_XUSB_FS>, 582 <&bpmp TEGRA186_CLK_PLLU>, 583 <&bpmp TEGRA186_CLK_CLK_M>, 584 <&bpmp TEGRA186_CLK_PLLE>; 585 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 586 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 587 "pll_u_480m", "clk_m", "pll_e"; 588 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 589 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 590 power-domain-names = "xusb_host", "xusb_ss"; 591 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 592 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 593 interconnect-names = "dma-mem", "write"; 594 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 status = "disabled"; 598 599 nvidia,xusb-padctl = <&padctl>; 600 }; 601 602 usb@3550000 { 603 compatible = "nvidia,tegra186-xudc"; 604 reg = <0x0 0x03550000 0x0 0x8000>, 605 <0x0 0x03558000 0x0 0x1000>; 606 reg-names = "base", "fpci"; 607 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 609 <&bpmp TEGRA186_CLK_XUSB_SS>, 610 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 611 <&bpmp TEGRA186_CLK_XUSB_FS>; 612 clock-names = "dev", "ss", "ss_src", "fs_src"; 613 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 614 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 615 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 616 power-domain-names = "dev", "ss"; 617 nvidia,xusb-padctl = <&padctl>; 618 status = "disabled"; 619 }; 620 621 fuse@3820000 { 622 compatible = "nvidia,tegra186-efuse"; 623 reg = <0x0 0x03820000 0x0 0x10000>; 624 clocks = <&bpmp TEGRA186_CLK_FUSE>; 625 clock-names = "fuse"; 626 }; 627 628 gic: interrupt-controller@3881000 { 629 compatible = "arm,gic-400"; 630 #interrupt-cells = <3>; 631 interrupt-controller; 632 reg = <0x0 0x03881000 0x0 0x1000>, 633 <0x0 0x03882000 0x0 0x2000>; 634 interrupts = <GIC_PPI 9 635 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 636 interrupt-parent = <&gic>; 637 }; 638 639 cec@3960000 { 640 compatible = "nvidia,tegra186-cec"; 641 reg = <0x0 0x03960000 0x0 0x10000>; 642 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&bpmp TEGRA186_CLK_CEC>; 644 clock-names = "cec"; 645 status = "disabled"; 646 }; 647 648 hsp_top0: hsp@3c00000 { 649 compatible = "nvidia,tegra186-hsp"; 650 reg = <0x0 0x03c00000 0x0 0xa0000>; 651 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 652 interrupt-names = "doorbell"; 653 #mbox-cells = <2>; 654 status = "disabled"; 655 }; 656 657 gen2_i2c: i2c@c240000 { 658 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 659 reg = <0x0 0x0c240000 0x0 0x10000>; 660 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 clocks = <&bpmp TEGRA186_CLK_I2C2>; 664 clock-names = "div-clk"; 665 resets = <&bpmp TEGRA186_RESET_I2C2>; 666 reset-names = "i2c"; 667 status = "disabled"; 668 }; 669 670 gen8_i2c: i2c@c250000 { 671 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 672 reg = <0x0 0x0c250000 0x0 0x10000>; 673 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 clocks = <&bpmp TEGRA186_CLK_I2C8>; 677 clock-names = "div-clk"; 678 resets = <&bpmp TEGRA186_RESET_I2C8>; 679 reset-names = "i2c"; 680 status = "disabled"; 681 }; 682 683 uartc: serial@c280000 { 684 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 685 reg = <0x0 0x0c280000 0x0 0x40>; 686 reg-shift = <2>; 687 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&bpmp TEGRA186_CLK_UARTC>; 689 clock-names = "serial"; 690 resets = <&bpmp TEGRA186_RESET_UARTC>; 691 reset-names = "serial"; 692 status = "disabled"; 693 }; 694 695 uartg: serial@c290000 { 696 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 697 reg = <0x0 0x0c290000 0x0 0x40>; 698 reg-shift = <2>; 699 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&bpmp TEGRA186_CLK_UARTG>; 701 clock-names = "serial"; 702 resets = <&bpmp TEGRA186_RESET_UARTG>; 703 reset-names = "serial"; 704 status = "disabled"; 705 }; 706 707 rtc: rtc@c2a0000 { 708 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 709 reg = <0 0x0c2a0000 0 0x10000>; 710 interrupt-parent = <&pmc>; 711 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 713 clock-names = "rtc"; 714 status = "disabled"; 715 }; 716 717 gpio_aon: gpio@c2f0000 { 718 compatible = "nvidia,tegra186-gpio-aon"; 719 reg-names = "security", "gpio"; 720 reg = <0x0 0xc2f0000 0x0 0x1000>, 721 <0x0 0xc2f1000 0x0 0x1000>; 722 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 723 gpio-controller; 724 #gpio-cells = <2>; 725 interrupt-controller; 726 #interrupt-cells = <2>; 727 }; 728 729 pmc: pmc@c360000 { 730 compatible = "nvidia,tegra186-pmc"; 731 reg = <0 0x0c360000 0 0x10000>, 732 <0 0x0c370000 0 0x10000>, 733 <0 0x0c380000 0 0x10000>, 734 <0 0x0c390000 0 0x10000>; 735 reg-names = "pmc", "wake", "aotag", "scratch"; 736 737 #interrupt-cells = <2>; 738 interrupt-controller; 739 740 sdmmc1_3v3: sdmmc1-3v3 { 741 pins = "sdmmc1-hv"; 742 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 743 }; 744 745 sdmmc1_1v8: sdmmc1-1v8 { 746 pins = "sdmmc1-hv"; 747 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 748 }; 749 750 sdmmc2_3v3: sdmmc2-3v3 { 751 pins = "sdmmc2-hv"; 752 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 753 }; 754 755 sdmmc2_1v8: sdmmc2-1v8 { 756 pins = "sdmmc2-hv"; 757 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 758 }; 759 760 sdmmc3_3v3: sdmmc3-3v3 { 761 pins = "sdmmc3-hv"; 762 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 763 }; 764 765 sdmmc3_1v8: sdmmc3-1v8 { 766 pins = "sdmmc3-hv"; 767 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 768 }; 769 }; 770 771 ccplex@e000000 { 772 compatible = "nvidia,tegra186-ccplex-cluster"; 773 reg = <0x0 0x0e000000 0x0 0x3fffff>; 774 775 nvidia,bpmp = <&bpmp>; 776 }; 777 778 pcie@10003000 { 779 compatible = "nvidia,tegra186-pcie"; 780 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 781 device_type = "pci"; 782 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 783 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 784 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 785 reg-names = "pads", "afi", "cs"; 786 787 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 788 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 789 interrupt-names = "intr", "msi"; 790 791 #interrupt-cells = <1>; 792 interrupt-map-mask = <0 0 0 0>; 793 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 794 795 bus-range = <0x00 0xff>; 796 #address-cells = <3>; 797 #size-cells = <2>; 798 799 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 800 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 801 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 802 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 803 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 804 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 805 806 clocks = <&bpmp TEGRA186_CLK_PCIE>, 807 <&bpmp TEGRA186_CLK_AFI>, 808 <&bpmp TEGRA186_CLK_PLLE>; 809 clock-names = "pex", "afi", "pll_e"; 810 811 resets = <&bpmp TEGRA186_RESET_PCIE>, 812 <&bpmp TEGRA186_RESET_AFI>, 813 <&bpmp TEGRA186_RESET_PCIEXCLK>; 814 reset-names = "pex", "afi", "pcie_x"; 815 816 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 817 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 818 interconnect-names = "dma-mem", "write"; 819 820 iommus = <&smmu TEGRA186_SID_AFI>; 821 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 822 iommu-map-mask = <0x0>; 823 824 status = "disabled"; 825 826 pci@1,0 { 827 device_type = "pci"; 828 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 829 reg = <0x000800 0 0 0 0>; 830 status = "disabled"; 831 832 #address-cells = <3>; 833 #size-cells = <2>; 834 ranges; 835 836 nvidia,num-lanes = <2>; 837 }; 838 839 pci@2,0 { 840 device_type = "pci"; 841 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 842 reg = <0x001000 0 0 0 0>; 843 status = "disabled"; 844 845 #address-cells = <3>; 846 #size-cells = <2>; 847 ranges; 848 849 nvidia,num-lanes = <1>; 850 }; 851 852 pci@3,0 { 853 device_type = "pci"; 854 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 855 reg = <0x001800 0 0 0 0>; 856 status = "disabled"; 857 858 #address-cells = <3>; 859 #size-cells = <2>; 860 ranges; 861 862 nvidia,num-lanes = <1>; 863 }; 864 }; 865 866 smmu: iommu@12000000 { 867 compatible = "arm,mmu-500"; 868 reg = <0 0x12000000 0 0x800000>; 869 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 934 stream-match-mask = <0x7f80>; 935 #global-interrupts = <1>; 936 #iommu-cells = <1>; 937 }; 938 939 host1x@13e00000 { 940 compatible = "nvidia,tegra186-host1x"; 941 reg = <0x0 0x13e00000 0x0 0x10000>, 942 <0x0 0x13e10000 0x0 0x10000>; 943 reg-names = "hypervisor", "vm"; 944 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 946 interrupt-names = "syncpt", "host1x"; 947 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 948 clock-names = "host1x"; 949 resets = <&bpmp TEGRA186_RESET_HOST1X>; 950 reset-names = "host1x"; 951 952 #address-cells = <1>; 953 #size-cells = <1>; 954 955 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 956 957 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 958 interconnect-names = "dma-mem"; 959 960 iommus = <&smmu TEGRA186_SID_HOST1X>; 961 962 dpaux1: dpaux@15040000 { 963 compatible = "nvidia,tegra186-dpaux"; 964 reg = <0x15040000 0x10000>; 965 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 967 <&bpmp TEGRA186_CLK_PLLDP>; 968 clock-names = "dpaux", "parent"; 969 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 970 reset-names = "dpaux"; 971 status = "disabled"; 972 973 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 974 975 state_dpaux1_aux: pinmux-aux { 976 groups = "dpaux-io"; 977 function = "aux"; 978 }; 979 980 state_dpaux1_i2c: pinmux-i2c { 981 groups = "dpaux-io"; 982 function = "i2c"; 983 }; 984 985 state_dpaux1_off: pinmux-off { 986 groups = "dpaux-io"; 987 function = "off"; 988 }; 989 990 i2c-bus { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 }; 994 }; 995 996 display-hub@15200000 { 997 compatible = "nvidia,tegra186-display"; 998 reg = <0x15200000 0x00040000>; 999 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1000 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1001 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1002 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1003 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1004 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1005 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1006 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1007 "wgrp3", "wgrp4", "wgrp5"; 1008 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1009 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1010 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1011 clock-names = "disp", "dsc", "hub"; 1012 status = "disabled"; 1013 1014 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1015 1016 #address-cells = <1>; 1017 #size-cells = <1>; 1018 1019 ranges = <0x15200000 0x15200000 0x40000>; 1020 1021 display@15200000 { 1022 compatible = "nvidia,tegra186-dc"; 1023 reg = <0x15200000 0x10000>; 1024 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1026 clock-names = "dc"; 1027 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1028 reset-names = "dc"; 1029 1030 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1031 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1032 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1033 interconnect-names = "dma-mem", "read-1"; 1034 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1035 1036 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1037 nvidia,head = <0>; 1038 }; 1039 1040 display@15210000 { 1041 compatible = "nvidia,tegra186-dc"; 1042 reg = <0x15210000 0x10000>; 1043 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1045 clock-names = "dc"; 1046 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1047 reset-names = "dc"; 1048 1049 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1050 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1051 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1052 interconnect-names = "dma-mem", "read-1"; 1053 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1054 1055 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1056 nvidia,head = <1>; 1057 }; 1058 1059 display@15220000 { 1060 compatible = "nvidia,tegra186-dc"; 1061 reg = <0x15220000 0x10000>; 1062 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1064 clock-names = "dc"; 1065 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1066 reset-names = "dc"; 1067 1068 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1069 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1070 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1071 interconnect-names = "dma-mem", "read-1"; 1072 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1073 1074 nvidia,outputs = <&sor0 &sor1>; 1075 nvidia,head = <2>; 1076 }; 1077 }; 1078 1079 dsia: dsi@15300000 { 1080 compatible = "nvidia,tegra186-dsi"; 1081 reg = <0x15300000 0x10000>; 1082 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&bpmp TEGRA186_CLK_DSI>, 1084 <&bpmp TEGRA186_CLK_DSIA_LP>, 1085 <&bpmp TEGRA186_CLK_PLLD>; 1086 clock-names = "dsi", "lp", "parent"; 1087 resets = <&bpmp TEGRA186_RESET_DSI>; 1088 reset-names = "dsi"; 1089 status = "disabled"; 1090 1091 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1092 }; 1093 1094 vic@15340000 { 1095 compatible = "nvidia,tegra186-vic"; 1096 reg = <0x15340000 0x40000>; 1097 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&bpmp TEGRA186_CLK_VIC>; 1099 clock-names = "vic"; 1100 resets = <&bpmp TEGRA186_RESET_VIC>; 1101 reset-names = "vic"; 1102 1103 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1104 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1105 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1106 interconnect-names = "dma-mem", "write"; 1107 iommus = <&smmu TEGRA186_SID_VIC>; 1108 }; 1109 1110 dsib: dsi@15400000 { 1111 compatible = "nvidia,tegra186-dsi"; 1112 reg = <0x15400000 0x10000>; 1113 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1115 <&bpmp TEGRA186_CLK_DSIB_LP>, 1116 <&bpmp TEGRA186_CLK_PLLD>; 1117 clock-names = "dsi", "lp", "parent"; 1118 resets = <&bpmp TEGRA186_RESET_DSIB>; 1119 reset-names = "dsi"; 1120 status = "disabled"; 1121 1122 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1123 }; 1124 1125 sor0: sor@15540000 { 1126 compatible = "nvidia,tegra186-sor"; 1127 reg = <0x15540000 0x10000>; 1128 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1130 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1131 <&bpmp TEGRA186_CLK_PLLD2>, 1132 <&bpmp TEGRA186_CLK_PLLDP>, 1133 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1134 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1135 clock-names = "sor", "out", "parent", "dp", "safe", 1136 "pad"; 1137 resets = <&bpmp TEGRA186_RESET_SOR0>; 1138 reset-names = "sor"; 1139 pinctrl-0 = <&state_dpaux_aux>; 1140 pinctrl-1 = <&state_dpaux_i2c>; 1141 pinctrl-2 = <&state_dpaux_off>; 1142 pinctrl-names = "aux", "i2c", "off"; 1143 status = "disabled"; 1144 1145 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1146 nvidia,interface = <0>; 1147 }; 1148 1149 sor1: sor@15580000 { 1150 compatible = "nvidia,tegra186-sor"; 1151 reg = <0x15580000 0x10000>; 1152 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1154 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1155 <&bpmp TEGRA186_CLK_PLLD3>, 1156 <&bpmp TEGRA186_CLK_PLLDP>, 1157 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1158 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1159 clock-names = "sor", "out", "parent", "dp", "safe", 1160 "pad"; 1161 resets = <&bpmp TEGRA186_RESET_SOR1>; 1162 reset-names = "sor"; 1163 pinctrl-0 = <&state_dpaux1_aux>; 1164 pinctrl-1 = <&state_dpaux1_i2c>; 1165 pinctrl-2 = <&state_dpaux1_off>; 1166 pinctrl-names = "aux", "i2c", "off"; 1167 status = "disabled"; 1168 1169 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1170 nvidia,interface = <1>; 1171 }; 1172 1173 dpaux: dpaux@155c0000 { 1174 compatible = "nvidia,tegra186-dpaux"; 1175 reg = <0x155c0000 0x10000>; 1176 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1178 <&bpmp TEGRA186_CLK_PLLDP>; 1179 clock-names = "dpaux", "parent"; 1180 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1181 reset-names = "dpaux"; 1182 status = "disabled"; 1183 1184 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1185 1186 state_dpaux_aux: pinmux-aux { 1187 groups = "dpaux-io"; 1188 function = "aux"; 1189 }; 1190 1191 state_dpaux_i2c: pinmux-i2c { 1192 groups = "dpaux-io"; 1193 function = "i2c"; 1194 }; 1195 1196 state_dpaux_off: pinmux-off { 1197 groups = "dpaux-io"; 1198 function = "off"; 1199 }; 1200 1201 i2c-bus { 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 }; 1205 }; 1206 1207 padctl@15880000 { 1208 compatible = "nvidia,tegra186-dsi-padctl"; 1209 reg = <0x15880000 0x10000>; 1210 resets = <&bpmp TEGRA186_RESET_DSI>; 1211 reset-names = "dsi"; 1212 status = "disabled"; 1213 }; 1214 1215 dsic: dsi@15900000 { 1216 compatible = "nvidia,tegra186-dsi"; 1217 reg = <0x15900000 0x10000>; 1218 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1220 <&bpmp TEGRA186_CLK_DSIC_LP>, 1221 <&bpmp TEGRA186_CLK_PLLD>; 1222 clock-names = "dsi", "lp", "parent"; 1223 resets = <&bpmp TEGRA186_RESET_DSIC>; 1224 reset-names = "dsi"; 1225 status = "disabled"; 1226 1227 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1228 }; 1229 1230 dsid: dsi@15940000 { 1231 compatible = "nvidia,tegra186-dsi"; 1232 reg = <0x15940000 0x10000>; 1233 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&bpmp TEGRA186_CLK_DSID>, 1235 <&bpmp TEGRA186_CLK_DSID_LP>, 1236 <&bpmp TEGRA186_CLK_PLLD>; 1237 clock-names = "dsi", "lp", "parent"; 1238 resets = <&bpmp TEGRA186_RESET_DSID>; 1239 reset-names = "dsi"; 1240 status = "disabled"; 1241 1242 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1243 }; 1244 }; 1245 1246 gpu@17000000 { 1247 compatible = "nvidia,gp10b"; 1248 reg = <0x0 0x17000000 0x0 0x1000000>, 1249 <0x0 0x18000000 0x0 0x1000000>; 1250 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1252 interrupt-names = "stall", "nonstall"; 1253 1254 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1255 <&bpmp TEGRA186_CLK_GPU>; 1256 clock-names = "gpu", "pwr"; 1257 resets = <&bpmp TEGRA186_RESET_GPU>; 1258 reset-names = "gpu"; 1259 status = "disabled"; 1260 1261 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1262 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1263 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1264 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1265 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1266 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1267 }; 1268 1269 sram@30000000 { 1270 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1271 reg = <0x0 0x30000000 0x0 0x50000>; 1272 #address-cells = <1>; 1273 #size-cells = <1>; 1274 ranges = <0x0 0x0 0x30000000 0x50000>; 1275 1276 cpu_bpmp_tx: sram@4e000 { 1277 reg = <0x4e000 0x1000>; 1278 label = "cpu-bpmp-tx"; 1279 pool; 1280 }; 1281 1282 cpu_bpmp_rx: sram@4f000 { 1283 reg = <0x4f000 0x1000>; 1284 label = "cpu-bpmp-rx"; 1285 pool; 1286 }; 1287 }; 1288 1289 bpmp: bpmp { 1290 compatible = "nvidia,tegra186-bpmp"; 1291 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1292 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1293 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1294 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1295 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1296 iommus = <&smmu TEGRA186_SID_BPMP>; 1297 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1298 TEGRA_HSP_DB_MASTER_BPMP>; 1299 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1300 #clock-cells = <1>; 1301 #reset-cells = <1>; 1302 #power-domain-cells = <1>; 1303 1304 bpmp_i2c: i2c { 1305 compatible = "nvidia,tegra186-bpmp-i2c"; 1306 nvidia,bpmp-bus-id = <5>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 status = "disabled"; 1310 }; 1311 1312 bpmp_thermal: thermal { 1313 compatible = "nvidia,tegra186-bpmp-thermal"; 1314 #thermal-sensor-cells = <1>; 1315 }; 1316 }; 1317 1318 cpus { 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 1322 cpu@0 { 1323 compatible = "nvidia,tegra186-denver"; 1324 device_type = "cpu"; 1325 i-cache-size = <0x20000>; 1326 i-cache-line-size = <64>; 1327 i-cache-sets = <512>; 1328 d-cache-size = <0x10000>; 1329 d-cache-line-size = <64>; 1330 d-cache-sets = <256>; 1331 next-level-cache = <&L2_DENVER>; 1332 reg = <0x000>; 1333 }; 1334 1335 cpu@1 { 1336 compatible = "nvidia,tegra186-denver"; 1337 device_type = "cpu"; 1338 i-cache-size = <0x20000>; 1339 i-cache-line-size = <64>; 1340 i-cache-sets = <512>; 1341 d-cache-size = <0x10000>; 1342 d-cache-line-size = <64>; 1343 d-cache-sets = <256>; 1344 next-level-cache = <&L2_DENVER>; 1345 reg = <0x001>; 1346 }; 1347 1348 cpu@2 { 1349 compatible = "arm,cortex-a57"; 1350 device_type = "cpu"; 1351 i-cache-size = <0xC000>; 1352 i-cache-line-size = <64>; 1353 i-cache-sets = <256>; 1354 d-cache-size = <0x8000>; 1355 d-cache-line-size = <64>; 1356 d-cache-sets = <256>; 1357 next-level-cache = <&L2_A57>; 1358 reg = <0x100>; 1359 }; 1360 1361 cpu@3 { 1362 compatible = "arm,cortex-a57"; 1363 device_type = "cpu"; 1364 i-cache-size = <0xC000>; 1365 i-cache-line-size = <64>; 1366 i-cache-sets = <256>; 1367 d-cache-size = <0x8000>; 1368 d-cache-line-size = <64>; 1369 d-cache-sets = <256>; 1370 next-level-cache = <&L2_A57>; 1371 reg = <0x101>; 1372 }; 1373 1374 cpu@4 { 1375 compatible = "arm,cortex-a57"; 1376 device_type = "cpu"; 1377 i-cache-size = <0xC000>; 1378 i-cache-line-size = <64>; 1379 i-cache-sets = <256>; 1380 d-cache-size = <0x8000>; 1381 d-cache-line-size = <64>; 1382 d-cache-sets = <256>; 1383 next-level-cache = <&L2_A57>; 1384 reg = <0x102>; 1385 }; 1386 1387 cpu@5 { 1388 compatible = "arm,cortex-a57"; 1389 device_type = "cpu"; 1390 i-cache-size = <0xC000>; 1391 i-cache-line-size = <64>; 1392 i-cache-sets = <256>; 1393 d-cache-size = <0x8000>; 1394 d-cache-line-size = <64>; 1395 d-cache-sets = <256>; 1396 next-level-cache = <&L2_A57>; 1397 reg = <0x103>; 1398 }; 1399 1400 L2_DENVER: l2-cache0 { 1401 compatible = "cache"; 1402 cache-unified; 1403 cache-level = <2>; 1404 cache-size = <0x200000>; 1405 cache-line-size = <64>; 1406 cache-sets = <2048>; 1407 }; 1408 1409 L2_A57: l2-cache1 { 1410 compatible = "cache"; 1411 cache-unified; 1412 cache-level = <2>; 1413 cache-size = <0x200000>; 1414 cache-line-size = <64>; 1415 cache-sets = <2048>; 1416 }; 1417 }; 1418 1419 thermal-zones { 1420 a57 { 1421 polling-delay = <0>; 1422 polling-delay-passive = <1000>; 1423 1424 thermal-sensors = 1425 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1426 1427 trips { 1428 critical { 1429 temperature = <101000>; 1430 hysteresis = <0>; 1431 type = "critical"; 1432 }; 1433 }; 1434 1435 cooling-maps { 1436 }; 1437 }; 1438 1439 denver { 1440 polling-delay = <0>; 1441 polling-delay-passive = <1000>; 1442 1443 thermal-sensors = 1444 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1445 1446 trips { 1447 critical { 1448 temperature = <101000>; 1449 hysteresis = <0>; 1450 type = "critical"; 1451 }; 1452 }; 1453 1454 cooling-maps { 1455 }; 1456 }; 1457 1458 gpu { 1459 polling-delay = <0>; 1460 polling-delay-passive = <1000>; 1461 1462 thermal-sensors = 1463 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1464 1465 trips { 1466 critical { 1467 temperature = <101000>; 1468 hysteresis = <0>; 1469 type = "critical"; 1470 }; 1471 }; 1472 1473 cooling-maps { 1474 }; 1475 }; 1476 1477 pll { 1478 polling-delay = <0>; 1479 polling-delay-passive = <1000>; 1480 1481 thermal-sensors = 1482 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1483 1484 trips { 1485 critical { 1486 temperature = <101000>; 1487 hysteresis = <0>; 1488 type = "critical"; 1489 }; 1490 }; 1491 1492 cooling-maps { 1493 }; 1494 }; 1495 1496 always_on { 1497 polling-delay = <0>; 1498 polling-delay-passive = <1000>; 1499 1500 thermal-sensors = 1501 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1502 1503 trips { 1504 critical { 1505 temperature = <101000>; 1506 hysteresis = <0>; 1507 type = "critical"; 1508 }; 1509 }; 1510 1511 cooling-maps { 1512 }; 1513 }; 1514 }; 1515 1516 timer { 1517 compatible = "arm,armv8-timer"; 1518 interrupts = <GIC_PPI 13 1519 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1520 <GIC_PPI 14 1521 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1522 <GIC_PPI 11 1523 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1524 <GIC_PPI 10 1525 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1526 interrupt-parent = <&gic>; 1527 always-on; 1528 }; 1529}; 1530