1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com 3 4#include "nuvoton-common-npcm8xx.dtsi" 5 6/ { 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 cpus { 11 #address-cells = <2>; 12 #size-cells = <0>; 13 14 cpu0: cpu@0 { 15 device_type = "cpu"; 16 compatible = "arm,cortex-a35"; 17 clocks = <&clk NPCM8XX_CLK_CPU>; 18 reg = <0x0 0x0>; 19 next-level-cache = <&l2>; 20 enable-method = "psci"; 21 }; 22 23 cpu1: cpu@1 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a35"; 26 clocks = <&clk NPCM8XX_CLK_CPU>; 27 reg = <0x0 0x1>; 28 next-level-cache = <&l2>; 29 enable-method = "psci"; 30 }; 31 32 cpu2: cpu@2 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a35"; 35 clocks = <&clk NPCM8XX_CLK_CPU>; 36 reg = <0x0 0x2>; 37 next-level-cache = <&l2>; 38 enable-method = "psci"; 39 }; 40 41 cpu3: cpu@3 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35"; 44 clocks = <&clk NPCM8XX_CLK_CPU>; 45 reg = <0x0 0x3>; 46 next-level-cache = <&l2>; 47 enable-method = "psci"; 48 }; 49 50 l2: l2-cache { 51 compatible = "cache"; 52 }; 53 }; 54 55 arm-pmu { 56 compatible = "arm,cortex-a35-pmu"; 57 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 61 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 62 }; 63 64 psci { 65 compatible = "arm,psci-1.0"; 66 method = "smc"; 67 }; 68 69 timer { 70 compatible = "arm,armv8-timer"; 71 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 72 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 74 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 75 }; 76}; 77