1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com 3 4#include <dt-bindings/clock/nuvoton,npcm845-clk.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 interrupt-parent = <&gic>; 12 13 soc { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 compatible = "simple-bus"; 17 interrupt-parent = <&gic>; 18 ranges; 19 20 gcr: system-controller@f0800000 { 21 compatible = "nuvoton,npcm845-gcr", "syscon"; 22 reg = <0x0 0xf0800000 0x0 0x1000>; 23 }; 24 25 gic: interrupt-controller@dfff9000 { 26 compatible = "arm,gic-400"; 27 reg = <0x0 0xdfff9000 0x0 0x1000>, 28 <0x0 0xdfffa000 0x0 0x2000>, 29 <0x0 0xdfffc000 0x0 0x2000>, 30 <0x0 0xdfffe000 0x0 0x2000>; 31 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 32 #interrupt-cells = <3>; 33 interrupt-controller; 34 #address-cells = <0>; 35 }; 36 }; 37 38 ahb { 39 #address-cells = <2>; 40 #size-cells = <2>; 41 compatible = "simple-bus"; 42 interrupt-parent = <&gic>; 43 ranges; 44 45 rstc: reset-controller@f0801000 { 46 compatible = "nuvoton,npcm845-reset"; 47 reg = <0x0 0xf0801000 0x0 0x78>; 48 #reset-cells = <2>; 49 nuvoton,sysgcr = <&gcr>; 50 }; 51 52 clk: clock-controller@f0801000 { 53 compatible = "nuvoton,npcm845-clk"; 54 #clock-cells = <1>; 55 reg = <0x0 0xf0801000 0x0 0x1000>; 56 }; 57 58 apb { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 compatible = "simple-bus"; 62 interrupt-parent = <&gic>; 63 ranges = <0x0 0x0 0xf0000000 0x00300000>, 64 <0xfff00000 0x0 0xfff00000 0x00016000>; 65 66 peci: peci-controller@100000 { 67 compatible = "nuvoton,npcm845-peci"; 68 reg = <0x100000 0x1000>; 69 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 70 clocks = <&clk NPCM8XX_CLK_APB3>; 71 cmd-timeout-ms = <1000>; 72 status = "disabled"; 73 }; 74 75 timer0: timer@8000 { 76 compatible = "nuvoton,npcm845-timer"; 77 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 78 reg = <0x8000 0x1C>; 79 clocks = <&clk NPCM8XX_CLK_REFCLK>; 80 clock-names = "refclk"; 81 }; 82 83 serial0: serial@0 { 84 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; 85 reg = <0x0 0x1000>; 86 clocks = <&clk NPCM8XX_CLK_UART>; 87 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 88 reg-shift = <2>; 89 status = "disabled"; 90 }; 91 92 serial1: serial@1000 { 93 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; 94 reg = <0x1000 0x1000>; 95 clocks = <&clk NPCM8XX_CLK_UART>; 96 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 97 reg-shift = <2>; 98 status = "disabled"; 99 }; 100 101 serial2: serial@2000 { 102 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; 103 reg = <0x2000 0x1000>; 104 clocks = <&clk NPCM8XX_CLK_UART>; 105 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 106 reg-shift = <2>; 107 status = "disabled"; 108 }; 109 110 serial3: serial@3000 { 111 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; 112 reg = <0x3000 0x1000>; 113 clocks = <&clk NPCM8XX_CLK_UART>; 114 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 115 reg-shift = <2>; 116 status = "disabled"; 117 }; 118 119 serial4: serial@4000 { 120 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; 121 reg = <0x4000 0x1000>; 122 clocks = <&clk NPCM8XX_CLK_UART>; 123 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 124 reg-shift = <2>; 125 status = "disabled"; 126 }; 127 128 serial5: serial@5000 { 129 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; 130 reg = <0x5000 0x1000>; 131 clocks = <&clk NPCM8XX_CLK_UART>; 132 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 133 reg-shift = <2>; 134 status = "disabled"; 135 }; 136 137 serial6: serial@6000 { 138 compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; 139 reg = <0x6000 0x1000>; 140 clocks = <&clk NPCM8XX_CLK_UART>; 141 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 142 reg-shift = <2>; 143 status = "disabled"; 144 }; 145 146 watchdog0: watchdog@801c { 147 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt"; 148 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 149 reg = <0x801c 0x4>; 150 status = "disabled"; 151 clocks = <&clk NPCM8XX_CLK_REFCLK>; 152 syscon = <&gcr>; 153 }; 154 155 watchdog1: watchdog@901c { 156 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt"; 157 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 158 reg = <0x901c 0x4>; 159 status = "disabled"; 160 clocks = <&clk NPCM8XX_CLK_REFCLK>; 161 syscon = <&gcr>; 162 }; 163 164 watchdog2: watchdog@a01c { 165 compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt"; 166 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 167 reg = <0xa01c 0x4>; 168 status = "disabled"; 169 clocks = <&clk NPCM8XX_CLK_REFCLK>; 170 syscon = <&gcr>; 171 }; 172 }; 173 }; 174 175 pinctrl: pinctrl@f0010000 { 176 compatible = "nuvoton,npcm845-pinctrl"; 177 ranges = <0x0 0x0 0xf0010000 0x8000>; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 nuvoton,sysgcr = <&gcr>; 181 status = "okay"; 182 gpio0: gpio@f0010000 { 183 gpio-controller; 184 #gpio-cells = <2>; 185 reg = <0x0 0xB0>; 186 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 187 gpio-ranges = <&pinctrl 0 0 32>; 188 }; 189 gpio1: gpio@f0011000 { 190 gpio-controller; 191 #gpio-cells = <2>; 192 reg = <0x1000 0xB0>; 193 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 194 gpio-ranges = <&pinctrl 0 32 32>; 195 }; 196 gpio2: gpio@f0012000 { 197 gpio-controller; 198 #gpio-cells = <2>; 199 reg = <0x2000 0xB0>; 200 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 201 gpio-ranges = <&pinctrl 0 64 32>; 202 }; 203 gpio3: gpio@f0013000 { 204 gpio-controller; 205 #gpio-cells = <2>; 206 reg = <0x3000 0xB0>; 207 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 208 gpio-ranges = <&pinctrl 0 96 32>; 209 }; 210 gpio4: gpio@f0014000 { 211 gpio-controller; 212 #gpio-cells = <2>; 213 reg = <0x4000 0xB0>; 214 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 215 gpio-ranges = <&pinctrl 0 128 32>; 216 }; 217 gpio5: gpio@f0015000 { 218 gpio-controller; 219 #gpio-cells = <2>; 220 reg = <0x5000 0xB0>; 221 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 222 gpio-ranges = <&pinctrl 0 160 32>; 223 }; 224 gpio6: gpio@f0016000 { 225 gpio-controller; 226 #gpio-cells = <2>; 227 reg = <0x6000 0xB0>; 228 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 229 gpio-ranges = <&pinctrl 0 192 32>; 230 }; 231 gpio7: gpio@f0017000 { 232 gpio-controller; 233 #gpio-cells = <2>; 234 reg = <0x7000 0xB0>; 235 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 236 gpio-ranges = <&pinctrl 0 224 32>; 237 }; 238 }; 239}; 240