1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/microchip,sparx5.h> 9 10/ { 11 compatible = "microchip,sparx5"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <1>; 15 16 aliases { 17 spi0 = &spi0; 18 serial0 = &uart0; 19 serial1 = &uart1; 20 }; 21 22 chosen { 23 stdout-path = "serial0:115200n8"; 24 }; 25 26 cpus { 27 #address-cells = <2>; 28 #size-cells = <0>; 29 cpu-map { 30 cluster0 { 31 core0 { 32 cpu = <&cpu0>; 33 }; 34 core1 { 35 cpu = <&cpu1>; 36 }; 37 }; 38 }; 39 cpu0: cpu@0 { 40 compatible = "arm,cortex-a53"; 41 device_type = "cpu"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 next-level-cache = <&L2_0>; 45 }; 46 cpu1: cpu@1 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 reg = <0x0 0x1>; 50 enable-method = "psci"; 51 next-level-cache = <&L2_0>; 52 }; 53 L2_0: l2-cache0 { 54 compatible = "cache"; 55 }; 56 }; 57 58 arm-pmu { 59 compatible = "arm,cortex-a53-pmu"; 60 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 61 interrupt-affinity = <&cpu0>, <&cpu1>; 62 }; 63 64 psci { 65 compatible = "arm,psci-0.2"; 66 method = "smc"; 67 }; 68 69 timer { 70 compatible = "arm,armv8-timer"; 71 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 72 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 73 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 74 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 75 }; 76 77 lcpll_clk: lcpll-clk { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <2500000000>; 81 }; 82 83 clks: clock-controller@61110000c { 84 compatible = "microchip,sparx5-dpll"; 85 #clock-cells = <1>; 86 clocks = <&lcpll_clk>; 87 reg = <0x6 0x1110000c 0x24>; 88 }; 89 90 ahb_clk: ahb-clk { 91 compatible = "fixed-clock"; 92 #clock-cells = <0>; 93 clock-frequency = <250000000>; 94 }; 95 96 sys_clk: sys-clk { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <625000000>; 100 }; 101 102 axi: axi@600000000 { 103 compatible = "simple-bus"; 104 #address-cells = <2>; 105 #size-cells = <1>; 106 ranges; 107 108 gic: interrupt-controller@600300000 { 109 compatible = "arm,gic-v3"; 110 #interrupt-cells = <3>; 111 #address-cells = <2>; 112 #size-cells = <2>; 113 interrupt-controller; 114 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ 115 <0x6 0x00340000 0xc0000>, /* GICR */ 116 <0x6 0x00200000 0x2000>, /* GICC */ 117 <0x6 0x00210000 0x2000>, /* GICV */ 118 <0x6 0x00220000 0x2000>; /* GICH */ 119 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 120 }; 121 122 cpu_ctrl: syscon@600000000 { 123 compatible = "microchip,sparx5-cpu-syscon", "syscon", 124 "simple-mfd"; 125 reg = <0x6 0x00000000 0xd0>; 126 mux: mux-controller { 127 compatible = "mmio-mux"; 128 #mux-control-cells = <0>; 129 /* 130 * SI_OWNER and SI2_OWNER in GENERAL_CTRL 131 * SPI: value 9 - (SIMC,SIBM) = 0b1001 132 * SPI2: value 6 - (SIBM,SIMC) = 0b0110 133 */ 134 mux-reg-masks = <0x88 0xf0>; 135 }; 136 }; 137 138 uart0: serial@600100000 { 139 pinctrl-0 = <&uart_pins>; 140 pinctrl-names = "default"; 141 compatible = "ns16550a"; 142 reg = <0x6 0x00100000 0x20>; 143 clocks = <&ahb_clk>; 144 reg-io-width = <4>; 145 reg-shift = <2>; 146 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 147 148 status = "disabled"; 149 }; 150 151 uart1: serial@600102000 { 152 pinctrl-0 = <&uart2_pins>; 153 pinctrl-names = "default"; 154 compatible = "ns16550a"; 155 reg = <0x6 0x00102000 0x20>; 156 clocks = <&ahb_clk>; 157 reg-io-width = <4>; 158 reg-shift = <2>; 159 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 160 161 status = "disabled"; 162 }; 163 164 spi0: spi@600104000 { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 compatible = "microchip,sparx5-spi"; 168 reg = <0x6 0x00104000 0x40>; 169 num-cs = <16>; 170 reg-io-width = <4>; 171 reg-shift = <2>; 172 clocks = <&ahb_clk>; 173 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 174 status = "disabled"; 175 }; 176 177 timer1: timer@600105000 { 178 compatible = "snps,dw-apb-timer"; 179 reg = <0x6 0x00105000 0x1000>; 180 clocks = <&ahb_clk>; 181 clock-names = "timer"; 182 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 183 }; 184 185 sdhci0: mmc@600800000 { 186 compatible = "microchip,dw-sparx5-sdhci"; 187 status = "disabled"; 188 reg = <0x6 0x00800000 0x1000>; 189 pinctrl-0 = <&emmc_pins>; 190 pinctrl-names = "default"; 191 clocks = <&clks CLK_ID_AUX1>; 192 clock-names = "core"; 193 assigned-clocks = <&clks CLK_ID_AUX1>; 194 assigned-clock-rates = <800000000>; 195 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 196 bus-width = <8>; 197 }; 198 199 gpio: pinctrl@6110101e0 { 200 compatible = "microchip,sparx5-pinctrl"; 201 reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; 202 gpio-controller; 203 #gpio-cells = <2>; 204 gpio-ranges = <&gpio 0 0 64>; 205 interrupt-controller; 206 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 207 #interrupt-cells = <2>; 208 209 cs1_pins: cs1-pins { 210 pins = "GPIO_16"; 211 function = "si"; 212 }; 213 214 cs2_pins: cs2-pins { 215 pins = "GPIO_17"; 216 function = "si"; 217 }; 218 219 cs3_pins: cs3-pins { 220 pins = "GPIO_18"; 221 function = "si"; 222 }; 223 224 si2_pins: si2-pins { 225 pins = "GPIO_39", "GPIO_40", "GPIO_41"; 226 function = "si2"; 227 }; 228 229 uart_pins: uart-pins { 230 pins = "GPIO_10", "GPIO_11"; 231 function = "uart"; 232 }; 233 234 uart2_pins: uart2-pins { 235 pins = "GPIO_26", "GPIO_27"; 236 function = "uart2"; 237 }; 238 239 i2c_pins: i2c-pins { 240 pins = "GPIO_14", "GPIO_15"; 241 function = "twi"; 242 }; 243 244 i2c2_pins: i2c2-pins { 245 pins = "GPIO_28", "GPIO_29"; 246 function = "twi2"; 247 }; 248 249 emmc_pins: emmc-pins { 250 pins = "GPIO_34", "GPIO_35", "GPIO_36", 251 "GPIO_37", "GPIO_38", "GPIO_39", 252 "GPIO_40", "GPIO_41", "GPIO_42", 253 "GPIO_43", "GPIO_44", "GPIO_45", 254 "GPIO_46", "GPIO_47"; 255 function = "emmc"; 256 }; 257 }; 258 259 i2c0: i2c@600101000 { 260 compatible = "snps,designware-i2c"; 261 status = "disabled"; 262 pinctrl-0 = <&i2c_pins>; 263 pinctrl-names = "default"; 264 reg = <0x6 0x00101000 0x100>; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 268 i2c-sda-hold-time-ns = <300>; 269 clock-frequency = <100000>; 270 clocks = <&ahb_clk>; 271 }; 272 273 i2c1: i2c@600103000 { 274 compatible = "snps,designware-i2c"; 275 status = "disabled"; 276 pinctrl-0 = <&i2c2_pins>; 277 pinctrl-names = "default"; 278 reg = <0x6 0x00103000 0x100>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 282 i2c-sda-hold-time-ns = <300>; 283 clock-frequency = <100000>; 284 clocks = <&ahb_clk>; 285 }; 286 287 tmon0: tmon@610508110 { 288 compatible = "microchip,sparx5-temp"; 289 reg = <0x6 0x10508110 0xc>; 290 #thermal-sensor-cells = <0>; 291 clocks = <&ahb_clk>; 292 }; 293 }; 294}; 295