1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 Radxa Limited 4 * Copyright (C) 2024 Collabora Ltd. 5 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6 */ 7 8#include "mt8195.dtsi" 9#include "mt6359.dtsi" 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 13#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> 14#include <dt-bindings/spmi/spmi.h> 15#include <dt-bindings/usb/pd.h> 16 17/ { 18 model = "Radxa NIO 12L"; 19 chassis-type = "embedded"; 20 compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195"; 21 22 aliases { 23 i2c0 = &i2c2; 24 i2c1 = &i2c3; 25 i2c2 = &i2c4; 26 i2c3 = &i2c0; 27 i2c4 = &i2c1; 28 ethernet0 = ð 29 serial0 = &uart0; 30 serial1 = &uart1; 31 spi0 = &spi1; 32 spi1 = &spi2; 33 }; 34 35 chosen { 36 stdout-path = "serial0:921600n8"; 37 }; 38 39 firmware { 40 optee { 41 compatible = "linaro,optee-tz"; 42 method = "smc"; 43 }; 44 }; 45 46 memory@40000000 { 47 device_type = "memory"; 48 reg = <0 0x40000000 0x1 0x0>; 49 }; 50 51 backlight: backlight { 52 compatible = "pwm-backlight"; 53 brightness-levels = <0 1023>; 54 default-brightness-level = <576>; 55 enable-gpios = <&pio 107 GPIO_ACTIVE_HIGH>; 56 num-interpolated-steps = <1023>; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&dsi0_backlight_pins>; 59 pwms = <&disp_pwm0 0 500000>; 60 status = "disabled"; 61 }; 62 63 wifi_vreg: regulator-wifi-3v3-en { 64 compatible = "regulator-fixed"; 65 regulator-name = "wifi_3v3_en"; 66 regulator-always-on; 67 regulator-min-microvolt = <3300000>; 68 regulator-max-microvolt = <3300000>; 69 enable-active-high; 70 gpio = <&pio 67 GPIO_ACTIVE_HIGH>; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&wifi_vreg_pins>; 73 vin-supply = <&vsys>; 74 }; 75 76 /* system wide switching 5.0V power rail */ 77 vsys: regulator-vsys { 78 compatible = "regulator-fixed"; 79 regulator-name = "vsys"; 80 regulator-always-on; 81 regulator-boot-on; 82 regulator-min-microvolt = <5000000>; 83 regulator-max-microvolt = <5000000>; 84 vin-supply = <&vcc5v0_vsys>; 85 }; 86 87 vsys_buck: regulator-vsys-buck { 88 compatible = "regulator-fixed"; 89 regulator-name = "vsys_buck"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <5000000>; 93 regulator-max-microvolt = <5000000>; 94 vin-supply = <&vcc5v0_vsys>; 95 }; 96 97 /* Rail from power-only "TYPE C DC" port */ 98 vcc5v0_vsys: regulator-vcc5v0-sys { 99 compatible = "regulator-fixed"; 100 regulator-name = "vcc5v0_sys"; 101 regulator-always-on; 102 regulator-boot-on; 103 }; 104 105 reserved-memory { 106 #address-cells = <2>; 107 #size-cells = <2>; 108 ranges; 109 110 /* 111 * 12 MiB reserved for OP-TEE (BL32) 112 * +-----------------------+ 0x43e0_0000 113 * | SHMEM 2MiB | 114 * +-----------------------+ 0x43c0_0000 115 * | | TA_RAM 8MiB | 116 * + TZDRAM +--------------+ 0x4340_0000 117 * | | TEE_RAM 2MiB | 118 * +-----------------------+ 0x4320_0000 119 */ 120 optee_reserved: optee@43200000 { 121 reg = <0 0x43200000 0 0xc00000>; 122 no-map; 123 }; 124 125 scp_mem: memory@50000000 { 126 compatible = "shared-dma-pool"; 127 reg = <0 0x50000000 0 0x2900000>; 128 no-map; 129 }; 130 131 vpu_mem: memory@53000000 { 132 compatible = "shared-dma-pool"; 133 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ 134 }; 135 136 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 137 bl31_secmon_mem: memory@54600000 { 138 reg = <0 0x54600000 0x0 0x200000>; 139 no-map; 140 }; 141 142 adsp_mem: memory@60000000 { 143 compatible = "shared-dma-pool"; 144 reg = <0 0x60000000 0 0xf00000>; 145 no-map; 146 }; 147 148 afe_dma_mem: memory@60f00000 { 149 compatible = "shared-dma-pool"; 150 reg = <0 0x60f00000 0 0x100000>; 151 no-map; 152 }; 153 154 adsp_dma_mem: memory@61000000 { 155 compatible = "shared-dma-pool"; 156 reg = <0 0x61000000 0 0x100000>; 157 no-map; 158 }; 159 160 apu_mem: memory@62000000 { 161 compatible = "shared-dma-pool"; 162 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ 163 }; 164 }; 165}; 166 167&adsp { 168 memory-region = <&adsp_dma_mem>, <&adsp_mem>; 169 status = "okay"; 170}; 171 172&afe { 173 memory-region = <&afe_dma_mem>; 174 status = "okay"; 175}; 176 177&cpu0 { 178 cpu-supply = <&mt6359_vcore_buck_reg>; 179}; 180 181&cpu1 { 182 cpu-supply = <&mt6359_vcore_buck_reg>; 183}; 184 185&cpu2 { 186 cpu-supply = <&mt6359_vcore_buck_reg>; 187}; 188 189&cpu3 { 190 cpu-supply = <&mt6359_vcore_buck_reg>; 191}; 192 193&cpu4 { 194 cpu-supply = <&mt6315_6_vbuck1>; 195}; 196 197&cpu5 { 198 cpu-supply = <&mt6315_6_vbuck1>; 199}; 200 201&cpu6 { 202 cpu-supply = <&mt6315_6_vbuck1>; 203}; 204 205&cpu7 { 206 cpu-supply = <&mt6315_6_vbuck1>; 207}; 208 209&dither0_out { 210 remote-endpoint = <&dsi0_in>; 211}; 212 213&dsi0 { 214 #address-cells = <1>; 215 #size-cells = <0>; 216 217 ports { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 221 port@0 { 222 reg = <0>; 223 dsi0_in: endpoint { 224 remote-endpoint = <&dither0_out>; 225 }; 226 }; 227 228 port@1 { 229 reg = <1>; 230 dsi0_out: endpoint { }; 231 }; 232 }; 233}; 234 235ð { 236 phy-mode = "rgmii-rxid"; 237 phy-handle = <&rgmii_phy>; 238 pinctrl-names = "default", "sleep"; 239 pinctrl-0 = <ð_default_pins>; 240 pinctrl-1 = <ð_sleep_pins>; 241 mediatek,tx-delay-ps = <2030>; 242 mediatek,mac-wol; 243 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; 244 snps,reset-delays-us = <0 20000 100000>; 245 status = "okay"; 246 247 mdio { 248 rgmii_phy: ethernet-phy@1 { 249 compatible = "ethernet-phy-id001c.c916"; 250 reg = <0x1>; 251 }; 252 }; 253}; 254 255&gpu { 256 mali-supply = <&mt6315_7_vbuck1>; 257 status = "okay"; 258}; 259 260&i2c2 { 261 clock-frequency = <400000>; 262 pinctrl-0 = <&i2c2_pins>; 263 pinctrl-names = "default"; 264 status = "okay"; 265 266 typec-mux@48 { 267 compatible = "ite,it5205"; 268 reg = <0x48>; 269 270 mode-switch; 271 orientation-switch; 272 273 vcc-supply = <&mt6359_vibr_ldo_reg>; 274 275 port { 276 it5205_sbu_mux: endpoint { 277 remote-endpoint = <&typec_con_mux>; 278 }; 279 }; 280 }; 281}; 282 283&i2c4 { 284 clock-frequency = <400000>; 285 pinctrl-0 = <&i2c4_pins>; 286 pinctrl-names = "default"; 287 status = "okay"; 288 289 /* I2C4 exposed at 39-pins MIPI-LCD connector */ 290}; 291 292&i2c6 { 293 clock-frequency = <400000>; 294 pinctrl-0 = <&i2c6_pins>; 295 pinctrl-names = "default"; 296 status = "okay"; 297 298 mt6360: pmic@34 { 299 compatible = "mediatek,mt6360"; 300 reg = <0x34>; 301 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; 302 interrupt-names = "IRQB"; 303 interrupt-controller; 304 #interrupt-cells = <1>; 305 pinctrl-0 = <&mt6360_pins>; 306 307 charger { 308 compatible = "mediatek,mt6360-chg"; 309 richtek,vinovp-microvolt = <14500000>; 310 311 otg_vbus_regulator: usb-otg-vbus-regulator { 312 regulator-name = "usb-otg-vbus"; 313 regulator-min-microvolt = <4425000>; 314 regulator-max-microvolt = <5825000>; 315 }; 316 }; 317 318 regulator { 319 compatible = "mediatek,mt6360-regulator"; 320 LDO_VIN1-supply = <&vsys_buck>; 321 LDO_VIN3-supply = <&mt6360_buck2>; 322 323 mt6360_buck1: buck1 { 324 regulator-name = "emi_vdd2"; 325 regulator-min-microvolt = <300000>; 326 regulator-max-microvolt = <1300000>; 327 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 328 MT6360_OPMODE_LP 329 MT6360_OPMODE_ULP>; 330 regulator-always-on; 331 }; 332 333 mt6360_buck2: buck2 { 334 regulator-name = "emi_vddq"; 335 regulator-min-microvolt = <300000>; 336 regulator-max-microvolt = <1300000>; 337 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 338 MT6360_OPMODE_LP 339 MT6360_OPMODE_ULP>; 340 regulator-always-on; 341 }; 342 343 mt6360_ldo1: ldo1 { 344 regulator-name = "ext_lcd_3v3"; 345 regulator-min-microvolt = <3300000>; 346 regulator-max-microvolt = <3300000>; 347 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 348 MT6360_OPMODE_LP>; 349 regulator-always-on; 350 }; 351 352 mt6360_ldo2: ldo2 { 353 regulator-name = "panel1_p1v8"; 354 regulator-min-microvolt = <1800000>; 355 regulator-max-microvolt = <1800000>; 356 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 357 MT6360_OPMODE_LP>; 358 }; 359 360 mt6360_ldo3: ldo3 { 361 regulator-name = "vmc_pmu"; 362 regulator-min-microvolt = <1200000>; 363 regulator-max-microvolt = <3600000>; 364 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 365 MT6360_OPMODE_LP>; 366 }; 367 368 mt6360_ldo5: ldo5 { 369 regulator-name = "vmch_pmu"; 370 regulator-min-microvolt = <3300000>; 371 regulator-max-microvolt = <3300000>; 372 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 373 MT6360_OPMODE_LP>; 374 regulator-always-on; 375 }; 376 377 mt6360_ldo6: ldo6 { 378 regulator-name = "mt6360_ldo6"; /* Test point */ 379 regulator-min-microvolt = <500000>; 380 regulator-max-microvolt = <2100000>; 381 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 382 MT6360_OPMODE_LP>; 383 }; 384 385 mt6360_ldo7: ldo7 { 386 regulator-name = "emi_vmddr_en"; 387 regulator-min-microvolt = <500000>; 388 regulator-max-microvolt = <2100000>; 389 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 390 MT6360_OPMODE_LP>; 391 regulator-always-on; 392 }; 393 }; 394 395 typec { 396 compatible = "mediatek,mt6360-tcpc"; 397 interrupts-extended = <&pio 100 IRQ_TYPE_LEVEL_LOW>; 398 interrupt-names = "PD_IRQB"; 399 400 connector { 401 compatible = "usb-c-connector"; 402 label = "USB-C"; 403 data-role = "dual"; 404 op-sink-microwatt = <10000000>; 405 power-role = "dual"; 406 try-power-role = "sink"; 407 408 source-pdos = <PDO_FIXED(5000, 1000, 409 PDO_FIXED_DUAL_ROLE | 410 PDO_FIXED_DATA_SWAP)>; 411 sink-pdos = <PDO_FIXED(5000, 3000, 412 PDO_FIXED_DUAL_ROLE | 413 PDO_FIXED_DATA_SWAP)>; 414 415 ports { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 419 port@0 { 420 reg = <0>; 421 typec_con_hs: endpoint { 422 remote-endpoint = <&mtu3_hs0_role_sw>; 423 }; 424 }; 425 426 port@2 { 427 reg = <2>; 428 typec_con_mux: endpoint { 429 remote-endpoint = <&it5205_sbu_mux>; 430 }; 431 }; 432 }; 433 }; 434 }; 435 }; 436}; 437 438&mfg0 { 439 domain-supply = <&mt6315_7_vbuck1>; 440}; 441 442&mfg1 { 443 domain-supply = <&mt6359_vsram_others_ldo_reg>; 444}; 445 446/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */ 447&mmc0 { 448 pinctrl-names = "default", "state_uhs"; 449 pinctrl-0 = <&mmc0_default_pins>; 450 pinctrl-1 = <&mmc0_uhs_pins>; 451 bus-width = <8>; 452 max-frequency = <200000000>; 453 hs400-ds-delay = <0x14c11>; 454 cap-mmc-highspeed; 455 cap-mmc-hw-reset; 456 mmc-hs200-1_8v; 457 mmc-hs400-1_8v; 458 no-sdio; 459 no-sd; 460 non-removable; 461 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 462 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 463 status = "okay"; 464}; 465 466/* MMC1 Controller: MicroSD card slot */ 467&mmc1 { 468 pinctrl-names = "default", "state_uhs"; 469 pinctrl-0 = <&mmc1_default_pins>, <&mmc1_pins_detect>; 470 pinctrl-1 = <&mmc1_default_pins>; 471 bus-width = <4>; 472 max-frequency = <200000000>; 473 cap-sd-highspeed; 474 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; 475 no-mmc; 476 no-sdio; 477 sd-uhs-sdr50; 478 sd-uhs-sdr104; 479 vmmc-supply = <&mt6360_ldo5>; 480 vqmmc-supply = <&mt6360_ldo3>; 481 status = "okay"; 482}; 483 484&mt6359_vaud18_ldo_reg { 485 regulator-always-on; 486}; 487 488&mt6359_vbbck_ldo_reg { 489 regulator-always-on; 490}; 491 492/* For USB Hub */ 493&mt6359_vcamio_ldo_reg { 494 regulator-always-on; 495}; 496 497&mt6359_vcn33_2_bt_ldo_reg { 498 regulator-min-microvolt = <3300000>; 499 regulator-max-microvolt = <3300000>; 500}; 501 502&mt6359_vcore_buck_reg { 503 regulator-always-on; 504}; 505 506&mt6359_vgpu11_buck_reg { 507 regulator-always-on; 508}; 509 510&mt6359_vproc1_buck_reg { 511 regulator-always-on; 512}; 513 514&mt6359_vproc2_buck_reg { 515 regulator-always-on; 516}; 517 518&mt6359_vpu_buck_reg { 519 regulator-always-on; 520}; 521 522&mt6359_vrf12_ldo_reg { 523 regulator-always-on; 524}; 525 526&mt6359_vsram_md_ldo_reg { 527 regulator-always-on; 528}; 529 530/* for GPU SRAM */ 531&mt6359_vsram_others_ldo_reg { 532 regulator-min-microvolt = <750000>; 533 regulator-max-microvolt = <750000>; 534}; 535 536&pio { 537 mediatek,rsel-resistance-in-si-unit; 538 539 audio_default_pins: audio-default-pins { 540 pins-cmd-dat { 541 pinmux = <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, 542 <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, 543 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, 544 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, 545 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, 546 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, 547 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>; 548 }; 549 }; 550 551 dsi0_backlight_pins: dsi0-backlight-pins { 552 pins-backlight-en { 553 pinmux = <PINMUX_GPIO107__FUNC_GPIO107>; 554 output-high; 555 }; 556 }; 557 558 eth_default_pins: eth-default-pins { 559 pins-cc { 560 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, 561 <PINMUX_GPIO86__FUNC_GBE_RXC>, 562 <PINMUX_GPIO87__FUNC_GBE_RXDV>, 563 <PINMUX_GPIO88__FUNC_GBE_TXEN>; 564 drive-strength = <8>; 565 }; 566 567 pins-mdio { 568 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, 569 <PINMUX_GPIO90__FUNC_GBE_MDIO>; 570 input-enable; 571 }; 572 573 pins-power { 574 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, 575 <PINMUX_GPIO92__FUNC_GPIO92>; 576 output-high; 577 }; 578 579 pins-rst { 580 pinmux = <PINMUX_GPIO93__FUNC_GPIO93>; 581 }; 582 583 pins-rxd { 584 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, 585 <PINMUX_GPIO82__FUNC_GBE_RXD2>, 586 <PINMUX_GPIO83__FUNC_GBE_RXD1>, 587 <PINMUX_GPIO84__FUNC_GBE_RXD0>; 588 }; 589 590 pins-txd { 591 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, 592 <PINMUX_GPIO78__FUNC_GBE_TXD2>, 593 <PINMUX_GPIO79__FUNC_GBE_TXD1>, 594 <PINMUX_GPIO80__FUNC_GBE_TXD0>; 595 drive-strength = <8>; 596 }; 597 }; 598 599 eth_sleep_pins: eth-sleep-pins { 600 pins-cc { 601 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, 602 <PINMUX_GPIO86__FUNC_GPIO86>, 603 <PINMUX_GPIO87__FUNC_GPIO87>, 604 <PINMUX_GPIO88__FUNC_GPIO88>; 605 }; 606 607 pins-mdio { 608 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, 609 <PINMUX_GPIO90__FUNC_GPIO90>; 610 bias-disable; 611 input-disable; 612 }; 613 614 pins-rxd { 615 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, 616 <PINMUX_GPIO82__FUNC_GPIO82>, 617 <PINMUX_GPIO83__FUNC_GPIO83>, 618 <PINMUX_GPIO84__FUNC_GPIO84>; 619 }; 620 621 pins-txd { 622 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 623 <PINMUX_GPIO78__FUNC_GPIO78>, 624 <PINMUX_GPIO79__FUNC_GPIO79>, 625 <PINMUX_GPIO80__FUNC_GPIO80>; 626 }; 627 }; 628 629 i2c2_pins: i2c2-pins { 630 pins-bus { 631 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 632 <PINMUX_GPIO13__FUNC_SCL2>; 633 bias-pull-up = <1000>; 634 drive-strength = <6>; 635 drive-strength-microamp = <1000>; 636 }; 637 }; 638 639 i2c4_pins: i2c4-pins { 640 pins-bus { 641 pinmux = <PINMUX_GPIO16__FUNC_SDA4>, 642 <PINMUX_GPIO17__FUNC_SCL4>; 643 bias-pull-up = <1000>; 644 drive-strength-microamp = <1000>; 645 }; 646 }; 647 648 i2c6_pins: i2c6-pins { 649 pins { 650 pinmux = <PINMUX_GPIO25__FUNC_SDA6>, 651 <PINMUX_GPIO26__FUNC_SCL6>; 652 bias-disable; 653 }; 654 }; 655 656 mmc0_default_pins: mmc0-default-pins { 657 pins-clk { 658 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 659 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 660 drive-strength = <6>; 661 }; 662 663 pins-cmd-dat { 664 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 665 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 666 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 667 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 668 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 669 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 670 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 671 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 672 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 673 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 674 drive-strength = <6>; 675 input-enable; 676 }; 677 678 pins-rst { 679 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 680 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 681 drive-strength = <6>; 682 }; 683 }; 684 685 mmc0_uhs_pins: mmc0-uhs-pins { 686 pins-clk { 687 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 688 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 689 drive-strength = <8>; 690 }; 691 692 pins-cmd-dat { 693 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 694 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 695 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 696 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 697 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 698 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 699 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 700 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 701 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 702 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 703 drive-strength = <8>; 704 input-enable; 705 }; 706 707 pins-ds { 708 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 709 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 710 drive-strength = <8>; 711 }; 712 713 pins-rst { 714 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 715 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 716 drive-strength = <8>; 717 }; 718 }; 719 720 mmc1_default_pins: mmc1-default-pins { 721 pins-clk { 722 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 723 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 724 drive-strength = <8>; 725 }; 726 727 pins-cmd-dat { 728 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 729 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 730 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 731 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 732 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 733 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 734 drive-strength = <8>; 735 input-enable; 736 }; 737 }; 738 739 mmc1_pins_detect: mmc1-detect-pins { 740 pins-insert { 741 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 742 bias-pull-up; 743 }; 744 }; 745 746 mt6360_pins: mt6360-pins { 747 pins-irq { 748 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>, 749 <PINMUX_GPIO101__FUNC_GPIO101>; 750 input-enable; 751 bias-pull-up; 752 }; 753 }; 754 755 panel_default_pins: panel-pins { 756 pins-rst { 757 pinmux = <PINMUX_GPIO108__FUNC_GPIO108>; 758 bias-pull-up; 759 }; 760 }; 761 762 pcie0_default_pins: pcie0-default-pins { 763 pins-bus { 764 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 765 <PINMUX_GPIO20__FUNC_PERSTN>, 766 <PINMUX_GPIO21__FUNC_CLKREQN>; 767 bias-pull-up; 768 }; 769 }; 770 771 pcie1_default_pins: pcie1-default-pins { 772 pins-bus { 773 pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>, 774 <PINMUX_GPIO1__FUNC_CLKREQN_1>, 775 <PINMUX_GPIO2__FUNC_WAKEN_1>; 776 bias-disable; 777 }; 778 }; 779 780 pwm0_default_pins: pwm0-pins { 781 pins-disp-pwm { 782 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>; 783 }; 784 }; 785 786 spi1_pins: spi1-default-pins { 787 pins-bus { 788 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>, 789 <PINMUX_GPIO137__FUNC_SPIM1_CLK>, 790 <PINMUX_GPIO138__FUNC_SPIM1_MO>, 791 <PINMUX_GPIO139__FUNC_SPIM1_MI>; 792 bias-disable; 793 }; 794 }; 795 796 spi2_pins: spi2-default-pins { 797 pins-bus { 798 pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>, 799 <PINMUX_GPIO141__FUNC_SPIM2_CLK>, 800 <PINMUX_GPIO142__FUNC_SPIM2_MO>, 801 <PINMUX_GPIO143__FUNC_SPIM2_MI>; 802 bias-disable; 803 }; 804 }; 805 806 touch_pins: touch-pins { 807 pins-touch-int { 808 pinmux = <PINMUX_GPIO132__FUNC_GPIO132>; 809 input-enable; 810 bias-disable; 811 }; 812 813 pins-touch-rst { 814 pinmux = <PINMUX_GPIO133__FUNC_GPIO133>; 815 output-high; 816 }; 817 }; 818 819 uart0_pins: uart0-pins { 820 pins-bus { 821 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, 822 <PINMUX_GPIO99__FUNC_URXD0>; 823 }; 824 }; 825 826 uart1_pins: uart1-pins { 827 pins-bus { 828 pinmux = <PINMUX_GPIO102__FUNC_UTXD1>, 829 <PINMUX_GPIO103__FUNC_URXD1>; 830 }; 831 }; 832 833 usb3_port0_pins: usb3p0-default-pins { 834 pins-vbus { 835 pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>; 836 input-enable; 837 }; 838 }; 839 840 usb2_port0_pins: usb2p0-default-pins { 841 pins-iddig { 842 pinmux = <PINMUX_GPIO130__FUNC_IDDIG_1P>; 843 input-enable; 844 bias-pull-up; 845 }; 846 847 pins-vbus { 848 pinmux = <PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P>; 849 output-low; 850 }; 851 }; 852 853 wifi_vreg_pins: wifi-vreg-pins { 854 pins-wifi-pmu-en { 855 pinmux = <PINMUX_GPIO65__FUNC_GPIO65>; 856 output-high; 857 }; 858 859 pins-wifi-vreg-en { 860 pinmux = <PINMUX_GPIO67__FUNC_GPIO67>; 861 }; 862 }; 863}; 864 865&pcie0 { 866 pinctrl-names = "default"; 867 pinctrl-0 = <&pcie0_default_pins>; 868 status = "okay"; 869}; 870 871&pcie1 { 872 pinctrl-names = "default"; 873 pinctrl-0 = <&pcie1_default_pins>; 874 status = "okay"; 875}; 876 877&pciephy { 878 status = "okay"; 879}; 880 881&pmic { 882 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 883}; 884 885&scp { 886 memory-region = <&scp_mem>; 887 firmware-name = "mediatek/mt8195/scp.img"; 888 status = "okay"; 889}; 890 891&sound { 892 compatible = "mediatek,mt8195_mt6359"; 893 model = "mt8395-evk"; 894 pinctrl-names = "default"; 895 pinctrl-0 = <&audio_default_pins>; 896 audio-routing = 897 "Headphone", "Headphone L", 898 "Headphone", "Headphone R"; 899 mediatek,adsp = <&adsp>; 900 status = "okay"; 901 902 headphone-dai-link { 903 link-name = "DL_SRC_BE"; 904 905 codec { 906 sound-dai = <&pmic 0>; 907 }; 908 }; 909}; 910 911&spi1 { 912 /* Exposed at 40 pin connector */ 913 pinctrl-0 = <&spi1_pins>; 914 pinctrl-names = "default"; 915 mediatek,pad-select = <0>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 status = "okay"; 919}; 920 921&spi2 { 922 /* Exposed at 40 pin connector */ 923 pinctrl-0 = <&spi2_pins>; 924 pinctrl-names = "default"; 925 mediatek,pad-select = <0>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 status = "okay"; 929}; 930 931&spmi { 932 #address-cells = <2>; 933 #size-cells = <0>; 934 935 mt6315_6: pmic@6 { 936 compatible = "mediatek,mt6315-regulator"; 937 reg = <0x6 SPMI_USID>; 938 939 regulators { 940 mt6315_6_vbuck1: vbuck1 { 941 regulator-name = "Vbcpu"; 942 regulator-min-microvolt = <300000>; 943 regulator-max-microvolt = <1193750>; 944 regulator-enable-ramp-delay = <256>; 945 regulator-allowed-modes = <0 1 2>; 946 regulator-always-on; 947 }; 948 }; 949 }; 950 951 mt6315_7: pmic@7 { 952 compatible = "mediatek,mt6315-regulator"; 953 reg = <0x7 SPMI_USID>; 954 955 regulators { 956 mt6315_7_vbuck1: vbuck1 { 957 regulator-name = "Vgpu"; 958 regulator-min-microvolt = <300000>; 959 regulator-max-microvolt = <1193750>; 960 regulator-enable-ramp-delay = <256>; 961 regulator-allowed-modes = <0 1 2>; 962 }; 963 }; 964 }; 965}; 966 967&u3phy0 { 968 status = "okay"; 969}; 970 971&u3phy1 { 972 status = "okay"; 973}; 974 975&u3phy2 { 976 status = "okay"; 977}; 978 979&uart0 { 980 /* Exposed at 40 pin connector */ 981 pinctrl-0 = <&uart0_pins>; 982 pinctrl-names = "default"; 983 status = "okay"; 984}; 985 986&uart1 { 987 /* Exposed at 40 pin connector */ 988 pinctrl-0 = <&uart1_pins>; 989 pinctrl-names = "default"; 990 status = "okay"; 991}; 992 993&ssusb0 { 994 pinctrl-names = "default"; 995 pinctrl-0 = <&usb3_port0_pins>; 996 role-switch-default-mode = "host"; 997 usb-role-switch; 998 vusb33-supply = <&mt6359_vusb_ldo_reg>; 999 status = "okay"; 1000 1001 port { 1002 mtu3_hs0_role_sw: endpoint { 1003 remote-endpoint = <&typec_con_hs>; 1004 }; 1005 }; 1006}; 1007 1008&ssusb2 { 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&usb2_port0_pins>; 1011 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1012 status = "okay"; 1013}; 1014 1015&xhci0 { 1016 vbus-supply = <&otg_vbus_regulator>; 1017 status = "okay"; 1018}; 1019 1020&xhci1 { 1021 phys = <&u2port1 PHY_TYPE_USB2>; 1022 /* MT7921's USB Bluetooth has issues with USB2 LPM */ 1023 usb2-lpm-disable; 1024 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1025 vbus-supply = <&vsys>; 1026 mediatek,u3p-dis-msk = <1>; 1027 status = "okay"; 1028}; 1029 1030&xhci2 { 1031 vbus-supply = <&vsys>; 1032 status = "okay"; 1033}; 1034