xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt8370.dtsi (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa)

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2025 Collabora Ltd.
 * Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
 */

/dts-v1/;
#include "mt8188.dtsi"

/ {
	compatible = "mediatek,mt8370";

	cpus {
		/delete-node/ cpu@400;
		/delete-node/ cpu@500;

		cpu-map {
			cluster0 {
				/delete-node/ core4;
				/delete-node/ core5;
			};
		};
	};
};

&cpu6 {
	clock-frequency = <2200000000>;
};

&cpu7 {
	clock-frequency = <2200000000>;
};

&cpu_little0_cooling_map0 {
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};

&cpu_little1_cooling_map0 {
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};

&cpu_little2_cooling_map0 {
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};

&cpu_little3_cooling_map0 {
	cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
				<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};

/*
 * Please note that overriding compatibles is a discouraged practice and is a
 * clear indication of nodes not being, well, compatible!
 *
 * This is a special case, where the GPU is the same as MT8188, but with one
 * of the cores fused out in this lower-binned SoC.
 */
&gpu {
	compatible = "mediatek,mt8370-mali", "arm,mali-valhall-jm";

	power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
			<&spm MT8188_POWER_DOMAIN_MFG3>;

	power-domain-names = "core0", "core1";
};

&ppi_cluster0 {
	affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
};