1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8192-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 12#include <dt-bindings/power/mt8192-power.h> 13 14/ { 15 compatible = "mediatek,mt8192"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clk26m: oscillator0 { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <26000000>; 24 clock-output-names = "clk26m"; 25 }; 26 27 clk32k: oscillator1 { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32768>; 31 clock-output-names = "clk32k"; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a55"; 41 reg = <0x000>; 42 enable-method = "psci"; 43 clock-frequency = <1701000000>; 44 cpu-idle-states = <&cpuoff_l &clusteroff_l>; 45 next-level-cache = <&l2_0>; 46 capacity-dmips-mhz = <530>; 47 }; 48 49 cpu1: cpu@100 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 reg = <0x100>; 53 enable-method = "psci"; 54 clock-frequency = <1701000000>; 55 cpu-idle-states = <&cpuoff_l &clusteroff_l>; 56 next-level-cache = <&l2_0>; 57 capacity-dmips-mhz = <530>; 58 }; 59 60 cpu2: cpu@200 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a55"; 63 reg = <0x200>; 64 enable-method = "psci"; 65 clock-frequency = <1701000000>; 66 cpu-idle-states = <&cpuoff_l &clusteroff_l>; 67 next-level-cache = <&l2_0>; 68 capacity-dmips-mhz = <530>; 69 }; 70 71 cpu3: cpu@300 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x300>; 75 enable-method = "psci"; 76 clock-frequency = <1701000000>; 77 cpu-idle-states = <&cpuoff_l &clusteroff_l>; 78 next-level-cache = <&l2_0>; 79 capacity-dmips-mhz = <530>; 80 }; 81 82 cpu4: cpu@400 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a76"; 85 reg = <0x400>; 86 enable-method = "psci"; 87 clock-frequency = <2171000000>; 88 cpu-idle-states = <&cpuoff_b &clusteroff_b>; 89 next-level-cache = <&l2_1>; 90 capacity-dmips-mhz = <1024>; 91 }; 92 93 cpu5: cpu@500 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a76"; 96 reg = <0x500>; 97 enable-method = "psci"; 98 clock-frequency = <2171000000>; 99 cpu-idle-states = <&cpuoff_b &clusteroff_b>; 100 next-level-cache = <&l2_1>; 101 capacity-dmips-mhz = <1024>; 102 }; 103 104 cpu6: cpu@600 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a76"; 107 reg = <0x600>; 108 enable-method = "psci"; 109 clock-frequency = <2171000000>; 110 cpu-idle-states = <&cpuoff_b &clusteroff_b>; 111 next-level-cache = <&l2_1>; 112 capacity-dmips-mhz = <1024>; 113 }; 114 115 cpu7: cpu@700 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a76"; 118 reg = <0x700>; 119 enable-method = "psci"; 120 clock-frequency = <2171000000>; 121 cpu-idle-states = <&cpuoff_b &clusteroff_b>; 122 next-level-cache = <&l2_1>; 123 capacity-dmips-mhz = <1024>; 124 }; 125 126 cpu-map { 127 cluster0 { 128 core0 { 129 cpu = <&cpu0>; 130 }; 131 core1 { 132 cpu = <&cpu1>; 133 }; 134 core2 { 135 cpu = <&cpu2>; 136 }; 137 core3 { 138 cpu = <&cpu3>; 139 }; 140 }; 141 142 cluster1 { 143 core0 { 144 cpu = <&cpu4>; 145 }; 146 core1 { 147 cpu = <&cpu5>; 148 }; 149 core2 { 150 cpu = <&cpu6>; 151 }; 152 core3 { 153 cpu = <&cpu7>; 154 }; 155 }; 156 }; 157 158 l2_0: l2-cache0 { 159 compatible = "cache"; 160 next-level-cache = <&l3_0>; 161 }; 162 163 l2_1: l2-cache1 { 164 compatible = "cache"; 165 next-level-cache = <&l3_0>; 166 }; 167 168 l3_0: l3-cache { 169 compatible = "cache"; 170 }; 171 172 idle-states { 173 entry-method = "arm,psci"; 174 cpuoff_l: cpuoff_l { 175 compatible = "arm,idle-state"; 176 arm,psci-suspend-param = <0x00010001>; 177 local-timer-stop; 178 entry-latency-us = <55>; 179 exit-latency-us = <140>; 180 min-residency-us = <780>; 181 }; 182 cpuoff_b: cpuoff_b { 183 compatible = "arm,idle-state"; 184 arm,psci-suspend-param = <0x00010001>; 185 local-timer-stop; 186 entry-latency-us = <35>; 187 exit-latency-us = <145>; 188 min-residency-us = <720>; 189 }; 190 clusteroff_l: clusteroff_l { 191 compatible = "arm,idle-state"; 192 arm,psci-suspend-param = <0x01010002>; 193 local-timer-stop; 194 entry-latency-us = <60>; 195 exit-latency-us = <155>; 196 min-residency-us = <860>; 197 }; 198 clusteroff_b: clusteroff_b { 199 compatible = "arm,idle-state"; 200 arm,psci-suspend-param = <0x01010002>; 201 local-timer-stop; 202 entry-latency-us = <40>; 203 exit-latency-us = <155>; 204 min-residency-us = <780>; 205 }; 206 }; 207 }; 208 209 pmu-a55 { 210 compatible = "arm,cortex-a55-pmu"; 211 interrupt-parent = <&gic>; 212 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 213 }; 214 215 pmu-a76 { 216 compatible = "arm,cortex-a76-pmu"; 217 interrupt-parent = <&gic>; 218 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 219 }; 220 221 psci { 222 compatible = "arm,psci-1.0"; 223 method = "smc"; 224 }; 225 226 timer: timer { 227 compatible = "arm,armv8-timer"; 228 interrupt-parent = <&gic>; 229 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 230 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 231 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 232 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 233 clock-frequency = <13000000>; 234 }; 235 236 soc { 237 #address-cells = <2>; 238 #size-cells = <2>; 239 compatible = "simple-bus"; 240 ranges; 241 242 gic: interrupt-controller@c000000 { 243 compatible = "arm,gic-v3"; 244 #interrupt-cells = <4>; 245 #redistributor-regions = <1>; 246 interrupt-parent = <&gic>; 247 interrupt-controller; 248 reg = <0 0x0c000000 0 0x40000>, 249 <0 0x0c040000 0 0x200000>; 250 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 251 252 ppi-partitions { 253 ppi_cluster0: interrupt-partition-0 { 254 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 255 }; 256 ppi_cluster1: interrupt-partition-1 { 257 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 258 }; 259 }; 260 }; 261 262 topckgen: syscon@10000000 { 263 compatible = "mediatek,mt8192-topckgen", "syscon"; 264 reg = <0 0x10000000 0 0x1000>; 265 #clock-cells = <1>; 266 }; 267 268 infracfg: syscon@10001000 { 269 compatible = "mediatek,mt8192-infracfg", "syscon"; 270 reg = <0 0x10001000 0 0x1000>; 271 #clock-cells = <1>; 272 }; 273 274 pericfg: syscon@10003000 { 275 compatible = "mediatek,mt8192-pericfg", "syscon"; 276 reg = <0 0x10003000 0 0x1000>; 277 #clock-cells = <1>; 278 }; 279 280 pio: pinctrl@10005000 { 281 compatible = "mediatek,mt8192-pinctrl"; 282 reg = <0 0x10005000 0 0x1000>, 283 <0 0x11c20000 0 0x1000>, 284 <0 0x11d10000 0 0x1000>, 285 <0 0x11d30000 0 0x1000>, 286 <0 0x11d40000 0 0x1000>, 287 <0 0x11e20000 0 0x1000>, 288 <0 0x11e70000 0 0x1000>, 289 <0 0x11ea0000 0 0x1000>, 290 <0 0x11f20000 0 0x1000>, 291 <0 0x11f30000 0 0x1000>, 292 <0 0x1000b000 0 0x1000>; 293 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 294 "iocfg_bl", "iocfg_br", "iocfg_lm", 295 "iocfg_lb", "iocfg_rt", "iocfg_lt", 296 "iocfg_tl", "eint"; 297 gpio-controller; 298 #gpio-cells = <2>; 299 gpio-ranges = <&pio 0 0 220>; 300 interrupt-controller; 301 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 302 #interrupt-cells = <2>; 303 }; 304 305 scpsys: syscon@10006000 { 306 compatible = "syscon", "simple-mfd"; 307 reg = <0 0x10006000 0 0x1000>; 308 #power-domain-cells = <1>; 309 310 /* System Power Manager */ 311 spm: power-controller { 312 compatible = "mediatek,mt8192-power-controller"; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 #power-domain-cells = <1>; 316 317 /* power domain of the SoC */ 318 power-domain@MT8192_POWER_DOMAIN_AUDIO { 319 reg = <MT8192_POWER_DOMAIN_AUDIO>; 320 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 321 <&infracfg CLK_INFRA_AUDIO_26M_B>, 322 <&infracfg CLK_INFRA_AUDIO>; 323 clock-names = "audio", "audio1", "audio2"; 324 mediatek,infracfg = <&infracfg>; 325 #power-domain-cells = <0>; 326 }; 327 328 power-domain@MT8192_POWER_DOMAIN_CONN { 329 reg = <MT8192_POWER_DOMAIN_CONN>; 330 clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 331 clock-names = "conn"; 332 mediatek,infracfg = <&infracfg>; 333 #power-domain-cells = <0>; 334 }; 335 336 power-domain@MT8192_POWER_DOMAIN_MFG0 { 337 reg = <MT8192_POWER_DOMAIN_MFG0>; 338 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 339 clock-names = "mfg"; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 #power-domain-cells = <1>; 343 344 power-domain@MT8192_POWER_DOMAIN_MFG1 { 345 reg = <MT8192_POWER_DOMAIN_MFG1>; 346 mediatek,infracfg = <&infracfg>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 #power-domain-cells = <1>; 350 351 power-domain@MT8192_POWER_DOMAIN_MFG2 { 352 reg = <MT8192_POWER_DOMAIN_MFG2>; 353 #power-domain-cells = <0>; 354 }; 355 356 power-domain@MT8192_POWER_DOMAIN_MFG3 { 357 reg = <MT8192_POWER_DOMAIN_MFG3>; 358 #power-domain-cells = <0>; 359 }; 360 361 power-domain@MT8192_POWER_DOMAIN_MFG4 { 362 reg = <MT8192_POWER_DOMAIN_MFG4>; 363 #power-domain-cells = <0>; 364 }; 365 366 power-domain@MT8192_POWER_DOMAIN_MFG5 { 367 reg = <MT8192_POWER_DOMAIN_MFG5>; 368 #power-domain-cells = <0>; 369 }; 370 371 power-domain@MT8192_POWER_DOMAIN_MFG6 { 372 reg = <MT8192_POWER_DOMAIN_MFG6>; 373 #power-domain-cells = <0>; 374 }; 375 }; 376 }; 377 378 power-domain@MT8192_POWER_DOMAIN_DISP { 379 reg = <MT8192_POWER_DOMAIN_DISP>; 380 clocks = <&topckgen CLK_TOP_DISP_SEL>, 381 <&mmsys CLK_MM_SMI_INFRA>, 382 <&mmsys CLK_MM_SMI_COMMON>, 383 <&mmsys CLK_MM_SMI_GALS>, 384 <&mmsys CLK_MM_SMI_IOMMU>; 385 clock-names = "disp", "disp-0", "disp-1", "disp-2", 386 "disp-3"; 387 mediatek,infracfg = <&infracfg>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 #power-domain-cells = <1>; 391 392 power-domain@MT8192_POWER_DOMAIN_IPE { 393 reg = <MT8192_POWER_DOMAIN_IPE>; 394 clocks = <&topckgen CLK_TOP_IPE_SEL>, 395 <&ipesys CLK_IPE_LARB19>, 396 <&ipesys CLK_IPE_LARB20>, 397 <&ipesys CLK_IPE_SMI_SUBCOM>, 398 <&ipesys CLK_IPE_GALS>; 399 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 400 "ipe-3"; 401 mediatek,infracfg = <&infracfg>; 402 #power-domain-cells = <0>; 403 }; 404 405 power-domain@MT8192_POWER_DOMAIN_ISP { 406 reg = <MT8192_POWER_DOMAIN_ISP>; 407 clocks = <&topckgen CLK_TOP_IMG1_SEL>, 408 <&imgsys CLK_IMG_LARB9>, 409 <&imgsys CLK_IMG_GALS>; 410 clock-names = "isp", "isp-0", "isp-1"; 411 mediatek,infracfg = <&infracfg>; 412 #power-domain-cells = <0>; 413 }; 414 415 power-domain@MT8192_POWER_DOMAIN_ISP2 { 416 reg = <MT8192_POWER_DOMAIN_ISP2>; 417 clocks = <&topckgen CLK_TOP_IMG2_SEL>, 418 <&imgsys2 CLK_IMG2_LARB11>, 419 <&imgsys2 CLK_IMG2_GALS>; 420 clock-names = "isp2", "isp2-0", "isp2-1"; 421 mediatek,infracfg = <&infracfg>; 422 #power-domain-cells = <0>; 423 }; 424 425 power-domain@MT8192_POWER_DOMAIN_MDP { 426 reg = <MT8192_POWER_DOMAIN_MDP>; 427 clocks = <&topckgen CLK_TOP_MDP_SEL>, 428 <&mdpsys CLK_MDP_SMI0>; 429 clock-names = "mdp", "mdp-0"; 430 mediatek,infracfg = <&infracfg>; 431 #power-domain-cells = <0>; 432 }; 433 434 power-domain@MT8192_POWER_DOMAIN_VENC { 435 reg = <MT8192_POWER_DOMAIN_VENC>; 436 clocks = <&topckgen CLK_TOP_VENC_SEL>, 437 <&vencsys CLK_VENC_SET1_VENC>; 438 clock-names = "venc", "venc-0"; 439 mediatek,infracfg = <&infracfg>; 440 #power-domain-cells = <0>; 441 }; 442 443 power-domain@MT8192_POWER_DOMAIN_VDEC { 444 reg = <MT8192_POWER_DOMAIN_VDEC>; 445 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 446 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 447 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 448 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 449 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 450 mediatek,infracfg = <&infracfg>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 #power-domain-cells = <1>; 454 455 power-domain@MT8192_POWER_DOMAIN_VDEC2 { 456 reg = <MT8192_POWER_DOMAIN_VDEC2>; 457 clocks = <&vdecsys CLK_VDEC_VDEC>, 458 <&vdecsys CLK_VDEC_LAT>, 459 <&vdecsys CLK_VDEC_LARB1>; 460 clock-names = "vdec2-0", "vdec2-1", 461 "vdec2-2"; 462 #power-domain-cells = <0>; 463 }; 464 }; 465 466 power-domain@MT8192_POWER_DOMAIN_CAM { 467 reg = <MT8192_POWER_DOMAIN_CAM>; 468 clocks = <&topckgen CLK_TOP_CAM_SEL>, 469 <&camsys CLK_CAM_LARB13>, 470 <&camsys CLK_CAM_LARB14>, 471 <&camsys CLK_CAM_CCU_GALS>, 472 <&camsys CLK_CAM_CAM2MM_GALS>; 473 clock-names = "cam", "cam-0", "cam-1", "cam-2", 474 "cam-3"; 475 mediatek,infracfg = <&infracfg>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 #power-domain-cells = <1>; 479 480 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 481 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 482 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 483 clock-names = "cam_rawa-0"; 484 #power-domain-cells = <0>; 485 }; 486 487 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 488 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 489 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 490 clock-names = "cam_rawb-0"; 491 #power-domain-cells = <0>; 492 }; 493 494 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 495 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 496 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 497 clock-names = "cam_rawc-0"; 498 #power-domain-cells = <0>; 499 }; 500 }; 501 }; 502 }; 503 }; 504 505 watchdog: watchdog@10007000 { 506 compatible = "mediatek,mt8192-wdt"; 507 reg = <0 0x10007000 0 0x100>; 508 #reset-cells = <1>; 509 }; 510 511 apmixedsys: syscon@1000c000 { 512 compatible = "mediatek,mt8192-apmixedsys", "syscon"; 513 reg = <0 0x1000c000 0 0x1000>; 514 #clock-cells = <1>; 515 }; 516 517 systimer: timer@10017000 { 518 compatible = "mediatek,mt8192-timer", 519 "mediatek,mt6765-timer"; 520 reg = <0 0x10017000 0 0x1000>; 521 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 522 clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 523 clock-names = "clk13m"; 524 }; 525 526 scp_adsp: clock-controller@10720000 { 527 compatible = "mediatek,mt8192-scp_adsp"; 528 reg = <0 0x10720000 0 0x1000>; 529 #clock-cells = <1>; 530 }; 531 532 uart0: serial@11002000 { 533 compatible = "mediatek,mt8192-uart", 534 "mediatek,mt6577-uart"; 535 reg = <0 0x11002000 0 0x1000>; 536 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 537 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 538 clock-names = "baud", "bus"; 539 status = "disabled"; 540 }; 541 542 uart1: serial@11003000 { 543 compatible = "mediatek,mt8192-uart", 544 "mediatek,mt6577-uart"; 545 reg = <0 0x11003000 0 0x1000>; 546 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 547 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 548 clock-names = "baud", "bus"; 549 status = "disabled"; 550 }; 551 552 imp_iic_wrap_c: clock-controller@11007000 { 553 compatible = "mediatek,mt8192-imp_iic_wrap_c"; 554 reg = <0 0x11007000 0 0x1000>; 555 #clock-cells = <1>; 556 }; 557 558 spi0: spi@1100a000 { 559 compatible = "mediatek,mt8192-spi", 560 "mediatek,mt6765-spi"; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 reg = <0 0x1100a000 0 0x1000>; 564 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 565 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 566 <&topckgen CLK_TOP_SPI_SEL>, 567 <&infracfg CLK_INFRA_SPI0>; 568 clock-names = "parent-clk", "sel-clk", "spi-clk"; 569 status = "disabled"; 570 }; 571 572 spi1: spi@11010000 { 573 compatible = "mediatek,mt8192-spi", 574 "mediatek,mt6765-spi"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 reg = <0 0x11010000 0 0x1000>; 578 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 579 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 580 <&topckgen CLK_TOP_SPI_SEL>, 581 <&infracfg CLK_INFRA_SPI1>; 582 clock-names = "parent-clk", "sel-clk", "spi-clk"; 583 status = "disabled"; 584 }; 585 586 spi2: spi@11012000 { 587 compatible = "mediatek,mt8192-spi", 588 "mediatek,mt6765-spi"; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 reg = <0 0x11012000 0 0x1000>; 592 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 593 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 594 <&topckgen CLK_TOP_SPI_SEL>, 595 <&infracfg CLK_INFRA_SPI2>; 596 clock-names = "parent-clk", "sel-clk", "spi-clk"; 597 status = "disabled"; 598 }; 599 600 spi3: spi@11013000 { 601 compatible = "mediatek,mt8192-spi", 602 "mediatek,mt6765-spi"; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 reg = <0 0x11013000 0 0x1000>; 606 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 607 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 608 <&topckgen CLK_TOP_SPI_SEL>, 609 <&infracfg CLK_INFRA_SPI3>; 610 clock-names = "parent-clk", "sel-clk", "spi-clk"; 611 status = "disabled"; 612 }; 613 614 spi4: spi@11018000 { 615 compatible = "mediatek,mt8192-spi", 616 "mediatek,mt6765-spi"; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 reg = <0 0x11018000 0 0x1000>; 620 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 621 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 622 <&topckgen CLK_TOP_SPI_SEL>, 623 <&infracfg CLK_INFRA_SPI4>; 624 clock-names = "parent-clk", "sel-clk", "spi-clk"; 625 status = "disabled"; 626 }; 627 628 spi5: spi@11019000 { 629 compatible = "mediatek,mt8192-spi", 630 "mediatek,mt6765-spi"; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 reg = <0 0x11019000 0 0x1000>; 634 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 635 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 636 <&topckgen CLK_TOP_SPI_SEL>, 637 <&infracfg CLK_INFRA_SPI5>; 638 clock-names = "parent-clk", "sel-clk", "spi-clk"; 639 status = "disabled"; 640 }; 641 642 spi6: spi@1101d000 { 643 compatible = "mediatek,mt8192-spi", 644 "mediatek,mt6765-spi"; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 reg = <0 0x1101d000 0 0x1000>; 648 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 649 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 650 <&topckgen CLK_TOP_SPI_SEL>, 651 <&infracfg CLK_INFRA_SPI6>; 652 clock-names = "parent-clk", "sel-clk", "spi-clk"; 653 status = "disabled"; 654 }; 655 656 spi7: spi@1101e000 { 657 compatible = "mediatek,mt8192-spi", 658 "mediatek,mt6765-spi"; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 reg = <0 0x1101e000 0 0x1000>; 662 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 663 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 664 <&topckgen CLK_TOP_SPI_SEL>, 665 <&infracfg CLK_INFRA_SPI7>; 666 clock-names = "parent-clk", "sel-clk", "spi-clk"; 667 status = "disabled"; 668 }; 669 670 nor_flash: spi@11234000 { 671 compatible = "mediatek,mt8192-nor"; 672 reg = <0 0x11234000 0 0xe0>; 673 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 674 clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 675 <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 676 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 677 clock-names = "spi", "sf", "axi"; 678 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 679 assigned-clock-parents = <&clk26m>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 status = "disable"; 683 }; 684 685 audsys: clock-controller@11210000 { 686 compatible = "mediatek,mt8192-audsys", "syscon"; 687 reg = <0 0x11210000 0 0x1000>; 688 #clock-cells = <1>; 689 }; 690 691 i2c3: i2c@11cb0000 { 692 compatible = "mediatek,mt8192-i2c"; 693 reg = <0 0x11cb0000 0 0x1000>, 694 <0 0x10217300 0 0x80>; 695 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 696 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 697 <&infracfg CLK_INFRA_AP_DMA>; 698 clock-names = "main", "dma"; 699 clock-div = <1>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 status = "disabled"; 703 }; 704 705 imp_iic_wrap_e: clock-controller@11cb1000 { 706 compatible = "mediatek,mt8192-imp_iic_wrap_e"; 707 reg = <0 0x11cb1000 0 0x1000>; 708 #clock-cells = <1>; 709 }; 710 711 i2c7: i2c@11d00000 { 712 compatible = "mediatek,mt8192-i2c"; 713 reg = <0 0x11d00000 0 0x1000>, 714 <0 0x10217600 0 0x180>; 715 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 716 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 717 <&infracfg CLK_INFRA_AP_DMA>; 718 clock-names = "main", "dma"; 719 clock-div = <1>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 }; 724 725 i2c8: i2c@11d01000 { 726 compatible = "mediatek,mt8192-i2c"; 727 reg = <0 0x11d01000 0 0x1000>, 728 <0 0x10217780 0 0x180>; 729 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 730 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 731 <&infracfg CLK_INFRA_AP_DMA>; 732 clock-names = "main", "dma"; 733 clock-div = <1>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 status = "disabled"; 737 }; 738 739 i2c9: i2c@11d02000 { 740 compatible = "mediatek,mt8192-i2c"; 741 reg = <0 0x11d02000 0 0x1000>, 742 <0 0x10217900 0 0x180>; 743 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 744 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 745 <&infracfg CLK_INFRA_AP_DMA>; 746 clock-names = "main", "dma"; 747 clock-div = <1>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 status = "disabled"; 751 }; 752 753 imp_iic_wrap_s: clock-controller@11d03000 { 754 compatible = "mediatek,mt8192-imp_iic_wrap_s"; 755 reg = <0 0x11d03000 0 0x1000>; 756 #clock-cells = <1>; 757 }; 758 759 i2c1: i2c@11d20000 { 760 compatible = "mediatek,mt8192-i2c"; 761 reg = <0 0x11d20000 0 0x1000>, 762 <0 0x10217100 0 0x80>; 763 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 764 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 765 <&infracfg CLK_INFRA_AP_DMA>; 766 clock-names = "main", "dma"; 767 clock-div = <1>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 status = "disabled"; 771 }; 772 773 i2c2: i2c@11d21000 { 774 compatible = "mediatek,mt8192-i2c"; 775 reg = <0 0x11d21000 0 0x1000>, 776 <0 0x10217180 0 0x180>; 777 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 778 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 779 <&infracfg CLK_INFRA_AP_DMA>; 780 clock-names = "main", "dma"; 781 clock-div = <1>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 status = "disabled"; 785 }; 786 787 i2c4: i2c@11d22000 { 788 compatible = "mediatek,mt8192-i2c"; 789 reg = <0 0x11d22000 0 0x1000>, 790 <0 0x10217380 0 0x180>; 791 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 792 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 793 <&infracfg CLK_INFRA_AP_DMA>; 794 clock-names = "main", "dma"; 795 clock-div = <1>; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 status = "disabled"; 799 }; 800 801 imp_iic_wrap_ws: clock-controller@11d23000 { 802 compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 803 reg = <0 0x11d23000 0 0x1000>; 804 #clock-cells = <1>; 805 }; 806 807 i2c5: i2c@11e00000 { 808 compatible = "mediatek,mt8192-i2c"; 809 reg = <0 0x11e00000 0 0x1000>, 810 <0 0x10217500 0 0x80>; 811 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 812 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 813 <&infracfg CLK_INFRA_AP_DMA>; 814 clock-names = "main", "dma"; 815 clock-div = <1>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 status = "disabled"; 819 }; 820 821 imp_iic_wrap_w: clock-controller@11e01000 { 822 compatible = "mediatek,mt8192-imp_iic_wrap_w"; 823 reg = <0 0x11e01000 0 0x1000>; 824 #clock-cells = <1>; 825 }; 826 827 i2c0: i2c@11f00000 { 828 compatible = "mediatek,mt8192-i2c"; 829 reg = <0 0x11f00000 0 0x1000>, 830 <0 0x10217080 0 0x80>; 831 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 832 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 833 <&infracfg CLK_INFRA_AP_DMA>; 834 clock-names = "main", "dma"; 835 clock-div = <1>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 i2c6: i2c@11f01000 { 842 compatible = "mediatek,mt8192-i2c"; 843 reg = <0 0x11f01000 0 0x1000>, 844 <0 0x10217580 0 0x80>; 845 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 846 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 847 <&infracfg CLK_INFRA_AP_DMA>; 848 clock-names = "main", "dma"; 849 clock-div = <1>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 status = "disabled"; 853 }; 854 855 imp_iic_wrap_n: clock-controller@11f02000 { 856 compatible = "mediatek,mt8192-imp_iic_wrap_n"; 857 reg = <0 0x11f02000 0 0x1000>; 858 #clock-cells = <1>; 859 }; 860 861 msdc_top: clock-controller@11f10000 { 862 compatible = "mediatek,mt8192-msdc_top"; 863 reg = <0 0x11f10000 0 0x1000>; 864 #clock-cells = <1>; 865 }; 866 867 msdc: clock-controller@11f60000 { 868 compatible = "mediatek,mt8192-msdc"; 869 reg = <0 0x11f60000 0 0x1000>; 870 #clock-cells = <1>; 871 }; 872 873 mfgcfg: clock-controller@13fbf000 { 874 compatible = "mediatek,mt8192-mfgcfg"; 875 reg = <0 0x13fbf000 0 0x1000>; 876 #clock-cells = <1>; 877 }; 878 879 mmsys: syscon@14000000 { 880 compatible = "mediatek,mt8192-mmsys", "syscon"; 881 reg = <0 0x14000000 0 0x1000>; 882 #clock-cells = <1>; 883 }; 884 885 imgsys: clock-controller@15020000 { 886 compatible = "mediatek,mt8192-imgsys"; 887 reg = <0 0x15020000 0 0x1000>; 888 #clock-cells = <1>; 889 }; 890 891 imgsys2: clock-controller@15820000 { 892 compatible = "mediatek,mt8192-imgsys2"; 893 reg = <0 0x15820000 0 0x1000>; 894 #clock-cells = <1>; 895 }; 896 897 vdecsys_soc: clock-controller@1600f000 { 898 compatible = "mediatek,mt8192-vdecsys_soc"; 899 reg = <0 0x1600f000 0 0x1000>; 900 #clock-cells = <1>; 901 }; 902 903 vdecsys: clock-controller@1602f000 { 904 compatible = "mediatek,mt8192-vdecsys"; 905 reg = <0 0x1602f000 0 0x1000>; 906 #clock-cells = <1>; 907 }; 908 909 vencsys: clock-controller@17000000 { 910 compatible = "mediatek,mt8192-vencsys"; 911 reg = <0 0x17000000 0 0x1000>; 912 #clock-cells = <1>; 913 }; 914 915 camsys: clock-controller@1a000000 { 916 compatible = "mediatek,mt8192-camsys"; 917 reg = <0 0x1a000000 0 0x1000>; 918 #clock-cells = <1>; 919 }; 920 921 camsys_rawa: clock-controller@1a04f000 { 922 compatible = "mediatek,mt8192-camsys_rawa"; 923 reg = <0 0x1a04f000 0 0x1000>; 924 #clock-cells = <1>; 925 }; 926 927 camsys_rawb: clock-controller@1a06f000 { 928 compatible = "mediatek,mt8192-camsys_rawb"; 929 reg = <0 0x1a06f000 0 0x1000>; 930 #clock-cells = <1>; 931 }; 932 933 camsys_rawc: clock-controller@1a08f000 { 934 compatible = "mediatek,mt8192-camsys_rawc"; 935 reg = <0 0x1a08f000 0 0x1000>; 936 #clock-cells = <1>; 937 }; 938 939 ipesys: clock-controller@1b000000 { 940 compatible = "mediatek,mt8192-ipesys"; 941 reg = <0 0x1b000000 0 0x1000>; 942 #clock-cells = <1>; 943 }; 944 945 mdpsys: clock-controller@1f000000 { 946 compatible = "mediatek,mt8192-mdpsys"; 947 reg = <0 0x1f000000 0 0x1000>; 948 #clock-cells = <1>; 949 }; 950 }; 951}; 952