1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 serial0 = &uart0; 15 }; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 memory@40000000 { 22 device_type = "memory"; 23 reg = <0 0x40000000 0 0x80000000>; 24 }; 25 26 /* system wide LDO 1.8V power rail */ 27 pp1800_ldo_g: regulator-1v8-g { 28 compatible = "regulator-fixed"; 29 regulator-name = "pp1800_ldo_g"; 30 regulator-always-on; 31 regulator-boot-on; 32 regulator-min-microvolt = <1800000>; 33 regulator-max-microvolt = <1800000>; 34 vin-supply = <&pp3300_g>; 35 }; 36 37 /* system wide switching 3.3V power rail */ 38 pp3300_g: regulator-3v3-g { 39 compatible = "regulator-fixed"; 40 regulator-name = "pp3300_g"; 41 regulator-always-on; 42 regulator-boot-on; 43 regulator-min-microvolt = <3300000>; 44 regulator-max-microvolt = <3300000>; 45 vin-supply = <&ppvar_sys>; 46 }; 47 48 /* system wide LDO 3.3V power rail */ 49 pp3300_ldo_z: regulator-3v3-z { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp3300_ldo_z"; 52 regulator-always-on; 53 regulator-boot-on; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 vin-supply = <&ppvar_sys>; 57 }; 58 59 /* separately switched 3.3V power rail */ 60 pp3300_u: regulator-3v3-u { 61 compatible = "regulator-fixed"; 62 regulator-name = "pp3300_u"; 63 regulator-always-on; 64 regulator-boot-on; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 /* enable pin wired to GPIO controlled by EC */ 68 vin-supply = <&pp3300_g>; 69 }; 70 71 pp3300_wlan: regulator-3v3-wlan { 72 compatible = "regulator-fixed"; 73 regulator-name = "pp3300_wlan"; 74 regulator-always-on; 75 regulator-boot-on; 76 regulator-min-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp3300_wlan_pins>; 80 enable-active-high; 81 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 82 }; 83 84 /* system wide switching 5.0V power rail */ 85 pp5000_a: regulator-5v0-a { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp5000_a"; 88 regulator-always-on; 89 regulator-boot-on; 90 regulator-min-microvolt = <5000000>; 91 regulator-max-microvolt = <5000000>; 92 vin-supply = <&ppvar_sys>; 93 }; 94 95 /* system wide semi-regulated power rail from battery or USB */ 96 ppvar_sys: regulator-var-sys { 97 compatible = "regulator-fixed"; 98 regulator-name = "ppvar_sys"; 99 regulator-always-on; 100 regulator-boot-on; 101 }; 102 103 reserved_memory: reserved-memory { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 scp_mem_reserved: scp@50000000 { 109 compatible = "shared-dma-pool"; 110 reg = <0 0x50000000 0 0x2900000>; 111 no-map; 112 }; 113 114 wifi_restricted_dma_region: wifi@c0000000 { 115 compatible = "restricted-dma-pool"; 116 reg = <0 0xc0000000 0 0x4000000>; 117 }; 118 }; 119}; 120 121&i2c0 { 122 status = "okay"; 123 124 clock-frequency = <400000>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&i2c0_pins>; 127 128 touchscreen: touchscreen@10 { 129 reg = <0x10>; 130 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&touchscreen_pins>; 133 }; 134}; 135 136&i2c1 { 137 status = "okay"; 138 139 clock-frequency = <400000>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&i2c1_pins>; 142}; 143 144&i2c2 { 145 status = "okay"; 146 147 clock-frequency = <400000>; 148 clock-stretch-ns = <12600>; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&i2c2_pins>; 151 152 trackpad@15 { 153 compatible = "elan,ekth3000"; 154 reg = <0x15>; 155 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&trackpad_pins>; 158 vcc-supply = <&pp3300_u>; 159 wakeup-source; 160 }; 161}; 162 163&i2c3 { 164 status = "okay"; 165 166 clock-frequency = <400000>; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&i2c3_pins>; 169}; 170 171&i2c7 { 172 status = "okay"; 173 174 clock-frequency = <400000>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&i2c7_pins>; 177}; 178 179&mmc0 { 180 status = "okay"; 181 182 pinctrl-names = "default", "state_uhs"; 183 pinctrl-0 = <&mmc0_default_pins>; 184 pinctrl-1 = <&mmc0_uhs_pins>; 185 bus-width = <8>; 186 max-frequency = <200000000>; 187 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 188 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 189 cap-mmc-highspeed; 190 mmc-hs200-1_8v; 191 mmc-hs400-1_8v; 192 supports-cqe; 193 cap-mmc-hw-reset; 194 mmc-hs400-enhanced-strobe; 195 hs400-ds-delay = <0x12814>; 196 no-sdio; 197 no-sd; 198 non-removable; 199}; 200 201&mmc1 { 202 status = "okay"; 203 204 pinctrl-names = "default", "state_uhs"; 205 pinctrl-0 = <&mmc1_default_pins>; 206 pinctrl-1 = <&mmc1_uhs_pins>; 207 bus-width = <4>; 208 max-frequency = <200000000>; 209 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 210 vmmc-supply = <&mt6360_ldo5_reg>; 211 vqmmc-supply = <&mt6360_ldo3_reg>; 212 cap-sd-highspeed; 213 sd-uhs-sdr50; 214 sd-uhs-sdr104; 215 no-sdio; 216 no-mmc; 217}; 218 219/* for CORE */ 220&mt6359_vgpu11_buck_reg { 221 regulator-always-on; 222}; 223 224&mt6359_vgpu11_sshub_buck_reg { 225 regulator-always-on; 226 regulator-min-microvolt = <575000>; 227 regulator-max-microvolt = <575000>; 228}; 229 230&mt6359_vrf12_ldo_reg { 231 regulator-always-on; 232}; 233 234&mt6359_vufs_ldo_reg { 235 regulator-always-on; 236}; 237 238&mt6359codec { 239 mediatek,dmic-mode = <1>; /* one-wire */ 240 mediatek,mic-type-0 = <2>; /* DMIC */ 241 mediatek,mic-type-2 = <2>; /* DMIC */ 242}; 243 244&nor_flash { 245 status = "okay"; 246 247 pinctrl-names = "default"; 248 pinctrl-0 = <&nor_flash_pins>; 249 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 250 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 251 252 flash@0 { 253 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 254 reg = <0>; 255 spi-max-frequency = <52000000>; 256 spi-rx-bus-width = <2>; 257 spi-tx-bus-width = <2>; 258 }; 259}; 260 261&pcie { 262 pinctrl-names = "default"; 263 pinctrl-0 = <&pcie_pins>; 264 265 pcie0: pcie@0,0 { 266 device_type = "pci"; 267 reg = <0x0000 0 0 0 0>; 268 num-lanes = <1>; 269 bus-range = <0x1 0x1>; 270 271 #address-cells = <3>; 272 #size-cells = <2>; 273 ranges; 274 275 wifi: wifi@0,0 { 276 reg = <0x10000 0 0 0 0x100000>, 277 <0x10000 0 0x100000 0 0x100000>; 278 memory-region = <&wifi_restricted_dma_region>; 279 }; 280 }; 281}; 282 283&pio { 284 /* 220 lines */ 285 gpio-line-names = "I2S_DP_LRCK", 286 "IS_DP_BCLK", 287 "I2S_DP_MCLK", 288 "I2S_DP_DATAOUT", 289 "SAR0_INT_ODL", 290 "EC_AP_INT_ODL", 291 "EDPBRDG_INT_ODL", 292 "DPBRDG_INT_ODL", 293 "DPBRDG_PWREN", 294 "DPBRDG_RST_ODL", 295 "I2S_HP_MCLK", 296 "I2S_HP_BCK", 297 "I2S_HP_LRCK", 298 "I2S_HP_DATAIN", 299 /* 300 * AP_FLASH_WP_L is crossystem ABI. Schematics 301 * call it AP_FLASH_WP_ODL. 302 */ 303 "AP_FLASH_WP_L", 304 "TRACKPAD_INT_ODL", 305 "EC_AP_HPD_OD", 306 "SD_CD_ODL", 307 "HP_INT_ODL_ALC", 308 "EN_PP1000_DPBRDG", 309 "AP_GPIO20", 310 "TOUCH_INT_L_1V8", 311 "UART_BT_WAKE_ODL", 312 "AP_GPIO23", 313 "AP_SPI_FLASH_CS_L", 314 "AP_SPI_FLASH_CLK", 315 "EN_PP3300_DPBRDG_DX", 316 "AP_SPI_FLASH_MOSI", 317 "AP_SPI_FLASH_MISO", 318 "I2S_HP_DATAOUT", 319 "AP_GPIO30", 320 "I2S_SPKR_MCLK", 321 "I2S_SPKR_BCLK", 322 "I2S_SPKR_LRCK", 323 "I2S_SPKR_DATAIN", 324 "I2S_SPKR_DATAOUT", 325 "AP_SPI_H1_TPM_CLK", 326 "AP_SPI_H1_TPM_CS_L", 327 "AP_SPI_H1_TPM_MISO", 328 "AP_SPI_H1_TPM_MOSI", 329 "BL_PWM", 330 "EDPBRDG_PWREN", 331 "EDPBRDG_RST_ODL", 332 "EN_PP3300_HUB", 333 "HUB_RST_L", 334 "", 335 "", 336 "", 337 "", 338 "", 339 "", 340 "SD_CLK", 341 "SD_CMD", 342 "SD_DATA3", 343 "SD_DATA0", 344 "SD_DATA2", 345 "SD_DATA1", 346 "", 347 "", 348 "", 349 "", 350 "", 351 "", 352 "PCIE_WAKE_ODL", 353 "PCIE_RST_L", 354 "PCIE_CLKREQ_ODL", 355 "", 356 "", 357 "", 358 "", 359 "", 360 "", 361 "", 362 "", 363 "", 364 "", 365 "", 366 "", 367 "", 368 "", 369 "", 370 "", 371 "", 372 "", 373 "", 374 "", 375 "", 376 "", 377 "", 378 "SPMI_SCL", 379 "SPMI_SDA", 380 "AP_GOOD", 381 "UART_DBG_TX_AP_RX", 382 "UART_AP_TX_DBG_RX", 383 "UART_AP_TX_BT_RX", 384 "UART_BT_TX_AP_RX", 385 "MIPI_DPI_D0_R", 386 "MIPI_DPI_D1_R", 387 "MIPI_DPI_D2_R", 388 "MIPI_DPI_D3_R", 389 "MIPI_DPI_D4_R", 390 "MIPI_DPI_D5_R", 391 "MIPI_DPI_D6_R", 392 "MIPI_DPI_D7_R", 393 "MIPI_DPI_D8_R", 394 "MIPI_DPI_D9_R", 395 "MIPI_DPI_D10_R", 396 "", 397 "", 398 "MIPI_DPI_DE_R", 399 "MIPI_DPI_D11_R", 400 "MIPI_DPI_VSYNC_R", 401 "MIPI_DPI_CLK_R", 402 "MIPI_DPI_HSYNC_R", 403 "PCM_BT_DATAIN", 404 "PCM_BT_SYNC", 405 "PCM_BT_DATAOUT", 406 "PCM_BT_CLK", 407 "AP_I2C_AUDIO_SCL", 408 "AP_I2C_AUDIO_SDA", 409 "SCP_I2C_SCL", 410 "SCP_I2C_SDA", 411 "AP_I2C_WLAN_SCL", 412 "AP_I2C_WLAN_SDA", 413 "AP_I2C_DPBRDG_SCL", 414 "AP_I2C_DPBRDG_SDA", 415 "EN_PP1800_DPBRDG_DX", 416 "EN_PP3300_EDP_DX", 417 "EN_PP1800_EDPBRDG_DX", 418 "EN_PP1000_EDPBRDG", 419 "SCP_JTAG0_TDO", 420 "SCP_JTAG0_TDI", 421 "SCP_JTAG0_TMS", 422 "SCP_JTAG0_TCK", 423 "SCP_JTAG0_TRSTN", 424 "EN_PP3000_VMC_PMU", 425 "EN_PP3300_DISPLAY_DX", 426 "TOUCH_RST_L_1V8", 427 "TOUCH_REPORT_DISABLE", 428 "", 429 "", 430 "AP_I2C_TRACKPAD_SCL_1V8", 431 "AP_I2C_TRACKPAD_SDA_1V8", 432 "EN_PP3300_WLAN", 433 "BT_KILL_L", 434 "WIFI_KILL_L", 435 "SET_VMC_VOLT_AT_1V8", 436 "EN_SPK", 437 "AP_WARM_RST_REQ", 438 "", 439 "", 440 "EN_PP3000_SD_S3", 441 "AP_EDP_BKLTEN", 442 "", 443 "", 444 "", 445 "AP_SPI_EC_CLK", 446 "AP_SPI_EC_CS_L", 447 "AP_SPI_EC_MISO", 448 "AP_SPI_EC_MOSI", 449 "AP_I2C_EDPBRDG_SCL", 450 "AP_I2C_EDPBRDG_SDA", 451 "MT6315_PROC_INT", 452 "MT6315_GPU_INT", 453 "UART_SERVO_TX_SCP_RX", 454 "UART_SCP_TX_SERVO_RX", 455 "BT_RTS_AP_CTS", 456 "AP_RTS_BT_CTS", 457 "UART_AP_WAKE_BT_ODL", 458 "WLAN_ALERT_ODL", 459 "EC_IN_RW_ODL", 460 "H1_AP_INT_ODL", 461 "", 462 "", 463 "", 464 "", 465 "", 466 "", 467 "", 468 "", 469 "", 470 "", 471 "", 472 "MSDC0_CMD", 473 "MSDC0_DAT0", 474 "MSDC0_DAT2", 475 "MSDC0_DAT4", 476 "MSDC0_DAT6", 477 "MSDC0_DAT1", 478 "MSDC0_DAT5", 479 "MSDC0_DAT7", 480 "MSDC0_DSL", 481 "MSDC0_CLK", 482 "MSDC0_DAT3", 483 "MSDC0_RST_L", 484 "SCP_VREQ_VAO", 485 "AUD_DAT_MOSI2", 486 "AUD_NLE_MOSI1", 487 "AUD_NLE_MOSI0", 488 "AUD_DAT_MISO2", 489 "AP_I2C_SAR_SDA", 490 "AP_I2C_SAR_SCL", 491 "AP_I2C_PWR_SCL", 492 "AP_I2C_PWR_SDA", 493 "AP_I2C_TS_SCL_1V8", 494 "AP_I2C_TS_SDA_1V8", 495 "SRCLKENA0", 496 "SRCLKENA1", 497 "AP_EC_WATCHDOG_L", 498 "PWRAP_SPI0_MI", 499 "PWRAP_SPI0_CSN", 500 "PWRAP_SPI0_MO", 501 "PWRAP_SPI0_CK", 502 "AP_RTC_CLK32K", 503 "AUD_CLK_MOSI", 504 "AUD_SYNC_MOSI", 505 "AUD_DAT_MOSI0", 506 "AUD_DAT_MOSI1", 507 "AUD_DAT_MISO0", 508 "AUD_DAT_MISO1"; 509 510 cr50_int: cr50-irq-default-pins { 511 pins-gsc-ap-int-odl { 512 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 513 input-enable; 514 }; 515 }; 516 517 cros_ec_int: cros-ec-irq-default-pins { 518 pins-ec-ap-int-odl { 519 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 520 input-enable; 521 bias-pull-up; 522 }; 523 }; 524 525 i2c0_pins: i2c0-default-pins { 526 pins-bus { 527 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 528 <PINMUX_GPIO205__FUNC_SDA0>; 529 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 530 drive-strength-microamp = <1000>; 531 }; 532 }; 533 534 i2c1_pins: i2c1-default-pins { 535 pins-bus { 536 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 537 <PINMUX_GPIO119__FUNC_SDA1>; 538 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 539 drive-strength-microamp = <1000>; 540 }; 541 }; 542 543 i2c2_pins: i2c2-default-pins { 544 pins-bus { 545 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 546 <PINMUX_GPIO142__FUNC_SDA2>; 547 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 548 }; 549 }; 550 551 i2c3_pins: i2c3-default-pins { 552 pins-bus { 553 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 554 <PINMUX_GPIO161__FUNC_SDA3>; 555 bias-disable; 556 drive-strength-microamp = <1000>; 557 }; 558 }; 559 560 i2c7_pins: i2c7-default-pins { 561 pins-bus { 562 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 563 <PINMUX_GPIO125__FUNC_SDA7>; 564 bias-disable; 565 drive-strength-microamp = <1000>; 566 }; 567 }; 568 569 mmc0_default_pins: mmc0-default-pins { 570 pins-cmd-dat { 571 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 572 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 573 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 574 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 575 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 576 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 577 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 578 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 579 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 580 input-enable; 581 drive-strength = <8>; 582 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 583 }; 584 585 pins-clk { 586 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 587 drive-strength = <8>; 588 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 589 }; 590 591 pins-rst { 592 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 593 drive-strength = <8>; 594 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 595 }; 596 }; 597 598 mmc0_uhs_pins: mmc0-uhs-pins { 599 pins-cmd-dat { 600 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 601 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 602 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 603 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 604 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 605 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 606 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 607 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 608 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 609 input-enable; 610 drive-strength = <10>; 611 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 612 }; 613 614 pins-clk { 615 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 616 drive-strength = <10>; 617 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 618 }; 619 620 pins-rst { 621 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 622 drive-strength = <8>; 623 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 624 }; 625 626 pins-ds { 627 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 628 drive-strength = <10>; 629 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 630 }; 631 }; 632 633 mmc1_default_pins: mmc1-default-pins { 634 pins-cmd-dat { 635 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 636 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 637 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 638 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 639 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 640 input-enable; 641 drive-strength = <8>; 642 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 643 }; 644 645 pins-clk { 646 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 647 drive-strength = <8>; 648 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 649 }; 650 651 pins-insert { 652 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 653 input-enable; 654 bias-pull-up; 655 }; 656 }; 657 658 mmc1_uhs_pins: mmc1-uhs-pins { 659 pins-cmd-dat { 660 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 661 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 662 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 663 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 664 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 665 input-enable; 666 drive-strength = <8>; 667 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 668 }; 669 670 pins-clk { 671 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 672 input-enable; 673 drive-strength = <8>; 674 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 675 }; 676 }; 677 678 nor_flash_pins: nor-flash-default-pins { 679 pins-cs-io1 { 680 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 681 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 682 input-enable; 683 bias-pull-up; 684 drive-strength = <10>; 685 }; 686 687 pins-io0 { 688 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 689 bias-pull-up; 690 drive-strength = <10>; 691 }; 692 693 pins-clk { 694 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 695 input-enable; 696 bias-pull-up; 697 drive-strength = <10>; 698 }; 699 }; 700 701 pcie_pins: pcie-default-pins { 702 pins-pcie-wake { 703 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 704 bias-pull-up; 705 }; 706 707 pins-pcie-pereset { 708 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 709 }; 710 711 pins-pcie-clkreq { 712 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 713 bias-pull-up; 714 }; 715 716 pins-wifi-kill { 717 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 718 output-high; 719 }; 720 }; 721 722 pp3300_wlan_pins: pp3300-wlan-pins { 723 pins-pcie-en-pp3300-wlan { 724 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 725 output-high; 726 }; 727 }; 728 729 scp_pins: scp-pins { 730 pins-vreq-vao { 731 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 732 }; 733 }; 734 735 spi1_pins: spi1-default-pins { 736 pins-cs-mosi-clk { 737 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 738 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 739 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 740 bias-disable; 741 }; 742 743 pins-miso { 744 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 745 bias-pull-down; 746 }; 747 }; 748 749 spi5_pins: spi5-default-pins { 750 pins-bus { 751 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 752 <PINMUX_GPIO37__FUNC_GPIO37>, 753 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 754 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 755 bias-disable; 756 }; 757 }; 758 759 trackpad_pins: trackpad-default-pins { 760 pins-int-n { 761 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 762 input-enable; 763 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 764 }; 765 }; 766 767 touchscreen_pins: touchscreen-default-pins { 768 pins-irq { 769 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 770 input-enable; 771 bias-pull-up; 772 }; 773 774 pins-reset { 775 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 776 output-high; 777 }; 778 779 pins-report-sw { 780 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 781 output-low; 782 }; 783 }; 784}; 785 786&pmic { 787 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 788}; 789 790&scp { 791 status = "okay"; 792 793 firmware-name = "mediatek/mt8192/scp.img"; 794 memory-region = <&scp_mem_reserved>; 795 pinctrl-names = "default"; 796 pinctrl-0 = <&scp_pins>; 797 798 cros-ec { 799 compatible = "google,cros-ec-rpmsg"; 800 mediatek,rpmsg-name = "cros-ec-rpmsg"; 801 }; 802}; 803 804&spi1 { 805 status = "okay"; 806 807 mediatek,pad-select = <0>; 808 pinctrl-names = "default"; 809 pinctrl-0 = <&spi1_pins>; 810 811 cros_ec: ec@0 { 812 compatible = "google,cros-ec-spi"; 813 reg = <0>; 814 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 815 spi-max-frequency = <3000000>; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&cros_ec_int>; 818 819 #address-cells = <1>; 820 #size-cells = <0>; 821 822 base_detection: cbas { 823 compatible = "google,cros-cbas"; 824 }; 825 826 cros_ec_pwm: pwm { 827 compatible = "google,cros-ec-pwm"; 828 #pwm-cells = <1>; 829 830 status = "disabled"; 831 }; 832 833 i2c_tunnel: i2c-tunnel { 834 compatible = "google,cros-ec-i2c-tunnel"; 835 google,remote-bus = <0>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 }; 839 840 mt6360_ldo3_reg: regulator@0 { 841 compatible = "google,cros-ec-regulator"; 842 reg = <0>; 843 regulator-min-microvolt = <1800000>; 844 regulator-max-microvolt = <3300000>; 845 }; 846 847 mt6360_ldo5_reg: regulator@1 { 848 compatible = "google,cros-ec-regulator"; 849 reg = <1>; 850 regulator-min-microvolt = <3300000>; 851 regulator-max-microvolt = <3300000>; 852 }; 853 854 typec { 855 compatible = "google,cros-ec-typec"; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 859 usb_c0: connector@0 { 860 compatible = "usb-c-connector"; 861 reg = <0>; 862 label = "left"; 863 power-role = "dual"; 864 data-role = "host"; 865 try-power-role = "source"; 866 }; 867 868 usb_c1: connector@1 { 869 compatible = "usb-c-connector"; 870 reg = <1>; 871 label = "right"; 872 power-role = "dual"; 873 data-role = "host"; 874 try-power-role = "source"; 875 }; 876 }; 877 }; 878}; 879 880&spi5 { 881 status = "okay"; 882 883 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 884 mediatek,pad-select = <0>; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&spi5_pins>; 887 888 cr50@0 { 889 compatible = "google,cr50"; 890 reg = <0>; 891 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 892 spi-max-frequency = <1000000>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&cr50_int>; 895 }; 896}; 897 898&spmi { 899 #address-cells = <2>; 900 #size-cells = <0>; 901 902 mt6315_6: pmic@6 { 903 compatible = "mediatek,mt6315-regulator"; 904 reg = <0x6 SPMI_USID>; 905 906 regulators { 907 mt6315_6_vbuck1: vbuck1 { 908 regulator-compatible = "vbuck1"; 909 regulator-name = "Vbcpu"; 910 regulator-min-microvolt = <300000>; 911 regulator-max-microvolt = <1193750>; 912 regulator-enable-ramp-delay = <256>; 913 regulator-allowed-modes = <0 1 2>; 914 regulator-always-on; 915 }; 916 917 mt6315_6_vbuck3: vbuck3 { 918 regulator-compatible = "vbuck3"; 919 regulator-name = "Vlcpu"; 920 regulator-min-microvolt = <300000>; 921 regulator-max-microvolt = <1193750>; 922 regulator-enable-ramp-delay = <256>; 923 regulator-allowed-modes = <0 1 2>; 924 regulator-always-on; 925 }; 926 }; 927 }; 928 929 mt6315_7: pmic@7 { 930 compatible = "mediatek,mt6315-regulator"; 931 reg = <0x7 SPMI_USID>; 932 933 regulators { 934 mt6315_7_vbuck1: vbuck1 { 935 regulator-compatible = "vbuck1"; 936 regulator-name = "Vgpu"; 937 regulator-min-microvolt = <606250>; 938 regulator-max-microvolt = <1193750>; 939 regulator-enable-ramp-delay = <256>; 940 regulator-allowed-modes = <0 1 2>; 941 }; 942 }; 943 }; 944}; 945 946&uart0 { 947 status = "okay"; 948}; 949 950&xhci { 951 status = "okay"; 952 953 wakeup-source; 954 vusb33-supply = <&pp3300_g>; 955 vbus-supply = <&pp5000_a>; 956}; 957 958#include <arm/cros-ec-keyboard.dtsi> 959#include <arm/cros-ec-sbs.dtsi> 960