1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6/dts-v1/; 7#include "mt8192.dtsi" 8#include "mt6359.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/spmi/spmi.h> 11 12/ { 13 aliases { 14 i2c0 = &i2c0; 15 i2c1 = &i2c1; 16 i2c2 = &i2c2; 17 i2c3 = &i2c3; 18 i2c7 = &i2c7; 19 mmc0 = &mmc0; 20 mmc1 = &mmc1; 21 serial0 = &uart0; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0 0x40000000 0 0x80000000>; 31 }; 32 33 backlight_lcd0: backlight-lcd0 { 34 compatible = "pwm-backlight"; 35 pwms = <&pwm0 0 500000>; 36 power-supply = <&ppvar_sys>; 37 enable-gpios = <&pio 152 0>; 38 brightness-levels = <0 1023>; 39 num-interpolated-steps = <1023>; 40 default-brightness-level = <576>; 41 }; 42 43 dmic_codec: dmic-codec { 44 compatible = "dmic-codec"; 45 num-channels = <2>; 46 wakeup-delay-ms = <50>; 47 }; 48 49 pp1000_dpbrdg: regulator-1v0-dpbrdg { 50 compatible = "regulator-fixed"; 51 regulator-name = "pp1000_dpbrdg"; 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pp1000_dpbrdg_en_pins>; 54 regulator-min-microvolt = <1000000>; 55 regulator-max-microvolt = <1000000>; 56 enable-active-high; 57 regulator-boot-on; 58 gpio = <&pio 19 GPIO_ACTIVE_HIGH>; 59 vin-supply = <&mt6359_vs2_buck_reg>; 60 }; 61 62 pp1000_mipibrdg: regulator-1v0-mipibrdg { 63 compatible = "regulator-fixed"; 64 regulator-name = "pp1000_mipibrdg"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pp1000_mipibrdg_en_pins>; 67 regulator-min-microvolt = <1000000>; 68 regulator-max-microvolt = <1000000>; 69 enable-active-high; 70 regulator-boot-on; 71 gpio = <&pio 129 GPIO_ACTIVE_HIGH>; 72 vin-supply = <&mt6359_vs2_buck_reg>; 73 }; 74 75 pp1800_dpbrdg: regulator-1v8-dpbrdg { 76 compatible = "regulator-fixed"; 77 regulator-name = "pp1800_dpbrdg"; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pp1800_dpbrdg_en_pins>; 80 enable-active-high; 81 regulator-boot-on; 82 gpio = <&pio 126 GPIO_ACTIVE_HIGH>; 83 vin-supply = <&mt6359_vio18_ldo_reg>; 84 }; 85 86 /* system wide LDO 1.8V power rail */ 87 pp1800_ldo_g: regulator-1v8-g { 88 compatible = "regulator-fixed"; 89 regulator-name = "pp1800_ldo_g"; 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <1800000>; 93 regulator-max-microvolt = <1800000>; 94 vin-supply = <&pp3300_g>; 95 }; 96 97 pp1800_mipibrdg: regulator-1v8-mipibrdg { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp1800_mipibrdg"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pp1800_mipibrdg_en_pins>; 102 enable-active-high; 103 regulator-boot-on; 104 gpio = <&pio 128 GPIO_ACTIVE_HIGH>; 105 vin-supply = <&mt6359_vio18_ldo_reg>; 106 }; 107 108 pp3300_dpbrdg: regulator-3v3-dpbrdg { 109 compatible = "regulator-fixed"; 110 regulator-name = "pp3300_dpbrdg"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pp3300_dpbrdg_en_pins>; 113 enable-active-high; 114 regulator-boot-on; 115 gpio = <&pio 26 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&pp3300_g>; 117 }; 118 119 /* system wide switching 3.3V power rail */ 120 pp3300_g: regulator-3v3-g { 121 compatible = "regulator-fixed"; 122 regulator-name = "pp3300_g"; 123 regulator-always-on; 124 regulator-boot-on; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 vin-supply = <&ppvar_sys>; 128 }; 129 130 /* system wide LDO 3.3V power rail */ 131 pp3300_ldo_z: regulator-3v3-z { 132 compatible = "regulator-fixed"; 133 regulator-name = "pp3300_ldo_z"; 134 regulator-always-on; 135 regulator-boot-on; 136 regulator-min-microvolt = <3300000>; 137 regulator-max-microvolt = <3300000>; 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300_mipibrdg: regulator-3v3-mipibrdg { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300_mipibrdg"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pp3300_mipibrdg_en_pins>; 146 enable-active-high; 147 regulator-boot-on; 148 gpio = <&pio 127 GPIO_ACTIVE_HIGH>; 149 vin-supply = <&pp3300_g>; 150 off-on-delay-us = <500000>; 151 }; 152 153 /* separately switched 3.3V power rail */ 154 pp3300_u: regulator-3v3-u { 155 compatible = "regulator-fixed"; 156 regulator-name = "pp3300_u"; 157 regulator-always-on; 158 regulator-boot-on; 159 regulator-min-microvolt = <3300000>; 160 regulator-max-microvolt = <3300000>; 161 /* enable pin wired to GPIO controlled by EC */ 162 vin-supply = <&pp3300_g>; 163 }; 164 165 pp3300_wlan: regulator-3v3-wlan { 166 compatible = "regulator-fixed"; 167 regulator-name = "pp3300_wlan"; 168 regulator-always-on; 169 regulator-boot-on; 170 regulator-min-microvolt = <3300000>; 171 regulator-max-microvolt = <3300000>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pp3300_wlan_pins>; 174 enable-active-high; 175 gpio = <&pio 143 GPIO_ACTIVE_HIGH>; 176 }; 177 178 /* system wide switching 5.0V power rail */ 179 pp5000_a: regulator-5v0-a { 180 compatible = "regulator-fixed"; 181 regulator-name = "pp5000_a"; 182 regulator-always-on; 183 regulator-boot-on; 184 regulator-min-microvolt = <5000000>; 185 regulator-max-microvolt = <5000000>; 186 vin-supply = <&ppvar_sys>; 187 }; 188 189 /* system wide semi-regulated power rail from battery or USB */ 190 ppvar_sys: regulator-var-sys { 191 compatible = "regulator-fixed"; 192 regulator-name = "ppvar_sys"; 193 regulator-always-on; 194 regulator-boot-on; 195 }; 196 197 reserved_memory: reserved-memory { 198 #address-cells = <2>; 199 #size-cells = <2>; 200 ranges; 201 202 afe_dma_mem: audio-dma-pool { 203 compatible = "shared-dma-pool"; 204 size = <0 0x100000>; 205 alignment = <0 0x10>; 206 no-map; 207 }; 208 209 scp_mem_reserved: scp@50000000 { 210 compatible = "shared-dma-pool"; 211 reg = <0 0x50000000 0 0x2900000>; 212 no-map; 213 }; 214 215 wifi_restricted_dma_region: wifi@c0000000 { 216 compatible = "restricted-dma-pool"; 217 reg = <0 0xc0000000 0 0x4000000>; 218 }; 219 }; 220 221 rt1015p: audio-codec { 222 compatible = "realtek,rt1015p"; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&rt1015p_pins>; 225 sdb-gpios = <&pio 147 GPIO_ACTIVE_HIGH>; 226 #sound-dai-cells = <0>; 227 }; 228 229 sound: sound { 230 mediatek,platform = <&afe>; 231 pinctrl-names = "aud_clk_mosi_off", 232 "aud_clk_mosi_on", 233 "aud_dat_mosi_off", 234 "aud_dat_mosi_on", 235 "aud_dat_miso_off", 236 "aud_dat_miso_on", 237 "vow_dat_miso_off", 238 "vow_dat_miso_on", 239 "vow_clk_miso_off", 240 "vow_clk_miso_on", 241 "aud_nle_mosi_off", 242 "aud_nle_mosi_on", 243 "aud_dat_miso2_off", 244 "aud_dat_miso2_on", 245 "aud_gpio_i2s3_off", 246 "aud_gpio_i2s3_on", 247 "aud_gpio_i2s8_off", 248 "aud_gpio_i2s8_on", 249 "aud_gpio_i2s9_off", 250 "aud_gpio_i2s9_on", 251 "aud_dat_mosi_ch34_off", 252 "aud_dat_mosi_ch34_on", 253 "aud_dat_miso_ch34_off", 254 "aud_dat_miso_ch34_on", 255 "aud_gpio_tdm_off", 256 "aud_gpio_tdm_on"; 257 pinctrl-0 = <&aud_clk_mosi_off_pins>; 258 pinctrl-1 = <&aud_clk_mosi_on_pins>; 259 pinctrl-2 = <&aud_dat_mosi_off_pins>; 260 pinctrl-3 = <&aud_dat_mosi_on_pins>; 261 pinctrl-4 = <&aud_dat_miso_off_pins>; 262 pinctrl-5 = <&aud_dat_miso_on_pins>; 263 pinctrl-6 = <&vow_dat_miso_off_pins>; 264 pinctrl-7 = <&vow_dat_miso_on_pins>; 265 pinctrl-8 = <&vow_clk_miso_off_pins>; 266 pinctrl-9 = <&vow_clk_miso_on_pins>; 267 pinctrl-10 = <&aud_nle_mosi_off_pins>; 268 pinctrl-11 = <&aud_nle_mosi_on_pins>; 269 pinctrl-12 = <&aud_dat_miso2_off_pins>; 270 pinctrl-13 = <&aud_dat_miso2_on_pins>; 271 pinctrl-14 = <&aud_gpio_i2s3_off_pins>; 272 pinctrl-15 = <&aud_gpio_i2s3_on_pins>; 273 pinctrl-16 = <&aud_gpio_i2s8_off_pins>; 274 pinctrl-17 = <&aud_gpio_i2s8_on_pins>; 275 pinctrl-18 = <&aud_gpio_i2s9_off_pins>; 276 pinctrl-19 = <&aud_gpio_i2s9_on_pins>; 277 pinctrl-20 = <&aud_dat_mosi_ch34_off_pins>; 278 pinctrl-21 = <&aud_dat_mosi_ch34_on_pins>; 279 pinctrl-22 = <&aud_dat_miso_ch34_off_pins>; 280 pinctrl-23 = <&aud_dat_miso_ch34_on_pins>; 281 pinctrl-24 = <&aud_gpio_tdm_off_pins>; 282 pinctrl-25 = <&aud_gpio_tdm_on_pins>; 283 }; 284}; 285 286&afe { 287 memory-region = <&afe_dma_mem>; 288}; 289 290&dsi0 { 291 status = "okay"; 292}; 293 294&dsi_out { 295 remote-endpoint = <&anx7625_in>; 296}; 297 298&gic { 299 mediatek,broken-save-restore-fw; 300}; 301 302&gpu { 303 mali-supply = <&mt6315_7_vbuck1>; 304 status = "okay"; 305}; 306 307&i2c0 { 308 status = "okay"; 309 310 clock-frequency = <400000>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&i2c0_pins>; 313 314 touchscreen: touchscreen@10 { 315 reg = <0x10>; 316 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&touchscreen_pins>; 319 }; 320}; 321 322&i2c1 { 323 status = "okay"; 324 325 clock-frequency = <400000>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&i2c1_pins>; 328 329 rt5682: audio-codec@1a { 330 /* Realtek RT5682i or RT5682s, sharing the same configuration */ 331 reg = <0x1a>; 332 interrupts-extended = <&pio 18 IRQ_TYPE_LEVEL_LOW>; 333 realtek,jd-src = <1>; 334 #sound-dai-cells = <1>; 335 336 AVDD-supply = <&mt6359_vio18_ldo_reg>; 337 DBVDD-supply = <&mt6359_vio18_ldo_reg>; 338 LDO1-IN-supply = <&mt6359_vio18_ldo_reg>; 339 MICVDD-supply = <&pp3300_g>; 340 }; 341}; 342 343&i2c2 { 344 status = "okay"; 345 346 clock-frequency = <400000>; 347 clock-stretch-ns = <12600>; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&i2c2_pins>; 350 351 trackpad: trackpad@15 { 352 compatible = "elan,ekth3000"; 353 reg = <0x15>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&trackpad_pins>; 356 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; 357 vcc-supply = <&pp3300_u>; 358 wakeup-source; 359 }; 360}; 361 362&i2c3 { 363 status = "okay"; 364 365 clock-frequency = <400000>; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&i2c3_pins>; 368 369 anx_bridge: anx7625@58 { 370 compatible = "analogix,anx7625"; 371 reg = <0x58>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&anx7625_pins>; 374 enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>; 375 reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; 376 vdd10-supply = <&pp1000_mipibrdg>; 377 vdd18-supply = <&pp1800_mipibrdg>; 378 vdd33-supply = <&pp3300_mipibrdg>; 379 380 ports { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 384 port@0 { 385 reg = <0>; 386 387 anx7625_in: endpoint { 388 remote-endpoint = <&dsi_out>; 389 }; 390 }; 391 392 port@1 { 393 reg = <1>; 394 395 anx7625_out: endpoint { 396 remote-endpoint = <&panel_in>; 397 }; 398 }; 399 }; 400 401 aux-bus { 402 panel: panel { 403 compatible = "edp-panel"; 404 power-supply = <&pp3300_mipibrdg>; 405 backlight = <&backlight_lcd0>; 406 407 port { 408 panel_in: endpoint { 409 remote-endpoint = <&anx7625_out>; 410 }; 411 }; 412 }; 413 }; 414 }; 415}; 416 417&i2c7 { 418 status = "okay"; 419 420 clock-frequency = <400000>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&i2c7_pins>; 423}; 424 425&mfg0 { 426 domain-supply = <&mt6315_7_vbuck1>; 427}; 428 429&mfg1 { 430 domain-supply = <&mt6359_vsram_others_ldo_reg>; 431}; 432 433&mipi_tx0 { 434 status = "okay"; 435}; 436 437&mmc0 { 438 status = "okay"; 439 440 pinctrl-names = "default", "state_uhs"; 441 pinctrl-0 = <&mmc0_default_pins>; 442 pinctrl-1 = <&mmc0_uhs_pins>; 443 bus-width = <8>; 444 max-frequency = <200000000>; 445 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 446 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 447 cap-mmc-highspeed; 448 mmc-hs200-1_8v; 449 mmc-hs400-1_8v; 450 supports-cqe; 451 cap-mmc-hw-reset; 452 mmc-hs400-enhanced-strobe; 453 hs400-ds-delay = <0x12814>; 454 no-sdio; 455 no-sd; 456 non-removable; 457}; 458 459&mmc1 { 460 status = "okay"; 461 462 pinctrl-names = "default", "state_uhs"; 463 pinctrl-0 = <&mmc1_default_pins>; 464 pinctrl-1 = <&mmc1_uhs_pins>; 465 bus-width = <4>; 466 max-frequency = <200000000>; 467 cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; 468 vmmc-supply = <&mt6360_ldo5_reg>; 469 vqmmc-supply = <&mt6360_ldo3_reg>; 470 cap-sd-highspeed; 471 sd-uhs-sdr50; 472 sd-uhs-sdr104; 473 no-sdio; 474 no-mmc; 475}; 476 477/* for CORE */ 478&mt6359_vgpu11_buck_reg { 479 regulator-always-on; 480}; 481 482&mt6359_vgpu11_sshub_buck_reg { 483 regulator-always-on; 484 regulator-min-microvolt = <575000>; 485 regulator-max-microvolt = <575000>; 486}; 487 488&mt6359_vrf12_ldo_reg { 489 regulator-always-on; 490}; 491 492&mt6359_vsram_others_ldo_reg { 493 regulator-min-microvolt = <750000>; 494 regulator-max-microvolt = <800000>; 495 regulator-coupled-with = <&mt6315_7_vbuck1>; 496 regulator-coupled-max-spread = <10000>; 497}; 498 499&mt6359_vufs_ldo_reg { 500 regulator-always-on; 501}; 502 503&mt6359codec { 504 mediatek,dmic-mode = <1>; /* one-wire */ 505 mediatek,mic-type-0 = <2>; /* DMIC */ 506 mediatek,mic-type-2 = <2>; /* DMIC */ 507}; 508 509&nor_flash { 510 status = "okay"; 511 512 pinctrl-names = "default"; 513 pinctrl-0 = <&nor_flash_pins>; 514 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 515 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; 516 517 flash@0 { 518 compatible = "winbond,w25q64jwm", "jedec,spi-nor"; 519 reg = <0>; 520 spi-max-frequency = <52000000>; 521 spi-rx-bus-width = <2>; 522 spi-tx-bus-width = <2>; 523 }; 524}; 525 526&pcie { 527 pinctrl-names = "default"; 528 pinctrl-0 = <&pcie_pins>; 529 530 pcie0: pcie@0,0 { 531 device_type = "pci"; 532 reg = <0x0000 0 0 0 0>; 533 num-lanes = <1>; 534 bus-range = <0x1 0x1>; 535 536 #address-cells = <3>; 537 #size-cells = <2>; 538 ranges; 539 540 wifi: wifi@0,0 { 541 reg = <0x10000 0 0 0 0x100000>, 542 <0x10000 0 0x100000 0 0x100000>; 543 memory-region = <&wifi_restricted_dma_region>; 544 }; 545 }; 546}; 547 548&pio { 549 /* 220 lines */ 550 gpio-line-names = "I2S_DP_LRCK", 551 "IS_DP_BCLK", 552 "I2S_DP_MCLK", 553 "I2S_DP_DATAOUT", 554 "SAR0_INT_ODL", 555 "EC_AP_INT_ODL", 556 "EDPBRDG_INT_ODL", 557 "DPBRDG_INT_ODL", 558 "DPBRDG_PWREN", 559 "DPBRDG_RST_ODL", 560 "I2S_HP_MCLK", 561 "I2S_HP_BCK", 562 "I2S_HP_LRCK", 563 "I2S_HP_DATAIN", 564 /* 565 * AP_FLASH_WP_L is crossystem ABI. Schematics 566 * call it AP_FLASH_WP_ODL. 567 */ 568 "AP_FLASH_WP_L", 569 "TRACKPAD_INT_ODL", 570 "EC_AP_HPD_OD", 571 "SD_CD_ODL", 572 "HP_INT_ODL_ALC", 573 "EN_PP1000_DPBRDG", 574 "AP_GPIO20", 575 "TOUCH_INT_L_1V8", 576 "UART_BT_WAKE_ODL", 577 "AP_GPIO23", 578 "AP_SPI_FLASH_CS_L", 579 "AP_SPI_FLASH_CLK", 580 "EN_PP3300_DPBRDG_DX", 581 "AP_SPI_FLASH_MOSI", 582 "AP_SPI_FLASH_MISO", 583 "I2S_HP_DATAOUT", 584 "AP_GPIO30", 585 "I2S_SPKR_MCLK", 586 "I2S_SPKR_BCLK", 587 "I2S_SPKR_LRCK", 588 "I2S_SPKR_DATAIN", 589 "I2S_SPKR_DATAOUT", 590 "AP_SPI_H1_TPM_CLK", 591 "AP_SPI_H1_TPM_CS_L", 592 "AP_SPI_H1_TPM_MISO", 593 "AP_SPI_H1_TPM_MOSI", 594 "BL_PWM", 595 "EDPBRDG_PWREN", 596 "EDPBRDG_RST_ODL", 597 "EN_PP3300_HUB", 598 "HUB_RST_L", 599 "", 600 "", 601 "", 602 "", 603 "", 604 "", 605 "SD_CLK", 606 "SD_CMD", 607 "SD_DATA3", 608 "SD_DATA0", 609 "SD_DATA2", 610 "SD_DATA1", 611 "", 612 "", 613 "", 614 "", 615 "", 616 "", 617 "PCIE_WAKE_ODL", 618 "PCIE_RST_L", 619 "PCIE_CLKREQ_ODL", 620 "", 621 "", 622 "", 623 "", 624 "", 625 "", 626 "", 627 "", 628 "", 629 "", 630 "", 631 "", 632 "", 633 "", 634 "", 635 "", 636 "", 637 "", 638 "", 639 "", 640 "", 641 "", 642 "", 643 "SPMI_SCL", 644 "SPMI_SDA", 645 "AP_GOOD", 646 "UART_DBG_TX_AP_RX", 647 "UART_AP_TX_DBG_RX", 648 "UART_AP_TX_BT_RX", 649 "UART_BT_TX_AP_RX", 650 "MIPI_DPI_D0_R", 651 "MIPI_DPI_D1_R", 652 "MIPI_DPI_D2_R", 653 "MIPI_DPI_D3_R", 654 "MIPI_DPI_D4_R", 655 "MIPI_DPI_D5_R", 656 "MIPI_DPI_D6_R", 657 "MIPI_DPI_D7_R", 658 "MIPI_DPI_D8_R", 659 "MIPI_DPI_D9_R", 660 "MIPI_DPI_D10_R", 661 "", 662 "", 663 "MIPI_DPI_DE_R", 664 "MIPI_DPI_D11_R", 665 "MIPI_DPI_VSYNC_R", 666 "MIPI_DPI_CLK_R", 667 "MIPI_DPI_HSYNC_R", 668 "PCM_BT_DATAIN", 669 "PCM_BT_SYNC", 670 "PCM_BT_DATAOUT", 671 "PCM_BT_CLK", 672 "AP_I2C_AUDIO_SCL", 673 "AP_I2C_AUDIO_SDA", 674 "SCP_I2C_SCL", 675 "SCP_I2C_SDA", 676 "AP_I2C_WLAN_SCL", 677 "AP_I2C_WLAN_SDA", 678 "AP_I2C_DPBRDG_SCL", 679 "AP_I2C_DPBRDG_SDA", 680 "EN_PP1800_DPBRDG_DX", 681 "EN_PP3300_EDP_DX", 682 "EN_PP1800_EDPBRDG_DX", 683 "EN_PP1000_EDPBRDG", 684 "SCP_JTAG0_TDO", 685 "SCP_JTAG0_TDI", 686 "SCP_JTAG0_TMS", 687 "SCP_JTAG0_TCK", 688 "SCP_JTAG0_TRSTN", 689 "EN_PP3000_VMC_PMU", 690 "EN_PP3300_DISPLAY_DX", 691 "TOUCH_RST_L_1V8", 692 "TOUCH_REPORT_DISABLE", 693 "", 694 "", 695 "AP_I2C_TRACKPAD_SCL_1V8", 696 "AP_I2C_TRACKPAD_SDA_1V8", 697 "EN_PP3300_WLAN", 698 "BT_KILL_L", 699 "WIFI_KILL_L", 700 "SET_VMC_VOLT_AT_1V8", 701 "EN_SPK", 702 "AP_WARM_RST_REQ", 703 "", 704 "", 705 "EN_PP3000_SD_S3", 706 "AP_EDP_BKLTEN", 707 "", 708 "", 709 "", 710 "AP_SPI_EC_CLK", 711 "AP_SPI_EC_CS_L", 712 "AP_SPI_EC_MISO", 713 "AP_SPI_EC_MOSI", 714 "AP_I2C_EDPBRDG_SCL", 715 "AP_I2C_EDPBRDG_SDA", 716 "MT6315_PROC_INT", 717 "MT6315_GPU_INT", 718 "UART_SERVO_TX_SCP_RX", 719 "UART_SCP_TX_SERVO_RX", 720 "BT_RTS_AP_CTS", 721 "AP_RTS_BT_CTS", 722 "UART_AP_WAKE_BT_ODL", 723 "WLAN_ALERT_ODL", 724 "EC_IN_RW_ODL", 725 "H1_AP_INT_ODL", 726 "", 727 "", 728 "", 729 "", 730 "", 731 "", 732 "", 733 "", 734 "", 735 "", 736 "", 737 "MSDC0_CMD", 738 "MSDC0_DAT0", 739 "MSDC0_DAT2", 740 "MSDC0_DAT4", 741 "MSDC0_DAT6", 742 "MSDC0_DAT1", 743 "MSDC0_DAT5", 744 "MSDC0_DAT7", 745 "MSDC0_DSL", 746 "MSDC0_CLK", 747 "MSDC0_DAT3", 748 "MSDC0_RST_L", 749 "SCP_VREQ_VAO", 750 "AUD_DAT_MOSI2", 751 "AUD_NLE_MOSI1", 752 "AUD_NLE_MOSI0", 753 "AUD_DAT_MISO2", 754 "AP_I2C_SAR_SDA", 755 "AP_I2C_SAR_SCL", 756 "AP_I2C_PWR_SCL", 757 "AP_I2C_PWR_SDA", 758 "AP_I2C_TS_SCL_1V8", 759 "AP_I2C_TS_SDA_1V8", 760 "SRCLKENA0", 761 "SRCLKENA1", 762 "AP_EC_WATCHDOG_L", 763 "PWRAP_SPI0_MI", 764 "PWRAP_SPI0_CSN", 765 "PWRAP_SPI0_MO", 766 "PWRAP_SPI0_CK", 767 "AP_RTC_CLK32K", 768 "AUD_CLK_MOSI", 769 "AUD_SYNC_MOSI", 770 "AUD_DAT_MOSI0", 771 "AUD_DAT_MOSI1", 772 "AUD_DAT_MISO0", 773 "AUD_DAT_MISO1"; 774 775 anx7625_pins: anx7625-default-pins { 776 pins-out { 777 pinmux = <PINMUX_GPIO41__FUNC_GPIO41>, 778 <PINMUX_GPIO42__FUNC_GPIO42>; 779 output-low; 780 }; 781 782 pins-in { 783 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 784 input-enable; 785 bias-pull-up; 786 }; 787 }; 788 789 aud_clk_mosi_off_pins: aud-clk-mosi-off-pins { 790 pins-mosi-off { 791 pinmux = <PINMUX_GPIO214__FUNC_GPIO214>, 792 <PINMUX_GPIO215__FUNC_GPIO215>; 793 }; 794 }; 795 796 aud_clk_mosi_on_pins: aud-clk-mosi-on-pins { 797 pins-mosi-on { 798 pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>, 799 <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>; 800 drive-strength = <10>; 801 }; 802 }; 803 804 aud_dat_miso_ch34_off_pins: aud-dat-miso-ch34-off-pins { 805 pins-miso-off { 806 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 807 }; 808 }; 809 810 aud_dat_miso_ch34_on_pins: aud-dat-miso-ch34-on-pins { 811 pins-miso-on { 812 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 813 }; 814 }; 815 816 aud_dat_miso_off_pins: aud-dat-miso-off-pins { 817 pins-miso-off { 818 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>, 819 <PINMUX_GPIO219__FUNC_GPIO219>; 820 }; 821 }; 822 823 aud_dat_miso_on_pins: aud-dat-miso-on-pins { 824 pins-miso-on { 825 pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>, 826 <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>; 827 drive-strength = <10>; 828 }; 829 }; 830 831 aud_dat_miso2_off_pins: aud-dat-miso2-off-pins { 832 pins-miso-off { 833 pinmux = <PINMUX_GPIO199__FUNC_GPIO199>; 834 }; 835 }; 836 837 aud_dat_miso2_on_pins: aud-dat-miso2-on-pins { 838 pins-miso-on { 839 pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>; 840 }; 841 }; 842 843 aud_dat_mosi_ch34_off_pins: aud-dat-mosi-ch34-off-pins { 844 pins-mosi-off { 845 pinmux = <PINMUX_GPIO196__FUNC_GPIO196>; 846 }; 847 }; 848 849 aud_dat_mosi_ch34_on_pins: aud-dat-mosi-ch34-on-pins { 850 pins-mosi-on { 851 pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>; 852 }; 853 }; 854 855 aud_dat_mosi_off_pins: aud-dat-mosi-off-pins { 856 pins-mosi-off { 857 pinmux = <PINMUX_GPIO216__FUNC_GPIO216>, 858 <PINMUX_GPIO217__FUNC_GPIO217>; 859 }; 860 }; 861 862 aud_dat_mosi_on_pins: aud-dat-mosi-on-pins { 863 pins-mosi-on { 864 pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>, 865 <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>; 866 drive-strength = <10>; 867 }; 868 }; 869 870 aud_gpio_i2s3_off_pins: aud-gpio-i2s3-off-pins { 871 pins-i2s3-off { 872 pinmux = <PINMUX_GPIO32__FUNC_GPIO32>, 873 <PINMUX_GPIO33__FUNC_GPIO33>, 874 <PINMUX_GPIO35__FUNC_GPIO35>; 875 }; 876 }; 877 878 aud_gpio_i2s3_on_pins: aud-gpio-i2s3-on-pins { 879 pins-i2s3-on { 880 pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>, 881 <PINMUX_GPIO33__FUNC_I2S3_LRCK>, 882 <PINMUX_GPIO35__FUNC_I2S3_DO>; 883 }; 884 }; 885 886 aud_gpio_i2s8_off_pins: aud-gpio-i2s8-off-pins { 887 pins-i2s8-off { 888 pinmux = <PINMUX_GPIO10__FUNC_GPIO10>, 889 <PINMUX_GPIO11__FUNC_GPIO11>, 890 <PINMUX_GPIO12__FUNC_GPIO12>, 891 <PINMUX_GPIO13__FUNC_GPIO13>; 892 }; 893 }; 894 895 aud_gpio_i2s8_on_pins: aud-gpio-i2s8-on-pins { 896 pins-i2s8-on { 897 pinmux = <PINMUX_GPIO10__FUNC_I2S8_MCK>, 898 <PINMUX_GPIO11__FUNC_I2S8_BCK>, 899 <PINMUX_GPIO12__FUNC_I2S8_LRCK>, 900 <PINMUX_GPIO13__FUNC_I2S8_DI>; 901 }; 902 }; 903 904 aud_gpio_i2s9_off_pins: aud-gpio-i2s9-off-pins { 905 pins-i2s9-off { 906 pinmux = <PINMUX_GPIO29__FUNC_GPIO29>; 907 }; 908 }; 909 910 aud_gpio_i2s9_on_pins: aud-gpio-i2s9-on-pins { 911 pins-i2s9-on { 912 pinmux = <PINMUX_GPIO29__FUNC_I2S9_DO>; 913 }; 914 }; 915 916 aud_gpio_tdm_off_pins: aud-gpio-tdm-off-pins { 917 pins-tdm-off { 918 pinmux = <PINMUX_GPIO0__FUNC_GPIO0>, 919 <PINMUX_GPIO1__FUNC_GPIO1>, 920 <PINMUX_GPIO2__FUNC_GPIO2>, 921 <PINMUX_GPIO3__FUNC_GPIO3>; 922 }; 923 }; 924 925 aud_gpio_tdm_on_pins: aud-gpio-tdm-on-pins { 926 pins-tdm-on { 927 pinmux = <PINMUX_GPIO0__FUNC_TDM_LRCK>, 928 <PINMUX_GPIO1__FUNC_TDM_BCK>, 929 <PINMUX_GPIO2__FUNC_TDM_MCK>, 930 <PINMUX_GPIO3__FUNC_TDM_DATA0>; 931 }; 932 }; 933 934 aud_nle_mosi_off_pins: aud-nle-mosi-off-pins { 935 pins-nle-mosi-off { 936 pinmux = <PINMUX_GPIO197__FUNC_GPIO197>, 937 <PINMUX_GPIO198__FUNC_GPIO198>; 938 }; 939 }; 940 941 aud_nle_mosi_on_pins: aud-nle-mosi-on-pins { 942 pins-nle-mosi-on { 943 pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>, 944 <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>; 945 }; 946 }; 947 948 cr50_int: cr50-irq-default-pins { 949 pins-gsc-ap-int-odl { 950 pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; 951 input-enable; 952 }; 953 }; 954 955 cros_ec_int: cros-ec-irq-default-pins { 956 pins-ec-ap-int-odl { 957 pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; 958 input-enable; 959 bias-pull-up; 960 }; 961 }; 962 963 i2c0_pins: i2c0-default-pins { 964 pins-bus { 965 pinmux = <PINMUX_GPIO204__FUNC_SCL0>, 966 <PINMUX_GPIO205__FUNC_SDA0>; 967 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 968 drive-strength-microamp = <1000>; 969 }; 970 }; 971 972 i2c1_pins: i2c1-default-pins { 973 pins-bus { 974 pinmux = <PINMUX_GPIO118__FUNC_SCL1>, 975 <PINMUX_GPIO119__FUNC_SDA1>; 976 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 977 drive-strength-microamp = <1000>; 978 }; 979 }; 980 981 i2c2_pins: i2c2-default-pins { 982 pins-bus { 983 pinmux = <PINMUX_GPIO141__FUNC_SCL2>, 984 <PINMUX_GPIO142__FUNC_SDA2>; 985 bias-pull-up = <MTK_PULL_SET_RSEL_011>; 986 }; 987 }; 988 989 i2c3_pins: i2c3-default-pins { 990 pins-bus { 991 pinmux = <PINMUX_GPIO160__FUNC_SCL3>, 992 <PINMUX_GPIO161__FUNC_SDA3>; 993 bias-disable; 994 drive-strength-microamp = <1000>; 995 }; 996 }; 997 998 i2c7_pins: i2c7-default-pins { 999 pins-bus { 1000 pinmux = <PINMUX_GPIO124__FUNC_SCL7>, 1001 <PINMUX_GPIO125__FUNC_SDA7>; 1002 bias-disable; 1003 drive-strength-microamp = <1000>; 1004 }; 1005 }; 1006 1007 mmc0_default_pins: mmc0-default-pins { 1008 pins-cmd-dat { 1009 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 1010 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 1011 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 1012 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1013 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1014 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1015 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1016 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1017 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1018 input-enable; 1019 drive-strength = <8>; 1020 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1021 }; 1022 1023 pins-clk { 1024 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1025 drive-strength = <8>; 1026 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1027 }; 1028 1029 pins-rst { 1030 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1031 drive-strength = <8>; 1032 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1033 }; 1034 }; 1035 1036 mmc0_uhs_pins: mmc0-uhs-pins { 1037 pins-cmd-dat { 1038 pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, 1039 <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, 1040 <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, 1041 <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, 1042 <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, 1043 <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, 1044 <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, 1045 <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, 1046 <PINMUX_GPIO183__FUNC_MSDC0_CMD>; 1047 input-enable; 1048 drive-strength = <10>; 1049 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1050 }; 1051 1052 pins-clk { 1053 pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; 1054 drive-strength = <10>; 1055 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1056 }; 1057 1058 pins-rst { 1059 pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; 1060 drive-strength = <8>; 1061 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 1062 }; 1063 1064 pins-ds { 1065 pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; 1066 drive-strength = <10>; 1067 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1068 }; 1069 }; 1070 1071 mmc1_default_pins: mmc1-default-pins { 1072 pins-cmd-dat { 1073 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1074 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1075 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1076 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1077 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1078 input-enable; 1079 drive-strength = <8>; 1080 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1081 }; 1082 1083 pins-clk { 1084 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1085 drive-strength = <8>; 1086 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1087 }; 1088 1089 pins-insert { 1090 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; 1091 input-enable; 1092 bias-pull-up; 1093 }; 1094 }; 1095 1096 mmc1_uhs_pins: mmc1-uhs-pins { 1097 pins-cmd-dat { 1098 pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, 1099 <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, 1100 <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, 1101 <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, 1102 <PINMUX_GPIO52__FUNC_MSDC1_CMD>; 1103 input-enable; 1104 drive-strength = <8>; 1105 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1106 }; 1107 1108 pins-clk { 1109 pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; 1110 input-enable; 1111 drive-strength = <8>; 1112 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1113 }; 1114 }; 1115 1116 nor_flash_pins: nor-flash-default-pins { 1117 pins-cs-io1 { 1118 pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, 1119 <PINMUX_GPIO28__FUNC_SPINOR_IO1>; 1120 input-enable; 1121 bias-pull-up; 1122 drive-strength = <10>; 1123 }; 1124 1125 pins-io0 { 1126 pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; 1127 bias-pull-up; 1128 drive-strength = <10>; 1129 }; 1130 1131 pins-clk { 1132 pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; 1133 input-enable; 1134 bias-pull-up; 1135 drive-strength = <10>; 1136 }; 1137 }; 1138 1139 pcie_pins: pcie-default-pins { 1140 pins-pcie-wake { 1141 pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; 1142 bias-pull-up; 1143 }; 1144 1145 pins-pcie-pereset { 1146 pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; 1147 }; 1148 1149 pins-pcie-clkreq { 1150 pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; 1151 bias-pull-up; 1152 }; 1153 1154 pins-wifi-kill { 1155 pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ 1156 output-high; 1157 }; 1158 }; 1159 1160 pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins { 1161 pins-en { 1162 pinmux = <PINMUX_GPIO19__FUNC_GPIO19>; 1163 output-low; 1164 }; 1165 }; 1166 1167 pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins { 1168 pins-en { 1169 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; 1170 output-low; 1171 }; 1172 }; 1173 1174 pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins { 1175 pins-en { 1176 pinmux = <PINMUX_GPIO126__FUNC_GPIO126>; 1177 output-low; 1178 }; 1179 }; 1180 1181 pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins { 1182 pins-en { 1183 pinmux = <PINMUX_GPIO128__FUNC_GPIO128>; 1184 output-low; 1185 }; 1186 }; 1187 1188 pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins { 1189 pins-en { 1190 pinmux = <PINMUX_GPIO26__FUNC_GPIO26>; 1191 output-low; 1192 }; 1193 }; 1194 1195 pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins { 1196 pins-en { 1197 pinmux = <PINMUX_GPIO127__FUNC_GPIO127>; 1198 output-low; 1199 }; 1200 }; 1201 1202 pp3300_wlan_pins: pp3300-wlan-pins { 1203 pins-pcie-en-pp3300-wlan { 1204 pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; 1205 output-high; 1206 }; 1207 }; 1208 1209 pwm0_pins: pwm0-default-pins { 1210 pins-pwm { 1211 pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>; 1212 }; 1213 1214 pins-inhibit { 1215 pinmux = <PINMUX_GPIO152__FUNC_GPIO152>; 1216 output-high; 1217 }; 1218 }; 1219 1220 rt1015p_pins: rt1015p-default-pins { 1221 pins { 1222 pinmux = <PINMUX_GPIO147__FUNC_GPIO147>; 1223 output-low; 1224 }; 1225 }; 1226 1227 scp_pins: scp-pins { 1228 pins-vreq-vao { 1229 pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; 1230 }; 1231 }; 1232 1233 spi1_pins: spi1-default-pins { 1234 pins-cs-mosi-clk { 1235 pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, 1236 <PINMUX_GPIO159__FUNC_SPI1_A_MO>, 1237 <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; 1238 bias-disable; 1239 }; 1240 1241 pins-miso { 1242 pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; 1243 bias-pull-down; 1244 }; 1245 }; 1246 1247 spi5_pins: spi5-default-pins { 1248 pins-bus { 1249 pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, 1250 <PINMUX_GPIO37__FUNC_GPIO37>, 1251 <PINMUX_GPIO39__FUNC_SPI5_A_MO>, 1252 <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; 1253 bias-disable; 1254 }; 1255 }; 1256 1257 trackpad_pins: trackpad-default-pins { 1258 pins-int-n { 1259 pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; 1260 input-enable; 1261 bias-pull-up = <MTK_PUPD_SET_R1R0_11>; 1262 }; 1263 }; 1264 1265 touchscreen_pins: touchscreen-default-pins { 1266 pins-irq { 1267 pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; 1268 input-enable; 1269 bias-pull-up; 1270 }; 1271 1272 pins-reset { 1273 pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; 1274 output-high; 1275 }; 1276 1277 pins-report-sw { 1278 pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; 1279 output-low; 1280 }; 1281 }; 1282 1283 vow_clk_miso_off_pins: vow-clk-miso-off-pins { 1284 pins-miso-off { 1285 pinmux = <PINMUX_GPIO219__FUNC_GPIO219>; 1286 }; 1287 }; 1288 1289 vow_clk_miso_on_pins: vow-clk-miso-on-pins { 1290 pins-miso-on { 1291 pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>; 1292 }; 1293 }; 1294 1295 vow_dat_miso_off_pins: vow-dat-miso-off-pins { 1296 pins-miso-off { 1297 pinmux = <PINMUX_GPIO218__FUNC_GPIO218>; 1298 }; 1299 }; 1300 1301 vow_dat_miso_on_pins: vow-dat-miso-on-pins { 1302 pins-miso-on { 1303 pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>; 1304 }; 1305 }; 1306}; 1307 1308&pmic { 1309 interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; 1310}; 1311 1312&pwm0 { 1313 status = "okay"; 1314 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&pwm0_pins>; 1317}; 1318 1319&scp { 1320 status = "okay"; 1321 1322 firmware-name = "mediatek/mt8192/scp.img"; 1323 memory-region = <&scp_mem_reserved>; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&scp_pins>; 1326 1327 cros-ec-rpmsg { 1328 compatible = "google,cros-ec-rpmsg"; 1329 mediatek,rpmsg-name = "cros-ec-rpmsg"; 1330 }; 1331}; 1332 1333&spi1 { 1334 status = "okay"; 1335 1336 mediatek,pad-select = <0>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&spi1_pins>; 1339 1340 cros_ec: ec@0 { 1341 compatible = "google,cros-ec-spi"; 1342 reg = <0>; 1343 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; 1344 spi-max-frequency = <3000000>; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&cros_ec_int>; 1347 wakeup-source; 1348 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 1352 cros_ec_pwm: pwm { 1353 compatible = "google,cros-ec-pwm"; 1354 #pwm-cells = <1>; 1355 1356 status = "disabled"; 1357 }; 1358 1359 i2c_tunnel: i2c-tunnel { 1360 compatible = "google,cros-ec-i2c-tunnel"; 1361 google,remote-bus = <0>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 }; 1365 1366 mt6360_ldo3_reg: regulator@0 { 1367 compatible = "google,cros-ec-regulator"; 1368 reg = <0>; 1369 regulator-min-microvolt = <1800000>; 1370 regulator-max-microvolt = <3300000>; 1371 }; 1372 1373 mt6360_ldo5_reg: regulator@1 { 1374 compatible = "google,cros-ec-regulator"; 1375 reg = <1>; 1376 regulator-min-microvolt = <3300000>; 1377 regulator-max-microvolt = <3300000>; 1378 }; 1379 1380 typec { 1381 compatible = "google,cros-ec-typec"; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 1385 usb_c0: connector@0 { 1386 compatible = "usb-c-connector"; 1387 reg = <0>; 1388 label = "left"; 1389 power-role = "dual"; 1390 data-role = "host"; 1391 try-power-role = "source"; 1392 }; 1393 1394 usb_c1: connector@1 { 1395 compatible = "usb-c-connector"; 1396 reg = <1>; 1397 label = "right"; 1398 power-role = "dual"; 1399 data-role = "host"; 1400 try-power-role = "source"; 1401 }; 1402 }; 1403 }; 1404}; 1405 1406&spi5 { 1407 status = "okay"; 1408 1409 cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; 1410 mediatek,pad-select = <0>; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&spi5_pins>; 1413 1414 tpm@0 { 1415 compatible = "google,cr50"; 1416 reg = <0>; 1417 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; 1418 spi-max-frequency = <1000000>; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&cr50_int>; 1421 }; 1422}; 1423 1424&spmi { 1425 #address-cells = <2>; 1426 #size-cells = <0>; 1427 1428 mt6315_6: pmic@6 { 1429 compatible = "mediatek,mt6315-regulator"; 1430 reg = <0x6 SPMI_USID>; 1431 1432 regulators { 1433 mt6315_6_vbuck1: vbuck1 { 1434 regulator-name = "Vbcpu"; 1435 regulator-min-microvolt = <400000>; 1436 regulator-max-microvolt = <1193750>; 1437 regulator-enable-ramp-delay = <256>; 1438 regulator-allowed-modes = <0 1 2>; 1439 regulator-always-on; 1440 }; 1441 1442 mt6315_6_vbuck3: vbuck3 { 1443 regulator-name = "Vlcpu"; 1444 regulator-min-microvolt = <400000>; 1445 regulator-max-microvolt = <1193750>; 1446 regulator-enable-ramp-delay = <256>; 1447 regulator-allowed-modes = <0 1 2>; 1448 regulator-always-on; 1449 }; 1450 }; 1451 }; 1452 1453 mt6315_7: pmic@7 { 1454 compatible = "mediatek,mt6315-regulator"; 1455 reg = <0x7 SPMI_USID>; 1456 1457 regulators { 1458 mt6315_7_vbuck1: vbuck1 { 1459 regulator-name = "Vgpu"; 1460 regulator-min-microvolt = <400000>; 1461 regulator-max-microvolt = <800000>; 1462 regulator-enable-ramp-delay = <256>; 1463 regulator-allowed-modes = <0 1 2>; 1464 regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; 1465 regulator-coupled-max-spread = <10000>; 1466 }; 1467 }; 1468 }; 1469}; 1470 1471&uart0 { 1472 status = "okay"; 1473}; 1474 1475&xhci { 1476 status = "okay"; 1477 1478 wakeup-source; 1479 vusb33-supply = <&pp3300_g>; 1480 vbus-supply = <&pp5000_a>; 1481}; 1482 1483#include <arm/cros-ec-keyboard.dtsi> 1484#include <arm/cros-ec-sbs.dtsi> 1485