1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2021 BayLibre, SAS. 4 * Author: Fabien Parent <fparent@baylibre.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 model = "Pumpkin MT8183"; 15 compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183"; 16 17 aliases { 18 serial0 = &uart0; 19 }; 20 21 memory@40000000 { 22 device_type = "memory"; 23 reg = <0 0x40000000 0 0x80000000>; 24 }; 25 26 chosen { 27 stdout-path = "serial0:921600n8"; 28 }; 29 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 scp_mem_reserved: scp_mem_region@50000000 { 36 compatible = "shared-dma-pool"; 37 reg = <0 0x50000000 0 0x2900000>; 38 no-map; 39 }; 40 }; 41 42 leds { 43 compatible = "gpio-leds"; 44 45 led-red { 46 label = "red"; 47 gpios = <&pio 155 GPIO_ACTIVE_HIGH>; 48 default-state = "off"; 49 }; 50 51 led-green { 52 label = "green"; 53 gpios = <&pio 156 GPIO_ACTIVE_HIGH>; 54 default-state = "off"; 55 }; 56 }; 57 58 ntc { 59 compatible = "murata,ncp03wf104"; 60 pullup-uv = <1800000>; 61 pullup-ohm = <390000>; 62 pulldown-ohm = <0>; 63 io-channels = <&auxadc 0>; 64 }; 65}; 66 67&auxadc { 68 status = "okay"; 69}; 70 71&i2c0 { 72 pinctrl-names = "default"; 73 pinctrl-0 = <&i2c_pins_0>; 74 status = "okay"; 75 clock-frequency = <100000>; 76}; 77 78&i2c1 { 79 pinctrl-names = "default"; 80 pinctrl-0 = <&i2c_pins_1>; 81 status = "okay"; 82 clock-frequency = <100000>; 83}; 84 85&i2c2 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&i2c_pins_2>; 88 status = "okay"; 89 clock-frequency = <100000>; 90}; 91 92&i2c3 { 93 pinctrl-names = "default"; 94 pinctrl-0 = <&i2c_pins_3>; 95 status = "okay"; 96 clock-frequency = <100000>; 97}; 98 99&i2c4 { 100 pinctrl-names = "default"; 101 pinctrl-0 = <&i2c_pins_4>; 102 status = "okay"; 103 clock-frequency = <100000>; 104}; 105 106&i2c5 { 107 pinctrl-names = "default"; 108 pinctrl-0 = <&i2c_pins_5>; 109 status = "okay"; 110 clock-frequency = <100000>; 111}; 112 113&i2c6 { 114 pinctrl-names = "default"; 115 pinctrl-0 = <&i2c6_pins>; 116 status = "okay"; 117 clock-frequency = <100000>; 118}; 119 120&mmc0 { 121 status = "okay"; 122 pinctrl-names = "default", "state_uhs"; 123 pinctrl-0 = <&mmc0_pins_default>; 124 pinctrl-1 = <&mmc0_pins_uhs>; 125 bus-width = <8>; 126 max-frequency = <200000000>; 127 cap-mmc-highspeed; 128 mmc-hs200-1_8v; 129 mmc-hs400-1_8v; 130 cap-mmc-hw-reset; 131 no-sdio; 132 no-sd; 133 hs400-ds-delay = <0x12814>; 134 vmmc-supply = <&mt6358_vemc_reg>; 135 vqmmc-supply = <&mt6358_vio18_reg>; 136 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 137 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 138 non-removable; 139}; 140 141&mmc1 { 142 status = "okay"; 143 pinctrl-names = "default", "state_uhs"; 144 pinctrl-0 = <&mmc1_pins_default>; 145 pinctrl-1 = <&mmc1_pins_uhs>; 146 bus-width = <4>; 147 max-frequency = <200000000>; 148 cap-sd-highspeed; 149 sd-uhs-sdr50; 150 sd-uhs-sdr104; 151 cap-sdio-irq; 152 no-mmc; 153 no-sd; 154 vmmc-supply = <&mt6358_vmch_reg>; 155 vqmmc-supply = <&mt6358_vmc_reg>; 156 keep-power-in-suspend; 157 enable-sdio-wakeup; 158 non-removable; 159}; 160 161&pio { 162 i2c_pins_0: i2c0 { 163 pins_i2c{ 164 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 165 <PINMUX_GPIO83__FUNC_SCL0>; 166 mediatek,pull-up-adv = <3>; 167 mediatek,drive-strength-adv = <00>; 168 }; 169 }; 170 171 i2c_pins_1: i2c1 { 172 pins_i2c{ 173 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 174 <PINMUX_GPIO84__FUNC_SCL1>; 175 mediatek,pull-up-adv = <3>; 176 mediatek,drive-strength-adv = <00>; 177 }; 178 }; 179 180 i2c_pins_2: i2c2 { 181 pins_i2c{ 182 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 183 <PINMUX_GPIO104__FUNC_SDA2>; 184 mediatek,pull-up-adv = <3>; 185 mediatek,drive-strength-adv = <00>; 186 }; 187 }; 188 189 i2c_pins_3: i2c3 { 190 pins_i2c{ 191 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 192 <PINMUX_GPIO51__FUNC_SDA3>; 193 mediatek,pull-up-adv = <3>; 194 mediatek,drive-strength-adv = <00>; 195 }; 196 }; 197 198 i2c_pins_4: i2c4 { 199 pins_i2c{ 200 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 201 <PINMUX_GPIO106__FUNC_SDA4>; 202 mediatek,pull-up-adv = <3>; 203 mediatek,drive-strength-adv = <00>; 204 }; 205 }; 206 207 i2c_pins_5: i2c5 { 208 pins_i2c{ 209 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 210 <PINMUX_GPIO49__FUNC_SDA5>; 211 mediatek,pull-up-adv = <3>; 212 mediatek,drive-strength-adv = <00>; 213 }; 214 }; 215 216 i2c6_pins: i2c6 { 217 pins_cmd_dat { 218 pinmux = <PINMUX_GPIO113__FUNC_SCL6>, 219 <PINMUX_GPIO114__FUNC_SDA6>; 220 mediatek,pull-up-adv = <3>; 221 }; 222 }; 223 224 mmc0_pins_default: mmc0-pins-default { 225 pins_cmd_dat { 226 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 227 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 228 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 229 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 230 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 231 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 232 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 233 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 234 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 235 input-enable; 236 drive-strength = <MTK_DRIVE_14mA>; 237 mediatek,pull-up-adv = <01>; 238 }; 239 240 pins_clk { 241 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 242 drive-strength = <MTK_DRIVE_14mA>; 243 mediatek,pull-down-adv = <10>; 244 }; 245 246 pins_rst { 247 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 248 drive-strength = <MTK_DRIVE_14mA>; 249 mediatek,pull-down-adv = <01>; 250 }; 251 }; 252 253 mmc0_pins_uhs: mmc0-pins-uhs { 254 pins_cmd_dat { 255 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 256 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 257 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 258 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 259 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 260 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 261 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 262 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 263 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 264 input-enable; 265 drive-strength = <MTK_DRIVE_14mA>; 266 mediatek,pull-up-adv = <01>; 267 }; 268 269 pins_clk { 270 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 271 drive-strength = <MTK_DRIVE_14mA>; 272 mediatek,pull-down-adv = <10>; 273 }; 274 275 pins_ds { 276 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 277 drive-strength = <MTK_DRIVE_14mA>; 278 mediatek,pull-down-adv = <10>; 279 }; 280 281 pins_rst { 282 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 283 drive-strength = <MTK_DRIVE_14mA>; 284 mediatek,pull-up-adv = <01>; 285 }; 286 }; 287 288 mmc1_pins_default: mmc1-pins-default { 289 pins_cmd_dat { 290 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 291 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 292 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 293 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 294 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 295 input-enable; 296 mediatek,pull-up-adv = <10>; 297 }; 298 299 pins_clk { 300 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 301 input-enable; 302 mediatek,pull-down-adv = <10>; 303 }; 304 305 pins_pmu { 306 pinmux = <PINMUX_GPIO178__FUNC_GPIO178>; 307 output-high; 308 }; 309 }; 310 311 mmc1_pins_uhs: mmc1-pins-uhs { 312 pins_cmd_dat { 313 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 314 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 315 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 316 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 317 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 318 drive-strength = <MTK_DRIVE_6mA>; 319 input-enable; 320 mediatek,pull-up-adv = <10>; 321 }; 322 323 pins_clk { 324 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 325 drive-strength = <MTK_DRIVE_8mA>; 326 mediatek,pull-down-adv = <10>; 327 input-enable; 328 }; 329 }; 330}; 331 332&mfg { 333 domain-supply = <&mt6358_vgpu_reg>; 334}; 335 336&cpu0 { 337 proc-supply = <&mt6358_vproc12_reg>; 338}; 339 340&cpu1 { 341 proc-supply = <&mt6358_vproc12_reg>; 342}; 343 344&cpu2 { 345 proc-supply = <&mt6358_vproc12_reg>; 346}; 347 348&cpu3 { 349 proc-supply = <&mt6358_vproc12_reg>; 350}; 351 352&cpu4 { 353 proc-supply = <&mt6358_vproc11_reg>; 354}; 355 356&cpu5 { 357 proc-supply = <&mt6358_vproc11_reg>; 358}; 359 360&cpu6 { 361 proc-supply = <&mt6358_vproc11_reg>; 362}; 363 364&cpu7 { 365 proc-supply = <&mt6358_vproc11_reg>; 366}; 367 368&uart0 { 369 status = "okay"; 370}; 371 372&scp { 373 status = "okay"; 374}; 375 376&dsi0 { 377 status = "disabled"; 378}; 379